Cirrus Logic AN241 User Manual

AN241

Analog Input Buffer Architectures

by Kevin L Tretter

1. Introduction

There are many considerations that must be taken into account when designing and implementing an an­alog input buffer. These include negligible noise contribution, input biasing, isolation from switched ca­pacitor currents, maintaining a low output impedance so as not to cause distortion, and providing anti­alias filtering appropriate for the modulator sampling rate.

This application note provides several filter topologies that address the above concerns. The following an­alog input buffers have been divided into four categories: fully differential, single-ended to differential, sin­gle-ended with dedicated reference pins for each channel, and single-ended with a common, or shared,
reference.

2. Fully Differential Analog Input Buffer

2.1 Applicable Converters

A fully differential analog input buffer is ideal for use with the following Cirrus Logic audio converters:

- CS5361

- CS5381

- CS4272

- CS42528/26/18/16

- CS42428/26/18/16

2.2 Introduction to Differential Signals

A differential signal can be defined as two nodes that have equal but opposite signals around a fixed point
(called the common mode level). The two signal nodes are typically referred to as positive and negative
(or non-inverting and inverting), as shown in the following example of a differential sine wave:

CSxxxx

3.91 V

2.50 V

1.09 V

3.91 V

2.50 V

1.09 V

Full Scale Input Level = (AIN+) - (AIN-) = 5.64 Vpp

Figure 1. Example of a Differential Signal

AIN+

AIN-

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Copyright  Cirrus Logic, Inc. 2003

(All Rights Reserved)

OCT ‘03

AN241REV1

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In the above example, the full scale input voltage is 5.64 Vpp (differentially), with each leg swinging

2.82 Vpp. Please note that the full scale input voltage level may vary from part to part. Also, the common
mode level (which in the above example is 2.5 0V) can also vary depending on the converter.

2.3 Recommended Filter Topology

Figure 2 shows a fully differential analog input buffer. This buffer provides proper biasing, isolation from
the switched capacitor currents, low output impedance, and anti-alias filtering. The noise contribution of
this buffer is determined primarily by the noise floor of the op-amp.

634

Ω

100 k

100 k

100 k

100 k

470 pF

CSxxxx

C0G

-

10µF

Ω

10 k

10 k

Ω

Ω

0.01µF

+

470 pF

C0G

-

91

634

91

Ω

AIN+

Ω

2700 pF

C0G

Ω

AIN-

Ω

10µF

+

VQ or

1µF

634

Ω

470 pF

C0G

-

10µF

Ω

10 k

10 k

Ω

Ω

0.01µF

+

470 pF

C0G

-

-

91

634

91

Ω

Ω

Ω

0.01µF

2700 pF

C0G

VCOM

AIN+

AIN-

+

Ω

10µF

Figure 2. Fully Differential Input Buffer

2.4 Overview of the Filter Topology

2.4.1 High Pass Filter and DC Biasing

The first stage of the buffer forms a high pass filter and provides the proper biasing to the positive termi­nals of the op-amps. The high pass filter is formed from the combination of the AC-coupling capacitor
along with the resistor to the bias voltage reference (VQ or VCOM, depending on the naming convention).
The 3 dB corner of the high pass filter can be calculated as follows:

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F

C

where: R is the value of the resistor (in Ohms)

C

is the value of the capacitor (in Farads)

R

In the input buffer shown in Figure 2,
mately 1.59 Hz. Typically, this corner should be at least one decade below the bandwidth of interest in
order to prevent a significant droop in the frequency response.

The proper DC biasing (common mode level) is set via the on-chip reference (VQ or VCOM). In the input
buffer shown above, the bias is set through a 10k
eral implications. Since the input impedance into the op-amp is extremely high, the effective input imped­ance into the analog input buffer will be determined by the value of the resistor to the bias voltage in
parallel with the 100 k
mately 9 k
ure 2, the AC-coupling capacitor will initially be charged up via the on-chip reference (VQ or VCOM). This
charge up time is dependent on the size of the AC-coupling capacitor and the amount of series resistance
to the reference voltage supply. The reference pin (VQ or VCOM) has an associated output impedance
that must also be considered when calculating the charge up time. The time constant can be calculated
as follows:

Ω.

Ideally, the larger this input impedance the better. However, in the input buffer shown in Fig-

Ω

shunt resistor. In the input buffer shown above, the input impedance is approxi-

= 10 kΩ and C = 10µF. This places the 3 dB corner at approxi-

1

=

RC

π

2

Ω

resistor. Please note that this resistor value has sev-

RC=

τ

R

where

In the input buffer shown in Figure 2,
pin), and C = 10µF. This produces a time constant of 0.35 s. This would indicate that the capacitor will
charge up to within 99% of the final DC value in approximately 1.75 s (which is 5 time constants). The
100 k
gardless of whether or not there is an input signal source present.

2.4.2 Op Amp Circuitry and Anti-Aliasing Capacitor

The op-amp topology used in the input buffer shown in Figure 2 addresses two issues. First, it provides
an extremely low output impedance and therefore minimizes the amount of distortion presented to the
converters internal sampling circuits. By placing the 91
divided by the open-loop gain of the op-amp, providing a sub-ohm output impedance. Secondly, this op­amp topology provides a low pass filter. Using the recommended values, this filter remains flat throughout
the audio passband and provides approximately 2 0dB of rejection at the modulator sampling rate (where
the converter is susceptible to aliasing). The characteristics of this low pass filter can be changed by ad­justing the values of the resistors and capacitors in the feedback loop. However, it is important to maintain
a flat frequency response throughout the passband of interest and to provide reasonable attenuation at
the input sampling rate of the converter. Also, low value resistors should be used to minimize the addition
of resistor thermal noise.

= the amount of resistance between the AC-coupling capacitor and reference voltage (in

Ohms)

C

= the value of capacitance of the AC-coupling capacitor (in Farads)

R

= 35 kΩ (assuming a 25kΩ output impedance on the reference

Ω

resistors to ground on the input node allow a DC path to charge the AC-coupling capacitors, re-

Ω

resistor in the feedback loop, it’s resistance is

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Figure 2 implements a common mode capacitor between the positive and negative nodes of the differen­tial inputs. This capacitor is commonly referred to as the anti-aliasing capacitor, and performs several
functions. The value of the capacitor affects the overall low pass filter response and the amount of atten­uation at the modulator sampling rate. This capacitor also acts as a charge reservoir for the internal sam­pling capacitors. Since this capacitor is located in the signal path, it is very important not to use capacitors
with a large voltage coefficient (such as general purpose ceramics) since they can degrade signal linear­ity.

3. Single-Ended to Differential Input Buffer

3.1 Applicable Converters

A single-ended to differential analog input buffer is ideal for use with the following Cirrus Logic audio con­verters:

- CS5361

- CS4272

- CS42528/26/18/16

- CS42428/26/18/16

3.2 Introduction

A single-ended signal consists of only one signal line and hence requires only one input pin. Single-ended
inputs typically require less input buffer components, but also have several disadvantages. First, at a giv­en voltage level, a single-ended input cannot produce as much signal swing as a differential signal, hence
reducing the dynamic range. Also, single-ended inputs are more prone to errors caused by DC offsets and
coupled-noise.

3.3 Recommended Filter Topology

Figure 3 shows a single-ended to differential analog input buffer. This buffer provides proper biasing, iso­lation from the switched capacitor currents, low output impedance, and anti-alias filtering. The second op­amp stage is set up in an inverting configuration to produce the negative node of the differential input. In
the input buffer shown below, the second stage has unity gain, and the single-ended input level will effec­tively be doubled when presented differentially to the converter. For example, a 2Vpp single-ended input
will provide a 4Vpp differential input to the converter.

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634

AN241

Ω

100 k

100 k

470 pF

C0G

1µF

Ω

Ω

3.3 k

Rk

3.3 k

Rk

VA

Ω

Ω

1µF

VA

Ω

Ω

100 k

0.01µF100µF

100 k

0.01µF100µF

-

+

Ω

470 pF

C0G

-

+

Ω

634

634

634

91

91

Ω

634

Ω

Ω

470 pF

C0G

Ω

634

91

91

Ω

Ω

-

+

Ω

Ω

Ω

470 pF

C0G

-

+

2700 pF

C0G

0.01µF1µF

2700 pF

C0G

CSxxxx

AIN+

AIN-

VQ or
VCOM

AIN+

AIN-

Figure 3. Single-Ended to Differential Input Buffer

3.4 Overview of the Filter Topology

3.4.1 High Pass Filter and DC Biasing

The first stage of the buffer forms a high pass filter and provides the proper biasing to the positive termi­nals of the op-amps. The value of the resistors denoted as “R” will vary depending on the optimal DC bias
for the given converter. Typically this is around half of the VA voltage supply. The high pass filter is formed
from the combination of the AC-coupling capacitor along with the resistor that connects the positive ter­minal of the op-amp to the DC bias voltage. The 3dB corner of the high pass filter can be calculated as
follows:

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