Cirrus Logic AN240 User Manual

AN240

t e y s k d s

EP9312 USB version 1.1 Slave Schematic

The attached schematic shows a reference design for at tachi ng the USB bus to the SRAM interface.

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MAY ‘03

AN240REV1

A A

B B

C C

1M, 0603

Notes:

-EP9312 symbol is incomplete as this is meant

-SENSE/EOT signal acts as both a USB Vbus detect

-Likewise, R10/R11 form a 3.3V pullup network for the EOT

-This schematic assumes minimal or no loading of the buses signal via the USB +5V bus rail. Thus, there is no pullup resistor

for the SENSE/EOT signal.

between the EP9312 and the PDIUSBD12. Depending on your

design, you may need additional buffering to reduce

the overall load on these signals.

datasheet for additional details.

AND the end-of-transfer signal for DMA operations.

This is intentional. Please see the Philips PDIUSBD12

only for reference purposes.

D D

SENSE/EOT

560K, 0603

R11

R10

FERRITE_BEAD, 0603

USB-B

GNDSHIELD

D+

D-

1 2

FERRITE_BEAD, 0603

SHIELD

PWR

123

1.5K, 0603

22PF, 0603

18.2_1%, 0603

C12

22PF, 0603

6MHZ, HC49-US

C11

18.2_1%, 0603

4.7K, 0603

INT1

VCC3

DREQ

VCC3

R159

GND

VCC

V3.3

PDIUSBD12, TSSOP28

SUSPEND

*RST

ALE

171214

XTAL1

XTAL2

*DMREQ

*INT

*DMACK

*EOT

*WR

*RD

*CS

1115161028

DA7

DA6

DA5

DA4

D-D+*GL

D0D1D2D3D4D5D6

1234678

DA3

DA0

DA2

DA1

SENSE/EOT

R12

4.7K

4.7K VCC3

4.7K

DA[7:0]

Title

Size Document Number Rev

Date: Sheet

<Doc> 0

EP9312 USB 1.1 Slave

INT1

DREQ

DA6

DA5

DA7

DA1

DA4

DA2

DA0

DA3

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

EGPIO7/DREQ0

EGPIO8/DACK0

EGPIO9/DEOT0

INT1

/CS7

/RD

/WR

AD0

AD1

AD2

AD3

VCC3

4.7K

11Tuesday, June 24, 2003

EP9312-D partial SRAM interface