Cirrus Logic AN234 User Manual

AN234

* Dynamic Range and THD+N specified with different input buffer topologies

AK5394A to CS5381 Conversion

by Kevi n L Tr etter

1. Introduction

The CS5381 is a complete analog-to-digital converter for digital audio systems. The CS5381 performs
sampling , analog- to-digital c onversion a nd anti-ali as filtering , generat ing 24-bit values for both left a nd
right chan nels.

The CS53 81 offers some unique advant ages over the A K5394A including:

- Over 70% REDUCTION in package size (TSSOP)

- 50% less power consumption

- Fewer external components required (See Section 2)

- Overflow detect

- Integrated level shifters

- Over 80% less group delay (48kHz output sample rate)

Table 1 sho w s a c om parison of the key specificat ions of these two devices.

AK5394A CS5381
Conversion (Bits) 24 24
Dynamic Range (A-weighted) dB 123* 120
THD+N dB -110* -110
Analog Core Power Supply (VA) V +5.0 V +5.0 V
Digital Core Power Supply (VD) +3.3 V to +5.0 V +3.3 V to +5.0 V
Digital Interface Power Supply (VL) N/A +2.5 V to +5.0 V
Maximum Power mW 870 348
Maximum Sample Rate kHz 216 200
Package

Table 1. Comparison of Key Specifications

28-pin SOP 24-pin SOIC/TSSOP

http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2003

(All Rights Reserved)

JUL ‘03

AN234REV1

1

2. Typical Connection Diagrams

+5 V to 3.3 V

+5V

+

1µF

+

1µF 0.1µF

*

µ

0.1

F

Ω

5.1

AN234

+

µ

F

0.1

µF

0.1

1µF

+5V to 2.5V

D

CS5381

A/D CONVERTER

200 µ

F

1µF

+

Analog

(Sectio n 8)

Analog

(Section 8)

+

Input

Buffer

Input

Buffer

VA V

FILT+

0.1µF

REFGND

µ

0.1

F

VQ

AINL+

AINL-

AINR+

AINR-

GND

Figure 1. CS5381 Typical Connecti on Diagr am

+5V

+ +

10

*

+

C

*

+

C

0.22µF

Analog

Input

Buffer

(Section 8)

µF 0.1

0.1

µ

F

VA

VREFL+

0.22µF

VREFL-

VCOML

AINL+

A/D CONVERTER

AINL-

AK5394A

L

V

SDOUT

GND

D

V

ZCAL

HPFE
SMODE2
SMODE1

DFS0

DFS1

SDATA

OVFL

RST

2

I

S/LJ
M/S

HPF

MDIV

LRCK

SCLK
MCLK

µF

RST

CAL

M0
M1

VL

10 k

*

Resistor may only

be used if VD is

derived from VA. If

used, do not drive

any other logic

from VD.

µ

F

10

Reset and
Calibration

Power Down

and Mode

Settings

Audio Dat a

Processor

Timing Logic

and Clo ck

+5V to 3.3

Control

Mode

Control

Audio Data

Processor

V

Analog

Input

Buffer

(Section 8)

*

C

*

C

+

+

0.22µF

0.22µF

AINR+

AINR-

VREFR+

VREFR-

VCO MR

AGND

BGND

FSYNC

DGND

LRCK

SCLK

MCLK

* See Section 9

Timing Logic

andClock

Figure 2. AK5394A Typical Connecti on Diagram

2

AN234

Pin Name

FILT+

Positive reference voltage

REFGND

Ground reference

VQ

Internal quiescent reference voltage

AINL+

Differential Left Channel Input

AINL-

Differential Left Channel Input

-

Zero Calibration Control

VD

Digital power

GND

Ground reference

-

Calibration Active Signal

RST

Reset

I2S/LJ

Digital Interface Format Select

M/S

Master/Slave Mode Select

LRCK

Left right clock

SCLK

Serial clock

SDOUT

Serial data

-

Frame Synchronization Signal

MCLK

Master clock

M0

Mode selection

HPF

High Pass Filter Enable

M1

Mode selection

-

Substrate Ground

GND

Ground reference

VA

Analog power

AINR-

Differential Right Channel Input

AINR+

Differential Right Channel Input

VL

Logic Power

MDIV

MCLK divider

15

OVFL

Overflow

3. Pin Compatibility

Table 1 sho w s th e pins of the AK5394A and the corresponding pins of the CS5381. Please not e that the
AK5394 A has 28 pins, and the CS5381 has 24 pins.

AK5394A CS5381 Description

Pin Number Pin Name Pin Number

1, 28 VREFL+, VREFR+ 24
2, 27 VREFL-, VREFR- 23
3, 26 VCOML, VCOMR 22

4 AINL+ 16
5 AINL- 17
6ZCAL ­7VD 6
8DGND 7

9CAL ­10 RST 1
11 SMODE2 12
12 SMODE1 2
13 LRCK 3
14 SCLK 4
15 SDATA 9
16 FSYNC ­17 MCLK 5
18 DFS0 13
19 HPFE 11
20 DFS1 14
21 BGND ­22 AGND 18
23 VA 19
24 AINR- 20
25 AINR+ 21

8

10

4. Offset Calibration

The CS5381, and AK5394A all have offset calibration capability. However, the calibration process varies
slightly bet w een the AK5394A and the CS5381.

4.1 CS5381

The CS53 81 implemen ts a high pass filter tha t can be controlled via the HPF
filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPF
pin is taken high during normal operation, the current value of the DC offset register is frozen and this DC
offset will c ontinue to be sub t rac t ed from the con v ersion result.

A system calibration can then be performed by first running the CS5381 with the high pass filter enabled
(HPF = LOW) until the filter settles. At this point, disable the high pass filter (HPF = HI), thereby freezing
the stored D C of f s et .

Table 2. Pin Compatibility Between AK5394A and CS5381

pin (pi n 11). The hi gh pass

3