Cirrus Logic AN232 User Manual
AN232
28-pin SOP 24-pin SOIC/TSSOP 24-pin SOIC/TSSOP
AK5393 to CS5361/81 Conversion
by Kevi n L Tr etter
1. Introduction
The CS5361 and CS5381 are complete analog-to-digital converters for digital audio systems. They perform sam pling, a nalog-to -digita l convers ion and a nti-alias filtering , gener ating 24 -bit va lues for bo th left
and right ch annels.
The CS5361 and CS5381 offer some unique advantages over the AK5393 including:
- Over 70% REDUCTION in package size (TSSOP)
- 50% less power consumption
- 192kHz sampling capability
- Overflow detect
- Integrated level shifters
- Over 65% less group delay (48kHz output sample rate)
- External components consume less board space (See Section 2)
Table 1 sho w s a c om parison of the key specificat ions of these th ree devices.
AK5393 CS5361 CS5381
Conversion (Bits) 24 24 24
Dynamic Range (A-weighted) dB 117 114 120
THD+N dB -105 -105 -110
Analog Core Power Supply (VA) V +5.0 V +5.0 V +5.0 V
Digital Core Power Supply (VD) +3.3 V to +5.0 V +3.3 V to +5.0 V +3.3 V to +5.0 V
Digital Interface Power Supply (VL) N/A +2.5 V to +5.0 V +2.5 V to +5.0 V
Maximum Power mW 680 161 348
Maximum Sample Rate kHz 108 200 200
Package
Table 1. Comparison of Key Specifications
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
JUL ‘03
AN232REV1
1
2. Typical Connection Diagrams
AN232
+5V
47µF
+
+5 V to 3.3 V
+
+
1µF
Analog
Input
Buffer
(Section 8)
Analog
Input
Buffer
(Section 8)
1µF
0.01µF
0.01µF
1µF
0.01µF
FILT+
REFGND
VQ
AINL+
AINL-
AINR+
AINR-
GND
+
VA V
*
Ω
5.1
D
CS5361
A/D CONVERTER
0.01 µF
L
V
0.01µF0.01µF
OVFL
2
I
S/LJ
HPF
MDIV
SDOUT
LRCK
SCLK
MCLK
GND
Figure 1. CS5361 Typical Connecti on Diagr am
RST
M/S
M0
M1
* Resistor may only be
used if VD is derived
from VA. If used , do
not drive any ot her
+
1µF
VL
10 kΩ
logic from VD
+5V to 2.5V
Power Down
and Mode
Settings
Audio Data
Processor
Timing Logic
andClock
200µ
+5 V to 3.3 V
+5V
+
F
1µF
+
Analog
Buffer
(Section 8)
Analog
Buffer
(Section 8)
+
1µF 0.1µF
+
1µF
0.1µF
0.1
FILT+
µ
F
*
Ω
5.1
VA V L
0.1
µF
µ
0.1
F
VD
REFGND
µ
F
Input
Input
0.1
VQ
AINL+
AINL-
AINR+
AINR-
GND
CS5381
A/D CONVERTER
OVFL
2
S/LJ
I
HPF
MDIV
SDOUT
LRCK
SCLK
MCLK
GND
RST
M/S
M0
M1
Figure 2. CS5381 Typical Connecti on Diagr am
+
1µF
VL
10 k
*
Resistor may only
be used if VD is
derived from VA. If
used, do not drive
any other log ic
from VD.
+5V to 2.5V
Power Down
and Mode
Settings
AudioData
Processor
Timing Logic
and Clock
2
AN232
1
+5V
0µF
10µF
+
Analog
Input
Buffer
(Section 8)
Analog
Input
Buffer
(Section 8)
+
+
µ
10
0.1
0.22
0.22µF
µF 0.1
0.1
F
VA D
VREFL
µF
GNDL
µF
VCOML
AINL+
A/D CONVERTER
AINL-
AINR+
AINR-
VREFR
µF
0.1
GNDR
VCO MR
AGND
BGND
AK5393
TEST
V
ZCAL
HPFE
SMODE2
SMODE1
SDATA
LRCK
SCLK
MCLK
FSYNC
DGND
RST
CAL
DFS
10
µ
F
Reset and
Calibration
+5V to 3.3V
Control
Mode
Control
Audio Data
Processor
Timing Logic
and Clock
+
µF
Figure 3. AK5393 Typical Connecti on Diagr am
3
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