Cirrus Logic AN186 User Manual

Application Note
BRINGING UP THE EP72/73XX DEVICE
Note: Cirrus Logic assumes no responsibility for the attached information which is
provided “AS IS” without warranty of any kind (expressed or implied).
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
Copyright  Cirrus Logic, Inc. 2000
(All Rights Reserved)
OCT ‘00
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TABLE OF CONTENTS

1. INTRODUCTION .......................................................................................................................3
2. THE SUPPORTED POWER MANAGEMENT STATES ........................................................... 3
3. THE DEGLITCHER ...................................................................................................................3
4. WAKEUP DELAYS ................................................................................................................... 3
4.1 Power-up Delay - 100us ....................................................................................................4
4.2 1 to 2 Second Delay .......................................................................................................... 4
4.3 Manual WAKEUP Signal Generation ................................................................................. 5
4.3.1 Automatic WAKEUP Signal Generation ................................................................5
5. LOCK-OUT PERIOD DELAYS ................................................................................................. 6
5.1 Rationale behind the Lock-out Period Delays .................................................................... 6
6. THE FUNCTION OF "RUN/CLKEN" OUTPUT PIN AS IT RELATES
TO WAKEUP OPERATIONS ......................................... ...... ....................................... ....... ..... 6
7. WAKEUP AND NURESET CAVEAT ........................................................................................ 7
8. TIMING DIAGRAMS ................................................................................................................. 8
8.1 Timing Diagram in the case of a Cold Boot .......................................................................8
8.2 Timing Diagrams for the Case of Wakeup from Standby State .........................................9
9. AUTOMATIC WAKEUP CIRCUIT ..........................................................................................11
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LIST OF FIGURES

Figure 1. EP72/73XX Power Management States .......................................................................... 3
Figure 2. Example Circuit for Keeping nURESET Inactive during Prescribed Period.....................7
Figure 3. Timing Diagram for the Case of a Cold Boot ...................................................................8
Figure 4. Timing Diagram, External OSC(13 MHz) with “CLKEN” on ‘”RUN/CLKEN” Pin..............9
Figure 5. Timing Diagram, External OSC (13 MHz) with “RUN” on “RUN/CLKEN” Pin.................. 9
Figure 6. Timing Diagram, PLL Clock with “CLKEN” on “RUN/CLKEN” Pin .................................10
Figure 7. Timing Diagram, PLL Clock with “RUN” on “RUN/CLKEN” Pin .....................................10
Figure 8. Automatic Wakeup Circuit..............................................................................................11

LIST OF TABLES

Table 1. Wakeup Delays ................................................................................................................. 6
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1. INTRODUCTION

This application note des cribes i n detail t he recomm ended pro cedure for apply ing power to th e EP72/73 XX device, an d how to transition from the Standby State into the Operating State.

2. THE SUPPORTED POWER MANAGEMENT STATES

The EP72/73XX supports the following Power Management States:
l Operating — The normal program Execution State is the Operating State; this is a full performance State where all of
the clocks and peripherals are enabled.
l Idle — The Idle State is the same as the Operating State with the exception of the CPU clock being halted. An interrupt
will return it back to the Operating State.
l Standby — The Standby State has the lowest power consumption; selecting this state shuts down the main oscillator,
leaving only the Real Time Clock (R TC) and its associated logic powered. When the EP72/73XX is in the S tandby State, the device is basically turned “off.” Only the WAKEUP pin or interrupt source can wake up the device.
See Figure 1 to see the interactions between the power management states.
Note: The WAKEUP signal is only used to exit the Standby State, not the Idle State. The only state that the
Standby State can transition to is the Operating State.

3. THE DEGLITCHER

Built into the EP72/73XX are six identical conditio ning circuits. They are designed to deglitch the following six sig nals:
l WAKEUP l nBATCHG l nPWRFL l nURESET l nMEDCHG l Low Battery Interrupt (combination of BATOK, nEXTPWR and the internal RUN signal).
For any of the above signals to become active internal to the EP72/73XX, they must first be deglitched. Each deglitcher is simply two D Flip Flops in series configured so that the input signal must be held active (HIGH) for a minimum of two clock edges. The clock source is derived from the RTC. It is ½ the RTC frequency (i.e., ½ of 32.768 kHz = 16.384 kHz). The deglitcher performs two tasks:
1) No input signal will pass through it, unless it is held active for at least two clock edges.
2) It guarantees that the output signal from the deglitcher will be active for a minimum of ~ 62us (i.e., 1/16.384 kHz).

4. WAKEUP DELAYS

The EP72/73XX device has several different time delays that may occur when powering up and/or exiting the Standby State. The sections below describe them all.
Interrupt or Rising Wakeup
STANDBY
OPERATING
Write to Standby Location, Low Battery, or User Reset
INTERRUPT
nPor, Low Battery, or User Reset

Figure 1. EP72/73XX Power Management States

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IDLE
Write to Halt
Location
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4.1 Power-up Delay - 100us

Upon power-up, the EP72/73XX is in an unknown state. It must first be reset by the power -on reset signal (nPOR). n POR (active low) should be held low until the power supply reaches its operational voltage to initialize the EP72/73XX pr operly, and to allow the RTC to stabilize. Since the power-on reset o perates asy nchro nously to the s ystem clo ck, i t is not requ ired to w ait unt il the system clock is stabilized. Therefore, the signal nPOR must be held low at 100us after the power supply has stabilized. Afterwards, nPOR should be held high.
During normal operation (i.e., after the initial power-up) if nPOR is used to reset the EP72/73XX, it needs to be held low for at least one clock cycle of the selected clock speed (e.g., when running at 13 MHz, the low pulse width needs to be > 1/13 MHz = 77 ns). This is done to guarantee that it will be detected low.
If the EP72/73XX V guarantee that all internal logic is in a known state. This especially applies to the internal State Control logic block. This logic block must be reset to guarantee proper operation of the device. To fully reset the device, nPOR must be used. The signals nPWRFL and nURESET do not reset the State Control block.
When nPOR transitions from a low to high state, it latches several signals into the EP72/73XX. These signals are the following:
l Test[0:1] l Port E[0:2] l nURESET l DRIVE[0:1] l nMEDCHG
Since the levels of each of the above signals are latched upon nPOR rising, they need to have settled to their desired level. The recommended method of accomplishing this is by tying each of the signals directly to V or low. Test[0:1] and nURESET are latched upon reset to determine if the EP72/73XX should enter a Test mode upon power­up. For normal operation, all three signals should be either tied or pulled high. See the product data sheet for a description of each of the other signals.
core supply ever drops below the DC recommended operating range, the device must be fully reset to
dd
or gnd, or by pulling them either high
dd

4.2 1 to 2 Second Delay

A power-up or cold boot delay occurs when power is first applied to the EP72/73XX. However, it can also occur after a battery change or power failure. A power failure could occur due to the battery or wall powered supply voltage dropping below a predefined level.
Built into the EP72/73XX is a circuit that has been created to prev ent the EP72/ 73XX from exi ting the Stan dby State due to a false battery GOOD indication caused by alkaline battery recov ery. The circuit r equires th at the p ower supply voltage be at the acceptable level for at least one second. The EP72/73XX implements this by conditioning several signals into another deglitcher. This deglitcher is clock ed by a 1 Hz clock so urce, deriv ed from the R TC. Therefore, the po wer to t he EP72/73 XX must be stable for at least 2 seconds (i.e., a minimum of two 1 Hz clock edges). Th e signals su ppli ed to this d eglitch er are the following:
l nPOR l nPWRFL l BATOK l nEXTPWR
In order for the output of this deglitcher to become active, it must have the signals nPOR and nPWRFL = 1, and either BATOK = 1 or nEXTPWR = 0.
After the above criteria is met, there are two methods that can be used to exit the Standby State:
1) By using the WAKEUP signal, or
2) By receiving a keypress, RTC, external, or media change interrupt. In order for this to work, the KBWEN bit must be set in the SYSCON2 register.
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