Cirrus Logic AN152 User Manual

Application Note
USING THE CS5521/23, CS5522/24/28, AND CS552 5/26
CHARGE PUMP DRIVE FOR EXTERNAL LOADS
By Bill Durbin and Jerome Johnston

INTRODUCTION

The CS5521/23, CS5522/24/28, and CS5525/26 series of A/D converters include on-chip circuitry to drive and regulate a diode charge pump. The purpose of this application note is to explain the charge pump circuitry and how it can be used in a system design.

CS552X Overview

The CS5521/23, CS5522/24/28, and CS5525/26 series of A/D converters include a chopper-stabi­lized instrumentation am plifier for measureme nt of
low level dc signals (±100 mV or less). This ampli­fier is designed to produce very low input sampling
1.The CS5529 is not included in this Application Note because it does not contain a charge pump.
Ve
+
-
T/C
10 K
10 K
0.1 uF
current (I input current minimizes the errors that can occur in
1
< 300 pA over -40 to +85 C). A low
CVF
thermocouple measurements when high impedance circuitry is used for input protection as shown in Figure 1.
The charge pump circuitry, illustrated in Figure 1, is used to generate a negative supply (approximate­ly -2.1 V) to power the on-chip instrumentation amplifier. This enables the amplifier to measure low level input signals that are negative relative to ground while maintaining low input current. With­in certain constraints, which are described in this document, the charge pump can be used to power some additional circuitry outside the converter, such as an amplifier or a multiplexer.
VA+
CS5521/23, CS5522/24/28,
I
+
-
& CS5525/26
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
NBV
External Load
BAT85
+
Charge Pump Circuit

Figure 1. Input Amplifier inside CS552x ADCs.

Copyright  Cirrus Logic, Inc. 1999
(All Rights Reserved)
CPD
1N4148
1N4148
AUG ‘99
AN152REV1
1
Frequency = f
+5 V
Q
AN152
1
C
1
D
2
-V
Q

Figure 2. Charge Pump Components

V
D
C
1
-
+
D
I
1
(a) (b)

Figure 3. Charge Pump Cycle Sequence

Charge Pump Basics

Figure 2 illustrates a basic diode charge pump. Transistors Q1 and Q2 represent the output transis­tors of a CMOS inverter. When the input to the in­verter causes transistor Q1 to be turned on (Q2 is off) C1 is charged through diode D1 to a voltage of approximately 5 V minus the forward voltage of the diode. When the output of inverter switches to Q1 off, Q2 on, the positively charged lead of C1 will be connected to ground. Since the voltage across a capacitor cannot change instantaneously, the lead of C1 which is connected to diode D2 will go negative, turning on diode D2. The charge on C1 will then flow onto C2 and produce a negative output voltage. Capacitor C2 acts as a reservoir for charge and is much larger than the charge pump ca­pacitor C1. After many charge pump cycles, capac­itor C2 will be charged to a voltage that is about two diode drops below 5 V.
Figure 3 illustrates each of the two charge pump se-
2
D
1
C
2
+
C
+
D
1
-
2
V
0
I
C
2
+
R
L
quences. Capacitor C2 acts as a reservoir for charge and is much larger than the charge pump ca­pacitor C1.

The CS552X’s Charge Pump

Figure 4 illustrates a simplified version of t he basic charge pump regulation loop that is inside the A/D converters listed in this application note. The charge pump drive pin (CPD) is driven from a clock (CPCLK) derived from the XIN frequency. In the CS5525 and CS5526 the XIN frequency is used directly. The CS5521/22/23/24/28 devices use a clock that is XIN/2. A regulator loop com­pares the magnitude of the voltage generated on the charge reservoir capacitor to a proportion of the VA+ supply magnitude. The loop is designed to regulate the voltage at NBV to be -[VA+/2.38] V. Note that if the VA+ supply voltage to the chip is above +5 V, the voltage that results out of the charge pump on NBV will be proportionally more negative. When the voltage on the NBV pin reach-
2 AN152REV1
AN152
VA+ = 5 V
+
-
-1x
Load Current
Extra Load
RD C
NBV
L3
D , D = 1N4148
2
1
D = BAT 85
3

Figure 4. ADC Charge Pump Regulation Loop

es the proper magnitude, cycles of the charge pump clock are deleted. The regulation loop maintains the pulse rate out of the CPD pin at an average fre­quency that yields the proper output voltage. The CPD driver output is supplied from the VD+ supply as shown in Figure 4. This can be +5 V or +3 V. The diode charge pump shown in Figure 4 is for a +5 V supply. Diode D3, a Schottky, ensures that the NBV pin will not go more than a diode drop above ground. This ensures proper start-up of the regula­tor loop. Figure 5 illustrates the diode connections needed if VD+ is 3 V.
Figure 6 illustrates a plot of the average freque ncy
VD+ = 5 V
CPCLK
D
DGND
1
CPD
C
1
+
-
Partial of ADC
D
2
2
+
output from CPD when the external load on the output of the charge pump is changed. The charge pump clock (CPCLK) is derived from XIN/2, therefore the maximum frequency which can be output from CPD is equal to XIN/2.
The load current in each of the plots exclude the current used by the on-chip instrumentation ampli­fier (approximately 450 µA for the CS5525/26; 375 µA for the CS5521/23; and 700 µA for the CS5522/24/28).
The plot illustrates the average CPD frequency for two different sizes of charge pump capacitors with the VA+ supply adjusted to 4.5, 5.0 and 5.5 V. The

Figure 5. Charge Pump Drive Diode Circuit For VD+ = 3V

AN152REV1 3
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