LCD COLOUR TV
1
SERVICE MANUAL
CHASSIS NO.:
Please read this manual carefully before service.
L S 0 6 W06
w
Contents
2
Part I: Specifications and Composition ............................................. 3
Part II: Function Introduction of Main IC........................................... 5
Part III: Circuit Schematic Diagram ........................................ 20
Part IV: Part Lists ............................................................... 31
Part V: Factory Setup and notice .......................................... 36
Part VI: PCB Silk Print ......................................................... 37
PartⅠ: Specifications and Composition
Region
Europe
America
Other Re
gion
Region
Europe
America
Australia
Color
PAL B/G、
Video system
200（0-199）
Audio output
220-240V
VCHIP
CCD
NICAM
SCART
Interface
None
VGA Signal Input
Yes YPbPr
High Definition
HDMI
Digital Input
Yes earphone
None
OSD
Language
English
In TV mode, the LCD
TV will automatically power off within 5
3
1. Models for this Chassis：
Model
Number
2. Main Feature：
Radio
Frequency
Signal
system
Sound
system
（or Y/C）
Channels preset
（THD≤7%）
Power source
Teletext
、
Audio
Signal
Auto Off if no signal
input
PAL
7W+7W
100 Pages
None
X 2
minutes and enter into the power energy saving mode if there is
no signal input
PAL,NTSC,NTSC4.43,
SECAM
3. Unit IC Compositions：
4
This chassis LCD TV is Using a high performance and fully integrated chip MST9E89X,，
see this IC frame as below:
Number
Location
Type
Main Function
T
uner
audio output and
picture video
Pin Definition
Description
1 NC NC 2 BT NC 3
VCC +5V power supply
4
SCL IIC bus(clock
) 5 SDA IIC bus(data
) 6 AS ground
7
AFS ground
8 NC NC 9 NC NC 10 NC NC 11
SIF/Out
auto gain control
12 Video/Out
CVBS
signal output
13
VCC（+5V）
+5V power supply
14
Audio/Out
audio signal output
5
PartⅡ: Brief Introduction of Main IC Function
1. Main ICs and Functions：
1 TUNER100 JS-6H2/121
2 N003 MST9E89AL-LF Main chip
3 N008 HY5DU281622FTP-4
4 N002 W25X40VSNIG Flash
5 N005 24LC32A/ 24LC32AI EEPROM
6 N004 TS5V330PW Video Switch
7 N032 R2S15102NP Digital audio amplifier
8 N018,N024 TL062CD OA
，
signal
SDRAM，to storage the picture signal
2. IC And Main component Function Introduction
1. Tuner (JS-6H2/121)
（intermediate frequency of
audio output）
6
FEATURES
MST9E89AL
HDTV Controller with Video Decoder & 10-bit Dual LVDS Transmitter
Preliminary Data Sheet Version 0.4
Ÿ LCD TV controller with PIP/POP display functions
Ÿ Input supports up to SXGA & 1080P
Ÿ Panel supports up to full HD panels (1920x1080)
Ÿ TV decoder with 3-D comb filter
Ÿ Multi-Standard TV sound demodulator and
decoder
Ÿ 10-bit triple-ADC for TV and RGB/YPbPr
Ÿ 10-bit video data processing
Ÿ Integrated DVI/HDCP/HDMI compliant
receiver
Ÿ High-quality dual scaling engines & 3-D video
de-interlacers
Ÿ Full function PIP/PBP/POP
Note
Ÿ MStarACE-3 picture/color processing engine
Ÿ Embedded On-screen display controller (OSD)
engine
Ÿ Built-in MCU supports PWM & GPIO
Ÿ Built-in dual-link 8/10-bit LVDS transmitter
Ÿ 5 Volt tolerant inputs
Ÿ Low EMI and power saving features
Ÿ 256-pin LQFP
n NTSC/PAL/SECAM Video Decoder
Ÿ Supports NTSC M, NTSC-J, NTSC-4.43, PAL
(B,D,G,H,M,N,I,Nc), and SECAM
Ÿ Automatic TV standard detection
Ÿ Motion adaptive 3-D comb filter for NTSC/PAL
Ÿ 8 configurable CVBS & Y/C S-video inputs
Ÿ Supports Teletext level-1.5, WSS, VPS,
Closed-caption, and V-chip
Ÿ Macrovision detection
Ÿ CVBS video output
n Multi-Standard TV Sound Decoder
Ÿ Supports BTSC/NICAM/A2/EIA-J demodulation
and decoding
Ÿ FM stereo & SAP demodulation
Ÿ L/Rx4, mono, and SIF audio input
Ÿ L/R loudspeaker and line outputs
Ÿ Supports sub-woofer output
Ÿ Built-in audio output DAC’s
Ÿ Audio processing for loudspeaker channel,
including volume, balance, mute, tone, EQ,
and virtual stereo/surround
n Digital Audio Interface
Ÿ I2S digital audio input & output
Ÿ S/PDIF digital audio input & output
Ÿ HDMI audio channel processing capability
Ÿ Programmable delay for audio/video
synchronization
n Analog RGB Compliant Input Ports
Ÿ Three analog ports support up to 150MHz
Ÿ Supports PC RGB input up to SXGA@75Hz
Ÿ Fast blanking and function selection switch
support full SCART functions
Ÿ Supports HDTV RGB/YPbPr/YCbCr up to 1080P
Ÿ Supports Composite Sync and SOG
(Sync-on-Green) separator
Ÿ Automatic color calibration
n DVI/HDCP/HDMI Compliant Input Port
Ÿ Operates up to 150 MHz (up to SXGA @75Hz)
Ÿ Single link on-chip DVI 1.0 compliant receiver
Ÿ High-bandwidth Digital Content Protection
(HDCP) 1.1 compliant receiver
Ÿ High Definition Multimedia Interface (HDMI)
1.2 compliant receiver
Ÿ Long-cable tolerant robust receiving
Ÿ Support HDTV up to 1080P
n Auto-Configuration/Auto-Detection
Ÿ Auto input signal format and mode detection
Ÿ Auto-tuning function including phasing,
positioning, offset, gain, and jitter detection
Ÿ Sync Detection for H/V Sync
n Digital Video Input Port
Ÿ One 4:2:2 ITU-R BT.656 8/10-bit digital video
input port
Ÿ One 4:2:2 ITU-R BT.601 16-bit digital video
input port
n High-Performance Scaling Engine
Ÿ Fully Programmable shrink/zoom capabilities
Ÿ Nonlinear video scaling supports various
modes including Panorama
Ÿ Supports keystone correction for projectors
n Video Processing & Conversion
Ÿ 3-D motion adaptive video de-interlacers
Ÿ Edge-oriented adaptive algorithm for smooth
low-angle edges
7
Ÿ Automatic 3:2 pull-down & 2:2 pull-down
detection and recovery
Ÿ PIP/PBP/POP
Note
with programmable size and
location, supports multi-video applications
Ÿ MStar 3rd Generation Advanced Color Engine
(MStarACE-3) automatic picture enhancement
gives:
Ÿ Brilliant and fresh color
Ÿ Intensified contrast and details
Ÿ Vivid skin tone
Ÿ Sharp edge
Ÿ Enhanced depth of field perception
Ÿ Accurate and independent color control
Ÿ sRGB compliance allows end-user to
experience the same colors as viewed on CRTs
and other displays
Ÿ Programmable 12-bit RGB gamma CLUT
Ÿ 3-D video noise reduction
Ÿ Frame rate conversion
n On-Screen OSD Controller
Ÿ 16/256 color palette
Ÿ 256/512 1-bit/pixel font
Ÿ 128/256 4-bit/pixel font
Ÿ Supports texture function
Ÿ Supports 4K attribute/code
Ÿ Horizontal and vertical stretch of OSD menus
Ÿ Pattern generator for production test
Ÿ Supports OSD MUX and alpha blending
capability
Ÿ Supports blinking and scrolling for closed
caption applications
MST9E89AL
HDTV Controller with Video Decoder & 10-bit Dual LVDS Transmitter
Preliminary Data Sheet Version 0.4
n LVDS/TTL Panel Interface
Ÿ Supports 8/10-bit dual link LVDS up to full HD
panel (1920x1080)
Ÿ Supports 8-bit single TTL panel
Ÿ Supports 2 data output formats: Thine & TI
data mappings
Ÿ Compatible with TIA/EIA
Ÿ With 6/8 bits options
Ÿ Reduced swing for LVDS for low EMI
Ÿ Supports flexible spread spectrum frequency
with 360Hz~11.8MHz and up to 25%
modulation
n Integrated Micro Controller
Ÿ Embedded 8032 micro controller
Ÿ Configurable PWM’s and GPIO’s
Ÿ Low-speed ADC inputs for system control
Ÿ SPI bus for external flash
Ÿ Supports external MCU option controlled
through 4-wire double-data-rate direct MCU
bus or 8-bit direct MCU bus
n External Connection/Component
Ÿ 16-bit data bus for external frame buffer (SDR
or DDR DRAM)
Ÿ All system clocks synthesized from a single
external clock
Note:
Availability of 3D video processing in some PIP/POP
combinations is dependent on the selected DRAM speed
and panel resolution.
GENERAL DESCRIPTION
The MST9E89AL is a high performance and fully integrated IC for multi-function LCD monitor/TV with
resolutions up to full HD (1920x1080). It is configured with an integrated triple-ADC/PLL, an integrated
DVI/HDCP/HDMI receiver, a multi-standard TV video and audio decoder, two video de-interlacers, two scaling
engines, the MStarACE-3 color engine, an on-screen display controller, an 8-bit MCU and a built-in output panel
interface. By use of external frame buffer, PIP/POP is provided for multimedia applications Furthermore, 3-D
video decoding and processing are fulfilled for high-quality TV applications. To further reduce system costs,
the MST9E89AL also integrates intelligent power management control capability for green-mode requirements
and spread-spectrum support for EMI management.
8
MST9E89AL
HDTV Controller with Video Decoder & 10-bit Dual LVDS Transmitter
Preliminary Data Sheet Version 0.4
PIN DIAGRAM (MST9E89AL)
AVDD_MPLL
XIN
XOUT
HWRESET
VDDP
DI[14]
DI[13]
DI[12]
DI[11]
RXCKN
RXCKP
GND
RX0N
RX0P
AVDD_DVI
RX1N
RX1P
GND
RX2N
RX2P
AVDD_DVI
REXT
DDCD_DA
DDCD_CK
HSYNC1
VSYNC1
RMID
VCLAMP
REFP
REFM
BIN1P
BIN1M
SOGIN1
GIN1P
GIN1M
RIN1P
RIN1M
BIN0M
BIN0P
GIN0M
GIN0P
SOGIN0
RIN0M
RIN0P
AVDD_ADC
GND
HSYNC0
VSYNC0
VSYNC2
BIN2P
BIN2M
SOGIN2
GIN2P
GIN2M
RIN2P
RIN2M
VCOM2
CVBS3
CVBS2
CVBS1
VCOM1
CVBS0
VCOM0
CVBSOUT
GND
SIF0M
SIF0P
AVDD_SIF
SIF1P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
C1
49
Y1
50
C0
51
Y0
52
53
54
55
56
57
58
59
60
61
62
63
64
DI[15]
256
255
254
253
252
250
251
249
Pin 1
65666768697173
707274
GND
AUL0
SIF1M
AUR0
AUVREF
AUVRANP
AVDD_AU
AUVRADN
DI[9]
DI[10]
DI[8]
244
248
246
247
245
7778818285878991929496
75
76
AUL1
AUL2
AUR1
AUR2
AUCOM
DI[4]
DI[6]
DI[5]
GND
VDDC
DI[7]
VDDP
DI[3]
DI[2]
DI[1]
243
240
239
236
242
241
79808384868890
AUL3
AUR3
AUMONO
AUOUTL3
234
238
237
235
AUOUTL
AUOUTS
AUOUTR
AUOUTL2
AUOUTR3
AUOUTR2
DI[0]
233
NC
Note 1: This pin diagram is based LVDS output. For details, please see the Output Type vs. Pin Configuration at the end of
Pin Description section.
IVSYNC
IHSYNC
IDE
ICLK
GPIOE[0]
232
230
229
231
228
XXXXX
939597
NC
NCNCNCNCNCNCNC
GPIOE[1]
227
GPIOE[2]
226
XXXXXXXXXXX
GPIOE[3]
GND
VDDP
LVB0M
LVB0P
LVB1M
LVB1P
LVB2M
LVB2P
LVBCKM
LVBCKP
LVB3M
LVB3P
LVB4M
LVB4P
GND
VDDP
LVA0M
LVA0P
LVA1M
LVA1P
LVA2M
LVA2P
LVACKM
LVACKP
LVA3M
LVA4P
VDDP
PWM3
VDDC
AVDD_MPLL
LVA3P
LVA4M
225
223
221
218
216
224
222
220
MST9E89AL
98
99
100
101
GND
VDDP
VDDC
DQS[1]
MDATA[15]
214
219
217
215
213
212
211
210
209
207
206
205
208
204
203
202
201
200
198
196
194
199
197
195
193
192
PWM2
191
DIGO[8]
190
DIGO[7]
189
DIGO[6]
188
DIGO[5]
187
DIGO[4]
186
DIGO[3]
DIGO[2]
185
184
DIGO[1]
183
DIGO[0]
182
VDDC
181
GND
180
VDDP
179
IRIN
178
INT
177
DDCA_CK
176
DDCA_DA
175
DDCR_CK
174
DDCR_DA
173
PWM1
172
PWM0
171
SAR3
170
SAR2
169
SAR1
168
SAR0
167
SDO
166
CSZ
165
SDI
164
SCK
163
GND
162
VDDP
161
ALE
160
RDZ
159
WRZ
158
AD[7]
157
AD[6]
156
AD[5]
155
AD[4]
154
AD[3]
153
AD[2]
152
AD[1]
151
AD[0]
150
MADR[11]
149
MADR[10]
148
MADR[9]
147
MADR[8]
146
VDDC
145
GND
144
VDDM
143
MADR[7]
142
MADR[6]
141
MADR[5]
140
MADR[4]
139
MADR[3]
138
MADR[2]
137
MADR[1]
136
MADR[0]
135
WEZ
134
CASZ
133
AVDD_MEMPLL
132
VDDM
131
GND
130
RASZ
129
BADR[0]
103
105
107
102
104
106
108
109
110
111
112
114
115
116
113
117
118
119
120
121
123
125
127
122
124
126
128
GND
MDATA[14]
MDATA[13]
MDATA[12]
GND
VDDM
VDDM
MDATA[9]
MDATA[8]
MDATA[11]
MDATA[10]
VDDM
MDATA[7]
MDATA[6]
MDATA[5]
MDATA[4]
DQM
MCLK
MCLKE
MCLKZ
MVREF
DQS[0]
MDATA[3]
MDATA[2]
MDATA[1]
MDATA[0]
BADR[1]
9
HDTV Controller with Video Decoder & 10-bit Dual LVDS Transmitter
Preliminary Data Sheet Version 0.4
MST9E89AL
PIN DESCRIPTION
MCU Interface
Pin Name Pin Type Function Pin
HWRESET Schmitt Trigger Input
w/ 5V-tolerant
ALE I/O w/ 5V-tolerant MCU Bus ALE, active high /
RDZ I/O w/ 5V-tolerant MCU Bus RDZ, active low /
WRZ I/O w/ 5V-tolerant MCU Bus WDZ, active low /
INT I/O w/ 5V-tolerant MCU Bus Interrupt; 4mA driving strength /
AD[7:0] I/O w/ 5V-tolerant 8051 bus AD[7:0]; 4mA driving strength /
Hardware Reset, active high 253
161
General Purpose Input/Output (GPIOC[10])
160
General Purpose Input/Output (GPIOC[9])
159
General Purpose Input/Output (GPIOC[8])
178
General Purpose Output (GPIOD[12])
158-151
External Flash/RAM Data Bus (FLSHD[7:0]) /
General Purpose Input/Output (GPIOC[7:0])
Analog Interface
Pin Name Pin Type Function Pin
RMID Mid-Scale Voltage Bypass 18
VCLAMP CVBS/YC Mode Clamp Voltage Bypass 19
REFP Internal ADC Top De-coupling Pin 20
REFM Internal ADC Bottom De-coupling Pin 21
REXT Analog Input External Resister 390 ohm to AVDD_DVI 13
HSYNC0 Schmitt Trigger Input
w/ 5V-tolerant
VSYNC0 Schmitt Trigger Input
w/ 5V-tolerant
BIN0M Analog Input Reference Ground for Analog Blue Input from Channel 0 29
BIN0P Analog Input Analog Blue Input from Channel 0 30
GIN0M Analog Input Reference Ground for Analog Green Input from Channel 0 31
GIN0P Analog Input Analog Green Input from Channel 0 32
SOGIN0 Analog Input Sync On Green Input from Channel 0 33
RIN0M Analog Input Reference Ground for Analog Red Input from Channel 0 34
RIN0P Analog Input Analog Red Input from Channel 0 35
HSYNC1 Schmitt Trigger Input
w/ 5V-tolerant
Analog HSYNC Input from Channel 0 /
Function Select Switch Input from Channel 0 (FSSW0)
Analog VSYNC Input from Channel 0 /
Fast Blanking Input from Channel 0 (FBLK0)
Analog HSYNC Input from Channel 1 /
Function Select Switch Input from Channel 1 (FSSW1)
38
39
16
10
Pin Name Pin Type Function Pin
HDTV Controller with Video Decoder & 10-bit Dual LVDS Transmitter
Preliminary Data Sheet Version 0.4
MST9E89AL
VSYNC1 Schmitt Trigger Input
w/ 5V-tolerant
BIN1M Analog Input Reference Ground for Analog Blue Input from Channel 1 23
BIN1P Analog Input Analog Blue Input from Channel 1 22
SOGIN1 Analog Input Sync On Green Input from Channel 1 24
GIN1M Analog Input Reference Ground for Analog Green Input from Channel 1 26
GIN1P Analog Input Analog Green Input from Channel 1 25
RIN1M Analog Input Reference Ground for Analog Red Input from Channel 1 28
RIN1P Analog Input Analog Red Input from Channel 1 27
BIN2M Analog Input Reference Ground for Analog Blue Input from Channel 2 42
BIN2P Analog Input Analog Blue Input from Channel 2 41
VSYNC2 Schmitt Trigger Input
w/ 5V-tolerant
SOGIN2 Analog Input Sync On Green Input from Channel 2 /
GIN2M Analog Input Reference Ground for Analog Green Input from Channel 2 45
GIN2P Analog Input Analog Green Input from Channel 2 44
Analog VSYNC Input from Channel 1 /
Fast Blanking Input from Channel 1 (FBLK1)
Analog VSYNC Input from Channel 2 /
Fast Blanking Input from Channel 2 (FBLK2)
Function Select Switch input from Channel 2 (FSSW2)
17
40
43
RIN2M Analog Input Reference Ground for Analog Red Input from Channel 2 47
RIN2P Analog Input Analog Red Input from Channel 2 46
Analog Video Input/Output Interface
Pin Name Pin Type Function Pin
C1 Analog Input Chroma Video Input 1 /
CVBS Input Channel 7 (CVBS7)
Y1 Analog Input Luma Video Input 1 /
CVBS Input Channel 5 (CVBS5)
C0 Analog Input Chroma Video Input 0 /
CVBS Input Channel 6 (CVBS6)
Y0 Analog Input Luma Video Input 0 /
CVBS Input Channel 4 (CVBS4)
VCOM2 Analog Input YC Video Input Reference Ground 52
VCOM1 Analog Input CVBS1, CVBS2, CVBS3 Video Input Reference Ground 56
VCOM0 Analog Input CVBS0 Video Input Reference Ground 58
CVBS3 Analog Input CVBS (Composite) Video Input Channel 3 53
48
49
50
51
CVBS2 Analog Input CVBS (Composite) Video Input Channel 2 54
CVBS1 Analog Input CVBS (Composite) Video Input Channel 1 55
11
Pin Name Pin Type Function Pin
CVBS0 Analog Input CVBS (Composite) Video Input Channel 0 57
CVBSOUT Analog Output CVBS (Composite) Video Output 59
HDTV Controller with Video Decoder & 10-bit Dual LVDS Transmitter
Preliminary Data Sheet Version 0.4
MST9E89AL
Analog Audio Input/Output Interface
Pin Name Pin Type Function Pin
SIF0M Analog Input Reference Ground for SIF Audio Input Channel 0 61
SIF0P Analog Input SIF Audio Input Channel 0 62
SIF1P Analog Input SIF Audio Input Channel 1 64
SIF1M Analog Input Reference Ground for SIF Audio Input Channel 1 65
AUVRADN Negative Reference Ground for Audio ADC 67
AUVRADP Positive Reference Voltage for Audio ADC 68
AUVREF Reference Voltage for Audio Common Mode 69
AUL0 Analog Input Audio Line Input Left Channel 0 71
AUR0 Analog Input Audio Line Input Right Channel 0 72
AUL1 Analog Input Audio Line Input Left Channel 1 73
AUR1 Analog Input Audio Line Input Right Channel 1 74
AUCOM Analog Input Reference Ground for Audio Line Input 75
AUL2 Analog Input Audio Line Input Left Channel 2 76
AUR2 Analog Input Audio Line Input Right Channel 2 77
AUL3 Analog Input Audio Line Input Left Channel 3 78
AUR3 Analog Input Audio Line Input Right Channel 3 79
AUMONO Analog Input Mono Audio Input 80
AUOUTL3 Analog Output Main Audio Output Left Channel 3 81
AUOUTR3 Analog Output Main Audio Output Right Channel 3 82
AUOUTL2 Analog Output Main Audio Output Left Channel 2 83
AUOUTR2 Analog Output Main Audio Output Right Channel 2 84
AUOUTL Analog Output Main Audio Output Left Channel 85
AUOUTR Analog Output Main Audio Output Right Channel 86
AUOUTS Analog Output Main Audio Sub-Woofer Channel 87
DVI/HDMI Interface
Pin Name Pin Type Function Pin
RX0N Input DVI/HDMI Channel 0 Negative Data Input 4
RX0P Input DVI/HDMI Channel 0 Positive Data Input 5
RX1N Input DVI/HDMI Channel 1 Negative Data Input 7
12
HDTV Controller with Video Decoder & 10-bit Dual LVDS Transmitter
Preliminary Data Sheet Version 0.4
MST9E89AL
Pin Name Pin Type Function Pin
RX1P Input DVI/HDMI Channel 1 Positive Data Input 8
RX2N Input DVI/HDMI Channel 2 Negative Data Input 10
RX2P Input DVI/HDMI Channel 2 Positive Data Input 11
RXCKN Input DVI/HDMI Negative Clock Input 1
RXCKP Input DVI/HDMI Positive Clock Input 2
LVDS Interface
Note 1
Pin Name Pin Type Function Pin
LVA0M Output LVDS A-Link Channel 0 Negative Data Output 208
LVA0P Output LVDS A-Link Channel 0 Positive Data Output 207
LVA1M Output LVDS A-Link Channel 1 Negative Data Output 206
LVA1P Output LVDS A-Link Channel 1 Positive Data Output 205
LVA2M Output LVDS A-Link Channel 2 Negative Data Output 204
LVA2P Output LVDS A-Link Channel 2 Positive Data Output 203
LVA3M Output LVDS A-Link Channel 3 Negative Data Output 200
LVA3P Output LVDS A-Link Channel 3 Positive Data Output 199
LVA4M Output LVDS A-Link Channel 3 Negative Data Output 198
LVA4P Output LVDS A-Link Channel 3 Positive Data Output 197
LVACKM Output LVDS A-Link Negative Clock Output 202
LVACKP Output LVDS A-Link Positive Clock Output 201
LVB0M Output LVDS B-Link Channel 0 Negative Data Output 222
LVB0P Output LVDS B-Link Channel 0 Positive Data Output 221
LVB1M Output LVDS B-Link Channel 1 Negative Data Output 220
LVB1P Output LVDS B-Link Channel 1 Positive Data Output 219
LVB2M Output LVDS B-Link Channel 2 Negative Data Output 218
LVB2P Output LVDS B-Link Channel 2 Positive Data Output 217
LVB3M Output LVDS B-Link Channel 3 Negative Data Output 214
LVB3P Output LVDS B-Link Channel 3 Positive Data Output 213
LVB4M Output LVDS B-Link Channel 3 Negative Data Output 212
LVB4P Output LVDS B-Link Channel 3 Positive Data Output 211
LVBCKM Output LVDS B-Link Negative Clock Output 216
LVBCKP Output LVDS B-Link Positive Clock Output 215
Note 1: Please see the Output Type vs. Pin Configuration at the end of Pin Description section.
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