Casio MP-2000 Service Manual

SERVICE MANUAL

(without price)

ELECTRONIC CASH REGISTER

MP-2000 (EX-970)

Nov. 1999

CONTENTS

MP-2000 Page

1. Explanation of Product ................................................................................................... 2

1-1. System Overview ................................................................................................... 2

1-2. Unpacking ................................................................................................... 3

1-3. Installation ................................................................................................... 4

1-4. Specification (MP-2000 CPU module)............................................................................. 6

1-5. I/O Outlet ................................................................................................... 7

2. Model List ................................................................................................... 8

3. Disassembly ................................................................................................... 8

4. System Installation ..................................................................................................11

5.Circut Explanation ................................................................................................. 28

5-1. Block diagram ................................................................................................. 28

5-2. Jumper setting ................................................................................................. 29

6. Diagnostic Operation ................................................................................................. 33

6-1. Diagnostic softwares ................................................................................................. 33

6-2. Customer display ................................................................................................. 33

6-3. Drawer test ................................................................................................. 37

7. Trouble Shooting ................................................................................................. 38

8. Data sheet ................................................................................................. 40

8-1. 65550 (HiQV32TM) ................................................................................................. 41

8-2. M5113: Enhanced Super I/O Controller with Plan & Play.............................................. 55

8-3. uM9008: ISA/Plug & Play Super Ethernet Controller .................................................... 61

8-4. VT82580 ................................................................................................. 65

8-5. Pentium Processor ................................................................................................. 81

8-6. MN04326TAE SIMM ................................................................................................. 83

8-7. Power supply ................................................................................................. 84

9. Circuit Diagram ................................................................................................. 85

10. Parts list ............................................................................................... 106

— 1 —

1. Explanation of Product

1-1. System Overview

The MP-2000 series are Casio’s new PC based POS system. The MP-2000 equip 9.4 inch LCD display
and 84 soft keyboard.

MP-2000 (CPU module)

COVER-2 (optional)

HD access LED Power LED

MP-2040KY (84 keys Keyboard module)

Accessories

1. FDD External cable 1 pc

2. Utility (Floppy disk) 4 pcs

3. User’s manual 1 pc

with accessories

(Separately provided)

— 2 —

MP-2060DP

LCD display module

LCD – CPU interface cable

LCD power switch
Contrast control
Brightness control

Bios chip
(Installed in the MP-2000)

Inner interface cable/LCD control board
(installed in the MP-2000) with screws

(Separately provided)

1-2. Unpacking

The MP-2000 along with its accessories are packed in carton boxes. Make sure that all of the items listed
in previous page are present. After unpacking the cartons, place the system on a raised surface and
carefully inspect the system for any damage that might have occurred during shipment. If there are dam­aged or missing parts, contact your dealer immediately.

The MP-2040KY and the MP-2060DP are separate modules and packed along with accessories in each
carton boxes. Please refer user’s manual for each module packed in each carton box in detail.

— 3 —

1-3. Installation

For Installation for LCD display module (MODEL MP-2060DP), it is necessary to instal the BIOS chip
and LCD control board to the CPU module as showing the following steps.

1. Open the upper cover of CPU module. 2. Release the 4 screws for the insulation
sheet and the Alminum separator.

3. Fix the connector cable for LCD display. 4. Mount the LCD control board and connect the
LCD display cable.

— 4 —

5. Mount the insullation sheet and the Alminum 6. Mount the LCD control board and connect the

separator by 4 screws. LCD display cable.

Replace to New Bios chip.

7. Close the upper cover to the CPU module.

NOTES:

1. The MP-2000 CPU module do not equip any operating system. An operating system must be loaded
first before installing any software into the MP-2000 CPU module.

2. Be sure to ground yourself to keep from any static charge when you install the internal components.
Use a grounding wrist strap and place all electronic components in any static-shielded devices. Most
electronic components are sensitive to the static electric charge.

3. Disconnect the power cord from the MP-2000 before any installation. Make sure both the system and
the external devices are turned off and the MP-2000 is properly grounded. The sudden surge of power
could ruin any sensitive components.

4. The brightness of the LCD panel display will decrease with use. However, hours of use will vary de­pending on the application environment.

— 5 —

1-4. Specification (MP-2000 CPU module)

Processor; INTEL Pentium MMX 233MHz
Memory: 2 x 16MB SIMM(expandible to 128MB)

512KB cache

Expansion slots: 1 x 16 bit ISA, 2 x PCI
RS-232C ports: 4 external ports (with power 5V, 12V, 24V)

Parallel ports: 1
External Floppy disk: 1 port
Hard disk: 1 enhanced IDE
Operator display: 2MB video memory

External Mouse: 1 X PS/2 mouse port
External Keyboard: 1 x PS/2 keyboard port
Cash drawers: 2 ports with individual sensing
Software utilities: Ethernet setup /VGA
Communications: Ethernet control 10base-T

IEEE802.3 Ethernet standard
Operation system: Supports Windows 95,Windows NT 4.00 and MS-DOS V6.22
Power supply: 100VAC / 240VAC
Environmental

temperature: 5°C to 35°C
Dimensions

(main body size): 310mm(W) x 99mm(H) X 305mm(D)
Net weight: 4.2kg (CPU module)

Note:

1) Some functions or features that are newly implemented in the Windows98 can not be sup­ported by the MP-2000 system, for instance, Dual Display function, ACPI green function and so
on.

2) The system Bios that is installed in the standard MP-2000 does not support the MP-2060DP
LCD display. Please change the chip that is packed in the MP-2060DP in case to use the MP­2060DP together with the MP-2000.

— 6 —

1-5. I/O Outlet

< Bottom Panel >

165432

FDD MOUSE K/B

LCD

DRW 2 DRW 1

R

N COM 4 COM 3 COM 2 COM 1V

P

7890AB

1 External FDD 7 Parallel port
2 2 x Cash drawers 8 4 x COM ports( COM 1, 2, 3 and 4 )

G

AN E T

3 External PS/2 mouse 9 VGA port <*1>
4 LCD interface port (Not installed) 0 Ethernet 10 base-T
5 External PS/2 Keyboard A AC inlet
6 Expansion outlet B AC Power switch

NOTE *1: Automatic frequency detective type CRT only.

Do not connect telephone line to cash drawer ports or Ethernet connector.

Telefon Linie Stromkreis nicht mit “Cash Drawer Ports” oder “Ethernet Connection” verbinden.

< LCD Unit Rear Panel >

1 4
2
3

1 LCD power switch
2 Contrast control
3 Brightness control
4 PC interface port

— 7 —

2. Model List

No. Model Name Description Note
1 MP-2000 CPU module For USA, Canada, UK, and Germany
2 MP-2000S CPU module For countries other than above
3 MP-2040KY Keyboard 84 Key module
4 MP-2041KY Large Keyboard Large Key module
5 MP-2060DP LCD module Mono-LCD unit
6 COVER-2 Cable Cover Cable cover for CPU module
7 QT-7060D Customer Display
8 QT-7062D Customer Display With Pole (20cm)
9 QT-7063D Customer Display With Stand
10 DL-3615 Drawer L size (6coins/5bills)
11 DL-2765 Drawer M size (8coins/4bills)
12 DL-2909 Drawer M size (8coins/5bills)
13 UP-350 1ST T ermal printer Option Printer
14 SA-3075 2.5ST Printer Option Printer

3. Disassembly

To open the case

1. Place the machine up side down.

2. Release the 2 screws of the cable cover.

Cable cover (COVER-2) Cable cover is option item.

3. Then, slide the cable cover to the right side to remove it.

Slide the cable cover
(COVER-2).

Note: Cable cover is option item.

— 8 —

4. Release the screw. Then, remove the upper cover from front side.

5. Release the 2 screws of the Riser card. Then, remove the Riser card
from the mother board.

Release 2 screws.

6. Release the 4 screws of the Aluminum separator. Then, remove the
insulation sheet and Aluminum separator.

Release 4 screws.

— 9 —

7. Release the 4 screws of the LCD control board (Option item).
Then, remove the LCD control board.

Release 4 screws.

LCD control board is option item.

8. Release the 4 screws of the HDD fixing plate. Then, remove the
HDD fixing plate with HDD.

Release 4 screws.

9. Release the 9 screws of the Mother board. Then, remove the
Mother board.

Note: The view of FAN
may be changed.

1 2

7

3 4

— 10 —

5

6

8

9

4. System Installation

This Chapter describes the installation and the cable connection to the system connectors.
Sections of this chapter includes

* CPU
* DRAM
* HDD
* 4 X Serial Ports
* Parallel Port
* VGA
* Ethernet
* Drawer interface
* Keyboard
* PS/2Mouse
* External FDD
* Expansion Slot

* System O/S and Software Installation
The MP-2000 has a Pentium little board with a free PCI/ISA slot inside. It already builds in a Pentium CPU,
16MB of DRAM and a 2.5" HDD. These are all standard and the system is ready to play. Variety of the I/O
ports located at the back side of the chassis are available for customers to connect external peripheral devices,
such as a monitor , serial devices, parallel printer.. .etc. However, the interface specification of the peripherals are
vary depend on the manufactures and may not applicable to the MP-2000 POS system. Please confirm list of
the peripheral devices which are test by Casio as the MP-2000 POS system before you choose the peripherals.
Note: Since all specification and quality of the system are assured by Casio as the MP-2000 POS system, any
local modification of the CPU, DRAM, HDD, jumper setting on the motherboard or system components by cus­tomer will not be applicable for Casio’s guarantee or warranty unless modification are assured by Casio.

CPU

The MP-2000 system already builds in a designated CPU in the socked on the motherboard.

MP-2000: Intel MMX Pentium 233MHz on the motherboard SBC8352

To maintain the CPU, follow the instructions below.

1. To remove the existing CPU requires the use of a chip removing tool.

2. Locate pin 1 at the corner of the CPU socket and align the CPU’s pin 1. Then place the CPU in the
socket. Check the notch on the corner of the CPU and the socket are properly aligned.

3. When a CPU is installed, the jumber settings on the motherboard are properly installed as factory
default for the MP-2000.

DRAM

The MP-2000 provides 2 x 72-pin SIMM sockets and 32 (16x2 ) MB of DRAM as standard. Maximum system
memory up to 128MB, respectively. To install the memory module, follow the instructions below and check the list
of DRAM memories tested as MP-2000.

1. Insert the memory module from the opening of the metal front compartment.

2. The memory module can only fit into the socket one way. Holding the memory module with the
notch on the upper right corner, then insert the memory module at a 45 degree angle and push the

module upright until it clicks into place.
The system is able to auto detect the new memory size automatically and it is not necessary to change the
system configuration after installation.

— 11 —

HDD

The standard MP-2000 already builds in a 2.5" hard disk drive. To maintain the HDD, follow the installation
instructions below and check the list of HDD tested as the MP-2000.

1. Take out the screws, the IDE cable and remove the HDD.

2. Reinstall the new HDD on the mounting. The four rubber stands act as cushions to lessen the vibration

which usually causes damage to a mechanical device like a HDD.

3. Connect the IDE cable to the HDD. Match pin 1 of the HDD and the pin 1 of the cable.

Serial Ports

MP-2000 has four onboard serial ports. For the MP-2000, COM1 and COM3 and COM4 are RS-232,and COM2
are RS-232/422/485, selected by jumpers. Each serial port is with +5V/+12V/24V power capabilities on both pin
1 and pin 9, ready to accommodate a wide array of serial devices. COM1 to COM4 are all D-SUB 9-pin connec­tors. In this case the COM2 for the MP-2000 is to set to RS-422/485, the related jumpers have to be set correctly.

The RS-485 pin assignment is listed as follows;

Pin Description Pin Description

1 TXD- 5 X
2 TXD+ 6 X
3 RXD+ 7 X
4 RXD- 8 X

Parallel Port

The printer interface is a 25-pin D-SUB connector located on the bottom side. To connect any parallel device, just
plug in the device connector to the 25pin D-SUB. There are variety of parallel port peripherals in the market and
interface specification vary depending on the peripherals. The peripherals which have been confirmed with the
MP-2000 terminals are listed in the Appendix and others may not be supported. Please confirm connectivity of
each peripherals before install to the customer site.

VGA

The MP-2000 has an analog RGB interface connector installed on the bottom side. It is able to connect to an
expansion CRT monitor, and the system can disply on both the LCD display and the CRT simultaneously. How­ever, the BIOS mounted as standard MP-2000 supports CRT display only. Resolution and color can be con­trolled by video system setup to meet the connected CRT. In case to use the LCD display MP-2060D, change
the BIOS packed with the MP-2060DP. It can support both LCD and CRT display, however, resolution is fixed
VGA 640 x 480 only and can not be controlled by user due to specification of the MP-2060DP LCD display.
Also, since horizontal frequency for the CRT display is designed as 34KHz, an automatic horizontal frequency
detective type CRT is only approved for the MP-2000 system.

— 12 —

Ethernet

The MP-2000 provide an NE2000 compatible Ethernet (RJ-45) interface. For network connection, just plug in
one end of cable of a 10-Base-T hub to the standard Ethernet phone jack. The pin assignment of the RJ-45 is
listed below;

RJ-45 Connector Pin Assignment

Pin Description

1 Tx+ (Data transmission positive)
2 Tx- (Data transmission negative)
3 Rx+(Data reception positive)
6 Rx- (Data reception negative)

others Not use

Cash Drawer

The MP-2000 provides two Cash Drawer interface. Cash Drawers are assigned as one of I/O in this system and
controlled by the Digital I/O port on the motherboard (SBC8352).
The pin assignment for the Cash Drawer connector is as follows.

Cash Drawer connector Pin Assignment

Pin Description

FG

1

Out Switch

2

Read Switch

3

+24V

4

NC

5

6 GND

1 2 3 4 5 6

Cash Drawer control Software Programming

The Cash Drawer is assigned as one of I/O device in the system. The I/O address assigned for the Cash Drawers
220h. The MP-2000 can support two Cash Drawers and each Cash Drawers can be controlled respectively by
output or input data to this I/O address. The open/close status of drawers also can be read by reading this I/O
address. Following is software programming method for Casio standard Cash Drawer model DL-2765, DL-2909,
and DL-3615.

I/O Address Bit Output Data to Open Input data for status
Drawer A 220 0 01h FEh (open)
Drawer B 220 1 02h FDh (open)

Example program; < Drawer A open >

Out 220h, 01h : Drawer A open signal on

< 100 ms timer > : Open signal on 100 ms

Out 220h,00h : Drawer open signal off

— 13 —

Example program; < Read Drawer open status >

Input 220h : Read Drawer open status

If data is FFh: Drawer A , B closed
If data is FEh: Drawer A is open, Drawer B is closed.
If data is FDh: Drawer A is closed, Drawer B is open.
If data is FCh: Drawer A is open, Drawer B is open.

Note: 1) Drawer open signal on time is 100 ms.

2) Do not open Drawer A and B at same time ( Output data 03 ). If two drawers were
open at same time, it may cause damage on system power supply.

Keyboard interface

The MP-2000 provides a standard PS/2 keyboard connector located at the interface panel.
Connect the POS keyboard module MP-2040KY to this port.

PS/2 Mouse interface

The MP-2000 has one PS/2 mouse connector located at the right side. A simple plug-in will make the connec­tion.

External FDD

The MP-2000 does not build in any floppy disk drive into the main system. Rather, it provides a FDD interface
located at the side panel. An external FDD cable is provided to connect a standard 3.5" FDD to the system for
system O/S and application software installation. Its pin position and pin assignment is listed as follows;

External FDD Pin Assignment

P 1 GND P 14 GND P 27 MOTE1­P 2 GND P 15 GND P 28 DIR­P 3 GND P 16 GND P 29 STEP­P 4 GND P 17 GND P 30 WDATA­P 5 GND P 18 GND P 31 WGATE­P 6 GND P 19 +12V P 32 TRKO­P 7 GND P 20 REDWC- P 33 WPT­P 8 GND P 21 NC P 34 RDATA-

P 9 GND P 22 NC P 35 SIDE1­P 10 GND P 23 INDEX- P 36 DSKCHG­P 11 GND P 24 MOTE0- P 37 Vcc
P 12 GND P 25 DRVS1­P 13 GND P 26 DRVS0-

— 14 —

Expansion Slot

The MP-2000 provides a free PCI/ISA + PCI expansion slot to accommodate either an ISA or PCI device at a
given time. The expansion card can be plugged into the riser card which is plugged in the onboard PCI/ISA slot
as standard. Due to the compact space design, a half-size expansion card can be adapted. To use the ISA or PCI
expansion, follow the installation instructions below;

1. Unscrew the metal slip located inside the expansion outlet.

2. Plug either an ISA or PCI card into the ISA or PCI slot on the riser card and fix the expansion card by screwing
it to the metal front compartment. All the connectors of the expansion card will come out from the expansion
outlet on the bottom side of the chassis for further cable connection.

System O/S and Software Installation

The MP-2000 is not equipped with any operating system. It builds in a 2.5" HDD as memory storage device. As
the device is built in the system chassis, to load any O/S or application software into the computer, an external
device is needed to act as a bridge. There are three major ways to load software into the system.

1. Use an external FDD: Attach a 3.5" FDD to the external FDD port via the provided external FDD cable.

The 37-pin FDD connector is to be plugged in to the system FDD connector; the
34-pin standard 3.5" FDD signal connector and the 4-pin FDD power connector
are to connect to the standard 3.5" FDD. Then, configure the system BIOS setup
and insert a 3.5" disk containing necessary software and start the installation.

2. Use ethernet: After install the O/S and necessary network utilities, download application

software from the network.

3. Use External CD-ROM/HDD: To use an external CD-ROM or HDD for software installation, an optional P-IDE

device is needed. The P-IDE device is a converter to convert the parallel port to
the IDE interface.

— 15 —

BIOS Setup

AMI BIOS Setup

Starting AMI BIOS Setup

As POST executes, the following appears:

Hit <DEL> if you want to run SETUP

Press <Del> to run AMI BIOS Setup.

AMI BIOS Setup Main Menu

When you enter the AMI BIOS Setup Utility, the main menu will appear on the screen as follows. Use the arrow
keys to move among the items and press <Enter> to accept and enter into the sub-menu.

— 16 —

Setup
The AMI BIOS Setup options described in this section are selected by choosing the appropriate high-level icon
from the AMI BIOS Setup main menu selection screen. Default setting for the QT-7100 is described in < > next to
each option. ( i.e.

<AUTO>

)

[Standard CMOS Setup]

When entering this item, the following screen will be shown;

Date, Day and Time Configuration

Select the Standard option. Select the Date and Time icon. The current values for each category are displayed.
Enter new values through the keyboard.

Pri Master
Pri Slave

< AUTO >

< AUTO >

Select one of these hard disk drive icons to configure the drive named in the option. A scrollable screen that lists
all valid disk drive types is displayed. Select the correct type and press <Enter>. The AMIBIOS is able to detect
the IDE drive parameters automatically and report them on this screen. To enable this auto-detect function, just
select the drive type

Floppy Drive A
Floppy Drive B

Auto

.

< Not Installed >
< Not Installed >

Move the cursor to these fields via and select the floppy type. The settings are 360KB 5.25 inch, 1.2 MB 5.25
inch, 720KB 3.5 inch, 1.44 MB 3.5 inch, or 2.88 MB 3.5 inch.

— 17 —

[Advanced CMOS Setup]

Boot Device

This option sets the sequence of boot drives either floppy drive A or hard disk drive C or CDROM that AMI BIOS
attempts to boot from after POST completes.

Floppy Drive Swap

This option enables the floppy swap function. The setting is

Floppy Drive Seek

This option enables AMI BIOS seek on floppy drive A before booting the system. The settings is

Disabled

System Keyboard

This option permits to configure workstations without keyboards. The setting is

Primary Display

Select this icon to configure the type of monitor attached to the system. The setting is

< 1st: FLOPPY, 2nd:IDE-0, 3rd:CDROM, 4th:Disabled >

< Disabled >

< Disabled >

.

< Absent >

< VGA/EGA >

Enable

or

Disable

.

Absent or Present.

Monochrome, Color 40x25,

Enabled

or

Color 80x25, VGA/PGA/EGA, or Not Installed.

Parity Check

This option enables or disables NMI. If the watchdog function selects NMI trigger, this option must be enabled.

< Disabled >

— 18 —

Wait for <F1> If Any Error

< Enable >

AMI BIOS POST runs system diagnostic tests that can generate a message followed by

Press <F1> to continue
Enable : AMI BIOS waits for the user to press <F1> before continuing.
Disabled : AMI BIOS continues the boot process without waiting for <F1> to be pressed.

External Cache

< Enabled >

If the onboard cache memory is to be enabled, there are two setting options,
it is set to

Disabled

.

[Advanced Chipset Setup]

Write Thru

or

Write Back

; otherwise,

Memory Parity Check

This option enables or disables parity error checking for system RAM. The setting is
parity is checked ) or

Disabled

.

Watchdog Time out Select

The option selects the watchdog function on time-out trigger set, the settings is 0.5 sec, 1 sec, 5 sec, 10 sec, 20
sec, 50 sec, 100 sec, 150 sec, 200 sec, 250 sec, 300 sec, 350 sec, 400 sec, 450 sec, 500 sec, or 1000 sec.

— 19 —

Enabled

( all system RAM

[Peripheral Setup]

Onboard FDC

This option enables the use of the built-in floppy drive controller. The setting is

OnBoard Serial Port 1 <3F8h, IRQ4>

NOTE: Do not change this setting, since COM1 is assigned for the touch screen. It may cause system
problem.

OnBoard Serial Port 2

IRQ3 is used for the second serial port COM2. This option selects the onboard serial port 2 Address set. The
setting is

OnBoard Serial Port 3

This option selects the serial port 3. The setting is

OnBoard Serial Port 4

This option selects the serial port 4. The setting is

OnBoard Parallel Port

This option selects onboard parallel port. The settings is

Parallel Port Mode

This option specifies the parallel port Mode. The setting is

The setting is

Auto, Disabled, 3F8h IRQ4

< 2F8h, IRQ3 >

Auto, Disabled, 2F8h IRQ3

< 3E8h, IRQ10 >

< 2E8h, IRQ11 >

< 378h >

< Normal >

or 2E

8h IRQ3.

, or

3E8h IRQ4.

Auto, Disabled, 3E8h IRQ10

Auto, Disabled, 2F8h IRQ11

Auto, 3BCh, 378h, 278h

Normal, Di-Dir, EPP

Auto, Enabled

or 3F

8h IRQ10.

or 2E

8h IRQ11

or

Disabled

or

ECP.

or

Disabled

.

.

— 20 —

PCI/Plug and Play Setup

POWER MANAGEMENT Setup

— 21 —

[Watchdog Function]

The MP-2000 features a system protective device, watchdog timer which can generate a CPU reset when the
system comes to a halt or failure. This function is to ensure the system’ s reliability during unattended operation.
The trigger sources for the watchdog contain both temperature over range and system failure. The system failure
may be caused by thunder, power glitch, radio interference, software bug or whatever reason.

To activate the watchdog timer, some program code similar to the following code has to be written to the system
running loops:

:

Loop:

read (0x121) ; enable and trigger WDT

: ; interval time between triggers
if (END) GOTO END ; must be smaller than time-out
GOTO Loop ; period

END:

read (0x120) ; disable WDT

:

The time-out period ranges from 0.5 to 1000 seconds. If special settings for temperature or time-out are needed,
please refer to the utility diskette.

How to Use Watchdog Function

The user can read I/O Port 121H to enable Watchdog or disable it by reading I/O Port 120H.

Reset Watchdog - Read I/O Port 121H
Time_A - Read I/O Port 121K
Time_B - Read I/O Port 121H

Disable Watchdog - Read I/O Port 120H

** Time_B Time_A<Time Out Setting **

In system Run_Time, you must still have to read I/O Port 121H to reset the Watchdog timer.

If the system fails, the TSR should be stopped and Watchdog reset action will be activated.

— 22 —

LCD display

LCD display (MP-2060) Specification

Model MP-2060DP

Display T ype MonoLCDdisplay

Panel Size 9.4"

Max Resolution 640x480

Colors 32 Gray scale

S/W Drivers

Before you begin the driver software installation, be sure to make backup copies of the Display Driver Diskettes.
Make sure you know the version of the application for wich you are installing drivers. Your Display Driver Dis­kettes contain drivers for several versions certain applications. For your driver to operate properly, you must
install the driver for your version of the application program.

Windows NT

These drivers are designed to work with Microsoft Windows NT.

Driver installation

Step 1

: Install Windows NT as you normally would do for a VGA display. Run Windows NT Control Panel from

the Main Group. Choose the Display

Display Type

the Select Device dialog box.

. Click on

Change

from the Adapter Type in the Display Type dialog box. Click on

option

. In the Display Settings dialog box, click on

Change

Other

in

Step 2

. Place the

Chips and Technologies Video Controller

STALL

and restarted.

Step 3

: Upon restart, at the Invalid Display Selection message, click on OK and select the desired display

settings from the Display Settings dialog box. The system must be shut down and restarted for the new
settings to take effect.

Windows NT Display Driver Diskette

to install the selected driver. Once the installation is complete, the system must be shut down

in drive A. Press <ENTER> and the name of the driver,

will appear highlighted in the Models list box. Click on

IN-

— 23 —

VGA Software Utilities
DOS Utility

These utility programs are designed to work with MS-DOS.

MODETEST

MODETEST is a DOS based diagnostic tool to set and display information for each video mode. To execute the
MODETEST utility program, type the following command:

MODETEST
All the VGA modes will be sequentially displayed by pressing <ENTER>. To display a specific mode, type the
following optional field after the command, where “xx” defines the desired VGA mode:

MODETEST [-m xx]
Press any key (expect <Esc>) to display the next screen. This will cycle through each video mode and display
the following information:

Mode number

Resolution (in characters if text mode; in pixels if graphics mode)

Number of available colors

Vertical scanning frequency

Horizontal scanning frequency

Dot Clock (pixel) frequency
This utility will also display a set of color bars to show the range of colors and put a border of changing colors
around the screen.
To execute the HELP file, type the following command:

MODETEST -?
Press <Esc> at any time to exit the program and return to DOS.

Windows 95 Utility

These utility programs are designed to work with Microsoft Windows 95.

CHIPSDSP.DLL

CHIPSDSP.DLL is located on the CHIPS Windows 95 driver disk. This file is a Windows 95 based utility for
selecting display type and refresh rate. It is a Display Properties Refresh window that is automatically installed
when installing CHIPS Windows 95 display drivers. The Display icon is in the Control Panel group. To invoke the
Display icon, simply click on the Start button, go to Settings, click on Control Panel and then double click on the
Display icon. Click on the property sheet with the heading Refresh.

How to use the utility

DISPLAY DEVICE allows you to select the display type from the following:

CRT only <ALT C>
LCD (LCD display) only <ALT L>
Both CRT and LCD (LCD display) <ALT B>

REFRESH RATE allows you to select the refresh rate from the following:

Interlaced
56 Hz
60 Hz
70 Hz
72 Hz

— 24 —

75 Hz
85 Hz
NOTE: 1. The refresh rates that are supported by the selected monitor are the only refresh rates

that will show and be selectable.

2. The above Refresh Rates may not be supported by all CHIPS products.

WINDOWS DEFAULT allows you to return to the default refresh rate setting for the selected monitor in Windows

95.

Setup Programs

The following setup programs were developed for the installation of CHIPS Display Drivers through Windows or
DOS. The driver files have been compressed wit the Microsoft Corporation (“MS”) COMPRESS.EXE utility.
Please note that we do not support driver installation through the MS Windows Setup due to the limitations of
their COMPRESS.EXE and EXPAND.EXE utilities.
The setup programs contain video chip detection and video memory detection at the time of installation. These
programs will automatically detect the CHIPS VGA controller and the amount of video memory present in the
system, then read the appropriate script file, and then install the appropriate drives. For example, when setup
identifies the VGA controller and 512Kb video memory, the setup program will read the script files identified by
the characters “5K”, and then install only the drivers that function with 512Kb of video memory.

English Environment

WINSETUP.EXE

WINSETUP.EXE is a setup program that allows the user to install driver files through Windows. This setup
program will expand driver files, and then install the drivers in the appropriate sub-directories. To install the
drivers, go to the Run command from the File menu in the Program Manager, and type A:\WINSETUP.

W*.INF

The W*.INF files are the script files for installation of the display drivers using WINSETUP.EXE. These files are
located in the root directory of Disk 3 and are required to be in the same directory as WINSETUP.EXE.
The W*.INF files may be edited by the OEM to tailor the WINSETUP.EXE program to install specific drivers.
These files may be modified by using any ASCII text editor. For example, if the OEM does not wish to install the
24bpp driver, W*.INF must be modified as follows:

Enter the W*.INF file into an ASCII text editor.
Go to the [Files] section of the W*.INF file.
Delete the line that contains the name of the file for the 24bpp driver.
Save the file and exit the text editor .

The W*.INF files may also be edited to install the drivers to another destination sub-directory. The default
destination sub-directory is \WINDOWS\SYSTEM. To change the destination sub-directory, replace “SYSTEM”
in the [Files] section of W*.INF with the destination sub-directory of your choice.
NOTE: Modifying other fields in the W*.INF file may cause WINSETUP .EXE to not function properly.

SETUP.EXE

SETUP.EXE is a setup program that allows the user to install driver files in DOS. This setup program will expand
driver files, and then install the drivers in the appropriate sub-directories. To install the drivers, type “SETUP” at
the DOS prompt.

— 25 —

[Ethernet]

Introduction

The MP-2000 is equipped with an NE2000 compatible high performance Ethernet interface.

Setup and Diagnostic Test

Following software are provided in the floppy disk (Disk 4) for setup and test the Ethernet system.

The Setup Program

The MP-2000’s Ethernet can be either set to PnP or non-PnP modes. In non-PnP mode, the configuration is
accompanied by the execution of the setup program, “SETUP.EXE”. After passed a series of tests, the following
screen will appear:

UM9008 PnP Ethernet Controller Configuration & Diagnostic Program

Copyright (c) reserved by UMC, 1996. V1.03 (03/2196)

Install drivers
Configuration
Diagnostics Program Find UM9008 PnP NIC’s Status
AutoDetect
Accept & Exit CARD 1(48 54 33 01 34 C1): IOBase-300, IRQ-2

Test Result ....................... Success

To change mode or configurations, please follow the instructions on the screen.

Install drivers

This menu is not available for the MP-2000. Please refer Installing Network Driver in this manual.

Configuration

Highlight

Configuration”

“Configuration”

and

“Quit”

option and press <ENTER>, a list of options including

will appear.

“Hardware configuration”

,

“Modify

Hardware configuration

The IRQ and I/O Base Address will appear after selecting this option. You can view the settings
and modify select the IRQ and I/O Base Address by “

Modify configuration

”.

Modify configuration

Highlight this option, and press <ENTER>, you can configure the settings of the onboard Ethernet.
A range of options is offered for IRQ, I/O and Boot ROM settings.

Diagnostic Test

The Diagnostic Test is a sub-function of SETUP.EXE. This diagnostic program tests all functions of MP-2000
Ethernet module and verifies its communication with another system on the network.

— 26 —

Automatic Detection

This function is used to change different modes, including Jumper-less, Automatic detect and PnP modes and
automatically configure the onboard Ethernet with available IRQ and I/O settings. To modify these settings, the
“Modify configuration” has to be selected.

Installing Network Driver

( Windows 95, Windows 98 or W indows NT)

1) select Add new hardware.

2) select net work card (adapter).
Recommended setup:

Manufacture : Novell/Anthem
Model : NE2000 compatible

3) select Novell NE2000 compatible Driver.

4) restart Windows 95, Windows 98 or Windows NT.

(MS-DOS)

1) Install IPX.COM and NETX.EXE. 2 files from Novell Server.

2) Run IPX.COM and NETX.EXE to connect Server.

— 27 —

5. Circuit Explanation
5-1. Block diagram

(1) MP-2000 System Diagram

To LCD unit

LCD control PCB (Option Item)

(2) MP-2000 system block diagram

COM1: Touch Screen

— 28 —

5-2. Jumper setting
(1) Mother Board for MP-2000

The default setting of the mother board for MP-2000 is as follows:

JP No. Pin setting Check
JP1 1-3
JP2 2-3
JP3 OPEN
JP5 OPEN
JP6 OPEN
JP7 OPEN
JP8 1-3,2-4
JP9 3-5,4-6
JP10 OPEN
JP1 1 1-2
JP12 3-4
JP13 1-2
JP14 1-2
JP15 7-9,8-10
JP16 3-5,4-6

9-11,10-12
JP17 7-9,8-10
JP18 7-9,8-10
JP19 5-6
JP20 7-9,8-10
JP22 1-2,

7-8

JP1

2 4 6 8 10

1 3 5 7 9

JP10

1 2

JP16

2 4 6 8 10 12

1 3 5 7 9 11

JP6

JP11

1 2 3

JP1 JP3

JP22

JP2

1 2 3

JP12

3
1

JP2

JP19

JP5

2 4 6

1 3 5

JP5

4
2

1 2 3

JP13

1 2

JP8,9

JP11

JP10

JP6

JP14

JP22

1
3
5
7

JP15

JP12,13

2 4 6

1 3 5

2 4 6 8

1 3 5 7

JP16

2
4
6
8

JP14

JP7
JP17
JP18

JP8

1
3
5

JP15,17,18,20

2 4 6 8 10

1 3 5 7 9

JP20

JP19

JP9

1

2
4
6

2

3

4

5

6

(2) Multi I/O Board (MP-2000)

The default setting of the Multi I/O Board for MP-2000 are as follows:

Multi I/O Board Jumper Setting (Default)

JP1,3

JP No. Pin setting Check
JP1 1-2
JP3 1-2
JP4 3-5,4-6
JP5 3-5,4-6
JP6 3-5,4-6

JP1 JP3

1
2
3

The top of view for Multi I/O board

JP7 3-5,4-6

(3) Riser Card Jumper switch (MP-2000)

The default setting of the Riser Card for MP-2000 are as follows:

PCI1

PCI2

JP1

JP2

JP7

JP1: 3-4

JP2: 1-2

JP4,5,6,7

2
4
6

JP4

JP6 JP5

2 4 6 8 10 12 14 16 18 20

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

1 3 5 7 9 11 13 15 17 19

1
3
5

— 29 —

5-2-1. Jumper Settings

The SBC8352 is configured to match the needs of your application by proper jumper settings.
The following tables show the specification of the jumper settings. < * : Default / X : Don’t Care >
Note: All specification and quality of the system are assured by Casio as the MP-2000, any local modification of
the jumper setting by customer will not be applicable for Casio’s guarantee or warranty.

1. Setting pin 35 of LCD display (J4): JP2, JP4

JP2: Setting pin 35 of LCD display connector (J4)

JP2

Pin 35 of J4 is –SHFCLK 1-2
Pin 35 of J4 is SHFCLK 2-3*

2. Setting Watchdog Timer Timeout: JP5

The watchdog timer is an indispensable feature of the SBC8352. It has a sensitive error detection function and
a report function. When the CPU processing comes to a halt, the watchdog can generate an NMI or resets the
CPU.

JP5 Watchdog Function

1-2 Activate NMI when Watchdog triggered
2-3 Reset system when Watchdog triggered
OPEN* Disable

3. LCD display Power Level Setting (V

5V Panel Power Setting 3-5,4-6*

3.3V Panel Power Setting 1-3,2-4

4. CPU Settings: JP6, JP8, JP12, JP22
Jumper Description

JP6 Set CPU clock ratio
JP8 Set Single/Dual power of CPU
JP12 Set CPU bus clock
JP22 Set CPU Core voltage level

CPU JP12 JP6 JP22 JP8
P55C-233 3-4* OPEN* 1-2, 7-8* 1-3,2-4*

5. CMOS SRAM Jumper: JP10

Clear CMOS SRAM data Short
Normal Operation Open*

6. System Flash BIOS Type: JP11
Flash BIOS Type JP11

5V Flash BIOS Short(1-2)*
12V Flash BIOS Open

) - Pins 5, 6, 43, 44 of J4: JP9

CCM

JP9

JP10

— 30 —

7. LCD display Type Selection: JP14

LCD display type JP14 NOTE

640x480 Monochrome Short 1-2
(for MP-2060DP)

8. Serial Ports Settings: JP15 ~ JP20

The SBC8352 provides four onboard serial ports, 3 x RS-232 and 1 x RS-232/422/485. Each serial port is
with +5V/+12V/+24V power capabilities on both Pin 1 and Pin 8, ready to accommodate a wide array of
serial devices. The corresponding jumper settings are shown below.

< SBC8352 means the motherboard and MTIO means the Multi I/O board in the MP-2000. >

COM1:Pin 1

SBC8352 MTIO
JP20 JP1 JP3 JP4

Normal COM 7-9* 1-2* 1-2* 3-5*
+5V 1-3 1-2 1-2 3-5
+12V 3-5 1-2 1-2 3-5
+24V X 1-2 1-2 1-3

COM1:Pin 9

SBC8352 MTIO
JP20 JP1 JP3 JP4

Normal COM 8-10* 1-2* 1-2* 4-6*
+5V 2-4 1-2 1-2 4-6
+12V 4-6 1-2 1-2 4-6
+24V x 1-2 1-2 2-4

COM2:Pin 1

SBC8352 MTIO

JP15 JP16 JP19 JP1 JP3 JP5

Normal COM/RS232 7-9* (3-5,4-6,9-11,10-12)* 5-6* 1-2* 1-2* 3-5*
Normal COM/RS422 7-9 (1-3,2-4,7-9,8-10) 3-4 1-2 1-2 3-5
Normal COM/RS485 7-9 (1-3,2-4,7-9,8-10) 1-2 1-2 1-2 3-5

+5V 1-3 (3-5,4-6,9-11,10-12) 5-6 1-2 1-2 3-5
+12V 3-5 (3-5,4-6,9-11,10-12) 5-6 1-2 1-2 3-5
+24V x (3-5,4-6,9-11,10-12) 5-6 1-2 1-2 1-3

— 31 —

COM2:Pin 9

SBC8352 MTIO

JP15 JP16 JP19 JP1 JP3 JP5

Normal COM/RS232 8-10* (3-5,4-6,9-11,10-12)* 5-6* 1-2* 1-2* 4-6*
Normal COM/RS422 8-10 (1-3,2-4,7-9,8-10) 3-4 1-2 1-2 4-6
Normal COM/RS485 8-10 (1-3,2-4,7-9,8-10) 1-2 1-2 1-2 4-6

+5V 2-4 (3-5,4-6,9-11,10-12) 5-6 1-2 1-2 4-6
+12V 4-6 (3-5,4-6,9-11,10-12) 5-6 1-2 1-2 4-6
+24V x (3-5,4-6,9-11,10-12) 5-6 1-2 1-2 2-4

COM3:Pin 1

SBC8352 MTIO
JP18 JP1 JP3 JP6

Normal COM 7-9* 1-2* 1-2* 3-5*
+5V 1-3 1-2 1-2 3-5
+12V 3-5 1-2 1-2 3-5
+24V X 1-2 1-2 1-3

COM3:Pin 9

SBC8352 MTIO
JP18 JP1 JP3 JP6

Normal COM 8-10* 1-2* 1-2* 4-6*
+5V 2-4 1-2 1-2 4-6
+12V 4-6 1-2 1-2 4-6
+24V X 1-2 1-2 2-4

COM4:Pin 1

SBC8352 MTIO
JP17 JP1 JP3 JP7

Normal COM 7-9* 1-2* 1-2* 3-5*
+5V 1-3 1-2 1-2 3-5
+12V 3-5 1-2 1-2 3-5
+24V X 1-2 1-2 1-3

COM4:Pin 9

SBC8352 MTIO
JP17 JP1 JP3 JP7

Normal COM 8-10* 1-2* 1-2* 4-6*
+5V 2-4 1-2 1-2 4-6
+12V 4-6 1-2 1-2 4-6
+24V x 1-2 1-2 2-4

9. CPU Hardware Reset/Turbo Switch/Turbo LED/IDE LED connector: JP3

Pin Description Pin Description

1 H/W Reset 2 GND
3 TUBSW 4 GND
5 TUBLED(-) 6 TUBLED(+)
7 IDE LED(-) 8 IDE LED(+)

— 32 —

6. Diagnostic Operation

6-1. Diagnositc softwares

Use the following softwares for checking each block.

Mother board ......................................AMI Diag.5.42 (available in the market)

Customer display ................................Diagnostic program built in the QT-7060D,7062D,7063D.

Drawer ................................................drw.exe (available from Casio)

6-2. Customer display

Necessary tools

■ Loop back connector

■ Stabilized power supply

Preparations

■ In case of QT-7060D or QT-7062D

1 Connect a loop back connector (male type) to customer display’s D-SUB connector.
2 Apply +24 V to pin 1 and GND to pin 5 of the loop back connector.
3 Short circuit pins 2 and 3 (DSR-RXD), and pins 4 and 6 (TXD-DTR).

+ 24V

Short circuited

1

6

+ 24V (pin 1)

GND (pin 5)

QT-7060D or QT-7062D

GND

5

9

Short circuited

Loop back connector

— 33 —

■ In case of QT-7063D

PCB

Loop back connector

AC adaptor jack

Display signal connector

1 Connect a loop back connector on Customer display stand unit.
2 Connect a testing customer display to Display signal connector.
3 Apply +24V DC to the AC adaptor jack.

CN3

5
9

TXD

DSR

RXD

DTR

4

8
3

7
2
6
1

PRINTER

5
9

4

8

3

7
2
6
1

HOST

Female

Male

5

9

4

8
3

7
2
6

1

5

9

4

8
3

7
2
6
1

Loop back connector

Sub PCB

Loop back connector circuit diagram

— 34 —

Precautions

1 For checking QT-7063D, use customer display stand unit.
2 Turn the power off before connecting the customer display.
3 After the check, be sure to set the DIP switch correctly.
4 Also check rotating mechanism of the customer display.

Diagnose

Screws

1 Unscrew four screws and remove display panel.

Reset switch

OFF

Initial position of DIP switch

ON
1
2
3
4
5
6
7
8

DIP switch

Display tube

2 Apply power supply (AC adaptor).

3 T urn all the DIP switches on.

4 Push the reset switch. Diagnostic program starts and display shows;

— 35 —

All dots off

All dots on

A vertical line moves from right to left.

1 2 3 4 5 6 7 8
1 1 1 1 1 1 1 1

— 36 —

5 Turn DIP switch 1~ 6 off.

1 2 3 4 5 6 7 8
0 0 0 0 0 0 1 0

1 2 3 4 5 6 7 8
0 0 0 0 0 0 0 0

6 Turn DIP switch 7 off.

7 Set the DIP switchi in the initial position (SW1 and SW5 on,

others off).

8 Turn the power off.

9 Set the display panel by four screws.

6-3. Drawer test

After 1 second, display turns off.

Execute drw.exe.

drw 1 ENTER

Drawer 1 Open
Drawer 2 Open

Switch#1 ' 0 '
Swtitch#2 ' 0 '

Switch#1 ' 1 '
Swtitch#2 ' 0 '

Switch#1 ' 1 '
Swtitch#2 ' 1 '

Drawer 1 opens then after a while, Drawer 2 opens)

Drawer switch 1 status '0' is shown when Drawer 1 opens.

)

Drawer switch 2 status '0' is shown when Drawer 2 opens.

Drawer switch 1 status '1' is shown when Drawer 1 is closed.

)

Drawer switch 2 status '1' is shown when Drawer 2 is closed.

)

— 37 —

7. T roubleshooting

This portion of the service manual lists all possible malfunctions that may occur when operating the MP-2000
system. To assist you in fully analyzing the problem, the following table also includes an up-to-date list of symp­toms and probable cause(s). In case you encounter problems or discover causes not included in this section, we
highly recommend you to consult CASIO engineers.

Symptoms Probable Causes

– Loose power cable connection at the bottom of the front panel

■Turn OFF system power then disconnect the power cord. Insert the
power cord back into the inlet connector then turn ON the system power.

The power LED – The connection of female jacks to the power supply inlet connector is
indicator on the front loose.
panel does not light ■Remove the back cover of the system and check each connection to the
up. power supply inlet connector.

– Loose connection on the bronze and blue copper wires of the power switch

■Check each connection.

– Power supply unit is out-of-order,

■Replace the power supply unit.

– Monitor cable is not properly installed to connector VGA of the system.

– Loose connection between the multi-I/O (VGA) expansion card and the
Abnormal VGA screen CPU card.
display ■Pull out the multi-I/O expansion card from the CPU card then re-install

it back. If symptoms persist, replace the multi-I/O expansion card.

– Defective CPU card

■Replace the CPU card of the System.

– The brightness control is not properly adjusted.

■Adjust the brightness control to a satisfactory level.

– Inverted connection (from LCD converter board to CPU card) of the 44-pin

LCD converter cable

■Adjust and install the LCD converter cable properly.

– Loose connection between the LCD converter board and the LCD panel

■Pull out the LCD converter board from the LCD panel then re-install it
Abnormal LCD screen back.
display

If symptoms still persist at this stage, replace the LCD converter board
and/or the LCD converter cable

– Defective LCD panel and/or inverter

■Replace the LCD panel and/or inverter.

– Defective CPU card

■Replace the CPU card of the system.

– Incorrect BIOS version

■Upgrade the BIOS version. Consult CASIO engineers for the latest

version.

– Loose connection between the multi-I/O (COMx) expansion card and the

CPU card.
COM Port is not ■Pull out the multi-I/O expansion card from the CPU card then re-install it
functioning back. If symptoms persist, replace the multi-I/O expansion card.

– Defective CPU card

■Replace the CPU card of the System.

— 38 —

Symptoms Probable Causes

– Improper connection of the network cable

■Check the RJ-45 connector installed on the NET port of the multi-I/O
expansion card.

Network function is not – Loose connection between the multi-I/O (NET) expansion card and the
working CPU card.

■Pull out the multi-I/O expansion card from the CPU card then re-install
it back. If symptoms persist, replace the multi-I/O expansion card.

– Defective CPU card

■Replace the CPU card of the System.

– Loose connection between the cash drawer connector board and multi-

I/O expansion card

■Pull out the cash drawer connector board from the multi-I/O expansion

Cash drawer ports not card then re-install it back. If symptoms persist, replace the cash drawer
functioning connector board.

– Defective multi-I/O expansion card

■Replace the multi-I/O expansion card of the system.

– Defective CPU card

■Replace the CPU card of the System.

– Loose connection between the multi-I/O (PRN) expansion card and the

CPU card.
Printer port is not ■Pull out the multi-I/O expansion card from the CPU card then re-install it
working back. If symptoms persist, replace the multi-I/O expansion card.

– Defective CPU card

■Replace the CPU card of the System.

– Loose connection between the keyboard /mouse/FDD expansion card

and the CPU card.
Keyboard/Mouse/FDD ■Pull out the keyboard/mouse/FDD expansion card from the CPU card
are not functioning then re-install it back. If symptoms persist, replace the keyboard/mouse/

FDD expansion card.

– Defective CPU card

■Replace the CPU card of the System.

– Inverted connection (from HDD to CPU card) of the 44-pin HDD cable

■Adjust and install the HDD cable properly.

HDD is not working – Defective hard drive

■Replace the hard disk drive of the system.

– Defective CPU card

■Replace the CPU card of the System.

– Improper connection (from CN1 of touchscreen control board to COM3 of

the multi-I/O expansion card) of the 10-pin touchscreen control cable
Touchscreen feature is ■Adjust and install the touchscreen control cable property.
not functioning – Loose power connection on CN2 of the touchscreen control board.
properly ■Pull out the power cable on CN2 then re-install it back. If symptoms

persist, consult CASIO engineers.

– Defective touchscreen control board

■Replace the touchscreen control board of the system.

— 39 —

8. Data Sheet

8-1 65550 (HiQV32TM)

High Performance MultiMedia Flat Panel/CRT GUI Accelerator

8-2 M5113

Enhanced Super I/O Controller with plug & play

8-3 UM9008

ISA/plug & play super Ethernet Controller

8-4 VT82580

Geen Pentium/P54C/M1/K5 PCI/ISA System with unified memory architecture,
Universal serial Bus and Master mode PCI-IDE Controller

1. VT82C585VP

System Controller

2. VT82C586VP

PCI to ISA Bridge

3. VT82C587VP

Data Buffer

8-5 PENTIUM® PROCESSOR with MMX Technology

8-6 MN04326TAE SIMM (Single Inline Memory Module)

8-7 POWER SUPPLY (100W)

— 40 —

8-1 65550 (HiQV32TM)

High Performance MultiMedia Flat Panel / CRT
GUI Accelerator’

■Highly integrated design Flat Panel and CRT GUI Accel­erator & Multimedia Engine, Palette/DAC, and Clock Syn­thesizer

■Hardware Windows Acceleration

• 64-bit Graphics Engine

- System-to-Screen and
Screen-to-Screen BitBLT

- 3-Operand Raster-Ops

- 8/16/24 Color Expansion

• Transparent BLT

- Optimized for Windows

TM

BitBLT format

■PCI Bus with Burst Mode capability and BIOS ROM sup­port.

■VL-Bus and 486 Local Bus support

■Flexible Memory Configurations

• 32-Bit memory interface

• Two or four 256Kx 16 DRAMS

(IMB or 2MB)

• One 512Kx32 DRAMS (2MB)

• Two 128Kx32 DRAMS (lMB)

• Four 128Kx16 DRAMS (lMB)

■High Performance:

• Deep write buffers

• EDO DRAM Support

- 40MHz@3.3v

■Hardware Multimedia Support

• Zoom Video port

• YUV input from System Bus or Video Port

• YUV-RGB Conversion

• Capture / Scaling

• Zoom up to 8x

• Interpolation

• Double Buffered Video

■Game Acceleration

• Source Transparent BLT

• Destination Transparent BLT

• Double buffer-support for YUV and 15/16bpp
Overlay Engine

• Instant Full Screen Page Flip

• Read back of CRT Scan line counters.

■Optimized for High-Performance Flat Panel Display at 3.3V

• 640x480 x 24bpp

• 800x600 X 24bpp

• 1024x768 x 16bpp

■CRT Support

• 8OMHz@3.3v

• 110 MHz@ 5.0v

■Direct interface to Color and Monochrome, Single Drive
(SS), and Dual Drive (DD), STN & TFT panels

■Flexible On-chip Activity Timer facilitates ordered shut-down
of the display system

■Advanced Power Management feature minimizes power
usage in:

• Normal operation

• Standby (Sleep) modes

• Panel-Off Power-Saving Mode

■VESA Standards supported

• VAFC Port for display of “Live” Video

• DPMS for CRT power-down (required for support of EPA

Energy-Star program)

• DDC for CRT Plug-Play & Display Control

■Composite NTSC / PAL Support

■Power Sequencing control outputs regulate application of

Bias voltage, +5V to the panel and +12V to the inverter for
backlight operation

■Display centering and stretching features for optimal fit of
VGA graphics and text on 800x600 and 1024x768 panels

■Simultaneous Hardware Cursor and Pop-up Window

• 64x64 pixels by 4 colors

• 128x128 pixels by 2 colors

— 41 —

■Mixed 3.3V and 5.0V Operation

®

■Fully Compatible with IBM

VGA

CPU Direct / VL-Bus Interface

Pin names in parentheses (...) indicate alternate functions.

Pin # Pin Name Type Active Description

207 RESET In Low Reset For VL-Bus interfaces, connet to RESET For

direct CPU local bus interfaces, connect to the system reset
generated by the motherboard system logic for all periph­erals (not the RESET# pin of the processor). This input is
ignored during Standby mode (STNDBY# pin low) so
that the remainder of the system (and the system bus)
may be safely powered down during Standby mode if
desired.

22 ADS# In Low Address Strobe. In VL-Bus and CPU local bus interfaces

ADS# indicates valid address and control signal information
is present. It is used for all decodes and to indicate the start
of a bus cycle.

31 M/IO# In Both Memory / IO. In VL-Bus and CPU local bus interfaces

M/I0# indicates either a memory or an I/O cycle:
I = memory, O = I/O.

11 W/R# In Both Write / Read. This control signal indicates a write (high) or

read (low) operation. It is sampled on the rising edge of the
(internal) 1x CPU clock when ADS# is active.

23 RDYRTN# for 1x Clock In Low Ready Return. Handshaking signal in VL-Bus interface

config High indicating synchronization of RDY# by the local bus master
CRESET for 2X clock config / controller to the processor. Upon receipt of this LCLK-

synchronous signal the chip will stop driving the bus (if a
read cycle was active) and terminate the current cycle.

24 LRDY# Out/ Low Local Ready. Driven low during VL-Bus and CPU local

OC bus cycles to indicate the current cycle should be completed.

This signal is driven high at the end of the cycle, then tri­stated. This pin is tri-stated during Standby mode (as are all
other bus interface outputs).

25 LDEV# Out Low Local Device. In VL-Bus and CPU local bus interfaces, this

pin indicates that the chip owns the current cycle based on
the memory or I/O address which has been broadcast. For
VL-Bus, it is a direct output reflecting a straight address
decode. This pin is tri-stated during Standby mode (as are
all other bus interface outputs).

27 LCLK In Both Local Clock. In VL-Bus this pin is connected to the CPU

1x clock. In CPU local bus interfaces it is connected to the
CPU 1x or 2x clock. If the input is a 2x clock, the processor
reset signal must be connected to CRESET (pin 23) for
synchronization of the clock phase

43 BE0# (BLE#) In Low Byte Enable 0. Indicates data transfer on D7:D0 for the

current cycle.

32 BE1# In Low Byte Enable 1. Indicates data transfer on D15:D8 for the

currant cycle.

21 BE2# In Low Byte Enable 2. Indicates data transfer on D23:D16 for the

current cycle.

10 BE3# In Low Byte Enable 3. BE3# indicates that data will transfer over

the data bus on D31:24 during the current access.

— 42 —

Pin # Pin Name Type Active Description

179 A2 In High System Address Bus. In VL-Bus, and direct CPU inter­180 A3 In High faces, the address pins are connected directly to the bus.
182 A4 In High In internal clock synthesizer test mode (TS# = 0 at Reset).
183 A5 In High A24 becomes VCLK out and A25 becomes MCLK out.
185 A6 In High A26 and A27 may be alternately be used as General Purpose
186 A7 In High I/O pins or as Activity indicator and Enable Backlight
187 A8 In High respectively (see panel interface pin descriptions and FR0F
188 A9 In High and FR0C for more details). If A26 and A27 are used as
189 A10 In High GPIO pins, they may be programmed as a 2-pin CRT
190 A11 In High Monitor DDC interface (VESATM “Display Data Channel”
191 A12 In High also referred to as the “Monitor Plug-n-Play” interface).
192 A13 In High Either A26 or A27 may also be used to output Composite
193 A14 In High Sync for support of an external NTSC / PAL encoder chip.
194 A15 In High
195 A16 In High
196 A17 In High
197 A18 In High
189 A19 In Nigh
199 A20 In High
200 A21 In High
201 A22 In High

28 A23 In High
29 A24 In High
30 A25 In High
53 A26 In High
54 A27 In High

51 D00 I/O High System Data Bus.
50 D01 I/O High In 32-bit CPU Local Bus designs these data lines connect
49 D02 I/O High directly to the processor data lines. On the VL-Bus they
48 D03 I/O High connect to the corresponding buffered or unbuffered data
47 D04 I/O High signal.
46 D05 I/O High These pins are tri-stated during Standby mode (as are all
45 D06 I/O High other bus interface outputs).
44 D07 I/O High
41 D08 I/O High
40 D09 I/O High
38 D10 I/O High
37 D11 I/O High
36 D12 I/O High
35 D13 I/O High
34 D14 I/O High
33 D15 I/O High
20 D16 I/O High
19 D17 I/O High
18 D18 I/O High
17 D19 I/O High
16 D20 I/O High
15 D21 I/O High
14 D22 I/O High
13 D23 I/O High

8 D24 I/O High
7 D25 I/O High
6 D26 I/O High
5 D27 I/O High
4 D28 I/O High
3 D29 I/O High
2 D30 I/O High
1 D31 I/O High

— 43 —

Bus Output Signal Status During Standby Mode

65550 Pin# Signal Name Signal Status

53 ACTI / A26 Driven Low

54 ENABKL / A27 Driven Low

24 LRDY# / RDY Tri-Stated

25 LDEV# Tri-Stated

51-44, 41-40, 38-33 D0 - 15 Tri-Stated

20 -13, 8 -1 D16 -31 Tri-Stated

PCI Bus Interface

Pin # Pin Name Type Active Description

207 RESET# In Low Reset. This input sets all signals and registers in the chip to

a known state. All outputs from the chip arc tri-stated or
driven to an inactive state. This pin is ignored during
Standby mode (STNDBY# pin low). The remainder of
the system (therefore the system bus) may be powered
down if desired (all bus output pins are tri-stated in
Standby mode).

201 CLK In High Bus Clock. This input provides the timing reference for all

bus transactions. All bus inputs except RESET# and INTA#
are sampled on the rising edge of CLK. CLK may be any
frequency from DC to 33MHz.

31 PAR I/O High Parity. This signal is used to maintain even parity across

AD0-31 and C/BE0-3#. PAR is stable and valid one clock
after the address phase. For data phases PAR is stable and
valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted on a read transaction.
Once PAR is valid, it remains valid until one clock after the
completion of the current data phase (i.e., PAR has the same
timing as AD0-31 but delayed by one clock). The bus
master drives PAR for address and write data phases; the
target drives PAR for read data phases.

22 FRAME# In Low Cycle Frame. Driven by the current master to indicate the

beginning and duration of an access. Assertion indicates a
bus transaction is beginning (while asserted, data transfers
continue); de-assertion indicates the transaction is in the
final data phase

23 IRDY# In Low Initiator Ready. Indicates the bus master’s ability to

complete the current data phase or the transaction. During a
write, IRDY# indicates valid data is present on AD0-31;
during a read it indicates the master is prepared lo accept
data. A data phase is completed on any clock when both
IRDY) and TRDY# are sampled then asserted (wait cycles
are inserted until this occurs).

24 TRDY# S/TS Low Target Ready. Indicates the target’s ability to complete the

current data phase or the transaction. During a read,
TRDY# indicates that valid data is present on AD0-31;
during a write it indicates the target is prepared to accept
data A data phase is completed on any clock when both
IRDY# and TRDY# are sampled then asserted (wait cycles
are inserted until this occurs).

— 44 —

Pin # Pin Name Type Active Description

27 STOP# S/TS Low Stop. Indicates the current target is requesting the master to

stop the current transaction

25 DEVSEL# S/TS Low Device Select. Indicates the current target has decoded its

address as the target of the current access

29 PERR# (VCLKOUT) S/TS Low Parity Error. This signal reports data parity errors (except

for Special Cycles where SERR is used). The PERR# pin
is Sustained Tri-state. The receiving agent will drive
PERR# active two clocks after detecting a data parity error.
PERR# will be driven high for one clock before being tri­stated as with all sustained tri-state signals. PERR# will not
report status until the chip has claimed the access by
asserting DEVSEL# and completing the data phase.

30 SERR# (MCLKOUT) OD Low System Error. Used to report system errors where the result

will be catastrophic (address parity error, data parity errors
for Special Cycle commands, etc.). This output is actively
driven for a single PCI clock cycle synchronous to CLK and
meets the same setup and hold time requirements as all other
bused signals. SERR# is not driven high by the chip after
being asserted, but is pulled high only by a weak pull-up
provided by the system. Thus, SERR# on the PCI Bus may
take two or three clock periods to fully return to an inactive
state.

179 ROMA0 Out High BIOS ROM address outputs. See MAD8-I5 (pins 170-177)
180 ROMA1 (GPIO3) Out High for BIOS ROM data inputs.
182 ROMA2 (GPIO4) Out High
183 ROMA3 (GPIO5) Out High BIOS ROMS are not normally required in portable computer
185 ROMA4 (GPIO6) Out High designs (Graphics System BIOS code is normally included
187 ROMA5 Out High in the System BIOS ROM). However, the 65550 provides
189 ROMA6 Out High BIOS ROM interface capability for development systems
191 ROMA7 Out High and add-in card Flat Panel Graphics Controllers.
192 ROMA8 Out High
190 ROMA9 Out High Since the PCI Bus specifications require only one load on
186 ROMA10 (GPIO7) Out High the bus for the entire graphics subsystem, the BIOS ROM
188 ROMA11 Out High interface is “through the chip”. In the VL-Bus mode, the
193 ROMA12 Out High BIOS ROM interface can be an external circuit on the ISA
194 ROMA 13 Out High Bus connector that does not require pins on the chip (see the
196 ROMA 14 Out High Application Schematics section for details).
195 ROMA15 Out High
197 ROMA 16 Out High For programming GPI03-7, see registers XR62-63
198 ROMA 17 Out High

200 ROMOE# Out Low BIOS ROM Output Enable.

199 Reserved In n/a This pin is always an input (A20 for VL-Bus, reserved for

28 Reserved In n/a This pin is always all input (A23 for VL-BUS, reserved for

future use on PCI Bus). To avoid abnormal Vcc current due
to a floating input for a PCI Bus, use a 10K resistor to
ground to pull this pin low

future use on PCI Bus). To avoid abnormal Vcc current due
to a floating input for a PCI Bus, use a 10K resistor to
ground to pull this pin low.

— 45 —

Pin # Pin Name Type Active Description

51 AD00 I/O High PCI Address / Data Bus
30 AD01 I/O High Address and data are multiplexed the same pins. A bus
49 AD02 I/O High transaction consists or an address phase followed by one or
48 AD03 I/O High more data phases (both read and write bursts are allowed by
47 AD04 I/O High the bus definition).
46 AD05 i/O High The address phase is the clock cycle in which FRAME# is
45 AD06 I/O High asserted (AD0-31 contain a 32-bit physical address). For
44 AD07 I/O High I/O, the address is a byte address, for memory and configu­41 AD08 I/O High ration the address is a DWORD address. During data
40 AD09 I/O High phases AD0-7 contain the LSB and 24-3 1 contain the MSB.
38 AD10 I/O High Write data is stable and valid when IRDY# is asserted; read
37 AD11 I/O High data is stable and valid when TRDY# is asserted. Data
36 AD12 I/O High transfers only during those clocks when both IRDY and
35 AD13 I/O High TRDY# are asserted.
34 AD14 I/O High
33 AD15 I/O High
20 AD16 I/O High
19 AD17 I/O High
18 AD18 I/O High
17 AD19 I/O High
16 AD20 I/O High
15 AD21 I/O High
14 AD22 I/O High
13 AD23 I/O High

8 AD24 I/O High
7 AD25 I/O High
6 AD26 I/O High
5 AD27 I/O High
4 AD28 I/O High
3 AD29 I/O High
2 AD30 I/O High
1 AD31 I/O High

CBE3-0 Command TypE 65550

0000 Interrupt Acknowledge
0001 Specie Cycle
0010 I/O Read Y
0011 I/O Write Y
0100 -reserved­0101 -reserved­0110 Memory Read Y

0111 Memory Write Y
1000 -reserved­1001 -reserved­1010 Configuration Read Y
1011 Configuration Write Y
1100 Memory Read Multiple
1101 Dual Address Cycle

1110 Memory Read Line

1111 Memory Read & Invalidate

43 C/BE0# In Low Bus Command / Byte Enables. During the address phase of
32 C/BE1# In Low a bus transaction, these pins define the bus command (see
21 C/BE2# In Low list above) . During the data phase, these pins are byte
10 C/BE3# In Low enables that determine which byte lanes carry meaningful

data:

byte 0 corresponds to AD0-7.
byte 1 corresponds to 8-15.
byte 2 corresponds to 16-23.
byte 3 corresponds to 24-31

11 IDSEL In High Initialization Device Select. Used as a chip select during

cofiguration read and write transactions

145 AA0 (LB#) (CFG0) I/O Low Address bus for DRAMS A and B
146 AA1 (Reserved) (CFG1) I/O High See the configuration table in the Extended Register
147 AA2 (2X#) (CFG2) I/O High description section for complete details on the configuration
148 AA3 (Reserved) (CFG3) I/O High options for CFG0-8 (XR70-71). See MAD2-7 (pins 164-169)
149 AA4 (Reserved) (CFG4) I/O High and XR71 for additional configuration inputs (CFG10- 15).
150 AA5 (OS#) (CFG5) I/O High
151 AA6 (AD#) (CFG6) I/O High
152 AA7 (TS#) (CFG7) I/O High
153 AA8 (LV#) (CFG8) I/O High

AA0 PCI Bus VL-Bus
AA2 2x Clock 1x Clock
AA5 Ext. Clock (14.3Mhz) Not supported
AA6 A26-A27 ENABL/ACTI
AA7 Clock Test Mode Clock Test mode disable
AA8 IVcc/CVcc = 3.3V IVcc/CVcc = 5.0V

Since the 65550 does not support the “internal oscillator”
option, pin CFG5 (AA5) must be pulled down on reset.

Low (=0) High (=1)

— 46 —

Pine Pin Name Type Active Description

90 CA0 (P16) Out High Address bus for DRAM C
91 CAI (P17) Out High
92 CA2 (P18) Out High
93 CA3 (P19) Out High
94 CA4 (P20) Out High
95 CA5 (P21) Out High
96 CA6 (P22) Out High
97 CA7 (P23) Out High
98 CA8 (BLANK) I/O Hi/Lo CA8 may be configured as VAFC BLANK# out or vertical

reference input (VREF) for video capture.

99 HREF In High Horizontal reference input for video capture.

156 RASA# (RASAB0#) Out Low RAS for DRAM A (or bank 0 in 2MB configurations)
123 RASB# (RASAB1#) Out Low RAS for DRAM B (or bank 1 in 2MB configurations)
101 RASC#) (VRDY) Out Low RAS for DRAM C or color key input from external PC-

(KEY) In High Video source (or VAFC “Video System Ready” input)

160 CASAL# (WEAL#) Out Low CAS for the DRAM A lower byte

159 CASAH# (CASA#) Out Low CAS for the DRAM A upper byte

126 CASBL# (WEBL#) Out Low CAS for the DRAM B lower byte

125 CASB# (CASB#) Out Low CAS for the DRAM B upper byte

104 CASCL# (WECL#) I/O Both DRAM C low byte CAS, video in red-6 or VAFC VP14

(VR6/VP14)

103 CASCH# (CASC#) I/O Both DRAM C high byte CAS, video in red-7 or VAFC VP15

(VR7/VP15)

157 WEA# (WEAH#) Out Low Write enable for DRAM A (or bank 0 in 2MB)

(WEAB0#)

124 WEB# (WEBH#) Out Low Write enable for DRAM B (or bank 1 in 2MB)

(WEAB1#) Out High

102 WEC# (WECH#) Out Both Write enable for DRAM C or video in port PCLK out

(PCLK)

155 OEAB0# Out Low Output enable for DRAMs A and B, bank 0,1 of 2MB

100 OEC# Out Low Output enable for DRAM C or VAFC “Video Input Clock”

(VCLK) In High in DRAM C not used

162 MAD0 (TSENA#) I/O High Memory data bus for DRAM A (lower 512KB of display
163 MAD1 (ICTENA#) I/O High memory)
164 MAD2 (CFG10) EDO/FPM I/O High MAD2-7 are latched into XR71 on reset for use as
165 MAD3 (CFG11) (PID0) I/O High additional configuration inputs (CFG 10 -12 are reserved by
166 MAD4 (CFG12) (PID1) I/O High software for input of panel ID). These bits have no other
167 MAD5 (CFG13) (PID2) I/O High internal hardware configuration function.
168 MAD6 (CFG14) (PID3) I/O High
169 MAD7 (CFG15) (Reserved) I/O High PCI Bus: MAD8-15 are used as BIOS ROM Data inputs
170 MAD8 (PCI ROMD0) I/O High during system startup (i.e., before the system enables the
171 MAD9 (PCI ROMD1) I/O High graphics controller memory interface). See also pins 179.
172 MAD10 (PCI ROMD2) I/O High 199 (in PCI Bus interface pin descriptions section) for BIOS
173 MAD11 (PCI ROMD3) I/O High ROM address and ROM Chip Select outputs. In the VL­174 MAD12 (PCI ROMD4) I/O High Bus mode, the BIOS ROM interface can be an external
173 MAD13 (PCI ROMD5) I/O High circuit on the ISA Bus connector (see Application
176 MAD14 (PCI ROMD6) I/O High Schematics).
177 MAD15 (PCI ROMD7) I/O High

— 47 —

Pine Pin Name Type Active Description

127 MBD0 I/O High Memory data bus for DRAM B (upper 5I2KB)
128 MBDI I/O High
129 MBD2 I/O High
130 MBD3 I/O High
131 MBD4 I/O High
132 MBD5 I/O High
133 MBD6 I/O High
134 MBD7 I/O High
135 MBD8 I/O High
136 MBD9 I/O High
137 MBD10 I/O High
138 MBD11 I/O High
140 MBD12 I/O High
141 MBD13 I/O High
143 MBD14 I/O High
144 MBD14 I/O High

106 MCD0 (VB2) (EVID#) I/O High Memory data bus for DRAM C (Frame Buffer)
107 MCD1 (VB3) (VP0) I/O High
109 MCD2 (VB4) (VP1) I/O High When a frame buffer DRAM is not required, this bus may
110 MCD3 (VB5) (VP2) I/O High be used to input up to 18 bits of RGB data from all external
111 MCD4 (VB6) (VP3) I/O High PC-Video subsystem or 16 bits of RGB from an external
112 MCD5 (VB7) (VP4) I/O High VAFC interface. Note that this configuration also provides
113 MCD6 (VG2) (VP3) I/O High additional panel outputs so that a video input port may be
114 MCD7 (VG3) (VP6) I/O High implemented along with a 24-bit true-color TFT panel (TFT
115 MCD8 (VG4) (VP7) I/O High panels never need DRAM C). In VAFC interface mode, pin
116 MCD9 (VG5) (VP8) I/O High 106 is the VAFC “Enable Video” input. The external
117 MCD10 (VG6) (VP9) I/O High VAFC interface drives this pin low to indicate data input on
118 MCD11 (VG7) (VP10) I/O High the VPO-15 EVID# is ignored (essentially reserved) in the
119 MCD12 (VR2) (GRDY) I/O High 65550 (VAFC data is always expected as inputs). In VAFC
120 MCD13 (VR3) (VP11) I/O High mode, pin 119 is “Graphics System Ready” out and is
121 MCD14 (VR4) (VP12) I/O High always driven high.
122 MCD15 (VR5) (VP13) I/O High

Note: S/TS stands for “Sustained Tri-state”. These signals are driven by only one device at a time, are driven high for

one clock before released, and are not driven for at least one cycle after being released by the previous device. A
pull-up provided by the bus controller is used to maintain an inactive level between transactions.

Pin names in parenthesis (...) indicate alternate functions.
If ICTENA# is low with RESET# low, a rising edge on XTALI will put the chip into “In circuit Test” (ICT)
mode. In ICT mode, all digital signal pins become inputs which are apart of a long path stating at ENAVDD (pin

62) and proceeding to lower pin numbers around the chip to pin 1 then to pin 208 and ending at VSYNC (pin 64).
If all pins in the path are high the VSYNC output will be high. If any pin is low, the VSYNC output will be low.
Thus the chip can be checked in circuit to determine if all pins are connected properly by toggling all pins one at a
time and observing the effect on VSYNC. XTALI must be toggled last because rising edges on XLTAI with
ICTENA# high or RESET# high will exit ICT mode. As a side effect, ICT mode effectively 3-states all pins
except VSYNC. If TSENA# is low with RESET# low, a rising edge on XTLAI will 3-state all pins. An XTALI
rising edge without enabling conditions exits 3-state.

For the ZV Port interface, Y0-7 correspond to VP0-7, and UV0-7 correspond to VP8-15

— 48 —

Flat Panel Display Interface

Pin # Pin Name Type Active Description

71 P0 OUT High 8, 9, 12, or 16-bit flat panel data output. 18-bit and 24-bit
72 P1 OUT High panel interfaces may also be supported (see CA0-7 for P16.
73 P2 OUT High 23).
74 P3 OUT High
75 P4 OUT High Refer to the table on the next page for the configurations for
76 P5 OUT High various panel types.
78 P6 OUT High
79 P7 OUT High
81 P8 (SHFCLKU) OUT High
82 P9 OUT High
83 P10 OUT High
84 P11 OUT High
85 P12 OUT High
86 P13 OUT High
87 P14 OUT High
88 P15 OUT High

70 SHFCLK (CL2) (SHFCLKL) OUT High Shift Clock. Pixel clock for flat panel data.

67 FLM OUT High First Line Marker. Flat Panel equivalent of VSYNC.

68 LP OUT High Latch Pulse. Flat Panel equivalent of HYSYNC.

(CLI)(DE) (BLANK#)

69 M OUT High M signal for panel AC drive control (may also be called

(DE) (BLANK#) ACDCLK). May also be configured as BLANK# or as

Display Enable (DE) for TFT Panels.

62 ENAVDD I/O Power sequencing controls for panel driver electronics
61 ENAVEE (ENABKL) I/O voltage VDD and panel LCD bias voltage VEE

53 ACTI I/O Activity indicator and Enable Backlight outputs. May be

(A26/GPO/DDAT/CS) configured for other functions (see Extension Registers

54 ENBKL(A27/GPI/DCLD/CS) I/O FR0C and FR0F and pin descriptions of MCD 0-15 and

A26/A27 for more information).

— 49 —

Mono Mono Mono Color Color Color

65550 SS DD DD TFT TFT TFT HR STN SS STN SS STN DD STN DD STN DD

Pin#

Pin

Name bit bit bit (X4bp) (4bp) (4bp) (4bp)

71 P0 – UD3 UD7 B0 B0 B00 R1 R1 UR1 UR0 UR0
72 P1 – UD2 UD6 B1 B1 B01 B1 G1 UG1 UG0 UG0

73 P2 – UD1 UD5 B2 B2 B02 G2 B1 UB1 UB0 UB0
74 P3 – UD0 UD4 B3 B3 B03 R3 R2 UR2 UR1 LR0
75 P4 – LD3 UD3 B4 B4 B10 B3 G2 LR1 LR0 LG0
76 P5 – LD2 UD2 G0 B5 B11 G4 B2 LG1 LG0 LB0
78 P6 – LD1 UD1 G1 B6 B12 R5 R3 LB1 LB0 UR1
79 P7 – LD0 UD0 G2 B7 B13 B5 G3 LR2 LR1 UG1
81 P8 P0 – LD7 G3 G0 G00 SHFCLKU B3 – UG1 UB1
82 P9 P1 – LD6 G4 G1 G01 – R4 – UB1 LR1
83 P10 P2 – LD5 G5 G2 G02 – G4 – UR2 LG1
84 P11 P3 – LD4 R0 G3 G03 – B4 – UG2 LB1
85 P12 P4 – LD3 R1 G4 G10 – R5 – LG1 UR2

8-bit 8-bit 16-bit

9/12/16 18/24 18/24 8-bit 16-bit 8-bit 16-bit

Color

STN

Color Color Color Color

24-bit

86 P13 P5 – LD2 R2 G5 G11 – G5 – LB1 UG2
87 P14 P6 – LD1 R3 G6 G12 – B5 – LR2 UB2
88 P15 P7 – LD0 R4 G7 G13 – R6 – LG2 LR2
90P16––––R0R00––––LG2
91 P17 – – – – R1 R01 – – – – LB2
92 P18 – – – – R2 R02 – – – – UR3
93 P19 – – – – R3 R03 – – – – UG3
94P20––––R4R10––––UB3
95 P21 – – – – R5 R11 – – – – LR3
96P22––––R6R12––––LG3
97 P23 – – – – R7 R13 – – – – LB3
70 SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK

Pixels/ 8 8 16 1 1 2 2-2/3 5-1/3 2-2/3 5-1/3 8
Clock:

Note: The 65550 also supports panel interfaces that transfer one pixel per word, but which use both edges or SHFCLK

to transfer one pixel on each edge. See FR12[0].

Note: The higher order output lines should be used when only 9 or 12 bits are needed from the 9/12/16-bit TFT

interface, or when only 18 bits are needed from the 18/24-bit TFT or TFT HR interfaces. The lower order bits
should be left unconnected

— 50 —

CRT & Clock Interface

Pin # Pin Name Type Active Description

65 HYSNC (CSYNC) OUT Both CRT Horizontal Sync (polarity is programmable) or

“Composite Sync” for support of various external NTSC/
PAL encoder chips. Note CSYNC can be set to output on
the ACTI or ENABKL pins.

64 VSYNC (VISINT) OUT Both CRT Vertical Sync (polarity is programmable) or “VSync

Interval” for support of various external NTSC 1 PAL
encoder chips.

60 RED OUT High CRT analog video outputs from the internal color palette
58 GREEN OUT High DAC. The DAC is designed for a 37.5Ω equivalent load on
57 BLUE OUT High each pin (e.g. 75Ω resistor on the board, in parallel with the

75Ω CRT load).

55 RSET In N/A Set point resistor for the internal color palette DAC. A 590

Ω 1% resistor is acquired between RSET and AGND.

59 AVCC VCC - Analog power and ground pins for noise isolation for the
56 AGND GND - internal color palette DAC. AVCC should be isolated from

digital VCC as described in the Functional Description of
the internal color palette DAC. For proper DAC operation.
AVCC should not be greater than IVCC. AGND should be
common with digital ground but must be tightly decoupled
to AVCC. See the Functional Description of the internal
color palette DAC for further information.

203 XTALI (MCLK) In High Crystal In. This pin serves as the input for an extemal

reference oscillator (usually 14.31818 MHz). Note that in
test mode for the internal clock synthesizer, MCLK is
output on A25 (pin 30) and VCLK is output on A24 (pin

29).

204 (Reserved) Reserved. For compatibility with the 65545, this pin

(formerly “Crystal Out” or “XTLAO”) must be discon­nected. In addition, pin 150 must be pulled down on reset.
The 65545 no longer supports the “internal oscillator”
option.

205 CVCC0 VCC - Analog power and ground pins for noise isolation for the
202 CGND0 GND - internal clock synthesizer. Must be the same as VCC for

internal logic. VCC/GND pair 0 and VCC/GND pair 1 pins
206 CVCCI VCC - must be carefully decoupled individually. Refer also to the
208 CGND1 GND - section on clock ground layout in the Functional

Description. Note that the CVCC voltage must be the same

as the voltage for the internal logic (IVCC).

154 32KHz (GPIO2) (AA9) In High Clock input for refresh of non-self-refresh DRAMS and

panel power sequencing. This pin can be programmed as

GP102 instead of 32KHz input, or AA9 for 512Kx32

memory configurations.

— 51 —

CRT/ PANEL Signal Status During Standby Mode

65550 Pin# Signal Name Signal Status

67 FLM Driven Low (weak)
68 LP Driven Low (weak)
70 SHFCLK Driven Low (weak)
69 M Driven Low (weak)
71 P0 Driven Low (weak)
72 P1 Driven Low (weak)
73 P2 Driven Low (weak)
74 P3 Driven Low (weak)
75 P4 Driven Low (weak)
76 P5 Driven Low (weak)
78 P6 Driven Low (weak)
79 P7 Driven Low (weak)
81 P8 Driven Low (weak)
82 P9 Driven Low (weak)
83 P10 Driven Low (weak)
84 P11 Driven Low (weak)
85 P12 Driven Low (weak)
86 P13 Driven Low (weak)
87 P14 Driven Low (weak)
88 P15 Driven Low (weak)
90 P16/CA0 Driven Low (weak)
91 P17/CA1 Driven Low (weak)
92 P18/CA2 Driven Low (weak)
93 P19/CA3 Driven Low (weak)
94 P20/CA4 Driven Low (weak)
95 P21/CA5 Driven Low (weak)
96 P22/CA6 Driven Low (weak)
97 P23/CA7 Driven Low (weak)
62 ENAVDD Driven Low
61 ENAVEE Driven Low
54 ENABKL/A27 Driven Low
65 HSYNC Driven low (weak)
64 VSYNC Driven High (weak)
53 ACTI/A26 Driven low

60,58,57 R.G.B Driven low

— 52 —

Display Memory Output Signal Status During Standby Mode

65550 Pin# Signal Name Signal Status

136 RASA# Driven Low
123 RASB# Driven Low
101 RASC# Driven Low (see note below)
157 WEA# Driven High
124 WEB# Driven High
102 WEC# Driven High (see note below)
160 CASAL# Driven Low
159 CASAH# Driven Low
126 CASBL# Driven Low
125 CASBH# Driven Low
104 CASCL# Driven Low (see note below)
103 CASCH# Driven Low (see note below)
155 OEAB# Driven Low
100 OEC# Driven High (see note below)

154-145 AA9-0 Pulled low with weak resistor

99-90 CA9-0 Driven Low (weak)

177-162 MAD15-0 Pulled low with weak resistor
144-143, MBD15-0 Pulled low with weak resistor
141-140,

138-127
122-109. MCD15-0 Pulled low with weak resistor

107-66 (see note below)

Note: These pins are inputs when using the video input port. These pins are driven as outputs

when using an external STN-DD buffer (DRAM “C”).

— 53 —

Power/ Ground and Standby Control

Pin # Pin Name Type Active Description

178 STNDBY# In Low Standby Control Pin. Pull this pin to place the chip in

Standby Mode.

80 IVCC VCC - Power / Ground (Internal Logic). 5V ±10% or 3.3V ±0.3V.
77 IGND GND - Note that this voltage must be the same as CVCC (voltage for

internal clock synthesizer). This voltage must also be equal
181 IVCC VCC - to or greater than, AVCC (voltage for DAC)
184 IGND GND

9 BVCC VCC - Power / Ground (Bus Interface). 5V ±10% or 3.3V ±0.3V
12 BNGD GND
26 BGND GND

42 BVCC VCC
39 BGND GND
52 BGND GND

66 BVCC VCC - Power / Ground (Bus Interface). 3V ±10% or 3.3V ±0.3V.
63 DGND GND
89 DGND GND

158 MVCCA Power/Ground (Bus Interface). 5V ±10% or 3.3V ±0.3V.
161 MGNDA

142 MVCCB Power / Ground (Bus Interface). 5V ±10% or 3.3V ±0.3V.
139 MGNDB

108 MVCCC Power / Ground (Bus Interface). 5V ±10% or 3.3V ±0.3V.
105 MGNDC

— 54 —

8-2 M5113 : Enhanced Super I/O Controller with Plug & Play

■ Supports Windows 95 Plug and Play

■ Enhanced ESD/LATCH up to over 4KV/300 mA

■ Supports SPP, PS/2, EPP and ECP parallel port

■ Enhanced UART (16550)

■ Supports IR from UART1, UART2 and two additional IR pins

■ Single-chip Notebook/Desktop solution

■ Supports 2.88-MB/1.44-MB/1.2-MB/720-KB/360-KB FDD formats

■Supports Windows 95 Plug and Play

■Supports FDC through Parallel port pins

■2.88MB Floppy Disk Controller

- Software compatible with 82077 and supports 16-byte
data FIFOS

- High performance internal data separator (No­external filter components required)

- Supports standard 1 Mbps / 500 Kbps /300 Kbps/250
Kbps data rate

- Supports 3 modes of 3.5" FDD (720K/1.2M/1.44MB)

- Swappable drives A and B

- Secondary Address Option

■Serial ports

- Two high performance 16550 compatible UARTs with
send/receive 16-byte FIFOs

- Programmable Baud Rate Generator up to 230K and
460K baud

- Serial Infra Red (SIR) and Amplitude Shift Keyed IR
(ASKIR) for wireless communications

- MIDI (Musical Instrument Digital Interface) compatible

- Supports IR from UART1 and UART2 or two additional
IR pins (S/W controls these two directions)

- Supports serial ports Plug-n-Play minimum 4 IRQS to
all IRQS (If connected systems Pnp SIRQI)

■Multi-mode Parallel Port

- Standard mode

- IBM PC/XT, PC/AT and PS/2 compatible Bi­directional parallel port

- Enhanced mode

- Enhanced Parallel Port (EPP) compatible

- High speed mode

- Supports Parallel port PnP min 3 IRQS to all IRQS (If
connected system’s PnP SIRQII)

- Microsoft and Hewlett Packard Extended Capabilities
Port (ECP) compatible

- includes protection circuit against damage caused
when printer is powered up, or operated at higher
voltages

- Supports ECP Plug and Play for DRQ1/DACK1 or
DRQ3/DACK3

- Supports PDIR for 1284 level 2 Compliance

■High performance Power Management for FDC, UART
and Parallel Port

■100-pin PQFP package, 0.6 µ CMOS process

— 55 —

Pin Description

The following table lists the functions of all M5113 pins. A low represents a logic 0 (0V nominal) and a high represents a logic 1 (+2.4v
nominal).

Name Number Type Description

HOST Processor Interface

D0-D7 18-51, 53-56 I/O24 Data bus. This connection is used by the host microprocessor to transmit data

to and from the M5113. These pins are in a high Impedance state when not in
the output mode.

IORJ 44 I I/O Read. This active low signal is issued by the host microprocessor to

indicate a read operation.

IOWJ 45 I I/O Write. This active low signal Is issued by the host microprocessor to

indicate a write operation.

AEN 46 I Address Enable. This active high signal indicates DMA operations on the host

data bus.

A0-A9 27, 29-34, I I/O Address. These bits determine the I/O address to be accessed during IORJ

41-43 and IOWJ cycles.

DACKA/ 28 I DMA Acknowledge. An active low input signal acknowledging the request for

a DMA transfer of data between the host and the printer port. This input
enables the DMA read or write internally.

PADCF O4 This active high signal is read and latched during reset active.

FDRQ 52 O24 FDC DMA request. This active high output is the DMA request for byte

transfers of data to the host. This signal is cleared on the last byte of the data
transfer by the DACKJ signal going low (or by IORJ going low if DACKJ was
already low as in demand mode.

DACKJ 36 I DMA acknowledge. This active low Input acknowledging the request for a

DMA transfer of data. This input enables the DMA read or write internally.

TC 35 I Terminal Count. This signal indicates to the M5113 that data transfer is

complete. TC is only accepted when DACKJ or PDACKJ is low. In AT, TC is
active high and in PS/2 mode, TC is active low.

UR1IRQA 38 O24 Primary Serial Port Interrupt. UR1IRQA is a source of PSP interrupt.

Externally, it should be connected to IRQ4 on PC/AT.

UR2IRQA 37 O24 Secondary Serial Port Interrupt. UR2IRQA is a source of SSP interrupt.

Externally, it should be connected to IRQ3 on PC/AT.

FINTR 40 O24 FDC Interrupt Request. This interrupt from the Floppy Disk Controller is

enabled/disabled via bit 3 of the Digital Output Register (DOR).

PINTR1 39 O24 Parallel Port Interrupt Request. This request from the Parallel Port is

enabled/disabled via bit 4 of the Parallel Port Control Register.
If EPP or ECP mode is enabled, this output is pulsed low, then released to
allow sharing of interrupts.

RESET 57 IS Reset. This active high signal resets the M5113 and must be valid for 500 ns

minimum. In M5113, the falling edge of reset latches the jumper configuration.
The jumper select lines must be valid 50 ns prior to this edge.

RDATAJ 16 IS Read Disk Data. The active-low, raw data read from the disk is connected

WGATEJ 10 O36 Write Gate. This active-low, high drive output enables the write circuitry of the

here. Each falling edge represents a flux transition of the encoded data.

selected disk drive. This signal prevents glitches during power-up and power­down. This prevents writing to the disk when power is cycled.

— 56 —

Name Number Type Description

Floppy Disk interface

WDATAJ 9 O36 Write Data. This active low output is a write- precompensated serial data to be

written onto the selected disk drive. Each falling edge causes a flux change on
the media.

HDSELJ 11 O36 Head Select. This active low output determines which disk drive head is active.

Low=Head 0, high (open) = Head 1.

DIRJ 7 O36 Direction. This active low output determines the direction of the head

movement (low = step-in, high = step-out). During the write or read modes, this
output is high.

STEPJ 8 O36 Step. This active low output produces a pulse at a software-programmable rate

to move the head during a seek operation.

DSKCHGJ 17 IS Disk Change. This disk interface input indicates when the disk drive door has

been opened. This active-low signal is read from bit D7 of address xx7h.

DSOJ, 4, 3 O36 Drive Select 0, 1. Active low, output select drives 0-1.

DSIJ

PDIR 99 O36 This bit is used to indicate the direction of the Parallel port data bus. 0=

output/write, 1= input/ read.

A10 97 I This pin is the A10 address input.

MTROJ, 2, 5 O35 Motor on 0, 1. These active low outputs select motor drives 0-1.

MTR1J

DACKB 96 I This signal is the Parallel port DMA acknowledge input.

DRQB 98 O36 In ECP mode, This is the Parallel Port DMA Request output active high signal.

DENSEL 1 O36 Density select. This signal indicates whether a low (250/300 kbps) or high

(500 kbps) data rate has been selected. This is determined by the DENSEL bits
in Configuration register 5.

WRTPRTJ 14 IS Write Protected. This active-low Schmitt Trigger input senses from the disk

drive that a disk is write-protected. An write command is ignored.

TRK0J 13 IS Track 00. This active low Schmitt Trigger input senses from the disk drive that

the head is positioned over the outermost track.

INDEXJ 12 IS Index. This active low Schmitt Trigger input senses from the disk drive that the

head is positioned over the beginning of a track, as marked by an index hole.

UR1IRQB 18 I/O36 Serial Port Interrupt Request. Alternate IRQ output from UART1, refer to CRO

bit 6.

DRATE0 19 I/O36 Data Rate 0. This output reflects bit 0 of the Data Rate Register. At power on,

this output is in a high impedance state.

Serial Port Interface

RXD1, 78,88 I Receive Data. Receiver serial data input.

RXD2

TXD1, 79 O4 Transmit Data. Transmitter serial data output from Primary Serial Port.

PCF0 Parallel Port configuration control 0. During reset active, this input signal is

read and latched to define the address of the Parallel port.

— 57 —

Name Number Type Description

RTS1J 81 O4 Request to send. Active low Request to send output for Primary Serial port.

Handshake output signal notifies modem that the UART is ready to transmit
data. This signal can be programmed by writing to bit 1 of Modem Control
Register (MCR). The hardware reset will clear the RTSJ signal to inactive mode
(high). Forced inactive during loop mode operation.

PCF I Parallel port configuration control 1. During reset active, this input is read

and latched to define the address of the Parallel port.

RTS2J 91 O4 Request to send. This active low output for Secondary Serial Port.

Handshake output signal notifies modem that the UART is ready to transmit
data. This signal can be programmed by writing to bit 1 of Modem Control
Register (MCR). The hardware reset will clear the RTSJ signal to inactive mode
(high). Forced inactive during loop mode operation.

S2CFO Secondary serial port configuration control 0. During reset active, this input

is read and latched to define the address of the Secondary serial port.

DTR1J 83 O4 Data Terminal Ready. This is an active low output for primary serial port.

Handshake output signal signifies modem that the UART is ready to establish
data communication link. This signal can be programmed by writing to bit 0 of
Modem Control Register (MCR). The hardware reset will clear the DTRJ signal
to inactive during loop mode operation.

IDECF I IDE Configuration control. When active, this input is read and latched to

enable, disable the IDE

DTR2J 9 O4 Data Terminal Ready. This active low output is for secondary serial port.

Handshake output signal notifies modem that the UART is ready to establish
data communication link. This signal can be programmed by writing to bit 0 of
Modem Control Register (MCR). The hardware reset will clear the DTRJ signal
to inactive mode (high). Forced inactive during loop mode operation.

S2GF1 I Secondary serial port configuration control 1. When active, this input is

read and latched to define the address of the Secondary Serial port.

TXD2 89 O4 Transmitter Serial Data output from Secondary Serial Port.

FDCCF I Floppy Disk Configuration. This input is read and latched during Reset to

enable/disable the Floppy Disk Controller.

CTS1J 82, 92 I Clear to Send. This active low input for primary and secondary serial ports.
CTS2J Handshake signal which notifies the UART that the modem is ready to receive

data. The CPU can monitor the status of CTSJ signal by reading bit 4 Modem
status Register (MSR). A CTSJ signal state change from low to high after the
last MSR read will set MSR bit 0 to a 1. If bit 3 of Interrupt Enable Register is
set, the Interrupt is generated when CTSJ changes state. The CTSJ signal has
no effect on the transmitter. Note: Bit 4 of MSR is the complement of CTSJ.

DSR1J 80, 90 I Data Set Ready. This active low input is for primary and secondary serial
DSR2J ports. Handshake signal which notifies the UART that the modem is ready to

establish the communication link. The CPU can monitor the status of DSRJ
signal by reading bit5 of Modem Status Register (MSR). A DSRJ signal state
change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit
3 of Interrupt Enable Register is set, the interrupt is generated when DSRJ
changes state. Note: Bit 5 of MSR is the complement of DSRJ.

DCD1J, 85, 87 I Data Carrier Detect. This active low input is for primary and secondary serial

DCD2J ports. Handshake signal which notifies the UART that carrier signal is detected

by the modem. The CPU can monitor the status of DCDJ signal by reading bit
7 of Modem Status Register (MSR). A DCDJ signal state changes from low to
high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is generated when DCDJ changes state.
Note : bit 7 of MSR is the complement of DCDJ.

— 58 —

Name Number Type Description

RI1J, RI2J 84, 86 I Ring Indicator. This active low input is for primary and secondary serial ports.

Handshake signal which notifies the UART that the telephone ring signal is
detected by the modem. The CPU can monitor the status of RIJ signal by
reading bit 6 of Modem Status Register (MSR). An RIJ signal state change
from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of
Interrupt Enable Register is set, the interrupt is generated when RIJ changes
state. Note: bit 6 of MSR is the complement of RIJ.

DRV2 94 I Drive 2. In PS/2 mode, this input indicates whether a second drive is

connected; this signal should be low if a second drive is connected. This status
is reflected in a read of Status Register A.

ADRxJ O24 Optional I/O port address decode output. Defaults to tri-state after power-

up. This pin has 30 µA internal pull-up.
This interrupt from the parallel port enabled/disabled via bit 4 of the Parallel

PINTR2 O24 Port Control Register. Refer to Configuration Registers CRC for more

Information.

ECPEN l Enhanced parallel port mode select. Read and latched during reset active.

SLCTINJ 73 O20 Printer select input. This active low signal selects the printer. This is the

complement of bit 3 or the Printer Control Register.

INITJ 74 O20 Initiate Output. This active low signal is bit 2 of the printer control register.

This is used to initiate the printer when low.

AUTOFDJ 76 O20 Autofeed Output. This active low output causes the printer to automatically

feed one line after each line is printed. This signal is the complement of bit 1 of
the Printer Control Register.

STROBEJ 77 O20 Strobe Output. This active low pulse is used to strobe the printer data into the

printer. This output signal is the complement of bit 0 of the Printer Control
Register.

BUSY 61 I Busy. This signal indicates the status of the printer. A high indicates the

printer is busy and not ready to receive new data. Bit 7 of the Printer Status
Register is the complement of the BUSY input.

ACKJ 62 I Acknowledge. This active low output from the printer indicates it has received

the data and is ready to accept new data. Bit 6 of the Printer Status Register
reads the ACKJ input.

PE 60 I Paper End. This signal indicates that the printer is out of paper. Bit 5 of the

Printer Status Register reads the PE input.

SLCT 59 I Printer Selected Status. This active high output from the printer indicates that

it has power on. Bit4 of the Printer Status Register reads the SLCT input. .

ERRORJ 75 I Error. This active low signal indicates an error condition at the printer.

PD0-PD7 71, 68, 66, 63 I/O20 Port Data. Thls bi-directional parallel data bus is used to transfer information

between CPU and peripherals.

IOCHRDY 100 OD24 IOCHRDY. In EPP mode, this pin is pulled low to extend the read/write

command.

DRQA/ 23 O24 DMA Request. Alternate DMA request output for parallel port. Refer to CR5 bit

3

SICF1 I Primary Serial Configuration 1. Read and latched during reset active to select

the address of the Primary Serial Port.

PINTR3/ 24 O24 Parallel Port Interrupt Request. Alternate IRQ output from Parallel Port.

SICF0 Refer to CR0 bit 4 for more information.

I Primary Serial Configuration 0. Read and latched during reset active to

define the address of the Primary Serial Port.

— 59 —

Name Number Type Description

IRTX2 25 O16 Alternate IR Transmit output.

IRRX2 26 O16 Alternate IR Receive input.

FACF Floppy Disk Address Control. This signal is read and latched during reset

active.

UR21RQB 22 I/O24 Serial Port Interrupt Request. Alternate IRQ output from UART2, refer to CR0

bit 5.

Miscellaneous

PWRGD 58 I Power Good. This input signal indicates that the power is valid. For device

operation, PWRGD must be active.

X1/CLK1 20 ICLK Clock 1. This external connection for a parallel resonant 24 MHz crystal. A

CMOS compatible oscillator is required if crystal is not used.

X2/CLK2 21 OCLK Clock 2. This is a 24 MHz crystal. If an external clock is used, this pin should

not be connected. This pin should not be used to drive an other drivers.

Vcc 15, 72 P Power. +5 Volt supply pin.

Vss 6, 47, 67, 95 Ground pins.

Type Descriptions:

I Input TTL compatible

IS Input with Schmitt trigger
I/O20 Input/Output with 20 mA sink @ 0.4 V, source 8 mA @ 2.4 V
I/O24 Input/Output with 24 mA sink @ 0.4 V, source 8 mA @ 2.4 V
I/O36 Input/Output with 36 mA sink @ 0.4 V, source 8 mA @ 2.4 V

ICLK CLK input at 24 MHz

OCLK CLK output at 24 MHz

O4 Output with 4 mA sink @ 0.4 V, source 4 mA @ 2.4 V.
O16 Output with 16 mA sink @ 0.4 V, source 8 mA @ 2.4 V.
O20 Output with 14 mA sink @ 0.4 V, source 14 mA @ 2.4 v,
O24 Output with 24 mA sink @ 0.4 V, source 12 mA @ 2.4 V.
O36 Output with 36 mA sink @ 0.4 V, source 8 mA @ 2.4 V.

OD24 Open drain outputs, sinks 24 mA @ 0.4 V.
OD36 Open drain outputs, sinks 36 mA @ 0.4 V.

— 60 —

8-3 UM9008: ISA/Plug & Play SuperEthernet Controller

Features

■Single chip solution for IEEE 802.3. 10BASE-T,
10BASE2 and 10BASE5

■Integrated ISA interface, 8Kx16 SRAM, Media Access
Control. ENDEC, and 10BASE-T transceiver

■Support ISA Plug and Play configuration function

■Software compatible with NOVELL NE2000

■Support PnP and Non-PnP Auto-Switch function

■PnP, Non-PnP, and Auto switch mode selectable by

software settings

■6 interrupt lines selectable

■Auto-Polarity detection and correction

■8 or 16-bit slot mode selectable

General Description

The UM9008 Ethernet controller is a super integrated
design to provide all Medial Access Control (MAC)
and the Encode-Decode (ENDEC) functions in accordance
with the IEEE 802.3 standard. The UM9008 provides
the network interfaces include 10BASE5 or 10BASE2
Ethernet via the AUI port and 10BASE-T via the
Twisted-pair. The UM9008 Ethernet controller can
also interface directly to PC-AT ISA bus without
any external device. The interface to PC-AT ISA
bus is fully compatible with NE2000 Ethernet adapter

■Provide 10BASE-T transceiver and Attachment Unit
Interface (AUI) auto detect and auto-Switch
function

■External EEPROM programmable

■Support BOOT ROM page mode

■Loopback capability for diagnostics

■Receiver and collision squeich circuit to reject

noise

■Low-power CMOS process with single 5V power supply

■Built-in predistortion resisters in 10BASE-T

application

■100-pin OFP package

cards, so all software programs designed for NE2000
can run on the UM9008 card without any modification.
The UM9006 Support both Microsoft’s Plug and Play and
the jumperless software configuration function. The
capability of the PnP and Non-PnP mode auto-Switch
function allows users to configure network card, truly
PnP. No any jumper or Switch is needed IO setting,
either the PC with PnP function or not. The integrated
8 x 16 SRAM and 10BASE-T transceiver make UM9008
more cost-effectively.

— 61 —

Pin Description

Pin No. Symbol I/O Description

PC ISA BUS INTERFACE PINS

96-99 SA0-SA3 I SYSTEM ADDRESS: These signals are connected to the address

3-5 SA4-SA6 bus of the PC I/O slot. They are used to select the UM9008

7 SA7 I/O ports or the boot ROM address

9 SA8
11-13 SA9-SA11
15-18 SA14-SA17

21, 22 SA18, SA19

26-33 SDO-SD7 I/O, Z SYSTEM DATA: These Signals are connected to the data bus of
88-81 SD8-SD15 the PC I/O bus slot. They are used to transfer data between

the PC and the UM9008

2 BALE I ADDRESS LATCH ENABLE: PC ISA bus BALE Signal; used only

to define the timing of IOCHRDY in Remote DMA

14 SYSCLK I SYSTEM CLOCK: PC ISA bus system clock

19 IOR I I/O READ: An active low signal used to read data from the

UM9008

21 IOW I I/O WRITE: An active low signal used to write data to the

UM9008

23 SMEMR I MEMORY READ: An active low signal used to read boot ROM data

35 RST I RESET: An active high signal used to power-on reset the UM9008

24 AEN I ADDRESS ENABLE: This is an active low signal used to enable the

system address for the UM9008

25 IOCHRDY O,Z I/O CHANNEL READY: The UM9008 sets this signal low to insert

wait states into the PC ISA bus

89 MEMW I MEMORY WRITE: PC ISA bus memory write Signal

90 MEMR I MEMORY READ: PC ISA bus memory read signal

95 IO16 O, Z 16-BIT I/O: This signal goes low when the data transfer between

the UM9008 and the PC ISA bus is word wide

6 IRQ3 O, Z INTERRUPT REQUESTS: These are 8 interrupt request pins. Only

8 IRQ4 one pin, which is decoded from Configuration Register A, can

10 IRQ5 be activated; the other pins are left floating. The activated
34 IRQ9 pin will go high when an interrupt request is generated from

94-92 IRQ10-12 the ENC module of the UM9008

91 IRQ15

MEMORY INTERFACE PINS

79 EECS O EEPROM CHIP SELECT: This signal goes high when the EEPROM is

selected by the UM9008

80 8PCS O BOOT ROM CHIP SELECT: This Signal goes low when the PC reads

the boot ROM data

— 62 —

Pin No. Symbol I/O Description

64-71 MD0-MD7 I/O, Z MEMORY DATA BUS: These are the memory data signals for the

boot ROM
When the EEPROM is loaded or written, MD0, 1, 2 are used as
the EEPROM signals

(64) (EED1) • EEPROM DATA IN: This pin is used as the serial input data

signal from the EEPROM

(65) (EED0) • EEPROM DATA OUT: This pin is used as the serial output data

signal to the EEPROM

(66) (EECK) • EEPROM CLOCK: This pin is used as the EEPROM clock signal

These memory data pins can also be used as switches when the
UM9008 is in reset state. There is an approximately 100K pull­low resistor on each pin, and a 10K pull-high resistor can be

connected to a pin when it is switched to logic high
(69) (BNCSW) • When this pin pulled high upon reset, pin 54 outputs 312.5KHz
(70) (SLOT) . • SLOT SELECTION: When this pin is pulled to high, the UM9008

is in NE2000 16-bit mode

63-56 PA0-PA7 O BOOT ROM PAGE ADDRESS. When the boot ROM is accessed, PA0-PA7

are used as the page address of the boot ROM

NETWORK INTERFACE PINS

37 TX - O TRANSMIT OUTPUT: Differential line driver which sends the encoded
38 TX+ data to the transceiver. The outputs are source followers which

require 270 ohm pull-down resistors

54 BNCEN O BNC OUTPUT ENABLE: This pin goes high if the value of the

Configuration Register B bit 1 is low and bit 0 is high.

Typically, this pin is used to control the DC-DC converter to

enable or disable the UM9092A (Coaxial Transceiver Interface)

• Output 312.5KHz clock: when the 69 pin (BNCSW) is pulled high,
this pin output 312.5KHz clock

78 XI CRYSTAL or EXTERNAL CLOCK INPUT

77 X2 O CRYSTAL FEEDBACK OUTPUT: Used in crystal connection only. Left

open when using an external clock

NETWORK INTERFACE PINS

39 RX- I RECEIVE INPUT: Differential receive input pair from the
40 RX+ transceiver

41 CD- I COLLISION INPUT: Differential collision input pair from the
42 CD+ transceiver

50 TPTX+ O TP Driver Outputs. These two outputs provide the TP drivers with
49 TPTX- pre-distortion capability

46 TPRX + I TP Receive Input. A differential receiver tie to the receive
45 TPRX- transformer pair of the twisted-pair wire.

The receive pair of the twisted-pair medium is driven with
10 Mbits/s Manchester-encoded data

55 LILED OPEN LINK and Traffic LED Driver: If TP is LINK-pass, this pin outputs

DRAIN low. This pin will go low for 80 ohms and then into high impedance

state for 50ms to indicate the presence of traffic on the network

76 NC No connection

— 63 —

POWER SUPPLY PINS

36, 47, 48 AVCC +5V DC power supply for analog CKT. A decoupling capacitor should

be connected between these pins and GND for analog CKT

43, 44, 51 AGND GND for analog CKT

1, 53, 72 VCC +5V DC power supply for digital CKT. A decoupling capacitor should

be connected betwneen these pins and GND for digital CKT

52,73,74,

75.100

GND GND for digital CKT

GND

SA3

SA2

SA1

SA0

1016

IRQ10

IRQ11

IRQ12

IRQ15

WCLR

99989796959493929190898887868584838281

VCC

BALE

SA4
SA5
SA6

IRQ3

SA7

IRQ4

SA8

IRQ5

SA9
SA10
SA11

SYSCLK

SA14
SA15
SA16
SA17

IOW

SA18

IOW

SA19

SREKA

ALEN

LOCLAOY

SD0

SD1

SD2

SD3

SD4

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

UM9008F

WCWH

SD8

SD9

SD10

SD11

SD12

SD13

SD14

SD15

50

80

BPC5

79

EEC5

78

X1

77

X2

76

MC

75

CM0

74

CN0

73

CM0

72

VCC

71

MO7

70

MO6/

69

MOS/

68

ND4

67

ND3

66

ND2/EECX

65

MD1/EEDO

64

MD0/EEDI

63

PA0

62

PA1

61

PA2

60

PA3

59

PA4

58

PA5

57

PA6

56

PA7

55

LILCD

54

BMCEN

53

VCC

52

GND

51

GND

SD5

SD6

SD7

IRQ9

R51

AVCC

IX-

IX+

AX-

CD-

AX+

— 64 —

CD+

AGND

AGND

IPRX-

IPRX+

AVCC

AVCC

IPIX-

IPIX+

8-4 VT82580

1. VT82C585VP

PIN DESCRIPTION

Signal Name Pin No. Power I/O Signal Description

CLOCK CONTROL

NCLK 59 cpu I HOST CLOCK: This pin receives a buffered host

clock. This clock is used by all of the VT82C585VP
logic that is in the Host clock domain. This should be
the same clock net that is delivered to the CPU.

PCLK 9 cpu I PCI CLOCK: This pin receives a buffered divided-by-

2 host clock. This clock is used by all of the
VT82C585VP logic that is in the PCI clock domain

RESET CONTROL

RESET# 52 pci I RESET: When asserted, this signal resets the

VT82C585VP and sets all register bits to the default
value.

CPU INTERFACE

ADS# 66 cpu I ADDRESS STROBE: The CPU asserts ADS# in T1 of

the CPU bus cycle.

M/IO# 54 cpu I MEMORY I/O.

W/R# 69 cpu I WRITE/READ.

D/C# 67 cpu I DATA/CONTROL

BE#[7:0] 44-51 cpu I BYTE ENABLES: The CPU byte enables indicate

which byte lane the current CPU cycle is accessing.

CA[31:3] 20, 22, cpu B ADDRESS BUS: CA[31:3] connect to the address bus

23, 19, of the CPU. During CPU cycles CA[31:3] are inputs.
14, 17, These signals are driven by the VT82C585VP during
18, 13, cache snooping operation.
11, 16,

12, 36-

32, 42,
40, 41,
39, 30,

31,37,
29, 25,
26, 28,

24, 21

BRDY# 62 cpu O BUS READY: The VT82C585VP asserts BDRY# to

indicate to the CPU that data is available on reads or
has been received on writes.

EADS# 65 cpu O EXTERNAL ADDRESS STROBE: Asserted by the

VT82C585VP to inquire the L1 cache when serving
PCI master accesses to main memory.

KEN#/INV 56 cpu O CACHE ENABLE/INVALIDATE: KEN#/INV

HITM# 68 cpu I HIT MODIFIED: Asserted by the CPU to indicate that

functions as both the KEN# signal during CPU read
cycles and the INV signal during L1 cache snoop cycle.

the address presented with the last assertion of EADS#
is modified in the LI cache and needs to be written back.

— 65 —

Signal Name Pin No. Power I/O Signal Description

HLOCK# 53 cpu I HOST LOCK: All CPU cycles sampled with the

assertion of HLOCK# and ADS#, until the negation of
HLOCK# must be atomic.

CACHE# 55 cpu I CACHEABLE: Asserted by the CPU during a read cycle

to indicate the CPU can perform a burst line fill. Asserted
by the CPU during a write cycle to indicate that the CPU
will perform a burst write-back cycle.

AHOLD 57 cpu O ADDRESS HOLD: The VT82C586 asserts AHOLD

when a PCI master is accessing main memory. AHOLD
is held for the duration of the PCI burst transfer.

NA# 63 cpu O NEXT ADDRESS:

BOFF# 64 cpu O BACK OFF: Asserted by the VT82C585VP when

required to terminate a CPU cycle that was in progress.

SMIACT# 58 cpu I SYSTEM MANAGEMENT INTERRUPT ACTIVE:

This is asserted by the CPU when it is in system
management mode as a result of SMI.

CACHE CONTROL

COE# 72 cpu O CACHE SRAM OUTPUT ENABLE:

CWE#[7;0] / 76-73, cpu O Multi-function pins:

SWE#A-B, 93-90 Global write option off (bit 2 of RX54h is 0): Cache
SRAS#A-B, SRAM write enable or each byte.
SCAS#A-B,

BWE#, Global write option on (bit 2 of RX 54h is 1):
GWE# Synchronous DRAM command indicators and

BWE#/GWE# for global write SRAM control.

TWE# 89 cpu O TAG WRITE ENABLE: When asserted, new state and

tag addresses are written into the external tag.

A3SEL/ 71 cpu O CACHE ADDRESS 3/CACHE ADDRESS STROBE:

CADS# This pin has two modes depending on the type of SRA

selected.
Async. SRAM: A3SEL is used to sequence through the
Qwords in a cache line during a burst operation.

Sync. SRAM: Its assertion causes the burst SRAM load
the BSRAM address register from BSRAM address pin.

A4SEL/ 70 cpu O CACHE ADDRESS 4/CACHE ADVANCE:

CADV# This pin has two modes depending on the type of SRA

selected.
Async. SRAM: A4SEL is used to sequence through the
Qwords in a cache line during a burst operation.

Sync. SRAM: its assertion causes the burst SRAM to
advance to advance to the next Qword in the cache line.

TA[9] / DB32 88, 87, cpu B TAG ADDRESS: These are inputs during CPU accesses

TA[8:0] 80, 81, and outputs during L2 cache line fills and L2 line

82, 85, invalidates during inquire cycles.

86, 79-77 TA9 is a multi-function pin. It will act as DB32 to

VT82C587VP when 32bit DRAM mode is enable.

— 66 —

CALE/CE1# 94 cpu O CACHE ADDRESS LATCH/CHIP ENABLE 1: This pin

has two modes depending on the type of SRAM
selected.

1. Async. SRAM: CALE is used to control the cache
address latches.

2. Sync. SRAM: CE1 is used as chip -select 1 for the
BSRAM.

DRAM CONTROL

MA[11:0] 125-120, dram O MEMORY ADDRESS: DRAM address lines.

118-115,
113, 112

RAS#[5:4] 103, 102 dram O ROW ADDRESS STROBE of each bank for

FPG/EDO/BEDO DRAM.

RAS#[3:0]/ 99-98, Multi-functional pins:

CS#[3:0] 101-100 1. FPG/EDO/BEDO DRAM: ROW ADDRESS

STROBE of each bank.

2. Synchronous DRAM: chip select of each bank.

CAS#[7:0]/ 104, 110, dram O Multi-functional pins:
DQM#[7:0] 106, 108, 1. FPG/EDO/BEDO DRAM: COLUMN ADDRESS

105, 111, STROBE of each byte line.
107, 109 2. Synchronous DRAM: data mask of each byte lane.

WE# 95 dram O DRAM write enable.

SRAS#A-B 73,74 dram O ROW ADDRESS COMMAND INDICATOR: for

Synchronous DRAM, two identical copies for better
driving.

SCAS#A-B 92, 93 dram O COLUMN ADDRESS COMMAND INDICATOR: for

Synchronous DRAM, two identical copies for better
driving.

SWE#A-B 75, 76 dram O WRITE ENABLE COMMAND INDICATOR: for

Synchronous DRAM, two identical copies for better
driving.

UNIFIED MEMORY INTERFACE

MREQ0# 163 dram I MEMORY REQUEST 0: This pin is asserted by the

graphic controller to get access to local DRAM.

MREQ1# 166 dram I MEMORY REQUEST 1: This pin is asserted by the

graphic controller to get access to local DRAM (It is
reserved if 2 pin protocol selected)

MGNT# 162 dram O MEMORY GRANT: VT82C585VP assert this pin to

relinquish DRAM bus to graphic controller.

DGNT# 126 dram O DATA GRANT: Controls external buffer for UMA

interface.

VT82C587VP INTERFACE

DB32 88 cpu B DRAM WIDTH: to control VT82C587VP if 32-bit

DRAM is used.

PLINK[15:0] 151-148, dram B PCI LINK: This is the data path between the CPU/main

146-143, memory and PCI. PCI main memory reads and CPU to PCI

134-127 writes are driven onto these pins by the VT82C587VP. CPU

reads from PCI and PCI writes to main memory are received
on this bus by the VT82C587VP. Each VT82C587VP
connected to one byte of this bus.

— 67 —

MSTB# 135 dram O MEMORY STROBE: Assertion causes data to be posted

in the DRAM Write Buffer.

HSTB# 136 dram O HOST STROBE: Assertion causes data to be posted in

the CPU Read Buffer.

CMD[4:0] 141-137 dram O COMMAND: VT82C585VP uses these signals to control

the buffers in VT82C587VP.

PCI Bus Interface

FRAME# 188 pci B FRAME: Assertion indicates the address phase of a PCI

transfer. Negation indicates that one more data transfer
is desired by the cycle initiator.

AD[31:0] 167- pci B ADDRESS DATA BUS: The standard PCI address and

174, data lines. The address is driven with FRAME#
177- assertion and data is driven or received in following
182, cycles.
185,
186,
197­199,
202­206,

208, 2-8

C/BE#[3:0] 176, pci B COMMAND, BYTE ENABLE: The command is

187, driven with FRAME# assertion. Byte enables
196, corresponding to supplied or requested data are driven

207 on following clocks.

IRDY# 189 pci B INITIATOR READY: Asserted when the initiator is

ready for data transfer.

TRDY# 190 pci B TARGET READY: Asserted when the target is ready

for data transfer.

STOP# 192 pci B STOP: Asserted by the target to request the master to

stop the current transaction.

DEVSEL# 191 pci B DEVICE SELECT: This signal is driven by the

VT82C585VP when a PCI initiator is attempting to
access main memory- It is an input when VT82C585VP
is acted as a PCI initiator.

PAR 194 pci B PARITY: A single parity bit is provided over AD[31:0]

and C/BE[3:0].

SERR# 195 pci B SYSTEM ERROR: VT82C5285VP will pulse this signal

when it detect a system error condition.

LOCK# 193 pci B LOCK: Used to establish, maintain, and release

resource lock on PCI

PREQ# 153 pci I PCI REQUEST: This signal comes from VT82C586.

PREQ# is the VT82C586 request for the PCI bus.

PGNT# 152 pci O PCI GRANT: This signal driven by the VT82C585VP

to grant PCI access to VT82C586.

REQ#[3:0] 155, pci I REQUEST: PCI master requests for PCI.

157,
159,

161

— 68 —

GNT#[3:0] 154, pci O GRANT: Permission is given to the master to use PCI.

156,
158,

160

POWER AND GROUND

VDD_CPU 10, 43, cpu I Power supply for the CPU bus.

61, 84

VDD_PCI 184, 201 pci I Power supply for PCI bus.

VDD 147, 165 I Power supply

VDD_DRAM 97, 114, dram 1 Power supply for the DRAM bus.

VSS 1, 15, 27, 0v I Ground

38, 60,
83, 96,

119, 142

164, 175,

183, 200

— 69 —

PIN OUT IN NUMERICAL ORDER

Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name

1 VSS 53 HLOCK# 105 CAS3# / DQM3# 157 REQ2#
2 AD6 54 M/IO# 106 CAS5# / DQM5# 158 GNTI#
3 AD5 55 CAHCE# 107 CAS1#/DQM1# 159 REQ1#
4 AD4 56 KEN# 108 CAS4# / DQM4# 160 GNT0#
5 AD3 57 AHOLD 109 CAS0# / DQM0# 161 REQ0#
6 AD2 58 SMIACT# 110 CAS6# / DQM6# 162 MGNT#
7 AD1 59 HCLK 111 CAS2# / DQM2# 163 MREQ0#
8 AD0 60 VSS 112 MA0 164 VSS

9 PCLK 61 VDD-cpu 113 MA1 165 VDD
10 VDD-cpu 62 BRDY# 114 VDD-dram 166 MREQ1#
11 CA23 63 NA# 115 MA2 167 AD3l
12 CA21 64 BOFF# 116 MA3 168 AD30
13 CA24 65 EADS# 117 MA4 169 AD29
14 CA27 66 ADS# 118 MA5 170 AD28
15 VSS 67 D/C 119 VSS 171 AD27
16 CA22 68 HITM# 120 MA6 172 AD26
17 CA26 69 W/R 121 MA7 173 AD25
18 CA25 70 A4SEL/CADV# 122 MA8 174 AD24
19 CA28 71 A3SEL/CADS# 123 MA9 175 VSS
20 CA31 72 COE# 124 MA10 176 CBE3#
21 CA3 73 CWE4#/SRASA# 125 MA11 177 AD23
22 CA30 74 CWE5# / SRASB# 126 DGNT# 178 AD22
23 CA29 75 CWE6# / SWEA# 127 PLINK0 179 AD21
24 CA4 76 CWE7# / SWEB# 128 PLINK1 180 AD20
25 CA7 77 TA0 129 PLINK2 181 AD19
26 CA6 78 TA1 130 TLINK3 182 AD18
27 VSS 79 TA2 131 PLINK4 183 VSS
28 CA5 80 TA7 132 PLINK5 184 VDD-pci
29 CA8 81 TA6 133 TLINK6 185 AD17
30 CA11 82 TA5 134 PLINK7 186 AD16
31 CA10 83 VSS 135 MSTB# 187 CBE2#
32 CA16 84 VDD-cpu 136 HSTB# 188 FRAME#
33 CA17 85 TA4 137 CMD0 189 IRDY#
34 CA18 86 TA3 138 CMD1 190 TRDY#
35 CA19 87 TA8 139 CMD2 191 DEVSEL#
36 CA20 88 TA9/DB32 140 CMD3 192 STOP#
37 CA9 89 TWE# 141 CMD4 193 LOCK#
38 VSS 90 CWE0#/GWE# 142 VSS 194 PAR
39 CA12 91 CWE1#/BWE# 143 PLINK8 195 SERR#
40 CA14 92 CWE2# / SCASA# 144 PLINK9 196 CBE1#
41 CA13 93 CWE3# /SCASB# 145 PLINK10 197 AD15
42 CA15 94 CALE/CE1# 146 PLINK11 198 AD14
43 VDD-cpu 95 WE# 147 VDD 199 AD13
44 BE7# 96 VSS 148 PLINK12 200 VSS
45 BE6# 97 VDD-dram 149 PLINK13 201 VDD-pci
46 BE5# 98 RAS2#/CS2# 150 PLINK14 202 AD12
47 BE4# 99 RAS3# /CS3# 151 PLINK15 203 AD11
48 BE3# 100 RAS0#/CS0# 152 PGNT# 204 AD10
49 BE2# 101 RAS1#/XS1# 153 PREQ# 205 AD9
50 BE1# 102 RAS4# 154 GNT3# 206 AD8
51 BE0# 103 RAS5# 155 REQ3# 207 CBE0#
52 RESET# 104 CAS7#/DQM7# 156 GNT2# 208 AD7

— 70 —

2. VT82C586

PIN DESCRIPTION

Signal Name Pin No. cpu I/O Signal Description

PCI Bus Interface

PCLK 2 pci I PCI CLOCK: PCLK provides timing for all

transactions on PCI Bus.

FRAME# 181 pci B FRAME: Assertion indicates the address phase of a

PCI transfer. Negation indicates that one more data
transfer is desired by the cycle initiator.

AD[3l:0] 204-199, 196- pci B ADDRESS DATA BUS: The standard PCI address

195, 192-189, and data lines. The address is driven with FRAME#
187-185, 183, assertion and data is driven or received in following
172, 170-167, cycles.
165-163, 161-

158, 155-152

C/BE#[3:0] 194, 182, 173, pci B COMMAND, BYTE ENABLE: The command is

162 driven with FRAME# assertion. Byte enables

corresponding to supplied or requested data are
driven on following clocks.

IRDY# 180 pci B INITIATOR READY: Asserted when the initiator

is ready for data transfer.

TRDY# 179 pci B TARGET READY: Asserted when the target is

ready for data transfer.

STOP# 176 pci B STOP: Asserted by the target to request the master

to stop the current transaction.

DEVSEL# 178 pci B DEVICE SELECT: VT82C586 asserts this signal to

claim PCI transaction through positive or
subtractive decoding.

PAR 174 pci B PARITY: A single parity bit is provided over

AD[31:0] and C/BE[3:0].

SERR# 175 pci I SYSTEM ERROR: SERR# can be pulsed active by

any PCI device that detect a system error condition.
Upon sampling SERR# active, the VT82CS86 can
be programmed to generate a NMI to the CPU.

IDSEL 193 pci I INITIALIZATION DEVICE SELECT: IDSEL is

used as a chip select during configuration read and
write cycles.

PIRQA-D# 1, 207-205 pci I PCI INTERRUPT REQUEST:

PREQ# 151 cpu O PCI REQUEST: This signal go to VT82C585VP.

PREQ# is the VT82C586 request for the PCI bus.

PGNT# I50 cpu I PCI GRANT: This signal driven by the

VT82CS85VP to grant PCI access to VT82C586.

SA[15:0]/ 20-25, 27-28, 5v B SYSTEM ADDRESS BUS/IDE DATA BUS:

DD[15:0] 36-38, 40-44

SA16 19 5v B SYSTEM ADDRESS BUS:

ISA BUS- CONTROL

— 71 —

LA23/DCS3B#, 63-67, 69-70 5v B Multifunction Pins:
LA22/DCS1B#, ISA Bus Cycles:
LA21/DCS3A#, UNLATCHED ADDRESS: The LA[23:17]
LA20/DCS1A#, address lines are bi-directional. These address

LA[19:17]/ lines allow accesses to physical memory on ISA

DA[2:0] bus up to 16mbytes.

PCI IDE Cycles:
CHIP SELECT: DCSIA# is for the ATA
command register block and corresponds to
CS1FX# on the primary IDE connector. DCS3A#
is for the ATA command register block and
corresponds to CS3FX# on the primary IDE
connector. DCSIB# is for the ATA command
register block and corresponds to CS17X# on the
primary IDE connector. DCS3B# is for the ATA
command register block and corresponds to
CS37X# on the primary IDE connector.
DISK ADDRESS: DA[2:O] are used to indicate
which byte in either the ATA command block or
control block is being access.

SD[15:8] 86-85, 83-80, 5v B SYSTEM DATA: SD[15:8] provide the high order

78-77 byte data path for devices residing on the ISA bus.

SBHE# 62 5v B SYSTEM BYTE HIGH ENABLE: SBHE# indicates,

when asserted, that a byte is being transferred on the
upper byte (SD[15:8]) of the data bus. SBHE# is
negated during refresh cycles.

IOR# 12 5v B I/O READ: IOR# is the command to an ISA I/O slave

device that the slave may drive data on to the ISA
data bus.

IOW# 11 5v B I/O WRITE: IOW# is the command to an ISA I/O

slave device that the slave may latch data from the
ISA data bus.

MEMR# 123 5v B MEMORY READ: MEMR# is the command to a

memory slave that it may drive data onto the ISA
data bus.

MEMW# 124 5v B MEMORY WRITE: MEMW# is the command to a

memory slave that it may latch data from the ISA
data bus.

SMEMR# 10 5v O STANDARD MEMORY READ: SMEMR# is the

command to a memory slave, under 1MB, that it
may drive data onto the ISA data bus

SMEMW# 9 5v O STANDARD MEMORY WRITE: SMEMW# is the

command to a memory slave, under 1MB, that it
may latch data from the ISA data bus.

BALE 35 5v O BUS ADDRESS LATCH ENABLE; BALE is an

active high signal asserted by the VT82586 to
indicate that the address(SA[19:0], LA[23:17] and
SBHE# signal lines are valid

IOCS16# 125 5v I 16-BIT I/O CHIP SELECT: This signal is driven by

I/O devices on the ISA Bus to indicate that they
support 16-bit 1/o bus cycles.

MEMCS16# 76 5v I MEMORY CHIP SELECT 16: ISA slave that are 16

bit memory devices drive this line low to indicate
they support 16-bit memory bus cycles.

MASTER# 137 5v I BUS MASTER: Master cycle indicator.

— 72 —

IOCHCK# 5 5v I I/O CHANNEL CHECK: When this signal asserted,

it indicates that a parity or an uncorrectable error has
occurred for a device or memory on the ISAbus.

IOCHRDY 8 5v I I/O CHANNEL READY: Devices on the ISA Bus

negate IOCHRDY to indicate that additional time
(wait states) is required to complete the cycle.

REFRESH# 29 5v B REFRESH: As an output REFRESH# indicates when

a refresh cycle is in progress. As an input REFRESH
is driver by 16-bit ISA Bus masters to indicate refresh
cycle.

AEN 15 5v O ADDRESS ENABLE: AEN is asserted during DMA

cycles to prevent I/O slaves from misinterpreting
DMA cycles as valid I/O cycles.

TC 32 5v O TERMINAL COUNT: The VT82C586 asserts TC to

DMA slaves as a terminal count indicator.

IRQ15, 14, 128-129, 127- 5v I INTERRUPT REQUEST: The IRQ signals provide

[11: 9], [7:3] 126, 61, 71-75 both system board components and ISA Bus I/O

devices with a mechanism for asynchronously
interrupting the CPU.

DRQ[7:5], 132, 130, 57, Sv I DMA REQUEST: The DREQ lines are used to

[3:0] 30, 7, 16, 59 request DMA services from VT82C586 DMA

controller.

DACK[7:5], 133, 131,58, 5v O Multifunction Pins:

[3:0] 31, 33, 18, 60 Normal Operation

DMA ACKNOWLEDGE: The DACK output
lines indicate that a request for DMA service has
been granted.
Power-up
General purpose inputs

SPKR 134 5v B Multi function pin:

Normal Operation
SPEAKER DRIVE: The SPKR signal is the
output of counter 2.
Power-up strapping
0: IDE fixed I/O base
1: IDE flexible I/O base

CPU Interface

CPURST 142 cpu O CPU RESET: The VT82C586 asserts CPURST to

reset the CPU during power-up.

INTR 145 cpu O CPU Interrupt: INTR is driven by VT82C586 to

signal the CPU that an interrupt request is pending
and needs service.

NMI 146 cpu O NON-MASKABLE INTERRUPT: NMI is used to

force a non-maskable interrupt to the CPU. The
VT82C586 generate an NMI when either SERR# or
IOCHK# is asserted.

INIT 143 cpu O INITIALIZATION: The VT82C586 asserts INIT if

it detects a shut-down special cycle on the PCI bus
or if a soft reset is initiated by the register

STPCLK# 148 cpu O STOP CLOCK: STPCLK# is asserted by the

VT82C586 to CPU in response to different Power­Management events.

— 73 —

SMI# 149 cpu O SYSTEM MANAGEMENT INTERRUPT: SMI# is

asserted by the VT82C586 to CPU in response to
different Power-Management events.

FERR# 141 cpu O NUMERICAL COPROCESSOR ERROR: This

signal is tied to the coprocessor error signal on the
CPU.

IGENN# 139 cpu O IGNORE ERROR: This pin is connected to the

ignore error pin on the CPU.

Enhanced IDE Interface

DIORA# 50 5v O DISK I/O READ A: Primary IDE channel drive

read strobe.

DIOWA# 51 5v O DISK I/O WRITE A: Primary IDE channel drive

write strobe.

DIORB# 54 5v O DISK I/O READ B: Secondary IDE channel drive

read strobe.

DIOWB# 55 5v O DISK I/O WRITE B: Secondary IDE channel drive

write strobe.

DRDY# 49 5v I I/O CHANNEL READY: IDE drive ready indicator.

SOE# 56 5v O SYSTEM ADDRESS TRANSCEIVER OUTPUT

ENABLE: This signal controls the output enables of
the 245 transceivers that interface the DD[15:0]
signals to the SA[15:0]

DREQA 45 5v I DISK DMA REQUEST A: Primary IDE channel

DMA request.

DREQB 46 5v I DISK DMA REQUEST B: IDE channel DMA

request.

DDACK#A 47 5v O DISK DMA ACKNOWLEDGE A: Primary IDE

channel DMA acknowledge.

DDACK#B 48 5v O DISK DMA ACKNOWLEDGE B: Secondary IDE

channel DMA acknowledge.
This pin is used as power-up strap option:
0/1: IDE fixed/relocatable I/O address

Reset and Clock

PWRGD 138 5v I POWER GOOD: Connected to the POWERGOOD

signal on Power Supply.

PCIRST# 3 pci O PCI RESET: An active low reset signal for the PCI

bus. The VT82C586 will generate PCIRST# during
the power-up or from the control register.

RSTDRV 4 5v O RESET DRIVE: RSTDRV is the reset signal to the

ISA bus.

BCLK 14 5v O BUS CLOCK: ISA bus clock

OSC 6 5v I OSCILLATOR: OSC is the 14.31818 Mhz clock

signal. It is used by the internal 8254

— 74 —

XD Interface

XD[7:0] 122-121,119- 5v B X-BUS DATA BUS:

116, 114-113 These pins are used as strap option during the

power-up:
XD0: 0/l - Disable/enable internal KBC
XD1: 0/l - Disable/enable internal PS/2 Mouse.
XD2: 0/l - Disable/enable internal RTC
XD3: 0/l - PIA/SIO
XD4~XD7: RP13~RP16 for internal KBC

XDIR 112 5v O X-BUS DIRECTION: XIDR# is tied directly to the

direction control of a 74F245 that buffer the X-Bus
data and ISA-Bus data.

RTCAS/ 94 5v O Multifunction Pin:
PCWE0 Internal RTC disable:

REAL TIME CLOCK ADDRESS STROBE:
RTCAS is connected directly to the address strobe
input of the external RTC.
Internal RTC enable:
GENERAL PURPOSE WRITE ENABLE 1:
LATCH enable signal to a external 373 for general
outputs.

ROMCS# / 135 5v O ROM CHIP SELECT / KEYBOARD

KBCS# CONTROLLER CHIP SELECT: Multi-function pin

Normal Operation
ISA memory cycle: Chip-select to the ROM-BIOS
ISA I/O cycle: Chip-select to the external
keyboard controller.
Power-up
0: DACKx by external 137, DACK0 as DACEN,
DACK1-7 as EXTSMI
1: DACKx as DACKx

PCWE1 93 5v O GENERAL PURPOSE WRITE ENABLE 1:

LATCH enable signal to a external 373 for general
outputs.

Universal Serial Bus Interface

USBDATA0+ 95 usb B USB PORT 0 DATA:

USBDATA0- 96 usb B USB PORT 0 DATA:

USBDATA1+ 97 usb B USB PORT 1 DATA:

USBDATA1- 98 usb B USB PORT 1 DATA:

USBCLK 99 usb I USB CLOCK: Clock input for Universal serial bus

interface

Keyboard Interface

KBCK / 108 5v B Multifunction Pin:

KA20G Internal Keyboard controller enable:

KEYBOARD CLOCK: CLOCK to keyboard interface.
Internal Keyboard controller disable:
KEYBOARD GATE A20: GATE A20 output
from external keyboard controller.

KBDT/ 109 5v B Multifunction Pin:

KBRC# Internal Keyboard controller enable:

KEYBOARD DATA: DATA to keyboard interface.
Internal Keyboard controller disable:
KEYBOARD RESET: Reset input from external
keyboard controller.

— 75 —

MSCK / IRQ1 110 5v B Multifunction Pin:

MSDT/ 111 5v B Multifunction Pin:

IRQ12 PS/2 mouse enable:

A20M 147 cpu O A20 MASK: Direct connect A20 mask on CPU.

PS/2 mouse enable:
MOUSE CLOCK: CLOCK to PS/2 mouse interface.
PS/2 mouse disable and internal KBC disable:
INTERRUPT REQUEST 1: IRQ 1 input from
external KBC.

MOUSE DATA: DATA to PS/2 mouse interface.
PS/2 mouse disable:
INTERRUPT REQUEST 12: IRQ 12 input from
external KBC

KEYLOCK 106 5v I KEYBOARD LOCK: Keyboard lock signal for

TURBO 107 5v I TURBO: Turbo mode indicator input

On Board PnP

MDRQ[1:0] 89, 91 5v I PLUG AND PLAY DMA REQUEST: DMA

MDACK[1:0] 90, 92 5v O PLUG AND PLAY DMA ACKNOWLEDGE:

MIROQ[1:0] 88, 87 5v I PLUG AND PLAY INTERRUPT REQUEST

Internal RTC

RTCX1 / 104 vbat I Multifunction Pin:

IRQ8# Internal RTC enable:

RTCX2 105 vbat O RTC CRYSTAL OUTPUT: 32.768Khz crystal output

internal keyboard controller

request inputs from non-PNP device to support the
PnP function.

DMA acknowledge outputs from non-PNP device to
support the PnP function.

Interrupt request inputs from non-PNP device to
support the PnP function.

RTC CRYSTAL INPUT: 32.768Khz crystal or
oscillator input.
Internal RTC disable:
INTERRUPT REQUEST 8: IRQ8 input from
external KBC

VBAT 102 I RTC BATTERY: BATTERY input for internal RTC

VEXT 103

EXTSM1# 136 5v I EXTERNAL SMI: External input to trigger SMI

VDD 17, 34, 53, 79, 115 5v I power supply of 4.5 to 5.5V.

VDD_PCI 157, 171, 184, 198 pci I PCI voltage, 3.3 or 5v

AVDD 100 usb I USB differential output power source

AGND 101 0v I USB differential output ground

VSS 13, 26, 39, 52, 68, 84, 0v I the ground

120, 140,156, 166,

177,188, 197, 208

VDD_CPU 144 cpu I CPU voltage, 3.3 or 5 volts

Misc.

output to the CPU.

Power and Ground

— 76 —

PIN OUT IN NUMERICAL ORDER

Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name

1 PIRQA# 53 VDD 105 RTCX2 157 VDD-pci

2 PCICLK 54 DIORB# 106 KEYLOCK 158 AD4

3 PCIRST# 55 DIOWB# 107 TURBO 159 AD5

4 RSTDRV 56 HSOE# 108 KBCK 160 AD6

5 IOCHCK# 57 DRQ5 109 KBDT 161 AD7

6 OSC 58 DACK5 110 MSCK 162 CBE0#

7 DRQ2 59 DRQ0 111 MSDT 163 AD8

8 IOCHRDY 60 DACK0 112 XDIR 164 AD9

9 SMEMW# 61 IRQ9 113 XD0 165 AD10
10 SMEMR# 62 SBHE 114 XD1 166 VSS
11 IOW# 63 LA23/DCS3B# 115 VDD 167 AD11
12 IOR# 64 LA22/DCS1B# I 16 XD2 168 AD12
13 VSS 65 LA21/DCS3A# 117 XD3 169 AD13
14 BCLK 66 LA20/DCS1A# 118 XD4 170 AD14
15 AEN 67 LA 19/DA2 119 XD5 171 VDD-pci
16 DRQ1 68 VSS 120 VSS 172 AD15
17 VDD 69 LA18/DA1 121 XD6 173 CBE1#
18 DACK1 70 LA17/DA0 122 XD7 174 PAR
19 SA16 71 IRQ7 123 MEMR# 175 SERR#
20 SA15/DD15 72 IRQ6 124 MEMW# 176 STOP#
21 SA14/DD14 73 IRQ5 125 IOCS16# 177 VSS
22 SA13/DD13 74 IRQ4 126 IRQ10 178 DEVSEL#
23 SA12/DD12 75 IRQ3 127 IRQ11 179 TRDY#
24 SA11/DD1 1 76 MEMCS16# 128 IRQ15 180 IRDY#
25 SA10/DD10 77 SD8 129 IRQ14 181 FRAME#
26 VSS 78 SD9 130 DRQ6 182 CBE2#
27 SA9/DD9 79 VDD 131 DACK6 183 AD16
28 SA8/DD8 80 SD10 132 DRQ7 184 VDD-pci
29 REFRESH# 81 SD11 133 DACK7 185 AD17
30 DRQ3 82 SD12 134 SPKR 186 AD18
31 DACK3 83 SD13 135 ROMCS# 187 AD19
32 TC 84 VSS 136 EXTSMI# 188 VSS
33 DACK2 85 SD14 137 MASTER# 189 AD20
34 VDD 86 SD15 138 PWRGD 190 AD21
35 BALE 87 MIRQ0 139 IGNNE# 191 AD22
36 SA7/DD7 88 MIRQ1 140 VSS 192 AD23
37 SA6/DD6 89 MDRQ1 141 FERR# 193 IDSEL
38 SA5/DD5 90 MDACK1 142 CPURST 194 CBE3#
39 VSS 91 MDRQ0 143 INIT 195 AD24
40 SA4/DD4 92 MDACK0 144 VDD-cpu 196 AD25
41 SA3/DD3 93 PCWE1 145 INTR 197 VSS
42 SA2/DD2 94 RTCAS 146 NMI 198 VDD-pci
43 SA1/DD1 95 USBDA TA0+ 147 A20M 199 AD26
44 SA0/DD0 96 USBDATA0- 148 STPCLK# 200 AD27
45 DDRQA 97 USBDATA1+ 149 SM1# 201 AD28
46 DDRQB 98 RTCCS#/USBDAT A1- 150 PGNT# 202 AD29
47 DDACKA# 99 USBCLK 151 PREQ# 203 AD30
48 DDACKB# 100 AVDD 152 AD0 204 AD31
49 HDRDY# 101 AGND 153 AD1 205 PIRQD#
50 DIORA# 102 VBAT 154 AD2 206 PIRQC#
51 DIOWA# 103 VEXT 154 AD3 207 PIRQB#
52 VSS 104 RTCS1/IRQ8# 156 VSS 208 VSS

— 77 —

3. VT82C587VP

PIN DESCRIPTION

Signal Name Pin No. cpu I/O Signal Description

CPU Data Port

HD[31:0] 24-17, 14- cpu B HOST DATA: These signals are connected to the

11, 9-2, 99- CPU data bus. The CPU data bus is interleaved

92, 89-86 between the two VT82C587VP for every byte,

effectively creating an even and odd 587VP.

DRAM Data Port

MD[31:0] 78, 74, 69, dram B MEMORY DATA: These signals are connected to

61, 56, 51, the DRAM data bus. The DRAM data bus is
46, 42, 76, interleaved between the two VT82C587VP for every

72 65, 63, byte, effectively creating an even and odd

58, 54 48, VT82C587VP.
44, 80, 75,
71, 62, 57,
52, 47, 43,
77, 73, 68,
64, 60, 55,

49, 45

VT82C585VP Interface

DB32 85 dram I DRAM WIDTH: This is used to control the width

of DRAM

CMD[5:0] 79, 25-29 dram I COMMAND: The buffers in the VT82C587VP are

controlled by 585VP through these command signals.

HSTB# 38 dram I HOST DATA STROBE: Assertion causes data to

be posted in the CPU read buffer

MSTB# 39 dram I MEMORY STROBE: Assertion causes data to be

posted in the DRAM write buffer.

PLINK[7:0] 30-37 dram B PCI LMK: These signals are connected to the PLINK

data bus on the VT82C585VP. This is the data path
between VT82C585VP and VT82C587VP. Each
VT82C587VP connects to one-byte of the i6-bit bus.

Clock and Misc. Control

HCLK 81 cpu I HOST CLOCK: Primary clock input used to drive

the part.

RESET# 84 cpu I HOST RESET: Primary reset signal for VT82C587VP.

CAS# 83 cpu Connects to DRAM CAS signal. It is sync. with DRAM

CAS. It is recommended to maintain same skew
among the 8 CAS of DRAM for Burst EDO operation.

Power and Ground

VDD_DRAM 53, 67 dram I Power supply for DRAM(3.3V or 5V)

VDD 41 dram I Power supply fixed 5V

VDD_CPU 16, 91, 100 cpu I Power supply for the CPU bus

VSS 1, 10, 15, 40, 0v I Ground

50, 59, 66,

70, 79, 90

— 78 —

PIN OUT IN NUMERICAL ORDER

Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name

1 VSS 31 PLINK6 51 MD26 81 HCLK
2 HD12 32 PLINK5 52 MD10 82 VSS
3 HD13 33 PLINK4 53 VDD-dram 83 CAS#
4 HD14 34 PLINK3 54 MD18 84 RESET#
5 HD15 35 PLINK2 55 MD2 85 DB32
6 HD16 36 PLINK1 56 MD27 86 HDO
7 HD17 37 PLINK0 57 MD11 87 HD1
8 HD18 38 HSTB# 58 MD19 88 HD2

9 HD19 39 MSTB# 59 VSS 89 HD3
10 VSS 40 VSS 60 MD3 90 VSS
11 HD20 41 VDD-fixed 5V 61 MD28 91 VDD-cpu
12 HD21 42 MD24 62 MD12 92 HD4
13 HD22 43 MD8 63 MD20 93 HD5
14 HD23 44 MD16 64 MD4 94 HD6
15 VSS 45 MD0 65 MD21 95 ND7
16 VDD-cpu 46 MD25 66 VSS 96 HD8
17 HD24 47 MD9 67 VDD-dram 97 HD9
18 HD25 48 MD17 68 MD5 98 HD10
19 HD26 49 MD1 69 MD29 99 HD11
20 HD27 50 VSS 70 VSS 100 VDD-cpu
21 HD28 71 MD13
22 HD29 72 MD22
23 HD30 73 MD6
24 HD31 74 MD30
25 CMD4 75 MD14
26 CMD3 76 MD23
27 CMD2 77 MD7
28 CMD1 78 MD31
29 CMD0 79 CMD5
30 PLINK7 80 MD15

— 79 —

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Parameter Min Max Unit

Ambient operating temperature 0 70 °C

Storage temperature -55 125 °C

Input voltage -0.5 5.5 Voltage

Output voltage (VDD = 5v) -0.5 5.5 Voltage
Output voltage (VDD = 3.1 - 3.6V) -0.5 VDD + 0.5 Voltage

Note:

Stress above these listed cause permanent damage to device. Functional operation of this device
should be restricted to the conditions described under operating conditions.

DC Characteristics

TA-0-70°C, VDD=5v+/-5%, GND=0V

Symbol Parameter Min Max Unit Condition

VIL Input low voltage -.50 0.8 V
VIH Input high voltage 2.0 VDD+0. 5 V

VOL Output low voltage - 0.45 V IOL=4.0mA

VOH Output high voltage 2.4 - V IOH=-1.0mA ‘

IIL Input leakage current - +/-10 uA 0<VIN <V
IOZ Tristate leakage current - +/-20 uA O.45<V
ICC Power supply current - 80 mA
Ibat Battery load current - 0.5 uA 2.5V<Vbat<3.4V

OUT

VDD=0V

DD

< V

DD

— 80 —

8-5 PENTIUM® PROCESSOR with MMXTM Technology

ARCHITECTURE OVERVIEW

®

The embedded Pentium

TM

Intel386

, and Intel436TM processor families, and with other Pentium processors. The embedded Pentium

processor family includes the following products.

* Pentium processor
* Pentium processor with V oltage Reduction Technology
* Pentium processor with MMX technology
* Low-Power embedded Pentium processor with MMX technology

The Pentium processor family supports the features of previous Intel Architecture processors, and provides
significant enhancements and additions including the following:

• Superscalar Architecture

• Dynamic Branch Prediction

• Pipelined Floating-Point Unit

• Improved Instruction Execution T ime

• Separate Code and Data Caches

• Writeback MESI Protocol in the Data Cache

• 64-Bit Data Bus

• Bus Cycle Pipelining

• Address Parity

• Internal Parity Checking

• Performance Monitoring

• IEEE 1149.1 boundary Scan

• System Management Mode

• Virtual Mode Extensions

• Dual processing support

• On-chip local APIC device

processor with MMXTM technology is binary compatible with the 8086/88, 80286,

In addition to the features listed above, the Pentium processor with MMX technology offers the following en­hancements over Pentium processor.

®

• Support for Intel

MMX technology

• Doubled code and data cache size to 16Kbytes each

• Inproved branch prediction

• Enhanced pipeline

• Deeper write buffers

The following feature are supported by the Pentium processor, but these features are not supported by the Pentium
processor with MMX technology:

• Functional redundancy check and Lock-Step operation.

• Support for Intel 82498/82493 and 82497/82492 cache chipset products

• Split-line accesses to the code cache

— 81 —

PENTIUM® PROCESSOR

PINOUT

Pinout and Pin Discriptions

— 82 —

8-6 MN04326TAE SIMM ( Single Inline Memory Module)

Feature: • 72 pin SIMM

• 16M bytes, no parity (4Mx32-bit data width)

• Access time: 60ns

• Single 5.V—0.25V

• EDO

Product & Description:

Name SIMM (Single Inline Memory module)
Model MN04326TAE

Contents Pin Assignment

Pin number Signal Pin number Signal

1 Vss 37 NC
2 DQ0 38 NC
3 DQ16 39 Vss
4 DQ1 40 /CE0
5 DQ17 41 /CE2
6 DQ2 42 /CE3
7 DQ18 43 /CE1
8 DQ3 44 /RE0

9 DQ19 45 /RE1
10 Vcc 46 NC
11 NC 47 /W
12 A0 48 NC
13 A1 49 DQ8
14 A2 50 DQ24
15 A3 51 DQ9
16 A4 52 DQ25
17 A5 53 DQ10
18 A6 54 DQ26
19 NC 55 DQ11
20 DQ4 56 DQ27
21 DQ20 57 DQ12
22 DQ5 58 DQ28
23 DQ21 59 Vcc
24 DQ6 60 DQ29
25 DQ22 61 DQ13
26 DQ7 62 DQ30
27 DQ23 63 DQ14
28 A7 64 DQ31
29 NC 65 DQ15
30 Vcc 66 NC
31 A8 67 NC
32 A9 68 NC
33 /RE3 69 Vcc
34 /RE2 70 NC
35 NC 71 NC
36 NC 72 Vss

— 83 —

8-7 Power Supply (100W)

The power supply used in the MP-2000 is a 100W open frame power supply. The specifications and features of this special
power supply are listed in the following sections.

Specifications

• High efficiency 100W output

• Universal input 90 to 264 VAC

• Overvoltage protection

• Small size 3" X 5" X 1.0” footprint

• Continuous short circuit protection

• Conductive EMI meets FCC & CISPR class B

Output Specifications

• Voltage Accuracy:
+5.1VDC output ±2%
+12.25VDC output ±5%

• Output Power 100W, continuous

• Hold-up time 10ms at full load, 115VAC

• Output protection Overvoltage and short circuit protection

• Turn -on Delay 5 seconds Max at 120VAC

• Ripple and noise 50mV on 5V, from 100mV to 150mV on12V,15V,24V outputs

Input Specifications

• Input voltage range 90~264 VDC

• Input frequency 47~63 Hz

• Efficiency Greater than 80%

— 84 —

9. Circuit Diagram

Page

1. Mother Board SBC8352 (CPU)1/16 ............................................................................... 86

2. Mother Board SBC8352 (VT82C585VPX/VT82C586B)2/16 ......................................... 87

3. Mother Board SBC8352 (VT82C587VP)3/16................................................................. 88

4. Mother Board SBC8352 (CACHE)4/16 .......................................................................... 89

5. Mother Board SBC8352 (DRAM)5/16............................................................................ 90

6. Mother Board SBC8352 (IDE)6/16................................................................................. 91

7. Mother Board SBC8352 (EISA/PC104 SLOT)7/16........................................................ 92

8. Mother Board SBC8352 (XIO/USB)8/16........................................................................ 93

9. Mother Board SBC8352 (ALI5113 Super I/O)9/16........................................................ 94

10. Mother Board SBC8352 (CLOCK BUFFER)10/16 ........................................................ 95

11. Mother Board SBC8352 (Power)11/16 .......................................................................... 96

12. Mother Board SBC8352 (10 BSAE/T ETHERNET)12/16 .............................................. 97

13. Mother Board SBC8352 (SERIAL PORT INTERFACE)13/16 ....................................... 98

14. Mother Board SBC8352 (DK65550PCI)14/16 ............................................................... 99

15. Mother Board SBC8352 (VIDEO RAM)15/16 .............................................................. 100

16. Mother Board SBC8352 (DK65550PCI)16/16 ............................................................. 101

17. Multi I/O port circuit EBL-0453(3) ................................................................................ 102

18. Drawer drive circuit EBL-0453(5)................................................................................. 103

19. Riser card (MP-2000) .................................................................................................... 104

20. LCD control board (LVDS Board OPTION ITEM) ........................................................ 105

— 85 —

Pentium Mother Board

1. Mother Board SBC8352 (CPU)1/16

A3

A5A6A7A8A11

A10

A17

A18

A13

A14

A15

A5A6A7A8A11

A10

A17

A18

A13

A14

AA11

AA8

AM32

AA10

RN22

AA9

AK30

AA17

22X4

AA10

AN31

A10

AA18

AA11

AL31

A11

AA13

AA12

AL29

A12

AA14

RN18

AA13

AK28

A13

A15

AA15

22X4

AA14

AL27

A14

246824681357246

135713572468135

AA5

AA6

AA7

AA8

RN17

22X4

AA3

AA4

AA5

AA6

AA7

AL35

AM34

AK32

AN33

AL33

A3A4A5A6A7A8A9

A16

A16

AA16

AA15

AK26

A15

A19

A19

AA19

AA16

AL25

A16

A20A9A12

A20A9A12

AA20

AA9

RN23

22X4

AA17

AA18

AK24

AL23

A17

A18

8

7

AA12

AA19

AK22

A19

AA20

AL21

A20

A21

A21

AF34

A21

A3
22

R159

AA3

A22

A22

AH36

A22

A4

A4
22

R155

AA4

A23

AE33

A23

A23

A24

A24

AG35

A24

A25

A25

AJ35

A25

A26

AH34

VCC3

0 -C

109876

RN15

12345

-AD5

H_-R

A26

A27

A28

A27

A28

A29

AG33

AK36

AK34

A26

A27

A28

AP

H8 -WT

-SMIACT

-BUSCHK

-SMI

VCC3

A29

A30

A31

A30

A31

AM36

AJ33

A29

A30

A31

4K7X8

AM2

ADSC

]

0, 7

[

-BE

-BE0

AL9

-BE

BE0

]

0, 7

[

-BE1

AK10

BE1

-BE2

AL11

BE2

109876

RN13

12345

M_IO

-BE3

-BE4

AK12

AL13

BE3

VCC3

-BOFF

-CACHE

-BE5

AK14

BE4

BE5

-NA

-KEN

-BE6

AL15

BE6

-BRDY

-BE7

AK16

BE7

-OPEN

VCC3

4K7X8

-FERR

-FERR

Q5

AJ1

FERR

R164

AHOLD

-HITM

AL5

HITH

BREQ

-HITM

AK6

HIT

4.7K

AF4

R167

PCHK

4.7K

APICEN

APICEN

AP

AJ3

AK2

AP

HLDA

R170

2.2K

-HLOCK

-HLOCK

AH4

AE5

LOCK

APCHK

-EHBE

AC5

AG5

PCD

PRDY//N

AL3

PWT

-CACHE

-CACHE

-ADS D W

U3

AJ5

CACHE

VCC3

864

RN14

753

-STPCLK

-C-R-IO

-ADS D W

-C-R-I0

AK4

D_C

ADS

AM6

FRC

W_R

-PEN

M

M

T4

M_YO

2

4K7X8

1

-UPVRM

FRC

AL17

Y35P4AG3

SCYC

FRCMC//IBC

4K7

R172

PICCLK

-SMIACT

-SMIACT

Q3R4S3S5M34

IERR//N

SMIACT

PM0_BP0//PMON0

J1

123

4

+12VVCC

N33

N35

P34

TD0

TD1

TCK

BP3//LBA

BP2//PMC

PM1_BP1//PMON1

BOX HEADER 1X4

PICCLK

-OPEN

Q33

H34

J33

TM5

TRST

PICCLK//N

2/5

BUS/CORE RATI0

BF1

CLOSED

FOR CPU FAN

BF0

CLOSED

1

APICEN

BF1

L35

AC3

AA3

AD4

AE3

X34

PBGNT//N

PBREQ//N

PHIT//EXC

PHITM//MPHITM

OPEN_PICD0//MP

APICEN_PICD1//N

1/3

1/2

OPEN

CLOSED

CLOSED

OPEN

3

BF0

Y33

//BF1

BF0//N

2/3

VCC3

OPEN

OPEN

HEADER 2X2

AE35

Q35

U_O/N/N

CPUTYP/N/N

4.7K

4.7K

R4R1R5

BF0

BF1

R34

S35

AN35

S33

N//TEST

N//BHOLD

N//DHOLD

4.7K

BF2

AL19

AJ15

N//N

N//CHOLD

N//MPBOFF

-UPVRM

AL1

AH32

N////UPVRM

GND///VCC2DET

D0D1D2D3D4D5D6D7D8D9D10

U3

K34

G35

J35

G33

F36

F34

D0D1D2D3D4D5D6D7D8D9D10

D0D1D2D3D4D5D6D7D8D9D10

E35

E33

D34

C37

C35

B36

D11

D11

D11

D32

D12

D12

D12

B34

D13

D13

D13

C33

D14

D14

D14

A35

D15

D15

D15

B32

D16

D16

D16

C31

D17

D17

D17

A33

D18

D18

D18

D28

D19

D19

D19

B30

D20

D20

D20

C29

D21

D21

D21

A31

D22

D22

D22

D26

D23

D23

D23

C27

D24

D24

D24

C23

D25

D25

D24

D26

D25

D26

D26

C21

D27

D27

D27

D22

D28

D28

D28

C19

D29

D29

D29

D20

D30

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

D46

D47

D48

D49

C17

C15

D16

C13

D14

C11

D12C9D10D8A5E9B4D6C5E7C3D4E5D2F4E3G5E1G3H4J3J5K4L5L3M4N3

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

D46

D47

D48

D49

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

D46

D47

D48

— 86 —

D49

D50

D50

D50

D51

D51

D51

D52

D52

D52

D53

D53

D53

D54

D54

D54

D55

D55

D55

D56

D56

D56

D57

D57

D57

D58

D58

D58

D59

D59

D59

D60

D60

D60

D61

D61

D61

D62

D62

D62

D63

D63

D63

D36

DP0

DP1

D30

DP2

DP3

DP4

C25

D18C7F6F2N5

DP5

DP6

DP7

CLK

BOFF

A20M

AK19Z4AK8

CPUCLK

-BOFF

A20M

-B0FF

-A20M

CPUCLK

INTR_LINT0

NMI_LINT1

IGNNE

KEN

FLUSH

AD34

AC33

AA35W5AN7V4AN4X4AK20U5Y5

INTR

NMI

-IGNNE

-KEN

-SMI

AHOLD

NMI

INTR

-KEN

-IGNNE

AHOLD

EADS

BRDY

RESET

INVNABUSCHK//QDUMP

-EADS

-BRDY

CPURST

-KEN

-NA

AHOLD

-EADS

-BRDY
CPURST

WB_WT//MPSH

INIT

AL7

AA5

AA33

AB34

-BUSCHK

WB -WT

CPUINIT

-SMI

-NA

CPUINIT

SKI

-SMI

R S//N

AC35

Z34

-PEN

PEN//N

STPCLK//SUSP

HOLD

EWBE

BRDYC

Y3

V34

AB4

W3

R163

-STPCKL

-EWBE

-STPCLK

PENTIUM P54C/P55C

330

VCC3

2. Mother Board SBC 8352 (VT82C585VPX/VT82C586B)2/16

A3A4A5A6A7A8A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

2124282625293731303941404232333435361216111318171419232220

A3A4A5A6A7A8A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

8765432

208

206

205

204

203

202

199

198

197

186

185

182

181

180

179

178

177

174

173

172

171

170

169

168

167

A D0

A D1

A D2

A D3

A D4

A D5

A D6

A D7

A D8

A D9

A D10

A D11

A D12

A D13

A D14

A D15

A D16

A D17

A D18

A D19

A D20

A D21

A D22

A D23

A D24

A D25

A D26

A D27

A D28

A D29

A D30

A D31

A D0

A D1

A D2

A D3

A D4

A D5

A D6

A D7

A D8

A D9

A D10

A D11

A D12

A D13

A D14

A D15

A D16

A D17

A D18

A D19

A D20

A D21

A D22

A D23

A D24

A D25

A D26

A D27

A D28

A D29

A D30

A D31

A D0

A D1

A D2

A D3

A D4

A D5

A D6

A D7

A D8

A D9

A3A4A5A6A7A8A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

-BE0

-BE1

-BE2

-BE3

-BE4

-BE5

-BE6

-BE7

-RRA50

-RRA51

RA50/CS0

RA51/CS1

RA52/CS2

RA53/CS3

RA54

RA55

CA50/DQM0

CA51/DQM1

CA52/DQM2

CA53/DQM3

CA54/DQM4

CA55/DQM5

CA56/DQM6

CA57/DQM7

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

MA10

MA11

MA12WECBOE0

A3SE0/CADS

A3SQL1/CADV

CALE/CE1

CWE0/GWE

CWE1/BWE

CWE2/SCASA

CWE3/SCASB

CWE4/SRASA

CWE5/SRASB

CWE6/SWEA

CWE7/SWEB

HCLK

PCLK

-RCA50

-RCA51

-RCA52

-RCA53

-RCA54

-RCA55

-RCA56

-RCA57

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

MA10

MA11

MA12

-WE

-COE0

-CADS

-CADV

-CEI

-CWE

-SWE

MA10

MA11

MA12

-WE

-COE0

-CADS

-CADV

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

-RCA50

-RCA51

-RCA52

-RCA53

-RCA54

-RCA55

-RCA56

-RCA57

-BE0

-BE1

-BE2

-BE3

-BE4

-BE5

-BE6

-BE7

AD5

M/IO

D/C

H/R

BRDY

HLOCK

KEN/INV

CACHE

HITM

AHOLD

BOFF

EAD5

SMIACT

NA

-BE0

-BE1

-BE2

-BE3

-BE4

-BE5

-BE6

-BE7

-AD5 M D W-BRDY

-HLOCK

-KEN

-CACHE

-HITM

AHOLD

-BOFF

-EADS

-SMIACT

-NA

51504948474645

44

66546769625356556857646558

63

100

101

98

99

102

103

109

107

111

105

108

106

110

104

112

113

115

116

117

118

120

121

122

123

124

125

126

95727170949091929373747576

59

9

-IO-C-R

-CEI

-CWE

-SWE

PMCHCLK

PMCPCLK

1043618497

114

VCC3

VCC3

PMCHCLK

VCC

VDD_CPU

VDD_CPU

VDD_CPU

VDD_CPU

VDD_DRAM

VDD_DRAM

C -BE0

C -BE1

C -BE2

C -BE3

C -BE0

C -BE1

C -BE2

C -BE3

C -BE0

C -BE1

C -BE2

C -BE3

162

173

182

194

152

153

154

155

158

159

160

161

163

164

165

167

168

169

170

172

183

185

186

187

189

190

191

192

195

196

199

200

201

202

203

204

-REQ0

-REQ1

-REQ2

-REQ3

-REQ0

-REQ1

-REQ2

-REQ3

-GNT0

-GNT1

-GNT2

-GNT3

-GNT0

-GNT1

-GNT2

-GNT3

PAR

-SERR

-PREQ

-PGNT

PAR

-SERR

-PREQ

-PGNT

PLINK0

PLINK1

PLINK2

PLINK3

PLINK4

PLINK5

PLINK6

PLINK7

PLINK8

PLINK9

PLINK10

PLINK11

PLINK12

PLINK13

PLINK14

PLINK15

PLINK0

PLINK1

PLINK2

PLINK3

PLINK4

PLINK5

PLINK6

PLINK7

PLINK8

PLINK9

PLINK10

PLINK11

PLINK12

PLINK13

PLINK14

PLINK15

-MSTB

-MSTB

CMD0

CMD1

CMD2

CMD3

CMD4

-MSTB

-HSTB

CMD0

CMD1

CMD2

CMD3

CMD4

-DRST

TA0

TA1

TA2

TA3

TA4

TA5

TA6

TA7

CPURST

DB32

RSET

-DRST

-TWE

TA0

TA1

TA2

TA3

TA4

TA5

TA6

TA7

CPURST

DB32

C/BE0

C/BE1

C/BE2

C/BE3

C/BE0

C/BE1

C/BE2

C/BE3

207

196

187

176

188

191

189

190

192

193

161

159

157

155

160

158

156

154

194

195

153

152

135

136

137

138

139

140

141

5289777879868582818087

88

163

166

162

127

128

129

130

131

132

133

134

143

144

145

146

148

149

150

151

-FRAME

-DEVSEL

-IRDY

-TRDY

-STOP

-PLOCK

-FRAME

-TRDY

-IRDY

-DEVSEL

A D18

-STOP

-SERR

PAR

-PCIRST

-INTR A

-INTR B

-INTR C

-INTR D

FRAME

TRDY

IRDY

DEVSEL

IDSEL

STOP

SERR

PAR

PCIRST

PIRQA

PIRQB

PIRQC

PIRQD

-FRAME

-DEVSEL

-IRDY

-TRDY

-STOP

-PLOCK

VDD

VDD

VDD_PCI

VDD_PCI

147

165

184

201

C5

10P

R35

N/F

VCC

RESET

TWE

TA0

TA1

TA2

TA3

TA4

TA5

TA6

TA7

TAB/RN

TA9/DB32

MREQ0

MREQ1

MGNT

FRAME

DEVSEL

IRDY

TRDY

STOP

LOCK

REQ0

REQ1

REQ2

REQ3

GNT0

GNT1

GNT2

GNT3

PAR

SERR

PREQ

PGNT

PLINK0

PLINK1

PLINK2

PLINK3

PLINK4

PLINK5

PLINK6

PLINK7

PLINK8

PLINK9

PLINK10

PLINK11

PLINK12

PLINK13

PLINK14

PLINK15

MSTB

HSTB

CMD0

CMD1

CMD2

CMD3

CMD4

147

165

184

201

1

1527386083

96

119

142

164

175

183

200

VDD GND

VDD _CPU

VDD _DRAM

1043618497

114

181

179

190

178

193

176

175

174

3

1

207

206

205

151

150

9192899088

87

149

148

136

143

145

146

141

139

555451504546474849

56

112

135

108

109

147

107

104

105

106

138

142

14

6

2

103

102

134

-PREQ

-PGNT

PDRQ0

-DRDYB

PIRQ1

PIRQ0

-SMI

-STPCLK

-EXTSMI

CPUINIT

INTR

NMI

-FERR

-IGNNE

-XDIOWA

-XDIORA

DDRQA

DDRQB

-DRDY

-SOE

XDIR

-ROMKBCS

KB CLK

KB DATA

-A20M

TURBO

-KB LOCK

PW GOOD

RSET

R169 33

R89

R47

33

0

BCLK

SIO OSC

SIOPCLK

SPEAK

SPEAK

A D10

A D11

A D12

A D13

A D14

A D15

A D16

A D17

A D18

A D19

A D20

A D21

A D22

A D23

A D24

A D25

A D26

A D27

A D28

A D29

A D30

A D31

SIO OSC

SIOPCLK

BCLK

-KB LOCK

PW GOOD

TURBO

IRQB-

-A20M

-ROMKBCS

KB CLK

KB DATA

-SOE

XDIR

-DRDY

DDACKA

-XDIOWA

-XDIORA

DDRQA

-IGNNE

-FERR

NMI

INTR

CPUINIT

-EXTSMI

-STPCLK

-SMI

-DRDYB

-PREQ

-PGNT

-INTR A

-INTR B

-INTR C

-INTR D

-PCIRST

PAR

-SERR

-FRAME

-TRDY

-IRDY

-DEVSEL

A D18

-STOP

PREQ

PGNT

MDRQ0

MDAK0

MDRQ1

MDACK1

MIRQ1

MIRQ0

SMI

STPCLK

EXTSMI

INIT

INTR

NMI

FERR

IGNNE

DIOWB

DIORB

DIOHA

DIORA

DREQA

DREQB

DDACKA

DDACKB

DRDY

SOE

XDIR

ROMCS/KBCS

DBCK/KA20G

KBDI/KBRC

A20H

TURBO

RTCX1/IRQB

RTCX2

KEYLOCK

PWRGD

CPURST

BCLK

OSC

PCICLKI

VEXT

VBAT

SPKR

4443424140383736282725242322212019706967666564639394999798

100

1019596

113

114

116

117

118

119

121

1227778808182838586

110757473727161

126

127

111

129

128591673057130

1326018333158131

13362322915351211123

124109

12576137584144

DD0

DD1

DD2

DD3

DD4

DD5

DD6

DD7

DD8

DD9

DD10

DD11

DD12

DD13

DD14

DD15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

DD0

DD1

DD2

DD3

DD4

DD5

DD6

DD7

DD8

DD9

DD10

DD11

DD12

DD13

DD14

DD15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

USBCLK

USBDAT 1+

-RTCCS

USBDATO+

USBDATO-

USBDATO+

USBDATO-

XD0

XD1

XD2

XD3

XD4

XD5

XD6

XD7

SD8

SD9

SD10

SD11

SD12

SD13

SD14

SD15

MS CLK

MS CLK

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ9

IRQ10

IRQ11

IRQ14

IRQ15

DREQ0

DREQ1

DREQ2

DREQ3

DREQ5

DREQ6

DREQ7

-DACK0

-DACK1

-DACK2

-DACK3

-DACK5

-DACK6

-DACK7

-SBHE

RTC

-REFRESH

RAEN

RBALE

-RIOR

-RIOW

-RMEMR

-RMEMW

-RSHEMR

-RSHEMW

-IOCS16

-MEMCS16

-MASTER

-IOCHCK

IOCHRDY

SIO RES

-MASTER

-IOCHCK

IOCHRDY

SIO RES

-MEMCS16

-IOCS16

-RSMEMR

-RSMMW

-RMEMR

-RMEMW

-RIOR

-RIOW

RBALE

RAEN

-REFRESH

RTC

-SBHE

DREQ0

DREQ1

DREQ2

DREQ3

DREQ5

DREQ6

DREQ7

-DACK0

-DACK1

-DACK2

-DACK3

-DACK5

-DACK6

-DACK7

MS DATA

IRQ14

IRQ15

IRQ10

IRQ11

IRQ9

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

XD0

XD1

XD2

XD3

XD4

XD5

XD6

XD7

SD8

SD9

SD10

SD11

SD12

SD13

SD14

SD15

C39

1OU

C37

D

1U

FB

FB1

VCC

-RTCCS

RTCAS

-OWS

R85

N/F

USBCLK

753

1

864

2

VCC

PDRQO

R45

4.7K

4.7KX4

RN37

-RTCC5

R36

N/F

VCC3

C160

.1U

DDRQA

R60

DDRQB

R59

5.6K

5.6K

-RTCC5

USBDAT1+

USBDAT0+

USBDAT0-

R128

R39

R44

R40

150K

150K

150K

150K

-AD5
M -IO

D -C

W -R

-BRDY

-HLOCK

-KEN

-CACHE

-HITM

AHOLD

-BOFF

-EADS

-SMIACT

-NA

-RRA50

-RRA51

VCC3

R156

2.2K

-HLOCK

DD0/SA0

DD1/SA1

DD2/SA2

DD3/SA3

DD4/SA4

DD5/SA5

DD6/SA6

DD7/SA7

DD8/SA8

DD9/SA9

DD10/SA10

DD11/SA11

DD12/SA12

DD13/SA13

DD14/SA14

DD15/SA15

SA16

DA0/LA17

DA1/LA18

DA2/LA19

DCS1A/LA20

DCS3A/LA21

DCS1B/LA22

DCS3B/LA23

PCWE1

RTCCAS/PCWE0

-OWS/USBCLK
USBDAT1+/GPI2

USBDAT1-/RTCCS

AVDD

AGND

USBDAT0+/GPI00

USBDAT0-/GPI01

XD0

XD1

XD2

XD3

XD4

XD5

XD6

XD7

PD0/SD8

PD1/SD9

PD2/SD10

PD3/SD11

PD4/SD12

PD5/SD13

PD6/SD14

PD7/SD15

MSCK/IRQ1

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ9

IRQ10

IRQ11

MSDT/IRQ12

IRQ14

IRQ15

DRQ0

DRQ1

DRQ2

DRQ3

DRQ5

DRQ6

DRQ7

DACK0

DACK1

DACK2

DACK3

DACK5

DACK6

DACK7

SBHE

TC

REFRESH

AEN

BALE

IOR

IOW

MEMR

MEMW

SMEMR

SMEMW

IOCS16

MEMCS16

MASTER

IOCHK

IOCHROY

RSTDRV

VDD_CPU

VT82C586B

VT82C585VPX

173453

79

115

157

171

184

198

1326395268

84

120

140

156

166

177

188

197

208

VCC GND

144

VCC3

U8

U12

— 87 —

3. Mother Board SBC 8352 (VT82C587VP)3/16

MD0

MD1

MD2

MD3

MD4

MD5

MD6

MD7

MD8

MD9

MD10

MD11

MD12

MD13

MD14

MD15

MD16

MD17

MD18

MD19

MD20

MD21

MD22

MD23

MD24

MD25

MD26

MD27

MD28

MD29

MD30

MD31

PLINK8

PLINK9

PLINK8

PLINK9

PLINK10

PLINK11

PLINK10

PLINK11

PLINK12

PLINK12

PLINK13

PLINK14

PLINK13

PLINK14

PLINK15

PLINK15

VCC3

VCC

454955606468737743475257627175804448545863657276424651566169747837363534333231

MD0

MD1

MD2

MD3

MD4

MD5

MD6

MD7

MD8

MD9

MD10

MD11

MD12

MD13

MD14

MD15

MD16

MD17

MD18

MD19

MD20

MD21

MD22

MD23

MD24

MD25

MD26

MD27

MD28

MD29

MD30

MD31

PLINK0

1

101540505966708290

GND

53

ODD

U1

HD0

HD1

HD2

HD3

HD4

8687888992939495969798

D8D9D10

D11

D12

D13

D[0, 63] MD[0, 63]

MD[0..63]

HD5

41

16

HD10

HD11

HD12

HD13

2345678

99

D27

D28

D29

D30

VCC3

HD14

D31

HD15

D40

91

HD16

D41

100

HD17

D42

HD18

9

D43

VCC

HD6

HD7

HD8

HD9

D14

D15

D24

D25

D26

67

VCC_DRAM

HD19

HD20

HD21

HD22

HD23

HD24

HD25

HD26

HD27

1112131417181920212223

D44

D45

D46

D47

D56

D57

D58

D59

D60

HD28

D61

HD29

D62

HD30

24

D63

HD31

MSTB

393829282726257985

-MSTB

-HSTB

PLINK1

PLINK2

HSTB

CMD0

PLINK3

PLINK4

CMD0

CMD1

CMD1

CMD2

PLINK5

PLINK6

CMD2

CMD3

CMD3

30

PLINK7

CMD4

CMD4

CMD5

16911005367

VCC3

VCC3

CMD5

DB32

HCLK

81

DB32

DBXCLK

41

VCC3

VCC_DRAM

VCC_DRAM

CAS

RESET

83

84

-587CAS1

RESET

-587CAS1

VCC

VT82C587VP

VCC

R175

CMD5

47K

VCC

MD[0..63]

MD0

MD1

MD2

MD3

MD4

MD5

MD6

MD7

MD8

MD9

MD10

MD11

MD12

MD13

MD14

MD15

MD16

MD17

MD18

MD19

MD20

MD21

MD22

MD23

MD24

MD25

MD26

MD27

MD28

MD29

R175

47K

454955606468737743475257627175804448545863657276424651566169747837363534333231

MD0

MD1

MD2

MD3

MD4

MD5

MD6

MD7

MD8

MD9

MD10

MD11

MD12

MD13

MD14

MD15

MD16

MD17

MD18

MD19

MD20

MD21

MD22

MD23

MD24

MD25

MD26

MD27

MD28

MD29

1

101540505966708290

GND

53

EVEN

HD0

HD1

HD2

HD3

HD4

HD5

U2

8687888992939495969798

D0D1D2D3D4D5D6D7D16

DC[0..63]

D[0..63]

HD6

HD7

DBX DBX

HD8

D17

HD9

VCC

D18

41

HD10

99

D19

HD11

VCC3

HD12

HD13

HD14

HD15

HD16

2345678

D20

D21

D22

D23

D32

16

D33

91

HD17

D34

100

HD18

9

D35

HD19

67

VCC_DRAM

HD20

HD21

HD22

HD23

HD24

HD25

HD26

HD27

HD28

HD29

111213141718192021222324393829282726257985

D36

D37

D38

D39

D48

D49

D50

D51

D52

D53

MD30

MD30

HD30

D54

MD31

MD31

HD31

D55

PLINK0

PLINK0

PLINK1

PLINK0

MSTB

-MSTB

-HSTB

-MSTB

PLINK1

PLINK2

PLINK2

PLINK3

PLINK1

PLINK2

HSTB

CMD0

-HSTB

PLINK3

PLINK4

PLINK4

PLINK3

PLINK4

CMD0

CMD1

CMD1

CMD0

CMD1

PLINK5

PLINK6

PLINK5

PLINK6

PLINK5

PLINK6

CMD2

CMD3

CMD2

CMD3

CMD2

CMD3

PLINK7

PLINK7

30

PLINK7

CMD4

CMD5

CMD4

CMD5

CMD4

VCC3VCC3

16911005367

VCC3

VCC3

VCC3

DB32

HCLK

83

81

-587CAS0

DB32

DBXCLK

DB32

DBXCLK

VCC

41

VCC

VCC_DRAM

VCC_DRAM

CAS

RESET

84

-DRST

-DRST

-587CAS0

VT82C587VP

4.7K

4.7K

4.7K

R168

R166

R165

PLINK0

PLINK5

PLINK13

(EN/DI5 32-BIT DRAM)

(0 / 1)

— 88 —

4. Mother Board SBC 8352 (CACHE)4/16

D55

D54

D53

D52

D51

D50

525356575859626368697273747578

D0D1D2D3D4D5D6D7D8

GND5101721264055606771

A0A1A2A3A4A5A6A7A8A9A10

3736353433

32

A3A4A5A6A7A8A9

D63

D62

D61

D60

D59

D58

525356575859626368697273747578

D0D1D2D3D4D5D6D7D8

D[0..63]

GND5101721264055606771

D49

D48

D39

D38

D37

D36

D35

D9

D10

D11

D12

A11

A12

998281484746454449

100

A10

A11

A12

A13

A14

A15

D57

D56

D47

D46

D45

D44

D43

D9

D10

D11

D12

D34

D33

D32

D23

D22

D21

D20

D19

D18

D17

23678

9

90

A16

90

D42

D13

A13

D13

A17

D41

D14

A14

D14

79

D15

A15

A18

D40

79

D15

121318192223242528

D16

D17

D18

D19

D20

D21

CLK

ADSC

ADSP

ADVDEGWE/ZZ/N

898584838688879394959698979231

SRCLK2

-CADS

-ADS

-CADV

-C0E0

-GWE

D31

D30

D29

D28

D27

D26

D25

23678

9

121318192223242528

D16

D17

D18

D19

D20

D21

D16D7D6D5D4D3D2D1D0

D22

D23

D24

D25

D26

D27

D28

D29

BWE/N/PDIS

BW0

BW1

BW2

BW3

CE1

CE2

-BWE

-BE6

-BE4

-BE2

-BE0

-CE1

-ECS2

-BE6

-BE4

-BE2

-BE0

D24

D15

D14

D13

D12

D11

D10D9D8

D22

D23

D24

D25

D26

D27

D28

D29

29

66504342393816

NCNCNCNCNCNCNC

D30

D31

CE2

NC,LB0

VCC

VCC

VCC

VCC

9177706561544127201511

MODE

VCC3VCC3

29

66504342393816

NCNCNCNCNCNCNC

D30

D31

VCC

VCC

VCC

VCC3

VCC

VCC3

VCC

641451

NC,ZZ

NC,FT

VCC

VCC

4

641451

NC,ZZ

NC,FT

80130

N/N/DQP0

N/N/DQP1

VCC

80130

N/N/DQP0

N/N/DQP1

N/N/DQP0

N/N/DQU2

SYNC_RAM_64K32

N/N/DQP0

N/N/DQU2

MODE

D[0..63]

U4 U5

A0A1A2A3A4A5A6A7A8A9A10

3736353433

A3A4A5A6A7A8A9

A[3..8]

A[3..8]

32

998281484746454449

100

A10

A11

TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA011

TA[0..7]

TA[0..7]

A11

A12

A13

A12

A13

A14

A15

A16

A17

1

9

D

7

1

8

D

6

1

7

D

5

1

6

D

4

1

5

D

3

1

3

D

2

1

2

D

1

D

0

A0A1A2A3A4A5A6A7A8A9A10

10

A5A6A7A8A9

A14

A15

CLK

ADSC

ADSP

ADVDEGWE/ZZ/N

BWE/N/PDIS

BW0

898584838688879394959698979231

SRCLK2

-CADS

-ADS

-CADV

-C0E0

-GWE

-BWE

-BE7

-ADS

-CADS

A10

A11

-CADV

-C0E0

252421

A12

A13

-GWE

-BWE

A14

A15

-BE5

-BE7

A11

23226

A16

A18

SRCLK2

9876543

BW1

-BE5

A17

BW2

-BE3

-BE3

A12

TAR13

N/F

R136

BW3

-BE1

-BE1

A13

1

TAR14

N/F

R137A18

CE1

-CE1

-CE1

A14

CE2

-ECS2

WECEOE

272022

TWE

-TWE

CE2

NC,LB0

VCC

VCC

VCC

VCC

VCC

9177706561544127201511

MODE

U35

SRAM.32K X 8

VDD

28

VCC

VCC

RN21

VCC

246

135

VCC

VCC

VCC

VCC

4

8

7

-EC52

TAR13

TAR14

TAG SRAM

8K X 8

16K X 8

TAG ADDR

A5-A17

A5-18

CACHE SIZE

ON/B 256K

ON/B 512K

VCC

10K X 4

SYNC_RAM_64K32

0

R6

— 89 —

5. Mother Board SBC 8352 (DRAM)5/16

PD3

3

8

PD2

3

7

PD1

3

6

PD0

6

MD6
MD6
MD6
MD6
MD5
MD5
MD5
MD5
MD5
MD5
MD5
MD5
MD5
MD5
MD4
MD4
MD4
MD4
MD4
MD4
MD4
MD4
MD4
MD4
MD3
MD3
MD3
MD3
MD3
MD3
MD3
MD3

MD3
MD3
MD2
MD2
MD2
MD2
MD2
MD2
MD2
MD2
MD2
MD2
MD1
MD1
MD1
MD1
MD1
MD1
MD1
MD1
MD1
MD1
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0

4

3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3

2
1
0
9
8
7
6
5
4
3
2

1
0
9
8
7
6

5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0

D31

6

2

D30

6

0

D29

5

8

D28

5

6

D27

5

4

D26

5

2

D25

5

0

D24

2

7

D23

2

5

D22

2

3

D21

2

19753

D20
D19
D18
D17
D16

6

5

D15

6

3

D14

6

1

D13

5

7

D12

5

5

D11

5

3

D10

5

1

D

9

4

9

D

8

2

6

D

7

2

4

D

6

2

2

D

5

2

08642

D

4

D

3

D

2

D

1

D

0

A0A1A2A3A4A5A6A7A8A9A10

121314151617182831321929474445343340434142

MAA0

MAA1

MAA2

MAA3

MAA4

MAA5

MAA6

MAA7

MAA8

PD3

3

8

PD2

3

7

PD1

3

6

PD0

6

4

D31

6

2

D30

6

0

D29

5

8

D28

5

6

D27

5

4

D26

5

2

D25

5

0

D24

2

7

D23

2

5

D22

2

3

D21

2

19753

D20
D19
D18
D17
D16

6

5

D15

6

3

D14

6

1

D13

5

7

D12

5

5

D11

5

3

D10

5

1

D

9

4

9

D

8

2

6

D

7

2

4

D

6

2

2

D

5

2

08642

D

4

D

3

D

2

D

1

D

0

A0A1A2A3A4A5A6A7A8A9A10

121314151617182831321929474445343340434142

MAA9

BANK0 HIGH

A11

WE

MAA10

MAA11

-WEA

BANK0 LOW

A11

WE

RAS0

-RAS0

-RAS1

RAS0

RAS1

RAS1

RAS2

RAS2

RAS3

-CAS4

RAS3

CAS0

-CAS5

CAS0

CAS1

-CAS6

CAS1

CAS2

-CAS7

CAS2

CAS3

CAS3

SIM2

SIM1

MAA0

MAA1

MAA2

2468246

1357135

RN7 22X4

MA0

MA1

MA2

MA0

MA1

MA2

-587CAS0

-587CAS0
22

R173

MAA3

MAA4

MAA5

MA3

MA4

MA5

MA3

MA4

-587CAS1

-587CAS1
22

R174

MAA6

MAA10

8

7

MA6

MA10

MA5

MA6

MA10

-CA55

-CA57

1357135

2468246

RN3 22X4

-RCA55

-RCA57

-RCA55

-RA50

22

22X4

RN6

R178

-RRA50

-CA56

-CA54

-RCA56

-RCA54

-RCA57

-RCA56

-RA51

22

R177

-RRA51

-RRA50

-RRA51

-CA51

-CA53

-RCA51

-RCA53

-RCA54

-RCA51

MAA7

246822

135

MA7

-CA52

-CA50

7

8

-RCA52

-RCA50

-RCA53

-RCA52

MAA11

MAA8

MA11

MA8

MA11

MA7

RN4 22X4

-RCA50

MAA9

7

MA9

MA8

-WEA

R176

-WE

MA9

-WE

MAA0

MAA1

MD[0..63]

MD[0..63]

MAA2

MAA3

MAA4

MAA5

MAA6

MAA7

MAA8

MAA9

MAA10

MAA11

-WEA

-RAS0

-RAS1

-CAS4

-CAS5

-CAS6

-CAS7

— 90 —

6. Mother Board SBC 8352 (IDE)6/16

IDDP8

IDDP9

IDDP10

IDDP11

IDDP12

IDDP13

IDDP14

IDDP15

246

8

1012141618202224262830323436384042

1357911131517192123252729313335373941

IDE1

DA2

-DC53A

44

43

CON2X22

IDELED

-DIOWA

-DIORA

DDREQ

IDEIRQ

PRIMARY

DA0

DA1

135

RN12

33X4

246

18171615141312

B0B1B2B3B4B5B6

A0A1A2A3A4A5A6

U33

2345678

SA17

SA18

SA17

DA2

SA19

SA18

-DC51A

7

8

SA20

SA19

SA20

VCC VCC

ISA OSC2

-DC53A

223333

R158

SA21

SA21

-IDERST

-IDERST

ISA OSC1

SYS CLK

SYS CLK

33

R97

R76

R91

11

B7

A7

9

BCLK

BCLK

ISA0SC

IDDP7

IDDP6

DIR

1

19

VCC

IDDP5

OE

IDDP4

IDDP3

F245

IDDP2

IDDP1

IDDP0

DDREQ

VCC

SA7

SA6

SA5

SA7

SA6

SA5

SA4

18171615141312

B0B1B2B3B4B5B6

A0A1A2A3A4A5A6

U27

2345678

DD7

DD6

DD5

DD4

-DIOWA

-DIORA

1K

R171

SA4

SA3

SA3

SA2

DD3

DD2

33

R119

-DRDY

-DRDY

SA2

SA1

SA1

DD1

-DDACKA

IDEIRQ

DA1

-DDACKA

SA0

SA0

11

B7

A7

DIR

9

1

-MASTER

DD0

DA0

OE

19

-SOE

-DCSIA

F245

SA15

SA14

SA13

SA15

SA14

SA13

SA12

18171615141312

B0B1B2B3B4B5B6

A0A1A2A3A4A5A6

U29

2345678

DD15

DD14

DD13

DD12

SA12

SA11

DD11

SA11

SA10

DD10

SA10

SA9

DD9

SA9

SA8

11

9

DD8

SA8

B7

A7

1

-MASTER

DIR

OE

19

-SOE

-SOE

-MASTER

F245

U34

246

8

RN11

135

7

-XDIOWA

-XDIORA

DDRQA

DDRQA

IRQ14

-XDIOWA

-XDIORA

XD[0..7]

XD7

XD6

XD5

XD4

XD3

XD2

18171615141312

B0B1B2B3B4B5B6

A0A1A2A3A4A5A6

2345678

SD7

SD6

SD5

SD4

SD3

SD2

33X4

XD1

SD1

XD[0..7]SD[0..7]

XD0

11

B7

A7

9

SD0

DIROEF245

1

19

XDIR

XDIR

DD3

DD2

DD1

DD0

DD7

DD6

DD5

DD4

DD8

DD9

DD10

DD11

DD12

135786422468753

246875311357864

IDDP3

IDDP2

IDDP1

IDDP0

IDDP7

IDDP6

IDDP5

IDDP4

IDDP8

IDDP9

IDDP10

IDDP11

IDDP12

RN8

33X4

RN2

33X4

RN7

33X4

DD13

DD14

IDDP13

IDDP14

RN10

33X4

DD15

1

2

IDDP15

DD[0..15]

DD[0..15]

— 91 —

SD[0..7]

7. Mother Board SBC 8352 (EISA/PC104 SLOT)7/16

C

VCC

109876

RN49

12345

SD3

SD2

-IOCHCK

-IOCHCK

A1A2A3A4A5A6A7A8A9

B1B2B3B4B5B6B7B8B9

SL2

SD1

SD0

VCC

SD7

SD6

SD5

SD7

SD6

SD5

RES DRV

IRQ9

IRQ9

RES DRV

4.7KX8

SD4

SD4

SD3

-5V

DREQ2

VCC

SD3

SD2

SD2

SD1

-12V

-OWS

DREQ2

135

RN47

246

IRQ7

SD1

SD0

-OWS

SD0

7

8

IRQ6

IRQ5

IRQ4

IOCHRDY

AEN

IOCHRDY

AEN

SA19

A10

A11

B10

B11

+12V

-SMEMW

-SMEMR

-SMEMW

4.7KX4

SA19

SA18

SA17

SA18

SA17

A12

A13

A14

B12

B13

B14

-IOW

-IOR

-IOW

-IOR

-SMEMR

RN26

SA16

SA15

SA16

SA15

A15

A16

B15

B16

-DACK3

DREQ3

DREQ3

-DACK3

135

246

IRQ12

IRQ14

SA14

SA13

SA14

SA13

A17

A18

B17

B18

-DACK1

DREQ1

DREQ1

-DACK1

7

4.7KX4

8

IRQ10

IRQ11

SA12

SA11

SA10

SA12

SA11

SA10

SA9

A19

A20

A21

B19

B20

B21

-REFRESH

SYS CLK

IRQ7

IRQ6

IRQ7

-REFRESH

SYS CLK

SA9

SA8

A22

B22

IRQ5

IRQ6

SA8

SA7

A23

B23

IRQ4

IRQ5

RN24

SA7

SA6

A24

B24

IRQ3

IRQ4

135

246

DREQ7

DREQ0

SA6

SA5

SA5

SA4

A25

A26

B25

B26

-DACK2

TC

IRQ3

-DACK2

7

8

DREQ6

DREQ5

SA4

SA3

SA3

A27

A28

B27

B28

BALE

TC

BALE

4.7KX4

SA2

SA1

SA2

SA1

SA0

A29

A30

B29

B30

ISA OSC2

ISA OSC2

SA0

A31

246

8

4.7KX4

RN29

135

7

DREQ1

DREQ3

DREQ2

-SBHE

SA23

SA22

SA21

SA20

SA19

-SBHE

SA23

SA22

SA21

SA20

SA19

SA18

C0C1C2C3C4C5C6C7C8

A32

B31

B32D0D1D2D3D4D5D6D7D8D9

-MEMCS16

-IOCS16

IRQ10

IRQ11

IRQ12

IRQ15

IRQ14

IRQ10

IRQ11

IRQ12

IRQ15

-IOCS16

-MEMCS16

VC

SA18

SA17

SA17

-DACK0

IRQ14

-DACK0

246

RN25

135

-OWS

-MEMR

-MEMR

-MEHW

C9

C10

D10

DREQ0

-DACK5

DREQ0

-DACK5

8

7

-MEMCS16

-REFRESH

-IOCS16

-MEHW

SD8

SD9

SD10

SD8

SD9

SD10

SD11

C11

C12

C13

D11

D12

D13

DREQ5

-DACK6

DREQ6

-DACK7

DREQ5

DREQ6

-DACK6

330X4

-MASTER

SD11

SD12

SD12

SD13

C14

C15

D14

D15

DREQ7

DREQ7

-DACK7

SD13

SD14

SD14

SD15

C16

C17

D16

D17

-MASTER

-MASTER

R731KR148 330

IOCHRDY

SD15

C18

C19

D18

D19

VCC

PC104

R31

N/F

-BIOR

-IOR

753

864

-BIOR

-BIOR

-BIOR

-BIOW

-BSMEMR

-IOW

-SMEMR

-BIOW

-BIOW

-BSMEMR

-BIOW

-BSMEMR

PCLK1

VCC

RN38

-MSMEMW

-SMEMW

1

2

-MSMEMW

-MSMEMW

R30

N/F

246

135

-IOR

-IOW

-SMEMR

AENTCTC

AEN

R77

RAEN

RAEN

8

4.7KX4

7

-SMEMW

BALE

333333

R61

R54

RTC

RBALE

RTC

VCC

BALE

RBALE

-MEMR

-MEMR

R43

-RMEMR

-RMEMR

R42

N/F

-MEMW

-MEMW

VCC

33

R41

-RMEMW

-RMEMW

RCLK1

VCC

RN50

864

753

-INTR C

-INTR A

-INTR B

-INTR C

-INTR A

R46

N/F

AQ15

109876

RN16

12345

-SERR

SA2

-SERR

2.2KX4

2

1

-INTR D

-INTR B

-INTR D

MEMR

MEMW

SA3

753

864

-REQ0

-REQ1

-REQ0

SRHR

VCC

RN36

2.2KX4

-REQ2

-REQ1

-REQ2

4.7KX8

1

2

-REQ3

-REQ3

VCC

VCC

RN55

246

135

C45 47P

TC

4.7K

4.7K

4.7K

R13R3R74

IRQ9

-FRAME

-IOCHCK

8

4.7KX4

7

4.7K

R62

IRQ3

-FRAME

-12V+12V

-5VVCC

VCC

IRQ9

DREQ2

RES DRV

RES DRV

IRQ9

-SV

DREQ2

B1B2B3B4B5B6B7B8B9

-5V

VCC

GND

IRQ9

RSTDRV

SL1

IOCHK-

SD7

SD6

SD5

SD4

A1A2A3A4A5A6A7A8A9

SD7

SD6

SD5

SD4

SD3

-IOCHCK

SD3

-12V

DRQ2

SD2

SD2

-OWS

-OWS

-12V

SD1

SD1

+12V

-SMEMW

B10

B11

+12V

OWS-

SD0

IOCHRDY

A10

SD0

IOCHRDY

-SMEMW

-SMEMR

-SMEMR

-IOW

B12

B13

GND

SMEMW-

AEN

SA19

A11

A12

A13

AEN

SA19

SA18

-IOW

-IOR

-DACK3

-IOR

-DACK3

B14

B15

IOR-

IOW-

SMEMR-

SA18

SA17

SA16

A14

A15

SA17

SA16

DREQ3

-DACK1

DREQ3

-DACK1

B16

B17

DRQ3

DACK3-

SA15

SA14

A16

A17

SA15

SA14

DREQ1

-REFRESH

DREQ1

-REFRESH

SYS CLK

B18

B19

B20

DRQ1

DACK1-

SA13

SA12

A18

A19

A20

SA13

SA12

SA11

IRQ7

IRQ6

IRQ5

SYS CLK

IRQ7

IRQ6

IRQ5

B21

B22

B23

IRQ7

IRQ6

SYSCLK

REFRESH

SA11

SA10

SA9

SA8

A21

A22

A23

SA10

SA9

SA8

IRQ4

B24

A24

SA7

IRQ4

IRQ3

B25

IRQ5

SA7

A25

SA6

IRQ3

IRQ4

SA6

-DACK2TCBALE

-DACK2TCBALE

B26

B27

B28

TC

IRQ3

DACK2-

SA5

SA4

SA3

A26

A27

A28

SA5

SA4

SA3

IRQ10

IRQ11

ISA OSC1

ISA OSC1

B29

B30

VCC

BALE

SA2

SA1

A29

A30

SA2

SA1

IRQ12

-MEMCS16

-IOCS16

-MEMCS16

-IOCS16

IRQ10

IRQ11

IRQ12

IRQ15

B31D1D2D3D4D5D6D7D8D9D10

OSC

GND

IRQ10

IRQ11

IRQ12

IOCS16-

MEMCS16-

SBHE-

SA23

SA22

SA21

SA20

SA0

A31

C1C2C3C4C5C6C7C8C9

SA0

SA23

SA22

SA21

SA20

SA19

-SBHE

IRQ15

IRQ14

IRQ14

IRQ13

IRQ14

SA19

SA18

-DACK0

-DACK0

DREQ0

DACK0-

SA18

SA17

SA17

-MEMR

DREQ0

-DACK5

-DACK5

DREQ5

D11

DRQ0

DACK5-

MEMR-

MEMW-

C10

-MEMW

DREQ5

-DACK6

-DACK6

D12

DRQ5

DACK6-

SD8

C11

C12

SD8

SD9

DREQ6

DREQ6

D13

DRQ6

SD9

SD10

C13

SD10

DREQ7

-DACK7

-DACK7

DREQ7

D14

D15

DRQ7

DACK7-

SD11

SD12

C14

C15

SD11

SD12

-MASTER

-MASTER

D16

D17

VCC

MASTER

SD13

SD14

C16

C17

SD13

SD14

PCLK1

R33

N/F

VCC

-INTR B

-INTR D
PCLK2

-INTR B

-INTR D

PCLK2

-NGT1

D18F1F2F3F4F5F6F7F8F9F10

KEY

VCC

GND

SD15

C18

SD15

VCC

GND

GND

PCLKF

PCIINT3-

PCIINT4-

GND

GND

PCIINT1-

PCIINT2-

VCC

KEY

VCC

PCIRST-

E1E2E3E4E5E6E7E8E9

-INTR A

-INTR C

-PCI RST

GND

GNT0-

-NGT0

R34

-NGT1

F11

GNT1-

REQ0-

E10

E11

-REQ0

N/F

-REQ1

F12

GND

GND

E12

PCLK1

-REQ1

A D31

A D31

A 29

F13

AD31

REQ1-

PCLKE

GND

E13

A 29

PCLK4

F14

F15

AD29

AD30

E14

E15

A D30

PCLK3

PCLK4

F16

KEY

3.3V

3.3V

KEY

E16

-REQ3

-REQ3

A D27

F17

F18

3.3V

3.3V

E17

E18

-REQ2

A D27

A D25

F19

AD27

AD28

E19

A D28

A D26

VCC

A D25

C -BE3

C -BE3

F20

AD25

CBE3-

AD26

AD24

E20

A D24

A D23

A D23

A D21

F21

F22

AD23

AD22

E21

E22

A D22

A D20

R50

A D21

A D19

A D19

F23

AD21

AD19

AD20

AD18

E23

A D18

N/F

-GNT3

-GNT3

F24

F25

3.3V

3.3V

E24

E25

-GNT2

KEY

KEY

RCLK1

F26

3.3V

3.3V

E26

A D17

A D17

-IRDY

F27

F28

AD17

AD16

E27

E28

A D16

-FRAME

R49

N/F

-IRDY

-PLOCK

-DEVSEL

-DEVSEL

-PLOCK

F29

F30

IRDY-

PLOCK-

DEVESEL-

FRAME-

CBE2-

TRDY-

E29

E30

C -BE2

-TRDY

-IRDY

-DEVSEL

-IRDY

-SERR

A D15

A D14

A D12

A D10

A D14

A D12

AD14

AD12

CBE1-

PAR

C -BE1

PAR

GND

GND

KEY

KEY

A D10

GND

GND

A D13

A D8

AD10

AD13

A D11

A D8

A D7

AD8

AD11

-PERR

-PERR

-SERR

A D15

F31H1H2H3H4H5H6H7H8H9H10

AD15

PERR-

SERR-

SDONE

SB0-

STOP-

G1G2G3G4G5G6G7G8G9

E31

-STOP

-PLOCK

-PERR

-DEVSEL

-PLOCK

A D7

A D5

A D5

A D3

H11

H12

AD7

AD5

AD9

CBE0-

G10

G11

G12

A D9

C -BE0

A D6

-PERR

A D3

A D1

A D1

H13

AD3

AD1

AD6

AD4

G13

A D4

A D0

A D0

H14

AD0

AD2

G14

A D2

H15

G15

H16

KEY

KEY

G16

VCC

VCC

H17

G17

VCC

VCC

H18

G18

H19

GND

GND

GND

GND

G19

ISA/CPI SLOT (EISA)

SD4

SD3

SD2

SD1

AEN

SD0

IOCHRDY

SA19

SA18

SA17

SA16

SA15

SA14

SA13

SA12

SA11

SA10

SA9

SA8

SA7

SA6

SA5

SA4

SD7

SD6

-IOCHCK

SD5

SA3

SA2

SA1

SA0

-SBHE

SA23

SA22

SA21

SA20

SA19

SA18

SA17

-MEMR

-MEMW

SD8

SD9

SD10

SD11

SD12

SD13

SD14

— 92 —

SD15

-INTR A

-INTR C

-REQ0

-NGT0

-PCI RST

PCLK1

A D30

PCLK3

-REQ2
A D28

A D26

A D24

A D22

A D20

A D18

-GNT2

A D16

-FRAME

-TRDY

C -BE2

-STOP

PAR

C -BE1

A D13

A D11

A D9

A D6

C -BE0

A D4

A D2

8. Mother Board SBC 8352 (XIO/USB)8/16

V

+12

VCC

1

A11

SA12

SA11

SA22

4.7K

R65

SA6

SA6

LB DT

KBVCC

A12

A13

A14

29

SA13

SA14

SA12

SA13

SA14

SA23

SA23

4.7K

R113

4.7K

R56

SA7

SA7

KBVCC

246

13579

KB CK

3

JP11

2
1

A15A6NCCEOE

3

2

222431

30

VCC VP

SA15

SA16

-ROMKBCS

SA15

SA16

VCC

MS CK

8

10

BOX HEADER 5X2

MS DT

HEADER 1X3

WE

33

-MEMR

R116

-MEMR

-ROMKBCS

-MEMW

-MEMW

109876

RN30

12345

SAB

SA9

SA10

SA8

SA9

SA10

FB7

FB5

MS CLK

MS DATA

SA11

SA11

C59

C55

VCC

4K7X8

47P

47P

VCC

VCC

246

RN43

135

SD15

864

4.7K

R154

TURBO

SD14

SD13

SD15

SD14

SD13

(EN INT KB)

(EN INT P52)

(DIS INT RTC)

(SIO)

2

753

1

XD0

XD1

XD2

XD3

4.7K

4.7K

R112

R123

-ROMKBCS

-KB LOCK

8

4.7KX4

7

SD12

SD12

4.7KX4

4.7K

R151

SPEAK

RN35

RN27

246

135

SD11

SD11

SD10

VCC

VCC

U10

XD[0..7]

XD[0..7]

SA16

R29

4.7K 4.7K

R98

SAI

FS1

FROM-128K 8

SA16

SAI

FUSE

XD0

XD1

XD2

XD3

XD4

XD5

XD6

XD7

12141517181920

121110

SA0

4.7K

R130

4.7K

F83

KB_CLK

21

D0D1D2D3D4D5D6

A0A1A2A3A4A5A6A7A8A9A10

SA0

SA17

R99

-TRDY

SA1

SA1

SA17

-TRDY

F84

98765

SA2

SA3

SA4

SA2

SA3

SA18

SA18

4.7K

R129

4.7K

R100

SA0

SA0

FB10

FB

C52

C47

KB_DATA

SA5

SA4

SA19

SA19

4.7K

R125

4.7K

R101

-STOP

-STOP

VCC

47P

47P

SA6

SA5

+12V

SA7

SA6

SA20

SA20

4.7K

R124

4.7K

R67

SA4

D7

272623

SA8

SA7

SA4

SA9

SA8

SA21

4.7K

R121

4.7K

R66

SA5

SA10

SA9

SA21

SA5

25428

SA11

SA10

SA22

4.7K

R117

J5

864

123

KB CLK

KB DATA

8

7

SD9

SD8

SD9

SD10

J7

VCC

2

4.7KX4

4

MS DATA

MS CLK

4.7KX4

SD8

123

33

R37

USBDATA-

USBDATA+

VCC

4

33

R35

C40

864

RN20

753

XD4

XD5

XD6

-PCI RST

-PCI RST

R150

33

R96

-PCIRST

-PCIRST

HEADER 1X4

47P

C41

47P

N/F

2

1

XD7

U38F

R48
R38

4.7KX4

RES DRV

13 12

15K
15K

U38E

74F04

11 10

SIO RES

-IDERST

33

R149

74F04

U38C

8

74F04

U38D

9

(U58 HEADE_1)

-DRST

33

R145

6

5

U38B

74F04

CTBLED

4

3

TURBO

74F04

R58

VCC

VCC

VCC

33

R138

10K

R147

10K

VCC

246

135

JP3

RSTSW

TURBOSW

TURBO-SW

R127

TURBO

U39A

1

864

753

8

7

CTBLED

IDELED

C68

.1U

22

C79

.1U

3

2

33

R135

-WDO

RSTSH

2

1

PW LED

HEADER 4X2

1N414B

D4

74F08

C70

VCC

123

.1U

876

WD0

MR

LS1

PW GOOD

5

RST

WDI

PF0

VCC

GND

PFI

4

VCC

MAX708

PW LED

SPEAKER

R161

U38A

VCC

246

13579

33

CSPEAK

2

74F04

1

SPEAKER

876

123

C119

8

10

VCC

SIO OSC

PW-LED

KEYLOCK

47P

HEADER 5X2

C120

.1U

5

DS1232LP(N/F)

4

-KB LOCK

-KB LOCK

C67

47P

MS CLK

KB_CLK

KB_DATA

MS DATA

USBDATA-

USBDATA+

— 93 —

-EXTSMI

TURBO

SPEAKER

9. Mother Board SBC 8352 (ALI5113 Super I/O)9/16

VCC

DENSEL

1

0

VCC

6789

1

06789

VCC

R24

1K

7531

RN48

1KX4

VCC

RN44

1KX8

5432154321

RN44

1KX8

13579111315161821232527293133

J6

246

8

10121416182022242628303234

8642

DENSEL

DRATEO

-INDEX

-MTRO

-DR1

DR0

-MTR1

-DIR

-STEP

-WDATA

-WGATE

-TRKO

2468101214161820222426

13579

11131517192123

-SLTN

-INIT

-ERR

-AFD

-STB

PD0

PD1

PD2

PD3

PD4

-WRPROT

-RDATA

-HDSEL

-SDKCHG

PD5

PD6

PD7

-ACK

BUSYPESLCT

VCCF

246

13579

JP15

VCCF

HEADER 3X2

VCCF

+12VF

246

13579

JP20

RI28

-RI2/CTS2-

+12VF

8

10

+12VF

DCD2

DCD28

FI1DCD1

8

10

BOX HEADER 5X2

HEADER 5X2

DSR1

RTS1

246

13579

JB

CTS1

8

10

BOX HEADER 5X2

R144

.1U

C143

.1U

-RT52/RT52+

SOUT2

DTR2

DCD2

SIN2

-DSR2/RT52-

-CT52/CT52+

VCC

25

C20

180P

C13

180P

C23

180P

111317

V+

VCC

C1+

C1-

U24

121415

.1U

C145

C146

.1U

C19

C9

180P

C10 C12 C15 C17

V-

C2+

231

T1OUT

C2-

T1IN

7

6

16

-RT52

TXD2

180P

180P

C11 C14 C15 C18

28

T2OUT

T3OUT

T2IN

T3IN

20

-DTR2

9

T4OUT

T4IN

21

4

272318

R1IN

R2IN

R1OUT

R2OUT

8

5

2622192425

-DCD2

BXD 232

-DSR2

VCC

-RI2/CT52-

R3IN

R4IN

R5IN

R3OUT

R4OUT

R5OUT

-CTS2

-RI2

GND

-EN

10

SHDN

ADM213

-DSR2/RT52-

J9

-DCD2/TX2-

485RXD-

876

VCC

ROREDE

U20

123

RXD 485

2

U36A

1

-RT52

-RT52/RT52

-CT52/CT52+

RI28

246

8

13579

SIN2/TX2+

SOUT2/RX2+

-DTR2/RX2-

485RXD+

5

B

A

GND

DI

4

TXD2

74F04

10

BOX HEADER 5X2

876

LTC485

U17

123

RXD 422

485RXD-

485RXD+

B

VCC

ROREDE

+12VF+12V

A

JP16

5

GND

4

485TXD+

SIN2/TX2+

246

13579

485TXD-

-DCD2/T2-

DI

LTC485

F53

SIN2

485RXD+

SOUT2/RX2+

8

DCD28

485RXD-

-DTR2/RX2-

C33

.1U

FUSE

SOUT2

10

DTR2

JP1913

12

11

RXD 485

RXD2

HEADER 6X2

RXD 422

RXD 232

246

5

VCC

4.7K

SUPIOCLK

R25

VCC

SUPIOCLK

4.7K

IRQ11

IOCHRDY

IOCHRDY

NO5

R195

TRQ9

SA0

SA0

DREQ1

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

DREQ2

IRQ4

IRQ3

IRQ6

IRQ7

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

DREQ2

IRQ4

IRQ3

IRQ6

IRQ7

-HGATE

4849505153545556523837403910911784398972596991798981918393

U14

D0D1D2D3D4D5D6

100

I

CHR

O

9

5

N

D

G

6

7

N

D

G

4

7

N

D

G

67

N

D

G

2

V

C

C

1

5

V

C

C

2

0

/

2

X

2

1

/

1

X

5

8

P

RGD

W

2

2

I

DED

2

6

HDC

2

5

HDCSD

2

4

I

E

D

2

3

I

E

D

2

7

I

C

O

282930313233344142434644453635571617141312181978888292809085878486

-DACK1 A0

D7

Y

D

LK1

4

C

_

A

D

R

Q
/

J

AMECS

G

/

7

K_A

DAC

IJ/

I

2

T

X

S

R

/

I

J

2

X

R

R

/

I

5

E

N

H

R

Q

/

I

L

1

1

E

N

R

Q

/

/

1

6

1

1

S

SA1

5

A

C

A1A2A3A4A5A6A7A8A9

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA1

SA2

SA3

SA4

SA5

SA6

SA7

IRQ4

IRQ3

FINTR/IRQ6

PINTR/IRQ7

FDRQ/DRQ2

AEN

IORJ

IOWJ

SA9

AEN

-IOR

-IOW

SA8

SA9

AEN

-IOR

-IOW

-DACK2TCRES DRV

-HDATA

-HDSEL

-DIR

-STEP

-DR0

DIR

STEPJ

HDATAJ

HGATEJ

HDSELLJ

DACK2JTCRESET

RDATAJ

DSKCHG

-RDATA

-DSKCHG

-WRPROT

-DACK2TCRES DRV

DREQ3

-DI1

DRV0J

DRV1J

DRV2J/VIO

WRTPTJ

TRKOJ

INDEXJ

-TRKO

-INDEX

SA10

SA10

-MTR0

-MTR1

DACK3

DENSEL

SOUT1

MTR0J

MTR1J

TXD1/PCF0

DRV3J/SA10

MTR3J/DRQ_C

MTR2J/DACK_C

DENSEL/DRVDEN0

PREN/DRVDEN1

DRV/IRQ_A

RXD1

RXD2

CTS1J

CTS2J

SIN1

RXD2

-CTS1

-CTS2

-DSR1

IRQ10

TXD2

-RTS1

-RTS2

-DTR1

RTS1J/PCF1

TXD2/TDCCF

RTS2J/S2CF0

DSR1J

DSR2J

DCO1J

DCD2J

-DSR2

-DCD1

-DCD2

-RI1

IRQ5

-DTR2

94

P

D

DTR1J/IDEF

IRQ_B/DRV2

P

D

DTR2J/S2CF1

P

D

P

D

P

D

P

D

P

D

P

D

T

S

B

E

R

O

TOF

A

U

D

INI

T

I

L

T

S

N

C

E

R

R

L

S

C

P
ACK
BUS

RI1J

RI2J

-RI2

— 94 —

C32

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

2468246

RN41

33X4

1357135

6

3

7

6

4

6

6

5

5

6

6

4

6

8

3

6

9

2

7

0

1

7

1

0

7

7

J

7

6

J

7

4

J

7

3

J

7

5

J

5

9

T

6

0

E

6

2

J

6

1

Y

RN46

864

753

-ACK

BUSYPESLCT

8

RN42

33X4

7

753

2

RN40

33X4

1

864

-SLIN

-INIT

-ERR

VCCFVCC

1

2

-STB

33X4

F52

-AFD

.1U

DCD1

RXD1

TXD1

RXD1

CTS1

RI1

272318

R1IN

R2IN

R3IN

R4IN

R5IN

R1OUT

R2OUT

R3OUT

R4OUT

R5OUT

5

2622192425

-DSR1

SIN1

-CTS1

-RI1

R184OR185

GND

-EN

DTR1

10

SHDN

ADM213

N/F

FUSE

VCC

R26 33

C139

U21

C141

.1U

111317

VCC

C1+

121415

.1U

C142

R140

V+

C1-

.1U

VCCF

+12VF

.1U

RT51

TXD1

DTR1

DCD1

DSR1

9

4

231

28

V-

T1OUT

T2OUT

T3OUT

T4OUT

C2+

C2-

T1IN

T2IN

T3IN

T4IN

7

6

8

16

20

21

-DCD1

-RT51

TXD1

-DTR1

VCC

10. Mother Board SBC 8352 (CLOCK BUFFER)10/16

U37A

1

-IOR

RTCRD-

3

2

74F32

U37B

RTCWR-

6

4

-IOR

-IOR

5

-RTCCS

R126

74F32

4.7K

MOT

1

J_RTC CONFIG

IRQ8-

IRQ8-

VCC: 24

GND: 12

23

19

IRQ-

SQW

CS-ASR/W-DSRESET-

1314151718

-RTCCS

RTCAS

RTCWR-

RTCRD-

-DRST

RTCAS

-RTCCS

IN: CLEAR CMOS

OUT: NORMAL

JP10

2

RTC RSV1

21

22

RSV1

RSV2

AD0

AD1

AD2

AD3

AD4

AD5

AD6

45678

9

10

XD0

XD1

XD2

XD3

XD4

XD5

XD6

HEADER 1X2

1

AD7

11

XD7

XD[0..7]

XD[0..7]

-IOCHCK

JPS

VCCVCCVCC

123

VCC

R188

10K

-WDO

HEADER 3

CLSWDT

ISAOSC1

181716151413121110

R87

RA1

RA0

VCC

CLKI

CLKO

RA2

RA3

RTCC

RST

GND

RB0

U42

123456789

R86

RB1

R85

RB2

R84

RB3

PIC16C54

SIO

SIO OSC

OSC

ISA_SLOT

USB

ISAOSC

USBCLK

SUPER I/O

585

SUPIOCLK

SMCPCLK

586

PCI 4

SIOPCLK

PCLK4

PCI 3

PCLK3

PCI 2

PCLK2

PCI 1

PCLK1

587+2

PBSRAM

DBXCLK

SRCLK2

585

CPU

PMCHCLK

CPUCLK

AEN

ENWDT

DISWDT

CLSWDT

AEN

VCC

22282726252423212019181716

NE

I12

IO8

IO7

IO6

IO5

VCC

NCI0I1I2I3I4I5I6I7I8I9

U9

1234567

SA0

SA1

SA2

SA3

SA4

SA5

SA0

SA1

SA2

SA3

SA4

SA5

DIOOUTCS

IO4

IO3

9

1011121314

SA6

SA7

SA8

SA6

SA7

-IOW

DIOINCS

-DRST

-DRST

-IOW

I11

IO2

IO1

I10

SA9

SA10

SA8

SA9

SA10

-IOR

-IOR

IOE

GND

15

NC

NC

8

GAL20V8-PLCC

R189

R190

10K

10K

DISWDT

ENWDT

X1

14.318MHz

2

10P

C48

1-2

JCKS

Freq

282725241516222119

REF0

OSCIN

235

1

10P
C49

3-4

open

50MHz

55MHz

REF1

48MHZ

OSCOUT

1-2

60MHz

24MHZ

OE

JP12

3-4

66MHz

BCLK0

SEL0

13

12

2

4

1

3

BCLK1

SEL1

VCC

18

BCLK2

BCLK3

BCLK4

BCLK5

CPUVCC

CPUVCC

VCC

1

8

1420264111723

HEADER 2X2

.1U .1U

C50 C51

VCC3

679

PCLK0

VCC

CPUVCC

FB9

PCLK1

PCLK2

VSS

C58 C54

C46

C65

+

10

PCLK3

VSS

.1U .1U

.1U

1OU

C74

VSS

.1U

VSS

ICS9159-14

— 95 —

11. Mother Board SBC 8352 (Power)11/16

VCO_CORE

C153

.1U

C150

.1U

10K

RA1

L6

1.3UH

10U

+

C155

8765432

VFB

VCCA

VCCD

GNDP

HIDRV

VCCQP

GNDD

GNDA

VREF

VID3

9

10111213141516

VCC

TC152

1500U

+

C151

1500U

+

D52

PB160L40

M11

876

DDD

555

123

5

876

SI4410DY

M12

123

+

DDD

555

C154

5

D

G

SI4410DY

4

1U

D

G

4

159

1000U

++ +

DS1

PSR16C30

1

IFB

CEXT

PRGD

VID2

VID1

VID0

C158

C157

C156

1000U

1000U

68P

JP22

135

246

VID3

VID2

VID1

7

8

VID0

HEADER 4X2

C85

C89

C93

.01U

C126

C118

C124

C71

C115

C116

10U

+

.1U

.1U

.1U

.1U

.1U

C81

C57

C114

C75

.1U

C128

.1U

.1U

C127

.1U

.1U

C22

.1U

.1U

C43

.1U

C106

.01U

TC6

100U

+

TCS

100U

+

.1U

.1U

C111

C102

C94

C107

C112

.01U

.01U

.01U

.01U

.01U

C62

.1U

VCC

Q1

LT1084CT

2

3

VCC3

VIN VOUT

C130

VCC

.1U

C117

.1U

C125

.1U

C123

.1U

1234J3

HEADER 4

-5V

-12V

VCC

+12V

C101

VCC_CORE

C103

+

C108

.1U

C29

.1U

10U

-12V

.1U

C78

1OU

+

TC3

C24

C83

1OU
+

.1U

.1U

C80

C28

.1U

.1U

-5V

10K

10K

10K

10K

C148

.1U

R204

10K

VCC

C149

R201

R202

R203

.1U

+12V

R200

VCC

CPUVCC

TC7

100U

+

VCC_CORE

VCC3

CPUVCC

246

C69

1OU

+

R141

120 1%

1

J

A

D

C121

1OU

+

JP8

R142

196 1%

135

HEADER 3X2

CB4 .1U

VCC3 VCC_CORE

C86

C88

C95

C113

C92

C96

C110

C104

+

+

+

.1U

.1U

.1U

.1U

.1U

.1U

.1U

.1U

TC2

CTC1

C127

100U

100U

10U

C90 C109C99C97C91C100C105C87C98

C82
+

.O1U .O1U .O1U .01U .01U .01U .01U .01U .01U

10U

FOR CPU DE_COUPLE

VCC3

VCC3

— 96 —

12. Mother Board SBC 8352 (10 BSAE/T ETHERNET)12/16

J15

TTX-

U15

VCC

246

8

135

7

BOX HEADER 4X2

TRX+

TTX+

16151413121110

16151413121110

1234567

1234567

TPRX+

TPRX+

TPRX-

R18

1K

GND1

TRX-

9

9

8

20F-00IN

8

C38

.1U

TPRX-

R28

51 1%

R27

51 1%

VCC

LED_YLE

LED1

636261605958575664656667686970

PA0

PA1

R17

PA2

VCC

C36

PA3

10K

.01U

PA4

R16

PA5

10K

PA6

PA7

VCC

EMD0

EMD1

DMD2

EEDI/MD0

EEDO/MD1

876

U19

123

EMD3

MD3

MD4

EECK/MD2

BNCSW/MD5

5

NC

NC

VCC

GND

CSCKDI

DO

4

EMD2

EMD1

MED0

EMD6

71

MD7

(SLOT)/MD6

IRQ3

6

IRQ3

93C46

IRQ4

8

X2

IRQ5

IRQ9

IRQ10

1034949392

IRQ4

IRQ5

IRQ9

+12V

246

135791113

JP21

VCC

CD+

CD-

BNCEN

VCC

C26

22P

R19 330

33

20MHZ

R22

C27

IRQ11

IRQ10

IRQ11

22P

IRQ12

IRQ15

91

IRQ12

IRQ15

LED2

EECS

BPCS

LED_RED

LPTX+

LILED

LPTX-

LPTX-

LPTX+

TPRX+

TPRX-

TPRX-

TPRX+

BNCEN

CD+

CD-

33

R23

77787980555049464554424140393837767574

X2

X1

8

101214

RX+

RX+

RX-

16

15

BOX HEADER 8X2

TX+

TX-

RX-

TX+

GND1

VCC

136474853724344515273

TX-

VCC

TEST1

TEST2

TEST3

R11

270 1%

R12

270 1%

R10

39 1%

R9

39 1%

R8

39 1%

R7

39 1%

P1P2P3

VCC

VCC

VCC

VCC

VCC

P11

GND1

C3

C21

P12

GND

GND

P13

.01U

.01U

GND

GND1

GND

GND

100

GND

VCC VCC VCC GND1

P13

P3

C35

.1U

P12

P2

C34

.1U

P11

P1

C31

.1U

C25

.1U

VCC

C73

.1U

SA[0..19]

SA[0..19]

U15

SA0

969798

SA0

SA1

SA1

SA2

SA2

99

SA3

SA3

SA4

345

SA4

SA5

SA5

SA6

SA6

SA7

7

SA7

SA8

SA9

9

111213151617182022

SA8

SA9

SA10

SA10

SA11

IRQ3

SA11

SA14

IRQ4

IRQ3

SA14

SA15

IRQ5

IRQ4

SA15

SA16

IRQ9

IRQ5

SA16

SA17

IRQ10

IRQ9

SA17

SA18

SA18

IRQ11

IRQ10

IRQ11

SA19

SA19

IRQ12

IRQ15

IRQ12

IRQ15

SD0

SD1

SD2

SD3

SD4

26272829303132

SD0

SD1

SD2

SD3

SD4

SD5

SD5

SD6

SD6

33

SD7

SD7

SD8

SD9

SD10

88878685848382

SD8

SD9

SD10

— 97 —

SD11

SD11

SD12

SD12

SD13

SD13

SD14

SD14

SD15

81

SD15

SD[0..15]

SD[0..15]

BALE

SYSCLK

IRO

IOW

SMEMR

RST

2

141921233524258990

BALE

SYSCLK

-IRO

-IOW

-SMEMR

RST

AEN

BALE

-IRO

-IOW

SYS CLK

-SMEMR

RST DRV

AEN

IOCHRDY

MEMW

IOCHRDY

-MEMW

AEN

-MEMW

IOCHRDY

MEMR

IO16

95

-MEMR

IOCS16

-MEMR
IOCS16

13. Mother Board SBC 8352 (SERIAL PORT INTERFACE)13/16

VCCF

+12VF

246

JP171357

RIC D

8

10

9

DSRC D

RTSC D

246

HEADER 5X2

13579

J11

CTSC D

8

10

BOX HEADER 5X2

VCCF

246

JP181357

+12VF

RIC C

8

10

HEADER 5X2

9

DSRC C

J10

RTSC C

CTSC C

246

13579

8

10

BOX HEADER 5X2

VCC

IRQ11

4.7K

R70

SUPIOCLK

VCC

SUPIOCLK

IRQ11

IOCHRDY

4.7KR69

IRQ9

VCC

IRQ9

IOCHRDY

SA0

SA0

VCCF

+12VF

C136

.1U

C135

.1U

SOUTC C

DTRC C

RTSC C

VCC

111317

2

3

1

V-

V+

VCC

T1OUT

T2OUT

C1+

C1-

C2+

C2-

T1IN

121415

.1U

.1U

SD4

SD5

SD4

SD5

4
A
AMECS

K_A

I

T

R

I

R

R

I

R

Q

I

R

Q

1

1

A

SA4

SA5

SA6

SA4

SA5

SD6

SD6

X
X
5
1
/

SA6

SA7

16

SD7

SD7

2
2

1
C

SA7

D7

SA8

T2IN

7

6

20

SOUTC-

DTRC-

RTSC-

IRQ10

IRQ9

IRQ10

IRQ9

IRQ6

IRQ4

IRQ3

FDRQ/DRQ2

J

+

S

SA9

AEN

-IOR

SA8

SA9

AEN

VCC

U28

C137

C138

SD0

SD1

SD2

SD3

SD0

SD1

SD2

SD3

4849505153545556523837403910911784398972596991798981918393

U13

D0D1D2D3D4D5D6

100

I

Y

CHR

D

O

9

5

N

D

G

6

7

N

D

G

4

7

N

D

G

67

N

D

G

2

V

C

C

1

5

V

C

C

2

0

/

2

LK1

X

C

2

1

/

1

_

X

D

R

5

8

2

2

2

6

2

5

2

4

2

3

2

7

G
/

P

RGD

G

W

I

/

7

DED

DAC
/

J

5

1

HDC

/

J

5

0

HDC
I

/

E

E

D

N

H

I

/

L

E

E

D

N

/

I

1

6

S

C

O

A0A1A2A3A4A5A6A7A8A9AEN

282930313233344142434644453635571617141312181978888292809085878486

SA1

SA2

SA3

SA1

SA2

SA3

DCDC C

CTSC C

RIC C

28

9

42723

R1IN

T3OUT

T4OUT

T3IN

T4IN

R1OUT

8

5

21

CT5D-

RID-

VCC

IRQ6

IRQ7

IRQ7

WDATAJ

WGATEJ

FINTR/IRQ6

PINTR/IRQ7

IORJ

IOWJ

DACK2JTCRESET

-IOW

RES DRV

-IOR

-IOW

SINC C

DSRC C

DCDC C

18

R2IN

R3IN

R4IN

R2OUT

R3OUT

R4OUT

262229

SIND-

DSRD-

DIR

STEPJ

HDSELJ

RDATAJ

DSKCHG

RES DRV

SINC C

SOUTC C

R5IN

R5OUT

24

DCDD-

DRV0J

DRV1J

WRTPTJ

TRKOJ

DTRC C

10

-EN
25

SA10

DRV2J/VIO

INDEXJ

IRQ10

VCC

GND

SHDN

ADM213

SA10

VCC

SOUTC-

MTR0J

MTR1J

TXD1/PCF0

DRV3J/SA10

MTR3J/DRQ_C

MTR2J/DACK_C

DENSEL/DRVDENO

PREN/DRVDEN1

DRV/IRQ_A

RXD1

RXD2

CTS1J

CTS2J

DSR1J

SINC

SIND

CTSC-

CTSD-

DSRC-

IRQ10

VCCF

C131

.1U

U22

C133

C134

SOUTD-

RTSC-

RTSD-

DTRC-

DTR1J/IDEF

RTS1J/PCF1

TXD2/TDCCF

RTS2J/S2CF0

DSR2J

DCD1J

DCD2J

RI1J

DSRD-

DCDC-

DCDD-

RIC-

DCDC D

+12VF

C132

.1U

111317

V-

V+

VCC

C1+

C1-

C2+

C2-

121415

16

.1U

.1U

IRQ5

DTRD-

94

P

D

IRQ_B/DRV2

P

D

DTR2J/52CF1

P

D

P

D

P

D

P

D

P

D

P

D

T

S

B

E

R

O

TOF

A

U

D

INI

T

I

L

T

S

N

C

E

R

R

L

S

C

P
ACK
BUS

RI2J

RID-

SOUTC D

DTRC D

RTSC D

2

3

1

T1OUT

T2OUT

T1IN

T2IN

7

6

20

SOUTD-

DTRD-

RTSD-

6

7

6

6

6

5

6

4

6

3

6

2

7

1

7

0

7

J

7

J

7

J

7

J

7

J

5

T

6

E

6

J

6

Y

28

T3OUT

T4OUT

T3IN

T4IN

21

3
4
5
6
8
9
0
1
7
6
4
3
5
9
0
2
1

SINC D

SOUTC D

CTSC D

RIC D

9

42723

R1IN

R1OUT

8

5

CT5D-

RID-

VCC

DTRC D

SINC D

DSRC D

R2IN

R3IN

R2OUT

R3OUT

262229

SIND-

DSRD-

DCDC D

18

R4IN

R5IN

R4OUT

R5OUT

DCDD-

-BIOR

-BIOW

-BSMEMR

-BSMEMW

SD0

SD1

SD2

SD3

-BIOR

-BIOW

-BSMEMR

-BSMEMW

975

1Y1

1A1

1Y2

1A2

12

1Y3

1A3

8

I3

257

U18

346

3

1Y4

2Y1

2Y2

2Y3

1A4

2A1

2A2

2A3

111315

17

-RIOR

-RIOW

-RSMEMR

-RSMEMW

-RIOR

-RIOW

-RSMEMR

000102

101215

Q1Q2Q3Q4Q5

D1D2D3D4D5

111314

SD0

SD1

SD2

2Y4

2A41G2G

1

19

DIOINCS

-RSMEMW

246

13579

J14

03

Q6

D6

CLK

9

SD3

DIOOUTCS

CLR

1

VCC

74F244

8

10

74F174

BOX HEADER 5X2

181614

10

GND

-EN

SHDN

24

25

U23

246

ADM213

I0I1I2

— 98 —

14. Mother Board SBC 8352 (DK65550PCI)14/16

RASB#

CASBH

CASBL

HEB#

BASA#

CASAH

CASAL

WEA#

AA8

153

AA8

156

RASA

159

160

CASAH

157

155

WEA

CASAL

OEAB#

OEAB

MBD[0..15]

MBD[0..15]

MBD0

MBD1

MBD2

127

128

129

MBD0

MBD1

MBD3

130

MBD2

MBD4

131

MBD3

MBD4

MBD5

132

MBD5

P[0..23]

P[0..23]

MAD[0..15]

VAA[0..8]

246

8

1357HEADER 4X2

JP14

246

VAA[0..8]

MAD[0..15]

U11

2

3

9

P

2

2

9

P

2

1

9

P

2

0

9

P

1

9

9

P

1

8

9

P

1

7

9

P

1

6

9

P

1

5

8

P

1

4

8

P

1

3

8

P

1

2

8

P

1

1

8

P

1

0

8

P

9

8

P

8

8

P

7

7

P

6

7

P

5

7

P

4

7

P

3

7

P

2

7

P

1

7

P

0

7

P

122
121
120
119
118
117
116
115
114
113
112
111
110
109
107
106

8

4.7KX4

RN33

135

7

MAD2

MAD3

MAD4

MAD5

MAD0

MAD1

MAD2

MAD3

MAD4

MAD5

MAD6

MAD7

MAD8

MAD9

MAD10

MAD11

MAD12

MAD13

MAD14

MAD15

AA0

AA1

AA2

AA3

AA4

AA5

AA6

AA7

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

145

146

147

148

149

150

151

152

AA0

AA1

AA2

AA3

AA4

AA5

AA6

MAD1

MAD2

MAD3

MAD4

MAD5

MAD6

MAD7

MAD8

MAD9

MAD10

MAD11

MAD12

MAD13

MAD14

MAD15

7

2

3

P

6

2

2

P

5

2

1

P

4

2

0

P

3

1

9

P

2

1

8

P

1

1

7

P

0

1

6

P

8

1

5

P

7

1

4

P

6

1

3

P

5

1

2

P

4

1

1

P

3

1

0

P

2

9

P

1

8

P

9

7

P

8

6

P

6

5

P

5

4

P

4

3

P

3

2

P

2

1

P

1

0

P

1

5

C

D

M

1

4

C

D

M

1

3

C

D

M

1

2

C

D

M

1

1

C

D

M

1

0

C

D

M

9

C

D

M

8

C

D

M

7

C

D

M

6

C

D

M

5

C

D

M

4

C

D

M

3

C

D

M

2

C

D

M

1

C

D

M

0

C

D

M

AA7

MBD6

MBD7

133

134

MBD6

MBD8

135

MBD7

MBD8

MBD9

MBD10

136

137

MBD9

MBD11

138

MBD10

MBD11

MBD12

MBD13

140

141

MBD12

MBD13

MBD14

MBD15

143

144

MBD14

MBD15

ENAVDD

SHFCLKMLP

SHFCLKMLP

M

SHFCLK

FLM

FLM

ENAVDD

R104

LP

FLM

ENAVDD

ENAVEE

ENAVEE

33

ENAVEE/ENAVDD

ENAVEE

ENABKL

ENABKL

33

R105

123

125

126

124

5354706968676261556058576564101

WEB

ACTI

RASB

CASBL

CASBH

ENABKL

560

R120

RSET

RED

RED

R

GREEN

BLUE

GREEN

BLUE

B

G

BHSYNC

BVSYNC

BHSYNC

BVSYNC

VSYNC

HSYNC

103

RASC

CASCH

104

102

CASCL

CGN
CGN

CVC
CVC

M
M
M

M
M
M

100

WEC

G
G
G

I
I

DGN
DGN
B
B
B
B
A

I
I
V
V
V
DVC
B
B
A

OEC

NDC
N
N
G
G

G
G
G
G
G

V
V
CCC
C
C

V
V
V

R2

0

655OPCI

VCC3

VCC

VCCM

R51

208

1

D

202

0

D

206

1

C

205

2

C

105
139

B

D

161

A

D

184

N

D

7

7

N

D

8

9

D

6

3

D

5

2

N

D

3

9

N

D

2

6

N

D

1

2

N

D

5

6

N

D

181

C

C

8

0

C

C

108
142

B

C

158

A

C

6

6

C

4

2

C

C

9

C

C

5

9

C

C

246

JP913

C61

FB8

2

1

+

C63

5

.1U

10U

HEADER 3X2

BEAD

0

VCCI

C/BE0

C/BE1

C/BE2

STOP

-STOP

PAR

-STOP

PAR

PAR

C -BE0

C -BE1

C -BE0

C -BE1

C/BE3

10

C -BE2

C -BE3

C -BE2

C -BE3

VCC

RESET

CLK

PERR

29

207

201

-PCI RST

PCLK3

-PERR

-PCI RST

R52

4.7K

SERR

30

-SERR

STNDBY

178

ROMA0

179

180

ROMA1

IDSEL MAD0

FRAME

IRDY

TRDY

DEVSEL

11

222324252731433221

-FRAME

-IRDY

-TRDY

-DEVSEL

A D21

-TRDY

-IRDY

-FRAME

-DEVSEL

ROMA2

182

183

ROMA3

ROMA4

185

187

ROMA5

ROMA6

189

191

ROMA7

ROMA8

192

190

ROMA9

ROMA10

186

188

ROMA11

ROMA12

ROMA13

193

194

ROMA14

ROMA15

196

195

ROMA16

ROMA17

197

198

ROMOE

XTALI

203

154

200

10K

R63

OCS

VCC

— 99 —

32KHZ

HREF

VREF

99

98

515049484746454441403837363534

A D00

4.7K

4.7K

R106

R107

A D[0..31]

A D[0..31]

AD00

A D01

AD01

A D02

AD02

A D03

AD03

A D04

AD04

A D05

AD05

A D06

AD06

A D07

AD07

A D08

AD08

A D09

AD09

A D10

AD10

A D11

AD11

A D12

AD12

A D13

AD13

AD14

33

A D14

A D15

AD15

AD16

AD17

AD18

AD19

AD20

AD21

20191817161514

A D16

A D17

A D18

A D19

A D20

A D21

AD22

AD23

AD24

8765432

13

A D22

A D23

A D24

A D25

AD25

A D26

AD26

A D27

AD27

A D28

AD28

A D29

AD29

A D30

AD30

1

A D31

AD31

VCC

AVCC

FB6

VCC

C42

FB2

10U

+

C44

.1U

2
1

C56

10U

+

C53

.1U

C64

10U

+

C60

.1U

2
1