California Micro Devices CM88L70CPEI, CM88L70CPE, CM88L70CP, CM88L70PEI, CM88L70PE Datasheet

CALIFORNIA MICRO DEVICES

CM88L70/70C

CMOS INTEGRATED DTMF RECEIVER, 3 VOLT VERSION

Features		Applications
• 2.7 to 3.6 volt operating range		•	PCMCIA
•	Full DTMF receiver	•	Portable TAD
• Less than 18mW power consumption		•	Mobile radio
•	Industrial temperature range	•	Remote control
• Uses quartz crystal or ceramic resonators		•	Remote data entry
• Adjustable acquisition and release times		•	Call limiting
• 18-pin DIP, 20-pin QSOP, 18-pin SOIC,		•	Telephone answering systems
	20-pin PLCC, 20-pin TSSOP	•	Paging systems
•	CM88L70
	- Power down mode
	- Inhibit mode

- Buffered oscillator output (OSC 3) to drive other devices

Product Description

The CAMD CM88L70/70C provides full DTMF receiver capability by integrating both the bandsplit filter and digital decoder functions into a single 18-pin DIP, SOIC, or 20-pin PLCC, TSSOP, or QSOP package. The CM88L70/70C is manufactured using state-of-the-art CMOS process technology for low power consumption (35mW, max.) and precise data handling. The filter section uses a switched capacitor technique for both high and low group filters and dial tone rejection. The CM88L70/70C decoder uses digital counting techniques for the detection and decoding of all 16 DTMF tone pairs into a 4-bit code. This DTMF receiver minimizes external component count by providing an on-chip differential input amplifier, clock generator, and a latched three-state interface bus. The on-chip clock generator requires only a low cost TV crystal or ceramic resonator as an external component.

Block Diagram

© 2000 California Micro Devices Corp. All rights reserved.

C0451098

6/16/2000 215 Topaz Street, Milpitas, California 95035

Tel: [phone]

Fax: [phone]

www.calmicro.com

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CALIFORNIA MICRO DEVICES

CM88L70/70C

Absolute Maximum Ratings: (Note 1)

ABSOLUTE MAXIMUM RATINGS

Parameter		Symbol	Value
Power Supply Voltage	(VDD-	VDD	6.0V Max
VSS)
Voltage on any Pin		Vt	VSS-0.3V to VDD+0.3V
Current on any Pin		It	10mA Max
Storage Temperature		TS	-65°C to +150°C

This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating.

Note:

1.Exceeding these ratings may cause permanent damage, functional operation under these conditions is not implied.

DC Characteristics: All voltages referenced to VSS, VDD = 3.0V + 20% / -10%, TA = -40°C to +85°C unless otherwise noted.

DC CHARACTERISTICS

Parameter			Symbol	Min	Typ	Max	Units	Test Conditions
Operating Supply Voltage			V DD	2.7	3.0	3.6	V	V
Operating Supply Current			IDD		3.0	5.0	mA
Standby Supply Current			IDDS		5.0	10	µA	PD=VDD
Low Level Input Voltage			V IL			1.0	V	VDD=3.0V
High Level Input Voltage			V IH	2.0			V	VDD=3.0V
Input Leakage Current			IIH/LIL		0.1		µA	VIN = VSS or VDD (Note 11)
Pull Up (Source) Current on TOE			Iso	-12	-2.0		µA	TOE = 0V
Pull down (sink) Current PD			IPD		1.0	45	µA	PD = 3.0V
Pull down (sink) Current INH			IINH		1.0	45	µA	IHN = 3.0V
Input Impedance, (IN+, IN-)			R IN		10		MΩ	@ 1KHz
Steering Threshold Voltage			V Tst		1.5		V
Low Level Output Voltage			V OL		0.1	0.4	V	IOL = 1.0mA
High Level Output Voltage			V OH	2.4	2.6		V	IOH = 400µA
Output High (Source) Current			IOH	1.0			mA	VOUT = 2.5V @ VDD = 2.7V
Output Voltage		VREF	V REF		1.5		V	No Load
Output Resistance			R OR		10		ΚΩ

Operating Characteristics: All voltages referenced to VSS, VDD = 3.0V + 20% / -10%, TA = -40°C to +85°C unless otherwise noted.

Gain Setting Amplifier

OPERATING CHARACTERISTICS

Parameter	Symbol	Min	Typ	Max	Units	Test Conditions
Input Leakage Current	IIN		100		nA	VSS < VIN < VDD
Input Resistance	R IN		10		MΩ
Input Offset Voltage	V OS		15	25	mV
Power Supply Rejection	PSR R	50	60		dB	1KHz (Note 12)
Common Mode Rejection	CMR R	40	60		dB	-3.0V < VIN < 3.0V
DC Open Loop Voltage Gain	AVOL	32	65		dB
Open Loop Unity Gain Bandwidth	fc	0.3	1.0		MH z
Output Voltage Swing	V O		2.2		V P-P	RL ≥ 100KΩ to VSS
Tolerable Capacitive Load (GS)	CL			100	pF
Tolerable Resistive Load (GS)	R L				KΩ
Common Mode Range (No Load)	V cm	5.0	1.5		V P-P	No Load

©2000 California Micro Devices Corp. All rights reserved.

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215 Topaz Street, Milpitas, California 95035

Tel: [phone]

Fax: [phone]

www.calmicro.com 8/16/2000

CALIFORNIA MICRO DEVICES

CM88L70/70C

AC Characteristics: All voltages referenced to VSS, VDD=3.0V + 20% / -10%, TA=-40°C to +85°C, fCLK=3.579545 MHz using test circuit (Fig. 1) unless otherwise noted.

AC CHARACTERISTICS

Parameter			Symbol	Min	Typ	Max	Units	Notes
Valid Input Signal Levels				-36		-6.4	dBm	1,2,3,4,5,8
(each tone of composite signal)				12.3		370	mVRMS
Positive Twist Accept						6	dB
Negative Twist Accept						6	dB
Freq. Deviation Accept Limit						1.5%±2Hz	Nom.	2,3,5,8,10
Freq. Deviation Reject Limit				±3.5%			Nom.	2,3,5
Third Tone Tolerance					-16		dB	2,3,4,5,8,9,13,14
Noise Tolerance					-12		dB	2,3,4,5,6,8,9
Dial Tone Tolerance					+22		dB	2,3,4,5,7,8,9
Tone Present Detection Time			tDP	5	8	14	mS	Refer to
Tone Absent Detection Time			tDA	0.5	3	8.5	mS	Timing Diagram
Min Tone Duration Accept			tREC			40	mS	(User Adjustable)
Max Tone Duration Reject			tREC	20			mS
								Times shown are
Min. Interdigit Pause Accept			tID			40	mS	obtained with
								circuit in Fig. 1)
Max. Interdigit Pause Reject			tDO	20			µS
Propagation Delay (St to Q)			tPQ		13		µS
Propagation Delay (St to	StD)		tPStD		8		µS	TOE = VDD
Output Data Set Up (Q to StD)			tQStD		3.4		µS
Propagation Delay (TOE to Q)		Enable	tPTE		200		nS	RL = 10KΩ
		Disable	tPTD		500		nS	CL = 50pF
Crystal/Clock Frequency			fCLK	3.5759	3.5795	3.5831	MHz
Clock Output (OSC 2)		Capacitive	CLO			30	pF
		Load

Notes:

1.dBm = decibels above or below a reference power of 1 mW into a 600 ohm load.

2.Digit sequence consists of all 16 DTMF tones.

3.Tone duration = 40mS. Tone pause = 40 mS.

4.Nominal DTMF frequencies are used.

5.Both tones in the composite signal have an equal amplitude.

6.Bandwidth limited (0 to 3 KHz) Gaussian Noise.

7.The precise dial tone frequencies are (350 Hz and 440 Hz) ±2%.

8.For an error rate of better than 1 in 10,000

9.Referenced to lowest level frequency component in DTMF signal.

10.Minimum signal acceptance level is measured with specified maximum frequency deviation.

11.Input pins defined as IN+, IN-, and TOE.

12.External voltage source used to bias VREF.

13.This parameter also applies to a third tone injected onto the power supply.

14.Referenced to Figure 1. Input DTMF tone level at -28 dBm.

© 2000 California Micro Devices Corp. All rights reserved.

6/16/2000 215 Topaz Street, Milpitas, California 95035

Tel: [phone]

Fax: [phone]

www.calmicro.com

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