Caen V2495, VX2495 User Manual

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CAEN

Tools for Discovery

Electronic Instrumentation

User Manual UM5175

V2495/VX2495

VME Programmable Logic Unit

Rev. 1 - October 11

, 2018

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Purpose of this Manual

This document contains the full hardware and software description of the V2495/VX2495 VME Programmable Logic Unit.

Change Document Record

Date

Revision

Changes

August 01st, 2016

Initial release

October 11th, 2018

Removed “Coming Soon” from the User Firmware FW2495SC in Tab.

1.2. Corrected caption in Fig. 10.1. Removed Subsect. “CAENComm

Demo” and added Subsect. PLULib Library in Sect. Software Tools. Updated Sect. Reference Documents, Sect. Flash Configuration

(0x8500-0x8AFF) , Sect. Introduction, Chap. 12.

Symbols, Abbreviated Terms and Notation

Address Modifier

FPGA

Field Programmable Gate Array

Geographical Address

GDG

Gate and Delay Generator

Local Bus

LBM

Local Bus Master

LBS

Local Bus Slave

LED

Light Emitting Diode

MFPGA

Main FPGA

SPI

Serial Peripheral Interface

Switch

UFPGA

User FPGA

USB

Universal Serial Bus

VBA

VME Base Address

VME

Versa Module Europa

Reference Documents

[RD1] GD2512 – CAENUpgrader QuickStart Guide [RD2] UM3181 – V1495 General Purpose VME Board [RD3] A967 Adapter for P50E – 068S 68 Pin Connectors [RD4] UM6510 – CAEN PLULib Library User Manual All documents can be downloaded at: http://www.caen.it/csite/LibrarySearch.jsp

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CAEN S.p.A. Via Vetraia, 11 55049 Viareggio (LU) - ITALY Tel. +39.0584.388.398 Fax +39.0584.388.959 [email protected] www.caen.it

Disclaimer

None of the parts of this manual may be reproduced in any form or by any means, electronic, mechanical, recording, or otherwise, without the prior written permission of CAEN SpA.

The information contained herein has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. CAEN SpA reserves the right to modify its products specifications without giving any notice; for up to date information please visit www.caen.it.

MADE IN ITALY: We stress the fact that all the boards are made in Italy because in this globalized world, where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who make them, at least you know that who made your board was reasonably paid and worked in a safe environment. (this obviously applies only to the boards marked "MADE IN ITALY", we cannot attest to the manufacturing process of "third party" boards).

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CAEN

Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

Index

Purpose of this Manual ......................................................................................................................................... 2

Change Document Record ................................................................................................................................... 2

Symbols, Abbreviated Terms and Notation ....................................................................................................... 2

Reference Documents ........................................................................................................................................... 2

Index ........................................................................................................................................ 4

List of Figures......................................................................................................................... 5

List of Tables .......................................................................................................................... 6

Safety Notices......................................................................................................................... 7

1 Introduction ..................................................................................................................... 8

2 Block Diagram .............................................................................................................. 10

3 Main Components and Interconnections .................................................................. 11

3.1 USB Interface............................................................................................................................................ 12

3.2 VME Interface ........................................................................................................................................... 12

3.3 Main FPGA ................................................................................................................................................ 12

3.4 User FPGA ................................................................................................................................................ 12

3.5 Gate and Delay Generator ...................................................................................................................... 12

3.6 Clock Distribution ..................................................................................................................................... 12

4 Front Panel Connectors, LEDs and Labels .............................................................. 13

5 Internal Connectors and LEDs ................................................................................... 16

6 Technical Specifications ............................................................................................. 19

7 Getting Started with V2495 ......................................................................................... 21

7.1 Shipping Content ...................................................................................................................................... 21

7.2 Mezzanine Boards Installation ............................................................................................................... 22

7.3 Front Panel Connector Cabling .............................................................................................................. 23

7.4 Setting the VME Base Address .............................................................................................................. 24

7.5 Selecting the User FPGA Firmware ...................................................................................................... 24

7.6 Power-on Configuration Sequence ........................................................................................................ 25

Boot Mode Selection ......................................................................................................................................................25

8 Driver and Software Installation ................................................................................. 26

8.1 Drivers ........................................................................................................................................................ 26

Direct USB Driver ............................................................................................................................................................26

VME Access ......................................................................................................................................................................29

8.2 Software Tools .......................................................................................................................................... 30

CAENUpgrader.................................................................................................................................................................30

PLULib Library .................................................................................................................................................................33

9 Communication Interfaces .......................................................................................... 34

9.1 VME Bus .................................................................................................................................................... 34

9.2 USB ............................................................................................................................................................ 34

9.3 Address Map ............................................................................................................................................. 35

User FPGA Data Access (0x0000-0x0FFF) ................................................................................................................35

User FPGA Register Access (0x1000-0x7FFF) .........................................................................................................35

VME Interface Registers (0x8000-0x80FF) ................................................................................................................36

VME Control Register .....................................................................................................................................................36

VME Interrupt Level Register .......................................................................................................................................36

VME Interrupt Status ID Register ................................................................................................................................36

Scratch Register ..............................................................................................................................................................36

VME Base Address Register ........................................................................................................................................36

Configuration ROM (0x8100-0x81FF) .........................................................................................................................37

Configuration and Status Registers (0x8200-0x83FF) ...........................................................................................38

MFPGA Firmware Revision Register ..........................................................................................................................38

Software Reset Register ................................................................................................................................................38

Scratch Register ..............................................................................................................................................................38

Flash Configuration (0x8500-0x8AFF)........................................................................................................................38

Internal Scratch SRAM(0x8C00-0x8FFF) ...................................................................................................................38

10 Firmware Development................................................................................................ 39

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CAEN

Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

10.1 Introduction................................................................................................................................................ 39

10.2 User FPGA I/O ports ................................................................................................................................ 40

10.3 Local Bus Interface .................................................................................................................................. 43

10.4 Gate and Delay Controller ...................................................................................................................... 45

General Description ........................................................................................................................................................45

Register Description .......................................................................................................................................................46

Example Procedures ......................................................................................................................................................47

10.5 Porting V1495 to V2495 .......................................................................................................................... 48

11 Demo Firmware ............................................................................................................ 49

11.1 Introduction................................................................................................................................................ 49

11.2 Demo Structure ........................................................................................................................................ 49

11.3 Demo Setup .............................................................................................................................................. 49

11.4 Gate Pattern Demo Description ............................................................................................................. 50

Introduction ......................................................................................................................................................................50

Register Map ....................................................................................................................................................................50

Register Description .......................................................................................................................................................50

11.5 Pattern Recorder Demo Description ..................................................................................................... 53

Introduction ......................................................................................................................................................................53

Register Map ....................................................................................................................................................................53

Register Description .......................................................................................................................................................53

11.6 DAC Demo Description ........................................................................................................................... 55

Introduction ......................................................................................................................................................................55

Register Map ....................................................................................................................................................................55

Register Description .......................................................................................................................................................55

11.7 Gate and Delay Demo Description ........................................................................................................ 57

Introduction ......................................................................................................................................................................57

Register Map ....................................................................................................................................................................57

Register Description .......................................................................................................................................................57

12 Software Development ................................................................................................ 60

13 CAEN Support ............................................................................................................... 61

13.1 Returns and Repairs ................................................................................................................................ 61

13.2 Technical Support Service ...................................................................................................................... 61

List of Figures

Fig. 2.1: Block diagram ......................................................................................................................................................................10

Fig. 3.1: Main components and interconnections ...........................................................................................................................11

Fig. 3.2: The UFPGA and GDG interface. .......................................................................................................................................12

Fig. 4.1: Front panels view ................................................................................................................................................................13

Fig. 5.1: On-board internal connectors and LEDs ..........................................................................................................................16

Fig. 7.1: V2495 motherboard with mezzanine boards ...................................................................................................................22

Fig. 7.2: Multi-pin connector pin assignment ..................................................................................................................................23

Fig. 7.3: CAEN A967 Cable Adapter ................................................................................................................................................23

Fig. 7.4: Base Address on-board rotary switches ..........................................................................................................................24

Fig. 7.5: User Firmware rotary switch ..............................................................................................................................................24

Fig. 7.6: Boot mode jumper for the Main FPGA .............................................................................................................................25

Fig. 8.1: V2495 hardware detection .................................................................................................................................................26

Fig. 8.2: USB driver manual installation: Step1 ..............................................................................................................................27

Fig. 8.3: USB driver manual installation: Step2 ..............................................................................................................................27

Fig. 8.4: USB driver manual installation: Step3 ..............................................................................................................................28

Fig. 8.5: USB driver manual installation: Step4 ..............................................................................................................................28

Fig. 8.6: USB driver manual installation: Step5 ..............................................................................................................................29

Fig. 8.7: CAENUpgrader Get Firmware Release menu ................................................................................................................30

Fig. 8.8: CAENUpgrader MFPGA Upgrade Firmware menu ........................................................................................................31

Fig. 8.9: CAENUpgrader UFPGA flash memory image menu ......................................................................................................32

Fig. 8.10: CAENUpgrader UFPGA Upgrade Firmware menu ......................................................................................................32

Fig. 8.11: CAEN PLULib Demo application prompt .......................................................................................................................33

Fig. 10.1: Simplified scheme related to Tab. 10.5. .........................................................................................................................41

Fig. 10.2: Local bus signals at a write access (x8BADF00D is written on register x1800) ......................................................43

Fig. 10.3: Local bus signal at a read access (x8BADF00D is read from register x1800) .........................................................43

Fig. 10.4: Prefetch mechanism .........................................................................................................................................................44

Fig. 10.5: Gate and Delay parameters representation ..................................................................................................................45

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Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

List of Tables

Tab. 1.1: Comparison table between V1495 and V2495 ................................................................................................................8

Tab. 1.2: Table of models and related items .....................................................................................................................................9

Tab. 6.1: V2495/VX2495 specifications table .................................................................................................................................19

Tab. 6.2: A395A Mezzanine specifications table............................................................................................................................19

Tab. 6.3: A395B Mezzanine specifications table............................................................................................................................20

Tab. 6.4: A395C Mezzanine specifications table ...........................................................................................................................20

Tab. 6.5: A395D Mezzanine specifications table ...........................................................................................................................20

Tab. 6.6: A395E Mezzanine specifications table............................................................................................................................20

Tab. 9.1: V2495 register address map ............................................................................................................................................35

Tab. 9.2: VME interface registers .....................................................................................................................................................36

Tab. 9.3: ROM Address Map of the V2495 .....................................................................................................................................37

Tab. 9.4: CSR registers .....................................................................................................................................................................38

Tab. 10.1: Clock ports description table ..........................................................................................................................................40

Tab. 10.2: Mainboard Robinson-Nugent connector description table .........................................................................................40

Tab. 10.3: LEMO G ports description table .....................................................................................................................................40

Tab. 10.4: Expansion I/O ports description table ...........................................................................................................................41

Tab. 10.5: A395D mapping................................................................................................................................................................41

Tab. 10.6: LED ports description table ............................................................................................................................................42

Tab. 10.7: Gate and Delay Generator ports description table ......................................................................................................42

Tab. 10.8: Local Bus ports description table ...................................................................................................................................42

Tab. 10.9: Main parameters of the Gate and Delay Generator ....................................................................................................45

Tab. 10.10: Local Bus registers description for the Gate and Delay Generator configuration ................................................46

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CAEN

Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

Safety Notices

CAUTION: this product may need proper cooling.

USING V2495 WITH MEZZANINE BOARDS MAY REQUIRE CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEATING MAY DAMAGE THE MODULE (refer to Chap. 6)

CAUTION: this product needs proper handling.

V2495 DOES NOT SUPPORT LIVE INSERTION (HOT SWAP)! TAKE CARE OF REMOVING OR INSERTING THE BOARD WHEN THE VME

CRATE IS POWERED OFF!

CAEN provides the specific document “Precautions for Handling, Storage and Installation”, available in the documentation tab of the product’s web page. The user is required to read this manual before using CAEN equipment.

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CAEN

Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

1 Introduction

The V2495 is a general-purpose programmable FPGA and I/O unit housed in a 1-unit wide VME 6U module. The board is a suitable solution for the implementation of digital functions such as Coincidence, Trigger Logic, Gate and Delay Generator, Input/Output Register and more.

The programmable architecture is based on the User FPGA (hereafter UFPGA). The UFPGA is directly interfaced to the front panel I/Os and to an onboard Gate and Delay Generator, that allows to delay and gate up to 32 signals. A second FPGA, the Main FPGA (hereafter MFPGA), is responsible for USB and VME interface management. The MFPGA communicates with the UFPGA through an internal local bus.

The presence of three expansion slots interfaced to the UFPGA allows to extend the channel interface of the V2495 by adding up to three independent mezzanine boards. Five mezzanine board types are available: A395A, A395B, A395C, A395D, A395E (see Tab. 1.2). The V2495 can reach a maximum of 194 I/O channels.

The board can be controlled and programmed through either the VME or the USB interface. The CAENUpgrader software tool is provided to upload the FPGA firmware. An onboard dedicated JTAG connector allows for in-system JTAG configuration and debugging (e.g. using Altera SignalTap).

The V2495 can be considered as an evolution of CAEN V1495 board with which it bears several analogies (e.g. the front panel connectors have the same function and nomenclature with respect to the V1495). In addition, it provides enhanced logic resources, features and interfaces.

The following Tab. 1.1 is a comparison table between the two modules.

V1495

V2495

User FPGA

Altera Cyclone EPI1C20, 20k LEs

Altera Cyclone V GX, 50k LEs

Front Panel I/O

Sections A and B (2 x 68-pin Robinson Nugent connector; 32 input channel each)

Section C (1 x 68-pin Robinson Nugent connector; 32 output channels)

Section G (2 X LEMO connector; input/output channels)

On-board Delay Generator

4 Delay lines

32 Gate and Delay lines

Local Bus

16-bit 50 MHz parallel interface

VME Bus

Addressing spaces: A24, A32

Data transfer modes: D16, D32, BLT32

Geographical addressing (VX2495)

USB Interface

Not Supported

USB2.0

Mezzanine

Boards

A395A, A395B, A395C, A395D, A395E

Tab. 1.1: Comparison table between V1495 and V2495

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UM5175 – V2495/VX2495 User Manual rev. 1

Tab. 1.2 lists the board models, the firmware and hardware related products as well as the ordering option

information.

Board Models

Description

Product Code

V2495

VME64 Programmable Logic Unit

WV2495XAAAAA

VX2495

VME64X Programmable Logic Unit

WVX2495XAAAA

User Firmware

Description

Product Code

FW2495SC

Channel Latching Scaler for V2495

WFW2495SCXAA

2 Block Diagram

B C

USER

PROGRAMMABLE

FPGA

(UFPGA)

MAIN FPGA

(MFPGA)

16 bit

VME BUS

LOCAL

BUS

Gate and Delay

Generator

E F

USB

Fig. 2.1: Block diagram

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Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

3 Main Components and Interconnections

User

FPGA

(Cyclone V GX)

Main FPGA

(Cyclone V E)

Gate and Delay

Generator

Local Bus

(16-bit@50MHz)

USB PHY

VME BUS (P1/P2)

FLASH

A PORT (IN) /

D PORT (IN/OUT)

B PORT (IN) /

E PORT (IN/OUT)

C PORT (OUT) /

F PORT (IN/OUT)

USB

G PORT (IN/OUT)

JTAG

USER FW

SELECTOR

50 MHz

AD9520

VME BASE ADDRESS

SELECTORS

Fig. 3.1: Main components and interconnections

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Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

3.1 USB Interface

The V2495 is equipped with a USB2.0 interface. The USB physical layer is managed by a high-speed (480 Mb/s) transceiver controlled by the Main FPGA.

3.2 VME Interface

The P1 and P2 are the standard VME connectors both interfaced with the Main FPGA.

3.3 Main FPGA

The MFPGA (Altera Cyclone V E) manages the VME and USB interfaces and the connection with the UFPGA through a proprietary 16-bit@50 MHz local bus. The MFPGA has a dedicated external flash memory for configuration purposes. It also pilots the flash memories dedicated to loading the firmware on the UFPGA and on the GDG.

3.4 User FPGA

The User FPGA (Altera Cyclone V GX) manages the I/O peripherals (A/D, B/E, G, C/F ports) and communicates with the GDG. A dedicated external flash memory can store a set of firmware images to be loaded on the User FPGA. A dedicated JTAG connector allows to program the UFPGA “on-the-fly” for fast firmware prototyping and debugging.

3.5 Gate and Delay Generator

The V2495 hosts a Gate and Delay Generator (see Fig. 3.2) able to provide up to 32 gated and delayed signals (“delayed signals”) triggered by 32 inputs (“start signals”). The gate width and delay value are user programmable. The GDG is an

external component implemented in a Xilinx Spartan-6 FPGA. It is connected through a serial bus (SPI) to the User FPGA for gate and delay register programming (refer to Sect. Gate and Delay Controller for detailed information). The GDG configuration is stored in a dedicated flash memory. The GDG firmware cannot be modified by the user.

User FPGA

Gate and Delay

Generator

Start signals

Delayed signals

Start[i]

Delayed[i]

Td Tg

Fig. 3.2: The UFPGA and GDG interface.

3.6 Clock Distribution

Each FPGA receives the same 50-MHz system clock generated by a common on-board oscillator.

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CAEN

Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

4 Front Panel Connectors, LEDs and Labels

USB PORT

VME DATA ACKNOWLEDGE LED

CONFIGURATION LED

‘A’ CONNECTOR (32-ch input only)

USB ACTIVITY LED

USER CONFIGURATION LEDs

‘B’ CONNECTOR (32-ch input only)

‘C’ CONNECTOR (32-ch output only)

G0, G1 CONNECTORS

(Input/Output selectable)

Fig. 4.1: Front panels view

V2495 and VX2495 have the same front panel and connectors.

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CAEN

Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

USB PORT

FUNCTION

MiniUSB connector to communicate with the V2495 by USB link for board configuration and firmware upgrade.

ELECTRICAL SPECS

N.A.

MECHANICAL SPECS

Series: miniUSB connectors. Type: SD-54819-026 (B-type). Manufacturer: Molex Inc.

CABLES

A 1-m USB standard cable is included with the V2495 (USB A-type to miniUSB B-type).

USB LED (GREEN): driven by the Main PFGA, this LED lights up if a USB read/write access to the board is performed.

DTACK LED

FUNCTION

This LED lights up whenever a VME read/write access to the board is performed.

COLOR

Green.

A, B, C CONNECTORS

FUNCTION

Motherboard I/O 34+34 pin connectors:

- A/B are inputs

- C is an output

ELECTRICAL SPECS See Tab. 6.1.

MECHANICAL SPECS

Series: 80-0009-0666-1. Type: P50E-068-P1-SR1-TG. Manufacturer: 3M.

CFG LED

FUNCTION

This LED is constantly on when all the onboard FPGAs are configured by the application firmware on their relevant flash memory (it is the OR of the internal configuration LEDs described in Chap. 5). The LED blinks if the MFPGA is in Factory mode.

COLOR

Green.

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Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

G0, G1 CONNECTORS

FUNCTION

Bidirectional single-ended connectors. Terminations can be activated/deactivated by dedicated on-board switches (see Chap. 5).

ELECTRICAL SPECS See Tab. 6.1.

MECHANICAL SPECS

Series: 00 LEMO Connectors. Type: EPY.00.250.NTN. Manufacturer: LEMO

0, 1, 2, …, 7 LEDs

FUNCTION

The status of these LEDs is user-programmable NOTE: when the UFPGA is in Factory mode,

odd and even LEDs alternatively blink.

COLOR

Green.

LABELS

Two blue labels on each insertion/extraction handle of the VME front panel report:

− Manufacturer name and board’s model

− Brief functional description

The label at the bottom of the front panel reports the 4-digit Serial Number (S/N) information.

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CAEN

Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

5 Internal Connectors and LEDs

UFPGA JTAG

MFPGA JTAG

MEZZANINE SOCKETS

UFPGA CONF_DONE LED

MFPGA CONF_DONE LED

GDG CONF_DONE LEDs

POWER SUPPLY LEDS

G-PORT

TERMINATION

SWITCHES

Fig. 5.1: On-board internal connectors and LEDs

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CAEN

Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

MAIN FPGA JTAG

FUNCTION

MFPGA-dedicated JTAG connector.

ELECTRICAL SPECS

N. A.

MECHANICAL SPECS

Series: 7610-6002 Board Connector. Type: 7610-6002-5+5-DR. Manufacturer: 3M.

USER FPGA JTAG

FUNCTION

UFPGA-dedicated JTAG connector.

ELECTRICAL SPECS

N. A.

MECHANICAL SPECS

Series: 7610-6002 Board Connector. Type: 7610-6002-5+5-DR. Manufacturer: 3M.

MEZZANINE SOCKET

FUNCTION

Mezzanine board expansion connector (x3)

ELECTRICAL SPECS

N. A.

MECHANICAL SPECS

Series: Stacking Board Connectors. Type: 61083-104400LF Manufacturer: AMPHENOL FCI.

G-PORTS TERMITNATION SWITCHES

FUNCTION

Two switches, one for each G connector, enable or disable the 50-Ω termination according to the input or output direction and the NIM or TTL configuration of the relevant connector.

• Position “ON” = 50 Ω termination

enabled

• Position “OFF” = termination disabled

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Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

MFPGA CONF_DONE LED

FUNCTION

This led lights up when the Main FPGA is properly programmed.

COLOR Green.

UFPGA CONF_DONE LED

FUNCTION

This LED lights up when the User FPGA is properly programmed.

COLOR

Green.

GDG CONF_DONE LEDs

FUNCTION

Two LEDs indicate the status of the Gate and Delay Generator:

• DX LED on (green): FPGA

programmed.

• SX LED on (orange): FPGA not

programmed.

COLOR

SX LED: Orange. DX LED: Green.

POWER SUPPLY LEDs

FUNCTION

Two LEDs, placed under the Gate and Delay Generator, light up if the 3.3V power supply for the digital circuitry is provided.

COLOR

Green.

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CAEN

Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

6 Technical Specifications

V2495/VX2495 Motherboard

FORM FACTOR

1-unit wide, 6U high VME64 (V2495) and VME64X (VX2495)

I/O SECTIONS A and B

Nr. of Channels

Direction

Input

Logic

Direct

Signal

Differential LVDS/ECL/PECL (single ended TTL optional) Z

diff

: 100 Ω Extended Common Mode Input range: -4V to +5V Fail Safe input feature

Bandwidth

200 MHz

Front Panel Connector

Robinson Nugent P50E-068-P1-SR1-TG type, (34+34) pins

I/O SECTION C

Nr. of Channels

32 channels

Direction

Output

Logic

Direct

Signal

Differential LVDS Require 100 Ω termination

Bandwidth

250 MHz

Front Panel Connector

Robinson Nugent P50E-068-P1-SR1-TG type, (34+34) pins

I/O SECTION G

Nr. of Channels

Direction

I/O selectable

Logic

TTL IN = Direct TTL OUT = Direct NIM IN = Invert NIM OUT = Direct

Signal

Single ended NIM/TTL selectable Open/50 Ω termination selectable

Bandwidth

250 MHz

Front Panel Connector

LEMO 00

GATE and DELAY GENERATOR

Minimum Delay/Gate Min.

Typ.

Max.

9.6 ns

10.7 ns

11.8 ns

Maximum Delay/Gate

631 µs

701.2 µs

771.5 µs

Maximum channel-to-channel spread: 20%

COMMUNICATION INTERFACE

VME

VME64X compliant Addressing space: A24, A32 Data Transfer mode: D16, D32, BLT32

USB

USB 2.0 compliant Geographical addressing (VX2495) Multicast commands

POWER REQUIREMENTS

1.0A (max.) @ +5V +12V and -12V rails are not used

Tab. 6.1: V2495/VX2495 specifications table

A395A Mezzanine Board

I/O SECTION

Nr. Of Channels

Direction Input

Logic

Direct

Signal

Differential LVDS/ECL/PECL (single ended TTL optional) Z

diff

: 100 Ω Extended Common Mode input range: -4V to +5V Fail Safe input feature

Bandwidth

200 MHz

Front Panel Connector

Robinson Nugent P50E-068-P1-SR1-TG type, (34+34) pins

POWER CONSUMPTIONS

0.1 A (max) @ +5V +12V and -12V rails are not used

Tab. 6.2: A395A Mezzanine specifications table

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Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

A395B Mezzanine Board

I/O SECTION

Nr. of Channels

Direction Output

Logic

Direct

Signal

Differential LVDS Requires 100 Ω termination

Bandwidth

250 MHz

Front Panel Connector

Robinson Nugent P50E-068-P1-SR1-TG type, (34+34) pins

POWER CONSUMPTIONS

0.1 A (max) @ +5V +12V and -12V rails are not used

Tab. 6.3: A395B Mezzanine specifications table

A395C Mezzanine Board

I/O SECTION

Nr. of Channels

Direction Output

Logic

Direct

Signal

Differential ECL

Bandwidth

300 MHz

Front Panel Connector

Robinson Nugent P50E-068-P1-SR1-TG type, (34+34) pins

POWER CONSUMPTIONS

1.4 A (max) @ +5V +12V and -12V rails are not used

Tab. 6.4: A395C Mezzanine specifications table

A395D Mezzanine Board

I/O SECTION

Nr. of Channels

Direction I/O selectable

Logic

Direct

Signal

TTL IN = Direct TTL OUT = Direct NIM IN = Invert NIM OUT = Direct

Bandwidth

250 MHz

Front Panel Connector LEMO 00

POWER CONSUMPTIONS

1.1 A (max) @ +5V +12V and -12V rails are not used

Tab. 6.5: A395D Mezzanine specifications table

A395E Mezzanine Board

I/O SECTION

Nr. of Channels

Direction Output

Logic

Analog

Signal

16-bit resolution

±5V @10kΩ RL ±4V @200Ω RL

Bandwidth

n.a.

Front Panel Connector LEMO 00

POWER CONSUMPTIONS

0.3 A (max) @ +5V +12V and -12V rails are not used

Tab. 6.6: A395E Mezzanine specifications table

OPERATING THE V2495 WITH MORE THAN ONE A395C OR A395D MEZZANINE BOARDS REQUIRES USING VME CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEATING DUE TO INSUFFICIENT VENTILATION MAY DAMAGE THE MODULE.

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Electronic Instrumentation

UM5175 – V2495/VX2495 User Manual rev. 1

7 Getting Started with V2495

7.1 Shipping Content

DESCRIPTION

ITEM

V2495 Programmable VME

Logic Unit

Without mezzanine board extension(s)

With mezzanine board extension(s), according to the order⁽¹⁾

USB cable

V2495 User Manual

⁽¹⁾ Mezzanine boards are available by ordering option (refer to Tab. 1.2).

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7.2 Mezzanine Boards Installation

In order to install an A395x-series mezzanine board on the V2495 motherboard, please use a Phillips screwdriver.

• Remove (unscrew) the metal cover of one of the available mezzanine slots.

• Plug the mezzanine board into the 100-pin expansion connector on the motherboard (see Chap. 5)

• Fix the mezzanine board with the screws

Fig. 7.1: V2495 motherboard with mezzanine boards

OPERATING THE V2495 WITH MORE THAN ONE A395C OR A395D MEZZANINE BOARDS REQUIRES USING VME CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEATING DUE TO INSUFFICIENT VENTILATION MAY DAMAGE THE MODULE.

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7.3 Front Panel Connector Cabling

Motherboard I/O sections A, B, C and A395A, A395B and A395C mezzanine boards feature the Robinson Nugent P50E068-P1-SR1-TG multi-pin connector (see Chap. 4), whose pin layout is shown in Fig. 7.2.

CH0+

CH0-

CH1+

CH1-

CH16+

CH16-

CH17+

CH17-

CH14+

CH14-

CH15+

CH15-

CH30+

CH30-

CH31+

CH31-

N.C.

Fig. 7.2: Multi-pin connector pin assignment

The CAEN A967 Cable Adapter (Fig. 7.3) allows to adapt each Robinson Nugent multi-pin connector into two 1” 17+17pin Header-type male connectors (3M, 4634-7301) with locks through two 25 cm long flat cables. Refer to the cable datasheet [RD3] for specifications and to Tab. 1.2 for the ordering option.

Fig. 7.3: CAEN A967 Cable Adapter

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7.4 Setting the VME Base Address

Fig. 7.4: Base Address on-board rotary switches

Four on-board rotary switches (SW1, SW2, SW3 and SW4 in Fig. 7.4), with 16 positions each, set the hexadecimal value of the VME Base Address (VBA) which univocally identifies the board over the VME bus. Such switches are placed on the component side of the motherboard (see Fig. 3.1).

• SW1 sets bits [31:28] of VBA;

• SW2 sets bits [27:24] of VBA;

• SW3 sets bits [23:20] of VBA;

• SW4 sets bits [19:16] of VBA.

VX2495 also supports the geographical addressing.

7.5 Selecting the User FPGA Firmware

Fig. 7.5: User Firmware rotary switch

The on-board SW5 rotary switch selects which of the six firmware images will be loaded on the UFPGA at power-on. Five demos and one boot and recovery (factory) firmware are preloaded in the flash memory (see Chap. 11 for details).

Default SW5 position map: Position 0 = Factory User Firmware; this copy is used as recovery boot and is not writable by the user. Position 1 = Gate Pattern Demo (see Sect. Gate Pattern Demo Description) Position 2 = Pattern Recorder Demo (see Sect. Pattern Recorder Demo Description) Position 3 = DAC (A395E) Demo (see Sect. DAC Demo Description) Position 4 = Gate and Delay Demo (see Sect. Gate and Delay Demo Description) Position 5 = available (empty)



Note: All the positions from 6 up to 15 are equivalent to position 0: factory firmware is loaded.

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7.6 Power-on Configuration Sequence

When the board is powered on, the on-board programmable devices are configured with the firmware images stored in their dedicated flash memories. If all programmable devices (MFPGA, UFPGA and GDG) are correctly configured, the CFG LED is lit on. In case an anomaly occurs, the CFG LED status can be:

1) BLINKING: the FPGAs are configured, but the Main FPGA remained in Factory mode. The MFPGA can be configured by two kind of firmware images which are stored on the dedicated flash memory: the

Factory firmware and the Application firmware. The Factory firmware is a basic firmware specifically intended for boot and recovery functions. The Application firmware is the standard operating firmware and can be upgraded by the user through the VME or the USB interface.

At power-on, the MFPGA configures itself with the Factory firmware image and subsequently attempts to load the Application firmware. If the application firmware is missing or corrupted, the MFPGA will remain in the factory mode. The Factory firmware guarantees the communication with the board and allows the MFPGA Application firmware upgrade.

2) OFF: one or more FPGAs may not have been configured. In this case, the user can take different actions according to the status of the internal configuration LEDs:

• If the MFPGA Configuration LED is off, an attempt to force the MFPGA in Factory mode can be performed (see

next paragraph). If the CFG LED starts blinking, an application firmware upgrade can be attempted.

• If the UFPGA Configuration LED is off when the SW5 selector is set on one of the positions between 1 and 5, the

switch should be set to position 0 and the board should be power-cycled. As a consequence, the UFPGA is configured in Factory mode and the CFG LED will start blinking. It is then possible to attempt a User Application firmware upgrade on the flash memory page which caused the issue.

• If the UFPGA Configuration LED is off and the SW5 selector is set to position 0 or the GDG Configuration LED

lights up orange, please contact CAEN for further instructions.

Refer to Chap. 12 for CAEN Support contacts.

Boot Mode Selection

The on-board J9 jumper (see Fig. 7.6), when short-circuited, forces the Main FPGA to be reconfigured in Factory mode. This procedure allows to restore the board from anomalous conditions.

Fig. 7.6: Boot mode jumper for the Main FPGA

J9 -> Open (default): configures the Main FPGA by the Application firmware (if present or valid) J9 -> Closed: forces the Main FPGA to configure itself with the Factory firmware (Factory mode).



Note: The jumper status is checked only at the board power-up.

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8 Driver and Software Installation

8.1 Drivers

To communicate with the board using one of the available communication buses, specific drivers should be installed on your host device.



Note: to ensure the best system performance, it is recommended to have always the latest drivers release installed.

Direct USB Driver

In order to communicate with the V2495 through the front panel USB interface (see Chap. 4), the related driver can be downloaded from the V2495 webpage in the Software/Firmware tab (login required).

The USB driver is provided for Windows and Linux OS.

➢ WINDOWS OS

A step-by-step driver installation procedure is given next.



Note: The procedure is based on a Windows 10 system. It may be slightly different for another Windows OS.

1. Download and unpack the driver installation package on the host PC.

2. Plug the USB cable on the V2495 and on the PC. Windows should detect the new hardware.

3. Go to the Device Manager area. The new hardware is listed in Other devices as “V2495” (see Fig. 2.1).

Fig. 8.1: V2495 hardware detection

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4. Right click on “V2495” item and select Update Driver Software option in the slide menu.

Fig. 8.2: USB driver manual installation: Step1

5. Select Browse my computer for driver software as in Fig. 8.3.

Fig. 8.3: USB driver manual installation: Step2

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6. Use the [Browse] button to point to the driver folder in the destination path on the host PC.

Fig. 8.4: USB driver manual installation: Step3

7. Click the [Close] button at the end of the installation process.

Fig. 8.5: USB driver manual installation: Step4

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8. Check that the “CAEN V2495“ item appears in the Universal Serial Bus controllers list.

Fig. 8.6: USB driver manual installation: Step5

➢ Linux OS

V2495 is fully supported by Linux kernels from kernel version 3.13 on.

VME Access

The V2495 can be accessed through the VME bus. CAEN provides a USB-to-VME bridge (mod. V1718) and a CONET-toVME CAEN Bridge (mod. V2718).

➢ V1718 USB Driver

The required driver can be downloaded from the V1718 web page in the Software/Firmware tab (login required) and manually installed. The installation procedure described for the direct USB driver can be taken as reference.

➢ CONET Driver

The V2718 requires the installation of either a PCI (mod. A2818) or a PCIe card (mod. A3818) on your PC. The related drivers should be installed: they can be downloaded from the A2818 and A3818 web pages in the Software/Firmware tab (login required) and manually installed. Please refer to the controller User Manual for the driver installation instructions.

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8.2 Software Tools

CAENUpgrader

CAENUpgrader allows to perform the following operations on the V2495 board:

• Upgrade the MFPGA firmware

• Load the User firmware on the UFPGA

• Verify the Main and User FPGA firmwares

• Read the release number of the MFPGA firmware

• Store and get the Product Unlock Code in case of paid firmware

• Get the Board Info file (useful in case of support requests)

CAENUpgrader can operate with Windows and Linux, 32 and 64-bit OSs The software installation package can be downloaded from the CAEN web site (login required) at:

Home / Products / Firmware/Software / Digitizer Software / Configuration Tools / CAENUpgrader

For any installation and functions which are not described in this manual, please refer to the software Quick Start Guide, [RD1].

➢ Get the V2495 Main FPGA Firmware Release

The following instructions allow to read the release number of the MFPGA firmware:

1. Select the “Get Firmware Release” option in the Board tab.

2. Select the “V2495” item in the Board Model combo box.

3. Set the connection parameters according to your communication link and hardware setup (all the parameters

are detailed in [RD1]).

4. Press the Get FW Rel button. The software displays the release number in a message window (see Fig. 8.7).

Fig. 8.7: CAENUpgrader Get Firmware Release menu

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➢ Upgrade the V2495 Main FPGA Firmware The MFPGA firmware is available on CAEN website at the V2495 web page (login required):

Home / Products / Modular Pulse Processing Electronics / VME / I/O Registers / V2495

The firmware file is available in Altera RPD format. The following instructions allow to upgrade the MFPGA firmware:

1. Select the “Upgrade Firmware” option in the Board tab.

2. Select the “V2495” item in the Board Model combo box.

3. Set the connection parameters according to your communication link and hardware setup (all the parameters

are detailed in [RD1]).

4. Select the MFPGA by checking the relevant checkbox.

5. Select the Main application firmware RPD file.

6. Press the Upgrade button. The outcome of the upgrade process is shown in a message window (see Fig. 8.8).

7. Power cycle the board to reconfigure the MFPGA with the firmware just updated on the flash. Please refer to

Sect. Power-on Configuration Sequence to check the outcome of the process.

Fig. 8.8: CAENUpgrader MFPGA Upgrade Firmware menu

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➢ Upgrade the V2495 User FPGA Firmware

The UFPGA demo firmware projects are available on CAEN website at the V2495 web page (login required):

Home / Products / Modular Pulse Processing Electronics / VME / I/O Registers / V2495

User demo firmware or custom user firmware can be recompiled and the generated RPD file can be uploaded into any of the available flash firmware images.

The following instructions allow to upgrade the UFPGA firmware:

1. Select the “Upgrade Firmware” option in the Board tab.

2. Select the “V2495” item in the Board Model combo box.

3. Set the connection parameters according to your communication link and hardware setup (all the parameters

are detailed in [RD1]).

4. Select the UFPGA by checking the relevant checkbox.

5. Select the target application image on which you want to upload your firmware (see Fig. 8.9).

Fig. 8.9: CAENUpgrader UFPGA flash memory image menu

6. Select your User firmware or a CAEN Demo firmware RPD file.

7. Press the Upgrade button. The outcome of the upgrade process is shown in a message window (see Fig. 8.10).

At the end of the upgrade process, the CAEN Upgrader will force a reconfiguration of the UFPGA from the application image selected by the rotary switch (see Fig. 7.5).

Fig. 8.10: CAENUpgrader UFPGA Upgrade Firmware menu



Note: The user can upgrade any flash memory application image independently on the SW5 rotary switch position.



Note: In order the UFPGA to be configured with latest updated firmware image, please check that the board has been powered up with the SW5 rotary switch position matching the application image selected in the software. Otherwise, it will be required to move the switch to that position and power cycle the board.

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PLULib Library

CAEN PLULib library is a library of C functions developed to control V2495/VX2495 and DT5495 programmable logic units through direct USB and Ethernet communication interfaces, but also through the VMEbus connection by using CAEN Bridges (V2718 and V1718), if supported.

The library includes a simple demo application, which is not intended for the board readout, but rather to automatically test the library functions. The user can then inspect the code as reference for his customized software development based on the PLU library.

Fig. 8.11: CAEN PLULib Demo application prompt

CAEN PLULib library can operate on Windows® and Linux®, 32 and 64-bit. The documentation [RD4] and installation packages can be downloaded on CAEN web site at the CAEN PLULib web page (login required).

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9 Communication Interfaces

The V2495 board can be accessed via both VME bus or USB interface. All registers are accessible from both communication interfaces (VME/USB).

9.1 VME Bus

The V2495/VX2495 boards can be individually addressed on the bus by means of their assigned base address. The base address is set by means of on-board rotary switches (see Sect. Setting the VME Base Address) for all VME

accesses except for geographical addressing. Geographical addressing is only supported on VX2495 modules inserted in VME64X crates: the module Base

Address(BA) is automatically set by the position of the module in the crate. Geographical Address (GA) will set BA[23:19].

Geographical addressing is only supported with address modifier (AM) for CR/CSR space (0x2F). The geographical address corresponds to the slot identification number of the standard VME crate (1 is the leftmost

slot; 21 is the rightmost slot). VX2495 module inserted in slot 3, for instance, could be accessed with 0x2F address modifier at base address equal to 0x180000.

Registers can all be accessed via VME bus in A24/A32 addressing mode and D32 mode. VME interface supports interrupt generation requested by the User PFGA: User FPGA can generate an interrupt

request by asserting its nINT signal (active low). The interrupt will be generated only if the appropriate registers have been configured (see Tab. 9.2).

USB and VME cycles cannot be performed at the same time. It is up to the user to guarantee that each bus cycle is mutually exclusive.

9.2 USB

USB interface grants access to the same address space and corresponding registers of the VME interface. Register access over USB must be performed with Base Address equal to 0. The BA parameter in any of the following

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9.3 Address Map

The following table illustrates the V2495 address map:

Address

Description

BA + 0x0000-0x0FFF

UFPGA data access

BA + 0x1000-0x7FFF

UFPGA register access

BA + 0x8000-0x80FF

VME Interface Registers

BA + 0x8100-0x81FF

Configuration ROM

BA + 0x8200-0x83FF

Configuration and Status Registers

BA + 0x8400-0x84FF

Reserved

BA + 0x8500-0x86FF

MFPGA flash configuration

BA + 0x8700-0x88FF

UFPGA flash configuration

BA + 0x8900-0x8AFF

GDG flash configuration

BA + 0x8B00-x8BFF

Reserved

BA + 0x8C00-0x8FFF

Internal scratch RAM

BA + 0x9000-0xFFFF

reserved

Tab. 9.1: V2495 register address map

User FPGA Data Access (0x0000-0x0FFF)

The UFPGA data access space is allocated specifically for the readout of data produced in the UFPGA logic which need to exploit the maximum readout throughput available. This space can be accessed by using the available block transfer mechanism over the VME or USB communication interfaces.

Block data transfer allows to implement a faster readout. Block transfers requests over VME or USB do not trigger any transfer over the internal local bus between the MFPGA and UFPGA: a data prefetch mechanism, implemented in the MFPGA, stores User data into a local data queue (prefetch data queue). Please, refer to the prefetch mechanism description in Sect. Local Bus Interface. In consequence, data from the UFPGA data access space are read from the prefetch data queue in the MFPGA.

User FPGA Register Access (0x1000-0x7FFF)

UFPGA register address range is allocated for User register read/write. A read or write transfer (single cycle) can be triggered on the local bus by performing a corresponding read transfer in

the 0x1000-0x7FFF address interval. The local bus master in the MFPGA acts as a transparent bridge between the communication interface (VME/USB) and

the local bus in this interval. A couple of examples are given to illustrate the transparent bridge behaviour.

• VME register access Assume the board has a base address set to 0x32100000. An access to a user register mapped at offset 0x1000 on

the local bus can be triggered by a VME corresponding read or write cycle at address 0x32101000.

• USB register access Each module can be individually identified over the USB bus by its serial number. An access to a user register

mapped at offset 0x1000 on the local bus can be triggered by a USB access cycle at address 0x1000.

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VME Interface Registers (0x8000-0x80FF)

Address

Read/Write

BA + 0x8000

VME Control Register

R/W

BA + 0x8004

reserved

BA + 0x8008

VME Interrupt Level

R/W

BA + 0x800C

VME Interrupt Status ID

R/W

BA + 0x8010

reserved

BA + 0x8014

reserved

BA + 0x8018

reserved

BA + 0x8020

Scratch Register

R/W

BA + 0x8024-0x80F8

reserved

BA + 0x80FC

VME Base Address

Tab. 9.2: VME interface registers

VME interface registers implement VME-related control and status information. They can also be accessed from USB for monitoring or configuration.

VME Control Register

Bit

Description

[31:1]

reserved

[0]

VME Interrupt Mode 0 = Release On Register Access (RORA) Interrupt mode (default) 1 = Release On AcKnowledge (ROAK) Interrupt mode

VME Interrupt Level Register

Bit

Description

[31:3]

reserved

[2:0]

VME Interrupt Level: 0 = interrupts are disabled (default) n = interrupts on IRQn line are enabled (n = 1, 2, ..., 7)

VME Interrupt Status ID Register

Bit

Description

[31:0]

This register contains the 32-bit STATUS/ID set by the module on the VME data bus during the Interrupt Acknowledge cycle

Scratch Register

Bit

Description

[31:0]

This register allows to perform 32-bit accesses for test purposes. Default value is 0xAAAAAAAA

VME Base Address Register

Bit

Description

[31:0]

This register allows to read the value of on-board rotary switches (see Fig.

7.4). It is meant to be used from the USB interface for testing purposes

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Configuration ROM (0x8100-0x81FF)

The following registers contain module configuration information according to Tab. 9.3. Only the 8 LSBs of each location of the Configuration ROM are significant.

Description

Address

Content

checksum

0x8100

An eight bit 2’s complement binary checksum The sum of the bytes starts from offset 0x8104 for the number of bytes specified in the length field (inclusive)

checksum_length2

0x8104

0x00

checksum_length1

0x8108

0x00

checksum_length0

0x810C

0x20

constant2

0x8110

0x84

constant1

0x8114

0x84

constant0

0x8118

0x01

c_code

0x811C

0x43

r_code

0x8120

0x52

oui2

0x8124

0x00

oui1

0x8128

0x40

oui0

0x812C

0xE6

version

0x8130

0x00 (V2495) / 0x01 (VX2495)

board2

0x8134

0x00

board1

0x8138

0x09

board0

0x813C

0xBF

revis3

0x8140

0x00

revis2

0x8144

0x00

revis1

0x8148

0x00

revis0

0x814C

PCB revision

sernum1

0x8180

Serial Number (MSB)

sernum0

0x8184

Serial Number (LSB)

Tab. 9.3: ROM Address Map of the V2495



Note: The oui0/1 fields represent CAEN Manufacturer identifier (IEEE OUI), which is equal to 0x40E6.



Note: The version field identifies the module version (V2495/VX2495).



Note: The board serial number can be read with two accesses: if the serial number on the module front panel is 1245 (hex 0x4DD), for instance, the Serial Number’s MSB (0x8180) will be 0x04, while the Serial Number’s LSB (0x8184) will be 0xDD.

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Configuration and Status Registers (0x8200-0x83FF)

Address

Read/Write

Base + 0x8200

MFPGA firmware revision

Base + 0x8204 ÷ 0x8214

reserved

Base + 0x8218

Software reset

Base + 0x8220

Scratch register

R/W

Base + 0x8224 ÷ 0x83FC

reserved

Tab. 9.4: CSR registers

MFPGA Firmware Revision Register

Bit

Description

[31:16]

reserved

[15:8]

Major revision number

[7:0]

Minor revision number

Software Reset Register

Bit

Description

[31:0]

The value written into this register will determine the kind of software reset: 1 = generate a local bus reset only (nLBRES local bus signal) Others = reserved for future options

Scratch Register

Bit

Description

[31:0]

This register allows to perform 32-bit accesses for test purposes. Default value is 0xAAAAAAAA

Flash Configuration (0x8500-0x8AFF)

This address range is reserved to flash remote programming.



Note: access to the FLASH is through the provided functions of the PLULib library (see Sect. Software Tools).

Internal Scratch SRAM(0x8C00-0x8FFF)

This area is available either for test access or for volatile data storage. Any address in this interval is implemented by an internal RAM location.

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10 Firmware Development

10.1 Introduction

The goal of this chapter is to let the user familiarize with the information and the tools needed to develop proprietary firmware for the V2495 board. A thorough description of the main firmware functionalities will be provided; the features of essential components like the local bus interface and the gate and delay generator will also be discussed.

The four demos provided in the UFPGA flash memory will also be discussed: a step-by-step guide will be given to run the examples. Their goal is to provide an extensive overview of the main functionalities of the V2495 board and of its mezzanine cards. The code of these demos, together with a template firmware, can be downloaded from the CAEN website. When developing custom projects, it is recommended to start with the included template firmware, as it includes the correct FPGA pinning and constraints. A short description of the user top-level I/O signals will also be given.

The V2495 board is an upgraded version of the V1495 board. The two boards have the same I/O connectors and mezzanine card support. On the firmware development side, there are differences, mainly due to the new Gate and Delay Generator and to the newly-introduced USB connection. Please refer to Sect. Porting V1495 to V2495 for the details to port the V1495 projects on the V2495 board.



Note: Due to the different I/O pin mapping and FPGA devices, the FPGA bit-streams and the projects previously developed for the V1495 board are not compatible with the V2495 board.

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10.2 User FPGA I/O ports

This section illustrates the I/O ports of the UFPGA. Port names are the same of the VHDL entity top-level ports used in the template and demo firmware.

➢ Clock: The user FPGA receives the board system clock

SIGNAL NAME

WIDTH

TYPE

DESCRIPTION

CLK

Input

50 MHz system clock

Tab. 10.1: Clock ports description table

➢ Mainboard Robinson Nugent connector ports: the ports A and B are input only. They feature 32 input channels that

reach the UFPGA as 32 single-ended LVTTL lines (3.3 V).

SIGNAL NAME

WIDTH

TYPE

DESCRIPTION

Input

A port values

Input

B port values

Output

C port value

Tab. 10.2: Mainboard Robinson-Nugent connector description table

➢ LEMO ports: each of the LEMOs on the front panel can be used as input or output. The signals used are the

following:

SIGNAL NAME

WIDTH

TYPE

DESCRIPTION

GIN

Input

Input values for G0, G1

GOUT

Output

Output values for G0, G1

SELG

Output

NIM/TTL selector 0 = NIM 1 = TTL

nOEG

Output

Output enable (active low) (0=output, 1=input)

Tab. 10.3: LEMO G ports description table

It should be noted that the ports G0, G1 can be set as inputs in two different ways:

• By setting nOEG=1 and driving the LEMO inputs. In this way both ports will be used as inputs; their status can be

read from GIN[0] and GIN[1].

• By setting to 0 both nOEG and the output signal of the input port and enabling the related 50 Ohm termination

(see Chap. 5). In this way it is possible to force a logic level without damaging the output and to use one port as an input and the other as an output.

Example: G0 input, G1 output nOEG=0 GOUT[0]=0 Enable the 50 Ohm G0 termination In this way, it is possible to provide an input on the G0 channel, while having an output on the G1 port (through the

GOUT[1] signal). Note that in this configuration G1 should not be externally forced, as this might damage the input circuit.

The 50 Ohm termination should also be enabled when a NIM input is provided (instead of a TTL). When the NIM logic level is chosen the logic levels are inverted with respect to the TTL case: It is up to the firmware to handle this inversion, for example using the SELG signal to invert the logic level as shown in the following VHDL assignment:

GIN_MOD <= GIN[0] when SELG=’1’ else not GIN[0];

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➢ Expansion I/O ports: for each mezzanine, Tab. 10.4 shows the supported signals (X = D, E, F).

SIGNAL NAME

WIDTH

TYPE

DESCRIPTION

IDx 3 Input

Card ID

“000” = A395A “001” = A395B “010” = A395C “011” = A395D “100” = A395E “111” = No mezzanine present

SELx

Output

NIM/TTL selector 0 = NIM 1 = TTL

nOEx

Output

Output enable (active low) 0 = output 1 = input

Input/Output

Data bus to/from the mezzanines

Tab. 10.4: Expansion I/O ports description table

Please note that:

• The SELx and nOEx signals are meaningful only for the A395D mezzanine card. When this mezzanine is not used,

these signals can be left undriven.

• Mezzanines with 32 I/O signals have a one-to-one correspondence between physical signals and I/O pins (i.e.

X[i] corresponds to the i-th channel of the mezzanine). In case the A395D mezzanine is used, the mapping between the external channels and the X bus is shown in

Tab. 10.5. A schematic view of the A395D board is shown in Fig. 10.1.

CHANNEL

INPUT SIGNALS

OUTPUT SIGNALS

X[2]

X[0] 1 X[18]

X[16] 2 X[3]

X[1] 3 X[19]

X[17]

X[14]

X[12]

X[30]

X[28]

X[15]

X[13]

X[31]

X[29]

Tab. 10.5: A395D mapping

Fig. 10.1: Simplified scheme related to Tab. 10.5.

For example:

• A395D channel 0 can be driven with signal X[0] and its status can be read from X[2].

• A395D channel 1 can be driven with signal X[16] and its status can be read from X[18].

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➢ User LEDs: Refer to the eight User LEDs on the front panel (see Chap. 4).

SIGNAL NAME

WIDTH

TYPE

DESCRIPTION

LED

Output

LED drivers

Tab. 10.6: LED ports description table

In order to switch on one of the eight LEDs on the front panel, the corresponding signal (LED[7:0]) should be set to 1.

➢ Gate & Delay Generator interface ports: The GDG is connected to the UFPGA via the following signals:

SIGNAL NAME

WIDTH

TYPE

DESCRIPTION

GD_START

Output

GDG start signals

GD_DELAYED

Input

GDG output signals

SPI_MISO

Input

SPI MISO (Master Input Slave Output)

SPI_SCLK

Output

Serial clock

SPI_CS

Output

SPI Chip Select

SPI_MOSI

Output

SPI MOSI (Master Output Slave Input)

Tab. 10.7: Gate and Delay Generator ports description table

➢ Local Bus ports: The Local Bus signals are shown in Tab. 10.8.

SIGNAL NAME

WIDTH

TYPE

DESCRIPTION

nLBRES

Input

Bus reset (active low)

nBLAST

Input

Last cycle (active low)

WnR

Input

Write/Read cycle 0 = read 1 = write

nADS

Input

Address strobe (active low)

nREADY

Output

Slave ready/Prefetch request

LAD

Input/Ou

tput

Data/address bus

Tab. 10.8: Local Bus ports description table

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10.3 Local Bus Interface

The Local Bus (LB) is the communication interface between the MFPGA and the UFPGA. It is made of a Master (LBM), implemented inside the MFPGA, and of a Slave (LBS), implemented inside the UFPGA. The

communication protocol between the LBM and the LBS is based on the following signals. In what follows OUT(IN) means that the signal goes from the LBM(LBS) to the LBS(LBM) and AL stands for active-low:

• nADS (OUT, AL): it is set by the LBM when a r/w operation is performed. The LBS samples the register address

from LAD when nADS is set.

• WnR (OUT): it notifies the LBS whether the access is in write- (WnR=1) or read- (WnR=0) mode. The value of

WnR is relevant only when nADS is set.

• nREADY (IN, AL): It is a dual purpose signal. it is set by the LBS to notify the LBM that the LBS is ready for r/w

data transfer. It can also be used for the data prefetch mechanism (see next).

• nBLAST (OUT, AL): it signals the last cycle of a data transfer. It is set when either the LBS is not ready or the LBM

cannot accept data (e.g. because the FIFO used for data prefetch is full).

• LAD (IN/OUT): the 16-bit bus used to read/write both address and data.

LBM can generate two kind of transfers over the local bus:

• Single word (32-bit) read/write transfer

• Multi word prefetch transfer

Single word transfers are initiated by the LBM for register access. It it composed by a single clock address phase and two 16-bit data phases. A data phase is completed if the LBS asserts nREADY low. The transfer ends on the second data phase when the LBM asserts the nBLAST signal low.

Examples of the signal logic taken using AlteraTM Signal Tap are shown in Fig. 10.2 and Fig. 10.3. For a read and a write access on the LBS.

Fig. 10.2: Local bus signals at a write access (x8BADF00D is written on register x1800)

Fig. 10.3: Local bus signal at a read access (x8BADF00D is read from register x1800)

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A data prefetch mechanism, implemented in the MFPGA, stores User data into a MFPGA local data queue (prefetch data queue). The MFPGA prefetch queue data is available for readout over the VME or USB interface (see Sect. Address Map). The prefetch mechanism is illustrated by Fig. 10.4.

nADS

LAD

WnR

nBLAST

nREADY

MAIN

FPGA

USER FPGA

LOCAL BUS

LOCAL

BUS

MASTER

LOCAL

BUS

SLAVE

PREFETCH

DATA

QUEUE

USER DATA

QUEUE

Fig. 10.4: Prefetch mechanism

Prefetch read cycles are initiated by the UFPGA logic: nREADY local bus signal must be used by the User logic to request a new data prefetch cycle by the local bus master (MFPGA): The request is active when the nREADY is low. The local bus master should have an internal prefetch queue (FIFO component). If a user request is pending and the local bus master has available space into the prefetch queue, it will start an internal block transfer from local bus address 0x0000 (fixed). The User logic is required to respond only to address 0x0000: data from its data queue are made available to the V2495 local bus. If a new register access is requested to the local bus master while a prefetch cycle is ongoing, the prefetch cycle will be interrupted by asserting the nBLAST signal and the register access will be served with priority. At the end of a register access, the user logic can keep the nREADY signal active to request a new prefetch cycle to the LBM, which will fetch new data in its queue.

Please refer to the lb_int.vhd source code in the User demo firmware projects.: it is a Local Bus slave implementation provided by CAEN as a reference. The lb_int.vhd found in the Pattern Recorder demo firmware (see Sect. Pattern Recorder Demo Description) is a demonstration of user logic implementation of the data prefetch mechanism.

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10.4 Gate and Delay Controller

General Description

The GDG can be used by the user logic to gate and delay up to 32 digital signals. The delay and gate values can be set using a dedicated serial bus (SPI bus). The signals are sent to the GDG, where they are gated and delayed according to the user settings and then returned to the UFPGA. The width of the delayed signal only depends on the gate value set and is not related to the width of the incoming signal.

The gate and delay values are 16-bit wide and their sum cannot exceed 65535 (0xFFFF). They are both generated by using an internal clock, which computes the number of clock cycles between the incoming signal and the leading and trailing edge of the gate signal. Referring to Fig. 10.5, the times of occurrence of the leading (T

lead

) and trailing (T

trail

)

can be obtained using the following formulas, where Ng(Nd) is the gate(delay) value set by register and T0, T1 are the time values reported in Tab. 10.9:

lead

= 0 if Nd=0

T0+T1(Nd-1) if Nd>0

trail

= 0 if Nd=Ng=0

T0+T1(Nd+Ng-1) if (Nd+Ng)≥1

The relationship between T

lead

, T

trail

and the delay and gate duration is:

delay=Tlead

gate=Ttrail-Tlead

Fig. 10.5: Gate and Delay parameters representation

T1 represents the minimum increment of either the gate or the delay value. The presence of T0 is due to a slightly longer duration of the minimum delay time increment (or gate increment, if the Ng=0) with respect to the standard T1 increment. It should be noted that both T1 and T0 can vary from channel to channel, with an expected variation interval of ±10% for both. Please also consider that, when setting Nd=0, the observed delay of the outgoing signal with respect to the incoming one is due to the paths on the PCB and inside the FPGAs, which are delay channel-dependent.

Example 1: If the delay value is set to 0x0 and the gate value is set to 0x5, the gate will last 12.2+10.7*4=55 ns. Example 2: If the delay value is set to 0x8 (typ. 12+7*10.7=86.9 ns), the maximum possible gate value is 0xFFF8 (typ.

65527*10.7 ≈ 701 µs).

Example 3: If the delay value is set to 0xFFF8 (≈ 701 µs), the ma maximum possible gate value is 0x8 (typ. 86.9 ns).

PARAMETER

VALUE

12 ns (typ.) ± 10%

10.7 ns (typ.) ± 10%

max

T0 + T1 (216-1)

Tab. 10.9: Main parameters of the Gate and Delay Generator

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The UFPGA can set the relevant configuration registers and read data from the generator through the SPI protocol. CAEN does not provide a detailed description of the communication protocol over the SPI bus for GDG configuration. A VHDL component is provided in the gd_control.vhd source code (GD_CONTROL), included in all the user demo firmware.

GD_CONTROL implements the following registers that can be accessed from the local bus. The LB_INT component reserves addresses starting from 0x7F00 to GD_CONTROL access. LB_INT and GD_CONTROL are connected by a dedicated interface for register write and read.

A set of LB registers are used to configure the GDG, as described in Tab. 10.10:

ADDRESS

ACCESS MODE

Read/Write

Base + 0x7F00 Base + 0x7F04 Base + 0x7F08 Base + 0x7F0C Base + 0x7F10

Data Write Command register Control register Data read Status register

A24/A32 A24/A32 A24/A32 A24/A32 A24/A32

D16/D32 D16/D32 D16/D32 D16/D32 D16/D32

R R R R R

Tab. 10.10: Local Bus registers description for the Gate and Delay Generator configuration

Register Description

➢ DATA WRITE: the datum (gate or delay) must be written here before it is transmitted through SPI to the GDG.

Address: 0x7F00. Mode: Read only.

Bit

Description

[31:0]

Gate or delay datum to transmit to the GDG

➢ COMMAND register: it is where the action to be performed is set. The action depends on the value of the 2 LSBs of

the Control register (read or write mode): one of these bits should be asserted to execute the related action. The channel interested by the action is set through the 6 LSBs of the register (relevant when [15:0] = 0x100 in write mode and [15:0] = 0x2000, 0x3000 in read mode).

Address: 0x7F04 Mode: Read only

Write Mode

Bit

Description

[31:16]

reserved

[15:0]

0x2000 = the internal gate value is modified with the content of the data write register (but

not sent to the DFPGA)

0x3000 = the internal delay value is modified with the content of the data write register (but

not sent to the DFPGA)

0x0100(+channel) = the gate AND delay values of the selected channel are modified with the

internal values, sent to the DFPGA by the UFPGA through SPI

0x0300 = the delay of all channels is reset

0x0400 = the delay of all channels is calibrated

0x0500 = the internal gate and delay values are broadcast to all 32 channels

Read Mode

Bit

Description

[31:16]

reserved

[15:0]

0x2000(+channel) = the gate value of the specified channel is read through SPI 0x3000(+channel) = the delay value of the specified channel is read through SPI

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➢ CONTROL register: bit[0] sets a write or read action.

Address: 0x7F08. Mode: Read only.

Bit

Description

[31:2]

reserved

[1]

1 = a read action is performed

[0]

1 = a write action is performed

➢ DATA READ: it is where the datum (gate or delay) can be read after an SPI read access to the GDG has been

performed (see the Read Mode of the COMMAND register).

Address: 0x7F0C. Mode: Read only.

Bit

Description

[31:0]

Gate or delay datum resulting from READ MODE access to GDG

➢ STATUS register

Address: 0x7F10. Mode: Read only.

Bit

Description

[31:1]

reserved

[0]

Gate and delay ready signal (when 0, the Gate and Delay controller is busy. A new command to the Gate and Delay controller should not be issued before this bit sets back to 1)

Example Procedures

• MODIFY THE GATE OR THE DELAY VALUE OF A CHANNEL

The gate or the delay of a signal from the UFPGA can be modified by following this procedure (the registers quoted are accessible via VME):

- Set a delay (gate) value in the DATA WRITE register

- Set the COMMAND register to 0x2000 (0x3000) to modify the delay (gate) internal value

- Set the control register to 0x1/0x0

- Set the COMMAND register to 0x100 + CHANNEL (6 bits) to write the gate and delay values on the FPGA

through the SPI bus, for the channel specified by the six LSBs. Note that the gate and delay values are written in the same action

- Set the CONTROL register to 0x1/0x0

• READ THE GATE OR THE DELAY VALUE OF A CHANNEL

- Set the COMMAND register to 0x2000 (0x3000) + CHANNEL (6 bits) to read the delay (gate) value of a

specific channel

- Set the CONTROL register to 0x2/0x0

- Read the required value in the DATA READ register

• BROADCAST A GATE OR DELAY VALUE OF A CHANNEL

- Set the desired values of the delay and gate values (see the first example, first two steps)

- Set the COMMAND register to 0x500

- Set the CONTROL register to 0x1/0x0

Note that in the case of a broadcast command the delay and gate values are serialized to the GDG at the same time. The bits related to the channel index (six LSBs of the CONTROL register) are irrelevant in this case.

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10.5 Porting V1495 to V2495

Firmware designs targeted to the V1495 User FPGA can be ported to V2495 by keeping in mind the following differences between the two modules:

- The V2495 FPGA device is different (Cyclone V versus Cyclone I) and with larger logic resources. While there will

be no resource constrains, the FPGA configuration scheme and output binary files are different for the two boards.

- A design that used on-board delay lines with V1495 must be redesigned to take into account the new features and

characteristics of the V2495 GDG.

- The address map of the V1495 VME FPGA and V2495 MAIN FPGA have some differences to take into account: o Registers in V1495 are mapped at 16-bit aligned addresses, while V2495 features a 32-bit aligned address

map. Access in VME D16 mode is still possible with V2495, but discouraged. Register access should always be in D32 mode.

o Common registers with different address:

▪ VME Interrupt level register:

• 0x8004 in V1495

• 0x8008 in V2495

▪ VME Interrupt Status/ID register:

• 0x8006 in V1495

• 0x800C in V2495

▪ GEO address register:

• 0x8008 in V1495

• 0x8010 in V2495

▪ Firmware revision:

• 0x800C in V1495

• 0x8200 in V2495

- The local bus map is the same for V1495 and V2495. Block transfers are allowed only in the 0x0000-0x0FFF

address interval. The same user data prefetch mechanism is implemented. Local bus register accesses are mapped to the same 0x1000-0x7FFF address interval.



Note: The V2495 no longer requires the 0x100C local bus address to be reserved for user firmware revision register with special constraints due to the firmware licensing mechanism. In V2495 all user register can be implemented in the allowed address range without any constraints of functionality or content

- The flash access register map and protocol is different between the two boards: the specific setting and tools

must be used for each module.

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11 Demo Firmware

11.1 Introduction

This chapter describes a set of UFPGA demos that CAEN provides as demonstration of the V2495 functionalities and as a guide for developing customized user application firmware.

The demos can be loaded on the UFPGA from a 6-page FLASH memory through the SW5 rotary switch (see Sect. Selecting the User FPGA Firmware). The switch position 0 loads the Factory firmware, while positions 1 to 5 load different demo firmware described in the following paragraphs. Positions higher than 5 load the Factory firmware (i.e. they are functionally equivalent to position 0).

To run a firmware “as it is”, it is required to use the functions of the CAEN PLULib library to access the proper (refer to Sect. Software Tools). To modify the demos and upload the new firmware on the FPGA, a basic knowledge of VHDL language and Altera Quartus II software are required.

In what follows, the features of the four demos loaded in the UFPGA’s flash memory will be described. By default, each demo lights front panel user LED with the following configurations:

Demo

Description

Demo1

LED 0 ON; others OFF

Demo2

LED 1 ON; others OFF

Demo3

LED 1 and LED 0 ON; others OFF

Demo4

LED 2 ON; others OFF

11.2 Demo Structure

All demo projects feature a common file structure:

• A configuration file (V2495_package.vhd), allowing to set the number of CONFIG and MONITOR registers, their

respective base address, the demo ID and the firmware revision. The CONFIG registers are mapped between 0x1000 and 0x17FC, while the MONITOR registers are mapped between 0x1800 and 0x1FFC.

• A gate and delay block (gd_control.vhd), acting as a controller for the GDG (the example in Sect. Gate and Delay

Demo Description specifically focuses on the configuration of GDG delays);

• The local bus slave (lb_int.vhd), allowing to read/write the registers needed in the demo operations;

• The SPI master (spi_master.vhd) and interface (spi_interface.vhd), allowing the communication to/from the

GDG to be serialized;

• A demo-specific part, containing core demonstration logic.

11.3 Demo Setup

In order to run one of the demo firmware, the following instructions should be followed:

• Select the desired position of the rotary switch and then restart the crate

• Connect to the V2495 board to read/write registers

• Set the required configuration through the control register(s).

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11.4 Gate Pattern Demo Description

Introduction

In this example, a logic combination of the input port signals A and B is sent to the C connector (32 lines). The user can choose the output among 10 available options by setting the 4 LSBs of the control register (see the register list). Apart from the value of A, B, A AND B and A OR B, the aforementioned signals in “capture” mode (a bit is set whenever a signal shows up) can be selected.

Register Map

In this example, 9 registers are used, 5 of which (MONITOR registers) can only be read and 4 (CONTROL registers) can be both read and written. All registers are 32 bit wide and can be accessed in single access mode.

ADDRESS

ACCESS MODE

Read/Write

Base + 0x1000 Base + 0x1004 Base + 0x1008 Base + 0x100C Base + 0x1010 Base + 0x1800 Base + 0x1804 Base + 0x1808 Base + 0x180C

Firmware version Value of port A (input) Value of port B (input) Value of port C (output) Status register Mask of input port A Mask of input port B Control register User Value of port C

A24/A32 A24/A32 A24/A32 A24/A32 A24/A32 A24/A32 A24/A32 A24/A32 A24/A32

D16/D32 D16/D32 D16/D32 D16/D32 D16/D32 D16/D32 D16/D32 D16/D32 D16/D32

R R R R R R/W R/W R/W R/W