Burr Brown Corporation ADS1252U-2K5, ADS1252U Datasheet

24-Bit, 40kHz

ANALOG-TO-DIGITAL CONVERTER

ADS1252

®

FEATURES

● 24 BITS NO MISSING CODES

● 19 BITS EFFECTIVE RESOLUTION UP TO

40kHz DATA RATE

● LOW NOISE: 2.5ppm

● DIFFERENTIAL INPUTS

● INL: 0.0015% (max)

● EXTERNAL REFERENCE

● POWER-DOWN MODE

● SYNC MODE

DESCRIPTION

The ADS1252 is a precision, wide dynamic range,
delta-sigma, Analog-to-Digital (A/D) converter with
24-bit resolution operating from a single +5V supply.
The delta-sigma architecture is used for wide dynamic
range and to guarantee 24 bits of no missing code
performance. An effective resolution of 19 bits (2.5ppm
of rms noise) is achieved for conversion rates up to
40kHz.

The ADS1252 is designed for high-resolution mea­surement applications in cardiac diagnostics, smart
transmitters, industrial process control, weigh scales,
chromatography, and portable instrumentation. The
converter includes a flexible, two-wire synchronous
serial interface for low-cost isolation.

The ADS1252 is a single-channel converter and is
offered in an SO-8 package.

APPLICATIONS

● CARDIAC DIAGNOSTICS

● DIRECT THERMOCOUPLE INTERFACE

● BLOOD ANALYSIS

● INFRARED PYROMETER

● LIQUID/GAS CHROMATOGRAPHY

● PRECISION PROCESS CONTROL

©

1999 Burr-Brown Corporation PDS-1550 Printed in U.S.A. June, 2000

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For most current data sheet and other product

information, visit www.burr-brown.com

ADS1252

4th-Order

∆Σ

Modulator

Digital

Filter

Serial

Interface

Control

+V

IN

CLK

V

REF

SCLK
DOUT/DRDY

+V

DD

GND

–V

IN

+

–

ADS1252

2

ADS1252

®

SPECIFICATIONS

All specifications at T

MIN

to T

MAX

, VDD = +5V, CLK = 16MHz, and V

REF

= 4.096, unless otherwise specified.

ADS1252U
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT

Input Voltage Range

(1)

0 ±V

REF

V
Input Impedance (differential) R = 6 ÷ (20pF • CLK) 19 kΩ
Input Capacitance 20 pF
Input Leakage At +25°C550pA

At T

MIN

to T

MAX

1nA

DYNAMIC CHARACTERISTICS

Data Rate 41.7 kHz
Bandwidth –3dB 9 kHz
Serial Clock (SCLK) 16 MHz
System Clock Input (CLK) 16 MHz

ACCURACY

Integral Linearity Error

(2)

±0.0004 ±0.0015 % of FSR
THD 1kHz Input; 0.1dB below FS 97 dB
Noise 2.5 3.8 ppm of FSR, rms
Resolution 24 Bits
No Missing Codes 24 Bits
Common-Mode Rejection

(3)

at DC 90 100 dB
Gain Error 0.4 1 % of FSR
Offset Error ±100 ±200 ppm of FSR
Gain Sensitivity to V

REF

V

REF

= 4.096V ±0.1V 1:1

Power Supply Rejection Ratio 60 80 dB

PERFORMANCE OVER TEMPERATURE

Offset Drift 0.07 ppm/°C
Gain Drift 13 ppm/°C

VOLTAGE REFERENCE

V

REF

4.096 V

Load Current 200 µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS
Logic Level: V

IH

+4.0 +VDD + 0.3 V

V

IL

–0.3 +0.8 V

V

OH

IOH = –500µA +4.5 V

V

OL

IOL = 500µA 0.4 V
Input (SCLK, CLK) Histeresis 0.6 V
Data Format Offset Two’s Complement

POWER SUPPLY REQUIREMENTS

Operation +4.75 +5 +5.25 VDC
Quiescent Current V

DD

= +5VDC 8 10 mA
Operating Power 40 50 mW
Power-Down Current 110µA

TEMPERATURE RANGE

Operating –40 +85 °C
Storage –60 +100 °C

NOTES: (1) In order to achieve the converter’s full-scale range, the input must be fully differential. If the input is single-ended (+V

IN

or –VIN is fixed), then the
full scale range is one-half that of the differential range. (2) Applies to full-differential signals. (3) The common-mode rejection test is performed with a 100mV
differential input.

3

®

ADS1252

PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER

(1)

MEDIA

ADS1252U SO-8 182 –40°C to +85°C ADS1252U ADS1252U Rails

"""""ADS1252U/2K5 Tape and Reel

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “ADS1252U/2K5” will get a single 2500-piece Tape and Reel.

PACKAGE/ORDERING INFORMATION

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap­propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.

Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr­Brown Corporation recommends that all integrated circuits be
handled and stored using appropriate ESD protection
methods.

Analog Input: Current................................................ ±100mA, Momentary

±10mA, Continuous

Voltage ....................................... GND –0.3V to V

DD

+ 0.3V

V

DD

to GND ..............................................................................–0.3V to 6V

V

REF

Voltage to GND ................................................. –0.3V to VDD + 0.3V

Digital Input Voltage to GND...................................... –0.3V to V

DD

+ 0.3V

Digital Output Voltage to GND ................................... –0.3V to V

DD

+ 0.3V

Lead Temperature (soldering, 10s) .............................................. +300°C

Power Dissipation (any package) .................................................. 500mW

ABSOLUTE MAXIMUM RATINGS

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life-support devices and/or systems.

PIN CONFIGURATION

Top View SO-8

PIN DESCRIPTIONS

PIN NAME PIN DESCRIPTION

1+V

IN

Analog Input: Positive Input of the Differential Analog Input.

2–V

IN

Analog Input: Negative Input of the Differential Analog Input.
3+VDDInput: Power Supply Voltage, +5V.
4 CLK Digital Input: Device System Clock. The system clock is in the form of a CMOS-compatible clock. This is a Schmitt-Trigger input.
5 DOUT/DRDY Digital Output: Serial Data Output/Data Ready. A logic LOW on this output indicates that a new output word is available from the

ADS1252 data output register. The serial data is clocked out of the serial data output shift register using SCLK.
6 SCLK Digital Input: Serial Clock. The serial clock is in the form of a CMOS-compatible clock. The serial clock operates indepen dently

from the system clock, therefore, it is possible to run SCLK at a higher frequency than CLK. The normal state of SCLK is LOW.

Holding SCLK HIGH will either initiate a modulator reset for synchronizing multiple converters or enter power-down mode. This

is a Schmitt-Trigger input.
7 GND Input: Ground.
8V

REF

Analog Input: Reference Voltage Input.

+V

IN

ADS1252U

GND

–V

IN

V

REF

+V

DD

SCLK

DOUT/DRDY

CLK

1

2

3

4

8

7

6

5

4

ADS1252

®

TYPICAL PERFORMANCE CURVES

At TA = +25°C, VDD = +5V, CLK = 14.7456MHz, and V

REF

= 4.096, unless otherwise specified.

RMS NOISE vs DATA OUTPUT RATE

Data Output Rate (Hz)

1k100 10k 100k

RMS Noise (ppm of FS)

3

2.5

2

1.5

1

0.5

0

3.4

3.3

3.2

3.1

3

2.9

2.8

RMS NOISE vs TEMPERATURE

Temperature (°C)

–40 –20 0 20 40 60 80 100

RMS Noise (ppm of FS)

3.5

3

2.5

2

1.5

1

0.5

0

RMS NOISE vs INPUT VOLTAGE

Differential Analog Input Voltage (V)

–4 –2 0 2 4

RMS Noise (ppm of FS)

8
7
6
5
4
3
2
1
0

INTEGRAL NON-LINEARITY vs TEMPERATURE

INL (ppm of FS)

Temperature (°C)

–40 –20 0 20 40 60 80 100

8
7
6
5
4
3
2
1
0

INTEGRAL NON-LINEARITY vs DATA OUTPUT RATE

Data Output Rate (Hz)

100 1k 10k 100k

INL (ppm of FS)

20
18
16
14
12
10

8
6
4
2
0

OFFSET DRIFT vs TEMPERATURE

Offset Drift (ppm of FS)

Temperature (°C)

–40 –20 0 20 40 60 80 100

5

®

ADS1252

TYPICAL PERFORMANCE CURVES (Cont.)

At TA = +25°C, VDD = +5V, CLK = 14.7456MHz, and V

REF

= 4.096, unless otherwise specified.

600
500
400
300
200
100

0
–100
–200
–300
–400

GAIN DRIFT vs TEMPERATURE

Temperature (°C)

–40 –20 0 20 40 60 80 100

Gain Drift (ppm of FS)

100

95
90
85
80
75
70
65
60

POWER SUPPLY REJECTION RATIO

vs TEMPERATURE

CLK Frequency (MHz)

0 5 10 15 20

PSRR (dB)

0
–20
–40
–60
–80

–100
–120
–140
–160
–180

TYPICAL FFT ANALYSIS

OF THE 1kHz f

S

INPUT SIGNAL

Frequency (Hz)

0 2000 60004000 8000 10000 12000 14000

Dynamic Range (dB)

45
40
35
30
25
20
15
10

5
0

POWER DISSIPATION vs CLOCK FREQUENCY

Clock Frequency (MHz)

0 5 10 15 20

Power Dissipation (mW)

9.5
9

8.5
8

7.5
7

6.5
6

5.5
5

CURRENT vs FREQUENCY

Temperature (°C)

–40 –20 0 20 40 60 80 100

Current (mA)

110

105

100

95

90

85

80

COMMON-MODE REJECTION RATIO

vs FREQUENCY

Frequency (Hz)

0 5 10 15 20

CMRR (dB)