Burr Brown Corporation ADS1211U-1K, ADS1211U, ADS1211P, ADS1211E-1K, ADS1211E Datasheet
...
®
1 ADS1210, 1211
®
ADS1210
ADS1211
24-Bit ANALOG-TO-DIGITAL CONVERTER
FEA TURES
● DELTA-SIGMA A/D CONVERTER
● 23 BITS EFFECTIVE RESOLUTION AT 10Hz
AND 20 BITS AT 1000Hz
● DIFFERENTIAL INPUTS
● PROGRAMMABLE GAIN AMPLIFIER
● FLEXIBLE SPI COMPATIBLE SSI
INTERFACE WITH 2-WIRE MODE
● PROGRAMMABLE CUT-OFF FREQUENCY
UP TO 15.6kHz
● INTERNAL/EXTERNAL REFERENCE
● ON CHIP SELF-CALIBRATION
● ADS1211 INCLUDES 4 CHANNEL MUX
DESCRIPTION
The ADS1210 and ADS1211 are precision, wide
dynamic range, delta-sigma analog-to-digital converters
with 24-bit resolution operating from a single +5V
supply. The differential inputs are ideal for direct
connection to transducers or low level voltage signals. The delta-sigma architecture is used for wide
dynamic range and to guarantee 22 bits of no missing
code performance. An effective resolution of 23 bits
is achieved through the use of a very low-noise input
amplifier at conversion rates up to 10Hz. Effective
resolutions of 20 bits can be maintained up to a
sample rate of 1kHz through the use of the unique
Turbo modulator mode of operation. The dynamic
range of the converters is further increased by providing a low-noise programmable gain amplifier with a
gain range of 1 to 16 in binary steps.
The ADS1210 and ADS1211 are designed for high
resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography and portable instrumentation. Both converters include a flexible synchronous serial interface
which is SPI compatible and also offers a two-wire
control mode for low cost isolation.
The ADS1210 is a single channel converter and is
offered in both 18-pin DIP and 18-lead SOIC packages. The ADS1211 includes a 4 channel input multiplexer and is available in 24-pin DIP, 24-lead SOIC,
and 28-lead SSOP packages.
APPLICATIONS
● INDUSTRIAL PROCESS CONTROL
● INSTRUMENTATION
● BLOOD ANALYSIS
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTS
● WEIGH SCALES
● PRESSURE TRANSDUCERS
ADS1211 Only ADS1210/11
ADS1210
ADS1211
ADS1210
ADS1211
ADS1211
PGA
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
Serial Interface
Second-Order
∆∑
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Third-Order
Digital Filter
Micro Controller
Modulator Control
AGND AVDDREF
OUT
REF
IN
V
BIAS
X
IN
X
OUT
MODE
DSYNC CS DRDY
AINP
A
IN
N
SCLK
DGND
DV
DD
SDIO
SDOUT
MUX
A
IN
1P
AIN1N
A
IN
2P
AIN2N
A
IN
3P
AIN3N
A
IN
4P
AIN4N
©
1996 Burr-Brown Corporation PDS-1284E Printed in U.S.A. May, 2000
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
2
ADS1210, 1211
®
All specifications T
MIN
to T
MAX
, AVDD = DVDD = +5V, f
XIN
= 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REF
OUT
disabled,V
BIAS
disabled,
and external 2.5V reference, unless otherwise specified.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
SPECIFICATIONS
ADS1210U, P/ADS1211U, P, E
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Input Voltage Range
(1)
0+5V
With V
BIAS
(2)
–10 +10 V
Input Impedance G = Gain, TMR = Turbo Mode Rate 4/(G • TMR)
(3)
MΩ
Programmable Gain Amplifier User Programmable: 1, 2, 4, 8, or 16 1 16
Input Capacitance 8pF
Input Leakage Current At +25°C550pA
At T
MIN
to T
MAX
1nA
SYSTEMS PERFORMANCE
Resolution 24 Bits
No Missing Codes f
DATA
= 60Hz 22 Bits
Integral Linearity f
DATA
= 60Hz ±0.0015 %FSR
f
DATA
= 1000Hz, TMR of 16 ±0.0015 %FSR
Unipolar Offset Error
(4)
See Note 5
Unipolar Offset Drift
(6)
1 µV/°C
Gain Error
(4)
See Note 5
Gain Error Drift
(6)
1 µV/°C
Common-Mode Rejection
(9)
At DC, +25°C 100 115 dB
At DC, T
MIN
to T
MAX
90 115 dB
50Hz, f
DATA
= 50Hz
(7)
160 dB
60Hz, f
DATA
= 60Hz
(7)
160 dB
Normal-Mode Rejection 50Hz, f
DATA
= 50Hz
(7)
100 dB
60Hz, f
DATA
= 60Hz
(7)
100 dB
Output Noise See Typical Performance Curves
Power Supply Rejection DC, 50Hz, and 60Hz 65 dB
VOLTAGE REFERENCE
Internal Reference (REF
OUT
) 2.4 2.5 2.6 V
Drift 25 ppm/°C
Noise 50 µVp-p
Load Current Source or Sink 1 mA
Output Impedance 2 Ω
External Reference (REF
IN
) 2.0 3.0 V
Load Current 2.5 µA
V
BIAS
Output Using Internal Reference 3.15 3.3 3.45 V
Drift 50 ppm/°C
Load Current Source or Sink 10mA
DIGITAL INPUT/OUTPUT
Logic Family TTL Compatible CMOS
Logic Level: (all except X
IN
)
V
IH
IIH = +5µA 2.0 DV
DD
+0.3 V
V
IL
IIL = +5µA –0.3 0.8 V
V
OH
IOH = 2 TTL Loads 2.4 V
V
OL
IOL = 2 TTL Loads 0.4 V
X
IN
Input Levels: V
IH
3.5 DV
DD
+0.3 V
V
IL
–0.3 0.8 V
X
IN
Frequency Range (f
XIN
) 0.5 10 MHz
Output Data Rate (f
DATA
) User Programmable 2.4 15,625 Hz
f
XIN
= 500kHz 0.12 781 Hz
Data Format User Programmable
Two’s Complement
or Offset Binary
SYSTEM CALIBRATION
Offset and Full-Scale Limits V
FS
= Full-Scale Differential Voltage
(8)
0.7 • (2 • REFIN)/G
VFS – | VOS |V
OS
= Offset Differential Voltage
(8)
1.3 • (2 • REFIN)/G
®
3 ADS1210, 1211
POWER SUPPLY REQUIREMENTS
Power Supply Voltage 4.75 5.25 V
Power Supply Current:
Analog Current 2mA
Digital Current 3.5 mA
Additional Analog Current with
REF
OUT
Enabled 1.6 mA
V
BIAS
Enabled No Load 1 mA
Power Dissipation 26 40 mW
TMR of 16 37 60 mW
f
XIN
= 2.5MHz 17 mW
f
XIN
= 2.5MHz, TMR of 16 27 mW
Sleep Mode 11 mW
TEMPERATURE RANGE
Specified –40 +85 °C
Storage –60 +125 °C
NOTES: (1) In order to achieve the converter’s full-scale range, the input must be fully differential (A
IN
N = 2 • REFIN – AINP). If the input is single-ended (AINN or
A
IN
P is fixed), then the full scale range is one-half that of the differential range. (2) This range is set with external resistors and V
BIAS
(as described in the text).
Other ranges are possible. (3) Input impedance is higher with lower f
XIN
. (4) Applies after calibration. (5) After system calibration, these errors will be of the order
of the effective resolution of the converter. Refer to the Typical Performance Curves which apply to the desired mode of operation. (6) Recalibration can remove
these errors. (7) The specification also applies at f
DATA
/i, where i is 2, 3, 4, etc. (8) Voltages at the analog inputs must remain within AGND to AVDD. (9) The common-
mode rejection test is performed with a 100mV differential input.
SPECIFICATIONS (CONT)
ADS1210U, P/ADS1211U, P, E
PARAMETER CONDITIONS MIN TYP MAX UNITS
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING TEMPERATURE
PRODUCT PACKAGE NUMBER
(1)
RANGE
ADS1210P 18-Pin Plastic DIP 218 –40°C to +85°C
ADS1210U 18-Lead SOIC 219 –40°C to +85°C
ADS1211P 24-Pin Plastic DIP 243 –40°C to +85°C
ADS1211U 24-Lead SOIC 239 –40°C to +85°C
ADS1211E 28-Lead SSOP 324 –40°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be
handled and stored using appropriate ESD protection
methods.
Analog Input: Current................................................ ±100mA, Momentary
±10mA, Continuous
Voltage ................................... AGND –0.3V to AV
DD
+0.3V
AV
DD
to DVDD...........................................................................–0.3V to 6V
AV
DD
to AGND .........................................................................–0.3V to 6V
DV
DD
to DGND.........................................................................–0.3V to 6V
AGND to DGND ................................................................................ ±0.3V
REF
IN
Voltage to AGND............................................–0.3V to AVDD +0.3V
Digital Input Voltage to DGND ..................................–0.3V to DV
DD
+0.3V
Digital Output Voltage to DGND ............................... –0.3V to DV
DD
+0.3V
Lead Temperature (soldering, 10s) .............................................. +300°C
Power Dissipation (Any package) .................................................. 500mW
ABSOLUTE MAXIMUM RATINGS
All specifications T
MIN
to T
MAX
, AVDD = DVDD = +5V, f
XIN
= 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REF
OUT
disabled,V
BIAS
disabled,
and external 2.5V reference, unless otherwise specified.
4
ADS1210, 1211
®
PGA
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
Serial Interface
Second-Order
∆Σ
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Third-Order
Digital Filter
Micro Controller
Modulator Control
11
9
10
12
13
AGND AV
DD
REF
OUT
REF
IN
V
BIAS
X
IN
X
OUT
3
1
2
16 17 18 4 7 8
65 1415
DSYNC CS DRDYMODE
AINP
A
IN
N
SCLK
DGND
DV
DD
SDIO
SDOUT
ADS1210
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
ADS1210 SIMPLIFIED BLOCK DIAGRAM
ADS1210 PIN DEFINITIONS
PIN NO NAME DESCRIPTION
1A
IN
P Noninverting Input.
2A
IN
N Inverting Input.
3 AGND Analog Ground.
4V
BIAS
Bias Voltage Output, +3.3V nominal.
5 CS Chip Select Input.
6 DSYNC Control Input to Synchronize Serial Output Data.
7X
IN
System Clock Input.
8X
OUT
System Clock Output (for Crystal or Resonator).
9 DGND Digital Ground.
10 DV
DD
Digital Supply, +5V nominal.
11 SCLK Clock Input/Output for serial data transfer.
12 SDIO Serial Data Input (can also function as Serial Data
Output).
13 SDOUT Serial Data Output.
14 DRDY Data Ready.
15 MODE SCLK Control Input (Master = 1, Slave = 0).
16 AV
DD
Analog Supply, +5V nominal.
17 REF
OUT
Reference Output, +2.5V nominal.
18 REF
IN
Reference Input.
TOP VIEW DIP/SOIC
ADS1210 PIN CONFIGURATION
®
5 ADS1210, 1211
PGA
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
Serial Interface
Second-Order
∆∑
Modulator
Third-Order
Digital Filter
Modulator Control
14
12
13
15
16
AGND AV
DD
REF
OUT
REF
IN
V
BIAS
X
IN
X
OUT
6 19 20 21 7 10 11
98 1718
DSYNC CS DRDYMODE
SCLK
DGND
DV
DD
SDIO
SDOUT
4
5
2
3
24
1
22
23
MUX
A
IN
1P
A
IN
1N
A
IN
2P
A
IN
2N
A
IN
3P
A
IN
3N
A
IN
4P
A
IN
4N
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Micro Controller
ADS1211 SIMPLIFIED BLOCK DIAGRAM
ADS1211P AND ADS1211U PIN DEFINITIONS
TOP VIEW DIP/SOIC
ADS1211P AND ADS1211U PIN CONFIGURATION
PIN NO NAME DESCRIPTION
1AIN3N Inverting Input Channel 3.
2AIN2P Noninverting Input Channel 2.
3A
IN
2N Inverting Input Channel 2.
4A
IN
1P Noninverting Input Channel 1.
5AIN1N Inverting Input Channel 1.
6 AGND Analog Ground.
7V
BIAS
Bias Voltage Output, +3.3V nominal.
8 CS Chip Select Input.
9 DSYNC Control Input to Synchronize Serial Output Data.
10 X
IN
System Clock Input.
11 X
OUT
System Clock Output (for Crystal or Resonator).
12 DGND Digital Ground.
13 DV
DD
Digital Supply, +5V nominal.
14 SCLK Clock Input/Output for serial data transfer.
15 SDIO Serial Data Input (can also function as Serial Data
Output).
16 SDOUT Serial Data Output.
17 DRDY Data Ready.
18 MODE SCLK Control Input (Master = 1, Slave = 0).
19 AV
DD
Analog Supply, +5V nominal.
20 REF
OUT
Reference Output: +2.5V nominal.
21 REF
IN
Reference Input.
22 A
IN
4P Noninverting Input Channel 4.
23 AIN4N Inverting Input Channel 4.
24 A
IN
3P Noninverting Input Channel 3.
ADS1211P
ADS1211U
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
A
IN
3P
A
IN
4N
A
IN
4P
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
6
ADS1210, 1211
®
ADS1211E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
NIC
NIC
CS
DSYNC
X
IN
X
OUT
DGND
A
IN
3P
A
IN
4N
A
IN
4P
REF
IN
REF
OUT
AV
DD
MODE
NIC
NIC
DRDY
SDOUT
SDIO
SCLK
DV
DD
ADS1211E PIN DEFINITIONS
PIN NO NAME DESCRIPTION
1A
IN
3N Inverting Input Channel 3.
2A
IN
2P Noninverting Input Channel 2.
3AIN2N Inverting Input Channel 2.
4A
IN
1P Noninverting Input Channel 1.
5A
IN
1N Inverting Input Channel 1.
6 AGND Analog Ground.
7V
BIAS
Bias Voltage Output, +3.3V nominal.
8 NIC Not Internally Connected.
9 NIC Not Internally Connected.
10 CS Chip Select Input.
11 DSYNC Control Input to Synchronize Serial Output Data.
12 X
IN
System Clock Input.
13 X
OUT
System Clock Output (for Crystal or Resonator).
14 DGND Digital Ground.
15 DV
DD
Digital Supply, +5V nominal.
16 SCLK Clock Input/Output for serial data transfer.
17 SDIO Serial Data Input (can also function as Serial Data
Output).
18 SDOUT Serial Data Output.
19 DRDY Data Ready.
20 NIC Not Internally Connected.
21 NIC Not Internally Connected.
22 MODE SCLK Control Input (Master = 1, Slave = 0).
23 AV
DD
Analog Supply, +5V nominal.
24 REF
OUT
Reference Output: +2.5V nominal.
25 REF
IN
Reference Input.
26 A
IN
4P Noninverting Input Channel 4.
27 AIN4N Inverting Input Channel 4.
28 A
IN
3P Noninverting Input Channel 3.
ADS1211E PIN CONFIGURATION
TOP VIEW SSOP
®
7 ADS1210, 1211
TYPICAL PERFORMANCE CURVES
At TA = +25°C, AVDD = DV
DD =
+5V, f
XIN
= 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of one, REF
OUT
disabled, V
BIAS
disabled, and external
2.5V reference, unless otherwise noted.
RMS NOISE vs INPUT VOLTAGE LEVEL
(60Hz Data Rate)
Analog Input Differential Voltage (V)
–5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0
RMS Noise (ppm)
2.5
2.0
1.5
1.0
0.5
24
22
20
18
16
14
12
EFFECTIVE RESOLUTION vs DATA RATE
(2.5MHz Clock)
Data Rate (Hz)
1 10 100 1k
Effective Resolution in Bits (rms)
Turbo 1
Turbo 2
Turbo 4
Turbo 8
Turbo 16
24
22
20
18
16
14
12
EFFECTIVE RESOLUTION vs DATA RATE
(5MHz Clock)
Data Rate (Hz)
10 100 1k
Effective Resolution in Bits (rms)
Turbo 1
Turbo 2
Turbo 4
Turbo 8
Turbo 16
EFFECTIVE RESOLUTION vs DATA RATE
(10MHz Clock)
Data Rate (Hz)
10 100 1k
Effective Resolution in Bits (rms)
Turbo 1
Turbo 2
Turbo 4
Turbo 8
Turbo 16
24
22
20
18
16
14
12
EFFECTIVE RESOLUTION vs DATA RATE
Data Rate (Hz)
10
100 1k
Effective Resolution in Bits (rms)
PGA 1
24
22
20
18
16
14
12
10
PGA 2 PGA 4
PGA 16
PGA 8
24
22
20
18
16
14
12
EFFECTIVE RESOLUTION vs DATA RATE
(1MHz Clock)
Data Rate (Hz)
1 10 100 1k
Effective Resolution in Bits (rms)
Turbo 1
Turbo 2
Turbo 4
Turbo 8
Turbo 16
8
ADS1210, 1211
®
POWER DISSIPATION vs TURBO MODE RATE
(REF
OUT
Enabled)
Turbo Mode Rate
10MHz
124816
Power Dissipation (mW)
50.0
40.0
30.0
20.0
5MHz
2.5MHz
1MHz
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, AVDD = DV
DD =
+5V, f
XIN
= 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REF
OUT
disabled, V
BIAS
disabled, and external
2.5V reference, unless otherwise noted.
85.0
80.0
75.0
70.0
65.0
PSRR vs FREQUENCY
PSRR (dB)
0.1 1 10 100
Frequency (Hz)
1k 10k 100k
120.0
115.0
110.0
CMRR vs FREQUENCY
CMRR (dB)
0.1 1 10
Frequency (Hz)
100 1k
POWER DISSIPATION vs TURBO MODE RATE
(External Reference; REF
OUT
)
Turbo Mode Rate
10MHz
124816
Power Dissipation (mW)
40.0
30.0
20.0
10.0
5MHz
2.5MHz
1MHz
LINEARITY vs TEMPERATURE
(60Hz Data Rate)
Analog Input Differential Voltage (V)
–5 –4 –3 –2 –1 0 1 2 3 4 5
Integral Nonlinearity (ppm)
8
6
4
2
0
–2
–4
–6
–40°C
–5°C
+25°C
+55°C
+85°C
®
9 ADS1210, 1211
ANALOG ANALOG INPUT
INPUT
(1)
UTILIZING V
BIAS
(1,2)
FULL- EXAMPLE FULL- EXAMPLE
SCALE VOLTAGE SCALE VOLTAGE
GAIN RANGE RANGE
(3)
RANGE RANGE
(3)
SETTING (V) (V) (V) (V)
1 10 0 to 5 40 ±10
2 5 1.25 to 3.75 20 ±5
4 2.5 1.88 to 3.13 10 ±2.5
8 1.25 2.19 to 2.81 5 ±1.25
16 0.625 2.34 to 2.66 2.5 ±0.625
NOTE: (1) With a 2.5V reference, such as the internal reference. (2) This
example utilizes the circuit in Figure 12. Other input ranges are possible. (3)
The ADS1210/11 allows common-mode voltage as long as the absolute
input voltage on A
IN
P or AINN does not go below AGND or above AVDD.
THEORY OF OPERATION
The ADS1210 and ADS1211 are precision, high dynamic
range, self-calibrating, 24-bit, delta-sigma A/D converters
capable of achieving very high resolution digital results.
Each contains a programmable gain amplifier (PGA); a
second-order delta-sigma modulator; a programmable digital filter; a microcontroller including the Instruction, Command and Calibration registers; a serial interface; a clock
generator circuit; and an internal 2.5V reference. The
ADS1211 includes a 4-channel input multiplexer.
In order to provide low system noise, common-mode rejection of 115dB and excellent power supply rejection, the
design topology is based on a fully differential switched
capacitor architecture. Turbo Mode, a unique feature of the
ADS1210/11, can be used to boost the sampling rate of the
input capacitor, which is normally 19.5kHz with a 10MHz
clock. By programming the Command Register, the sampling rate can be increased to 39kHz, 78kHz, 156kHz, or
312kHz. Each increase in sample rate results in an increase
in performance when maintaining the same output data rate.
The programmable gain amplifier (PGA) of the ADS1210/
11 can be set to a gain of 1, 2, 4, 8 or 16—substantially
increasing the dynamic range of the converter and simplifying the interface to the more common transducers (see Table
I). This gain is implemented by increasing the number of
samples taken by the input capacitor from 19.5kHz for a
gain of 1 to 312kHz for a gain of 16. Since the Turbo Mode
and PGA functions are both implemented by varying the
sampling frequency of the input capacitor, the combination
of PGA gain and Turbo Mode Rate is limited to 16 (see
Table II). For example, when using a Turbo Mode Rate of
8 (156kHz at 10MHz), the maximum PGA gain setting is 2.
TABLE I. Full-Scale Range vs PGA Setting.
TURBO MODE RATE AVAILABLE PGA SETTINGS
1 1, 2, 4, 8, 16
2 1, 2, 4, 8
4 1, 2, 4
8 1, 2
16 1
TABLE II. Available PGA Settings vs Turbo Mode Rate.
The output data rate of the ADS1210/11 can be varied from
a few hertz to as much as 15,625kHz, trading off lower
resolution results for higher data rates. In addition, the data
rate determines the first null of the digital filter and sets the
–3dB point of the input bandwidth (see the Digital Filter
section). Changing the data rate of the ADS1210/11 does not
result in a change in the sampling rate of the input capacitor.
The data rate effectively sets the number of samples which
are used by the digital filter to obtain each conversion result.
A lower data rate results in higher resolution, lower input
bandwidth, and different notch frequencies than a higher
data rate. It does not result in any change in input impedance
or modulator frequency, or any appreciable change in power
consumption.
The ADS1210/11 also includes complete on-board calibration that can correct for internal offset and gain errors or
limited external system errors. Internal calibration can be
run when needed, or automatically and continuously in the
background. System calibration can be run as needed and the
appropriate input voltages must be provided to the ADS1210/
11. For this reason, there is no continuous System Calibration Mode. The calibration registers are fully readable and
writable. This feature allows for switching between various
configurations—different data rates, Turbo Mode Rates, and
gain settings—without re-calibrating.
The various settings, rates, modes, and registers of the
ADS1210/11 are read or written via a synchronous serial
interface. This interface can operate in either a self-clocked
mode (Master Mode) or an externally clocked mode (Slave
Mode). In the Master Mode, the serial clock (SCLK) frequency is one-half of the ADS1210/11 XIN clock frequency.
This is an important consideration for many systems and
may determine the maximum ADS1210/11 clock that can be
used.
The high resolution and flexibility of the ADS1210/11 allow
these converters to fill a wide variety of A/D conversion
tasks. In order to ensure that a particular configuration will
meet the design goals, there are several important items
which must be considered. These include (but are certainly
not limited to) the needed resolution, required linearity,
desired input bandwidth, power consumption goal, and sensor output voltage.
The remainder of this data sheet discusses the operation of
the ADS1210/11 in detail. In order to allow for easier
comparison of different configurations, “effective resolution” is used as the figure of merit for most tables and
graphs. For example, Table III shows a comparison between
data rate (and –3dB input bandwidth) versus PGA setting at
a Turbo Mode Rate of 1 and a clock rate of 10MHz. See the
Definition of Terms section for a definition of effective
resolution.
10
ADS1210, 1211
®
DATA -3DB
RATE FREQUENCY
(HZ) (HZ) G = 1 G = 2 G = 4 G = 8 G = 16
10 2.62 21.5 21.0 21.0 21.0 20.0
25 6.55 20.5 20.5 20.5 20.0 19.5
30 7.86 20.5 20.5 20.5 20.0 19.5
50 13.1 20.0 20.0 20.0 19.5 19.0
60 15.7 19.5 19.5 19.5 19.0 19.0
100 26.2 18.0 18.0 18.0 18.0 18.0
250 65.5 15.0 15.0 15.0 15.0 15.0
500 131 12.5 12.5 12.5 12.5 12.5
1000 262 10.0 10.5 10.0 10.0 10.0
EFFECTIVE RESOLUTION (BITS RMS)
TABLE III. Effective Resolution vs Data Rate and Gain
Setting. (Turbo Mode Rate of 1 and a 10MHz
clock.)
DEFINITION OF TERMS
An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the definition
of each term is given as follows:
Analog Input Differential Voltage—For an analog signal
that is fully differential, the voltage range can be compared
to that of an instrumentation amplifier. For example, if both
analog inputs of the ADS1210 are at 2.5V, then the differential voltage is 0V. If one is at 0V and the other at 5V, then
the differential voltage magnitude is 5V. But, this is the case
regardless of which input is at 0V and which is at 5V, while
the digital output result is quite different.
The analog input differential voltage is given by the following equation: AINP – AINN. Thus, a positive digital output is
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced whenever the differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 2, the positive fullscale output is produced when the analog input differential
is 2.5V. The negative full-scale output is produced when the
differential is –2.5V. In each case, the actual input voltages
must remain within the AGND to AVDD range (see Table I).
Actual Analog Input Voltage—The voltage at any one
analog input relative to AGND.
Full-Scale Range (FSR)—As with most A/D converters,
the full-scale range of the ADS1210/11 is defined as the
“input” which produces the positive full-scale digital output
minus the “input” which produces the negative full-scale
digital output.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [2.5V (positive full scale) minus –2.5V (negative
full scale)] = 5V.
Typical Analog Input Voltage Range—This term describes the actual voltage range of the analog inputs which
will cover the converter’s full-scale range, assuming that
each input has a common-mode voltage that is greater than
REFIN/PGA and smaller than (AVDD – REFIN/PGA).
LSB Weight =
Full−Scale Range
2
N
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 2, the typical input
voltage range is 1.25V to 3.75V. However, an input range of
0V to 2.5V or 2.5V to 5V would also cover the converter’s
full-scale range.
Voltage Span—This is simply the magnitude of the typical
analog input voltage range. For example, when the converter
is configured with a 2.5V reference and placed in a gain
setting of 2, the input voltage span is 2.5V.
Least Significant Bit (LSB) Weight—This is the theoretical amount of voltage that the differential voltage at the
analog input would have to change in order to observe a
change in the output data of one least significant bit. It is
computed as follows:
where N is the number of bits in the digital output.
Effective Resolution—The effective resolution of the
ADS1210/11 in a particular configuration can be expressed
in two different units: bits rms (referenced to output) and
microvolts rms (referenced to input). Computed directly
from the converter’s output data, each is a statistical calculation based on a given number of results. Knowing one, the
other can be computed as follows:
The 10V figure in each calculation represents the full-scale
range of the ADS1210/11 in a gain setting of 1. This means
that both units are absolute expressions of resolution—the
performance in different configurations can be directly compared regardless of the units. Comparing the resolution of
different gain settings expressed in bits rms requires accounting for the PGA setting.
Main Controller—A generic term for the external
microcontroller, microprocessor, or digital signal processor
which is controlling the operation of the ADS1210/11 and
receiving the output data.
ER in bits rms =
20• log
10V
PGA
ER in Vrms
−1.76
6.02
ER in Vrms =
10
10V
PGA
6.02•ER in bits rms +1.76
20
®
11 ADS1210, 1211
f
DATA
=
f
XIN
•Turbo Mode
512• Decimation Ratio +1
()
f
DATA
=
f
XIN
•Turbo Mode
512• DecimationRatio +1
()
,t
DATA
=
1
f
DATA
FILTER RESPONSE
Frequency (Hz)
–40
–60
–80
–100
–120
–140
–160
45 46 47 48 49 50 51 52 53 54 55
FILTER RESPONSE
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
–140
–160
0 50 100 150 200 250 300
Gain (dB)
Gain (dB)
NORMALIZED DIGITAL FILTER RESPONSE
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
–140
–160
0123456
Gain (dB)
FIGURE 3. Digital Filter Response at a Data Rate of 60Hz.
f
MOD
=
f
XIN
•Turbo Mode
512
f
SAMP
=
f
XIN
•Turbo Mode• Gain Setting
512
FIGURE 1. Normalized Digital Filter Response.
FIGURE 2. Digital Filter Response at a Data Rate of 50Hz.
If the effective resolution at a 50Hz or 60Hz data rate is not
adequate for the particular application, then power line frequencies could still be rejected by operating the ADS1210/11
at 25/30Hz, 16.7/20Hz, 12.5/15Hz, etc. If a higher data rate
is needed, then power line frequencies must either be rejected
before conversion (with an analog notch filter) or after
conversion (with a digital notch filter running on the main
controller).
f
XIN
—The frequency of the crystal oscillator or CMOS
compatible input signal at the XIN input of the ADS1210/11.
f
MOD
—The frequency or speed at which the modulator of the
ADS1210/11 is running, given by the following equation:
f
SAMP
—The frequency or switching speed of the input
sampling capacitor. The value is given by the following
equation:
f
DATA
, t
DATA
—The frequency of the digital output data
produced by the ADS1210/11 or the inverse of this (the
period), respectively, f
DATA
is also referred to as the data rate.
Conversion Cycle—The term “conversion cycle” usually
refers to a discrete A/D conversion operation, such as that
performed by a successive approximation converter. As
used here, a conversion cycle refers to the t
DATA
time period.
However, each digital output is actually based on the modulator results from the last three t
DATA
time periods.
DIGITAL FILTER
The digital filter of the ADS1210/11 computes the output
result based on the most recent results from the delta-sigma
modulator. The number of modulator results that are used
depend on the decimation ratio set in the Command Register. At the most basic level, the digital filter can be thought
of as simply averaging the modulator results and presenting
this average as the digital output.
While the decimation ratio determines the number of modulator results to use, the modulator runs faster at higher Turbo
Modes. These two items, together with the ADS1210/11
clock frequency, determine the output data rate:
Also, since the conversion result is essentially an average,
the data rate determines where the resulting notches are in
the digital filter. For example, if the output data rate is 1kHz,
then a 1kHz input frequency will average to zero during the
1ms conversion cycle. Likewise, a 2kHz input frequency
will average to zero, etc.
In this manner, the data rate can be used to set specific notch
frequencies in the digital filter response (see Figure 1 for the
normalized response of the digital filter). For example, if the
rejection of power line frequencies is desired, then the data
rate can simply be set to the power line frequency. Figures
2 and 3 show the digital filter response for a data rate of
50Hz and 60Hz, respectively.
FILTER RESPONSE
Frequency (Hz)
–40
–60
–80
–100
–120
–140
–160
55 56 57 58 59 60 61 62 63 64 65
FILTER RESPONSE
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
–140
–160
0 50 100 150 200 250 300
Gain (dB) Gain (dB)
12
ADS1210, 1211
®
Filter Equation
The digital filter is described by the following transfer
function:
where N is the Decimation Ratio.
This filter has a (sin(x)/x)3 response and is referred to a sinc
3
filter. For the ADS1210/11, this type of filter allows the data
rate to be changed over a very wide range (nearly four orders
of magnitude). However, the –3dB point of the filter is 0.262
times the data rate. And, as can be seen in Figures 1 and 2,
the rejection in the stopband (frequencies higher than the
first notch frequency) may only be –40dB.
These factors must be considered in the overall system
design. For example, with a 50Hz data rate, a significant
signal at 75Hz may alias back into the passband at 25Hz.
The analog front end can be designed to provide the needed
attenuation to prevent aliasing, or the system may simply
provide this inherently. Another possibility is increasing the
data rate and then post filtering with a digital filter on the
main controller.
Filter Settling
The number of modulator results used to compute each
conversion result is three times the Decimation Ratio. This
means that any step change (or any channel change for the
ADS1211) will require at least three conversions to fully
settle. However, if the change occurs asynchronously, then at
least four conversions are required to ensure complete settling. For example, on the ADS1211, the fourth conversion
result after a channel change will be valid (see Figure 4).
|H(f)|=
sin
π•f • N
f
MOD
N •sin
π•f
f
MOD
3
the effective resolution of the output data at a given data rate,
but there is also an increase in power dissipation. For Turbo
Mode Rates 2 and 4, the increase is slight. For rates 8 and
16, the increase is more substantial. See the Typical Performance Curves for more information.
In a Turbo Mode Rate of 16, the ADS1210/11 can offer 20
bits of effective resolution at a 1kHz data rate. A comparison
of effective resolution versus Turbo Mode Rates and output
data rates is shown in Table IV while Table V shows the
corresponding noise level in µVrms.
TURBO MODE
The ADS1210/11 offers a unique Turbo Mode feature which
can be used to increase the modulator sampling rate by 2, 4,
8, or 16 times normal. With the increase of modulator
sampling frequency, there can be a substantial increase in
Data Turbo Turbo Turbo Turbo Turbo
Rate Mode Mode Mode Mode Mode
(Hz) Rate 1 Rate 2 Rate 4 Rate 8 Rate 16
10 21.5 22.0 22.5
20 21.0 22.0 22.0 22.5
40 20.0 21.5 22.0 22.5 23.0
50 20.0 21.5 21.5 22.0 23.0
60 19.5 21.0 21.5 22.0 23.0
100 18.0 20.0 21.0 21.5 22.5
1000 10.0 12.5 15.0 17.5 20.0
Effective Resolution (Bits rms)
TABLE IV. Effective Resolution vs Data Rate and Turbo Mode
Rate. (Gain setting of 1 and 10MHz clock.)
DATA TURBO TURBO TURBO TURBO TURBO
RATE MODE MODE MODE MODE MODE
(Hz) RATE 1 RATE 2 RATE 4 RATE 8 RATE 16
10 2.9 1.7 1.3
20 4.3 2.1 1.7 1.3
40 6.9 3.0 2.3 1.6 1.0
50 8.1 3.2 2.4 1.8 1.0
60 10.5 3.9 2.6 1.9 1.0
100 26.9 6.9 3.5 2.7 1.4
1000 6909.7 1354.5 238.4 46.6 7.8
TABLE V. Noise Level vs Data Rate and Turbo Mode Rate.
(Gain setting of 1 and 10MHz clock.)
NOISE LEVEL (µVrms)
The Turbo Mode feature allows trade-offs to be made
between the ADS1210/11 XIN clock frequency, power dissipation, and effective resolution. If a 5MHz clock is available
but a 10MHz clock is needed to achieve the desired performance, a Turbo Mode Rate of 2X will result in the same
effective resolution. Table VI provides a comparison of
effective resolution at various clock frequencies, data rates,
and Turbo Mode Rates.
DATA XIN CLOCK TURBO EFFECTIVE
RATE FREQUENCY MODE RESOLUTION
(Hz) (MHz) RATE (Bits rms)
60 10 1 19.5
60 5 2 19.5
60 2.5 4 19.5
60 1.25 8 19.5
60 0.625 16 19.5
100 10 1 18.0
100 5 2 18.0
100 2.5 4 18.0
100 1.25 8 18.0
100 0.625 16 18.0
TABLE VI. Effective Resolution vs Data Rate, Clock
Frequency, and Turbo Mode Rate. (Gain setting of 1.)
FIGURE 4. Asynchronous ADS1210/11 Analog Input Volt-
age Step or ADS1211 Channel Change to Fully
Settled Output Data.
DRDY
Serial
I/O
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Data
not
Valid
Data
not
Valid
Data
not
Valid
Significant Analog Input Change
or
ADS1211 Channel Change
t
DATA
®
13 ADS1210, 1211
The Turbo Mode Rate (TMR) is programmed via the Sampling Frequency bits of the Command Register. Due to the
increase in input capacitor sampling frequency, higher Turbo
Mode settings result in lower analog input impedance;
AIN Impedance (Ω) = (10MHz/f
XIN
)•4.3E6/(G•TMR)
where G is the gain setting. Because the modulator rate also
changes in direct relation to the Turbo Mode setting, higher
values result in a lower impedance for the REFIN input:
REFIN Impedance (Ω) = (10MHz/f
XIN
)•1E6/TMR
The Turbo Mode Rate can be set to 1, 2, 4, 8, or 16. Consult
the graphs shown in the Typical Performance Curves for full
details on the performance of the ADS1210/11 operating in
different Turbo Mode Rates. Keep in mind that higher Turbo
Mode Rates result in fewer available gain settings as shown
in Table II.
PROGRAMMABLE GAIN AMPLIFIER
The programmable gain amplifier gain setting is programmed
via the PGA Gain bits of the Command Register. Changes
in the gain setting (G) of the programmable gain amplifier
results in an increase in the input capacitor sampling frequency. Thus, higher gain settings result in a lower analog
input impedance:
AIN Impedance (Ω) = (10MHz/f
XIN
)•4.3E6/(G•TMR)
where TMR is the Turbo Mode Rate. Because the modulator
speed does not depend on the gain setting, the input impedance seen at REFIN does not change.
The PGA can be set to gains of 1, 2, 4, 8, or 16. These gain
settings with their resulting full-scale range and typical
voltage range are shown in Table I. Keep in mind that higher
Turbo Mode Rates result in fewer available gain settings as
shown in Table II.
SOFTWARE GAIN
The excellent performance, flexibility, and low cost of the
ADS1210/11 allow the converter to be considered for designs which would not normally need a 24-bit ADC. For
example, many designs utilize a 12-bit converter and a highgain INA or PGA for digitizing low amplitude signals. For
some of these cases, the ADS1210/11 by itself may be a
solution, even though the maximum gain is limited to 16.
To get around the gain limitation, the digital result can
simply be shifted up by “n” bits in the main controller—
resulting in a gain of “n” times G, where G is the gain
setting. While this type of manipulation of the output data
is obvious, it is easy to miss how much the gain can be
increased in this manner on a 24-bit converter.
For example, shifting the result up by three bits when the
ADS1210/11 is set to a gain of 16 results in an effective gain
of 128. At lower data rates, the converter can easily provide
more than 12 bits of resolution. Even higher gains are
possible. The limitation is a combination of the needed data
rate, desired noise performance, and desired linearity.
CALIBRATION
The ADS1210/11 offers several different types of calibration, and the particular calibration desired is programmed
via the Command Register. In the case of Background
Calibration, the calibration will repeat at regular intervals
indefinitely. For all others, the calibration is performed once
and then normal operation is resumed.
Each type of calibration is covered in detail in their respective section. In general, calibration is recommended immediately after power-on and whenever there is a “significant”
change in the operating environment. The amount of change
which should cause a re-calibration is dependent on the
application, effective resolution, etc. Where high accuracy is
important, re-calibration should be done on changes in
temperature and power supply. In all cases, re-calibration
should be done when the gain, Turbo Mode, or data rate is
changed.
After a calibration has been accomplished, the Offset Calibration Register and the Full-Scale Calibration Register
contain the results of the calibration. The data in these
registers are accurate to the effective resolution of the
ADS1210/11’s mode of operation during the calibration.
Thus, these values will show a variation (or noise) equivalent to a regular conversion result.
For those cases where this error must be reduced, it is
tempting to consider running the calibration at a slower data
rate and then increasing the converter’s data rate after the
calibration is complete. Unfortunately, this will not work as
expected. The reason is that the results calculated at the
slower data rate would not be valid for the higher data rate.
Instead, the calibration should be done repeatedly. After
each calibration, the results can be read and stored. After the
desired number of calibrations, the main controller can
compute an average and write this value into the calibration
registers. The resulting error in the calibration values will be
reduced by the square root of the number of calibrations
which were averaged.
The calibration registers can also be used to provide system
offset and gain corrections separate from those computed by
the ADS1210/11. For example, these might be burned into
E2PROM during final product testing. On power-on, the
main controller would load these values into the calibration
registers. A further possibility is a look-up table based on the
current temperature.
Note that the values in the calibration registers will vary from
configuration to configuration and from part to part. There is
no method of reliably computing what a particular calibration
register should be to correct for a given amount of system
error. It is possible to present the ADS1210/11 with a known
amount of error, perform a calibration, read the desired
calibration register, change the error value, perform another
calibration, read the new value and use these values to
interpolate an intermediate value.
Loading...