®
ADC76 2
SPECIFICATIONS
ELECTRICAL
At +25°C, and rated power supplies, unless otherwise noted.
ADC76J, K ADC76A, B
MODEL MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 16 * Bits
ANALOG INPUTS
Voltage Ranges: Bipolar ±2.5, ±5, ±10 * V
Unipolar 0 to +5, 0 to +10 * V
0 to +20 *
Impedance (Direct Input)
0 to +5V, ±2.5V 2.5 * kΩ
0 to +10V, ±5.0V 5 * kΩ
0 to +20V, ±10V 10 * kΩ
DIGITAL INPUTS
(1)
Convert Command Positive pulse 50ns wide (min) trailing edge (“1” to “0” initiates conversion)
Logic Loading 1 * TTL Load
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error
(2)
±0.1 ±0.2 * * %
Offset Error: Unipolar
(2)
±0.05 ±0.1 * * % of FSR
(3)
Bipolar
(2)
±0.1 ±0.2 * * % of FSR
Linearity Error:K, B ±0.003 * % of FSR
J, A ±0.006 * % of FSR
Inherent Quantization Error ±1/2 * LSB
Differential Linearity Error ±0.003 * % of FSR
Noise (3σ, p-p) ±0.001 ±0.003 * * % of FSR
POWER SUPPLY SENSITIVITY
±15VDC 0.003 * % of FSR/%V
S
+5VDC 0.001 * % of FSR/%V
S
CONVERSION TIME
(4)
14 Bits 15 * µs
15 Bits 16 * µs
16 Bits 17 * µs
WARM-UP TIME 5* Min
DRIFT
Gain ±15 * ppm/°C
Offset: Unipolar ±2 ±4 * * ppm of FSR/°C
Bipolar ±10 * ppm of FSR/°C
Linearity ±2 ±3 * * ppm of FSR/°C
No Missing Codes Temp Range
J, A (13-bit) 0 +70 –25 +85 °C
K, B (14-bit) 0 +70 –25 +85 °C
OUTPUT DIGITAL DATA
(All codes complementary)
Parallel
Output Codes
(5)
: Unipolar CSB *
Bipolar COB, CTC
(6)
*
Output Drive 2 * TTL Loads
Serial Data Code (NRZ) CSB, COB *
Output Drive 2 * TTL Loads
Status Logic “1” during conversion *
Status Output Drive 2 * TTL Loads
Internal Clock: Clock Output Drive 2 * TTL Loads
Frequency
(7)
933 1400 * * kHz
POWER SUPPLY REOUIREMENTS
Power Consumption 0.655 * W
Rated Voltage: Analog ±11.4 ±15 ±16***VDC
Digital +4.75 +5 +5.25 * * * VDC
Supply Drain: +15VDC +10 +15 * * mA
–15VDC –28 –35 * * mA
+5VDC +17 +20 * * mA
TEMPERATURE RANGE
Specification 0 +70 –25 +85 °C
Storage –55 +125 * * °C
*Specification same as ADC76J, K.
NOTES: (1) CMOS/TTL compatible, i.e., Logic “0” = 0.8V, max, Logic “1” = 2.0V, min for inputs. For digital outputs Logic “0” = 0.4V, max, Logic “1’ = 2.4V, min.
(2) Adjustable to zero. See “Optional External Gain and Offset Adjustment” section. (3) FSR means Full Scale Range. For example, unit connected for ±10V range
has 20V FSR. (4) Conversion time may be shortened with “Short Cycle” set for lower resolution and with use of Clock Rate Control. See “Optional Conversion Time
Adjustment” section. The Clock Rate Control (pin 23) should be connected to Digital Common for specified conversion time. Short Cycle (pin 32) should be left open
for 16-bit resolution or connected to the n + 1 digital output for n-bit resolution. For example, connect Short Cycle to Bit 15 (pin 15) for 14-bit resolution. For resolutions
less than 16 bits, pin 32 should also be tied to +5V through a 2kΩ resistor. (5) See Table I. CSB = Complementary Straight Binary, COB = Complementary Offset
Binary, CTC = Complementary Two’s Complement. (6) CTC coding obtained by inverting MSB (pin 1). (7) Adjustable with Clock Rate Control from approximately
933kHz to 1.4MHz.