BURR-BROWN OPA551, OPA552 User Manual

OPA551

O

P

A

5

5

O

P

A

5

5

1

1

SBOS100A – JULY 1999 – REVISED OCTOBER 2003

High-Voltage, High-Current

OPERATIONAL AMPLIFIERS

OPA551
OPA552

FEATURES

● WIDE SUPPLY RANGE: ±4V to ±30V

● HIGH OUTPUT CURRENT: 200mA Continuous

● LOW NOISE: 14nV/√Hz

● FULLY PROTECTED:

Thermal Shutdown
Output Current-Limited

● THERMAL SHUTDOWN INDICATOR

● WIDE OUTPUT SWING: 2V From Rail

● FAST SLEW RATE:

OPA551: 15V/µs
OPA552: 24V/µs

● WIDE BANDWIDTH:

OPA551: 3MHz
OPA552: 12MHz

● PACKAGES: DIP-8, SO-8, or DDPAK-7

APPLICATIONS

● TELEPHONY

● TEST EQUIPMENT

● AUDIO AMPLIFIERS

● TRANSDUCER EXCITATION

● SERVO DRIVERS

DESCRIPTION

The OPA551 and OPA552 are low cost op amps with high­voltage (60V) and high-current (200mA) capability.

The OPA551 is unity-gain stable and features high slew rate
(15Vµs) and wide bandwidth (3MHz). The OPA552 is
optimized for gains of 5 or greater, and offers higher speed
with a slew rate of 24V/µs and a bandwidth of 12MHz. Both
are suitable for telephony, audio, servo, and test applications.

These laser-trimmed, monolithic integrated circuits provide
excellent low-level accuracy along with high output swing.
High performance is maintained as the amplifier swings to
its specified limits.

The OPA551 and OPA552 are internally protected against
over-temperature conditions and current overloads. The
thermal shutdown indicator “flag” provides a current output
to alert the user when thermal shutdown has occurred.

The OPA551 and OPA552 are available in DIP-8 and
SO-8 packages, as well as a DDPAK-7 surface-mount
plastic power package. They are specified for operation
over the extended industrial temperature range, –40°C to
+125°C.

OPA551, OPA552

OPA551, OPA552

NC

1

–In

2

+In

3

V–

4

DIP-8 (P)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Flag

8

V+

7

Out

6

NC

5

V–
–In
+In

V–

OPA551, OPA552

1
2
3
4

SO-8 (U)

www.ti.com

Flag

8

V+

7

Out

6

V–

5

NOTE: Tab is
connected to
V– supply.

Copyright © 1999-2003, Texas Instruments Incorporated

1234

+In

–In

DDPAK-7 Surface-Mount (F)

NC

V–

6

7

5

V+

Flag

Out

SPECIFICATIONS: VS = ±30V

OPA551

At T

J

Boldface limits apply over the specified junction temperature range, T

PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE

Input Offset Voltage V

T
vs Temperature dVOS/dT ±7 µV/°C

vs Power Supply PSRR V

INPUT BIAS CURRENT

Input Bias Current I
Input Offset Current I

NOISE

Input Voltage Noise Density, f = 1kHz e
Current Noise Density, f = 1kHz i

INPUT VOLTAGE RANGE

Common-Mode Voltage Range V
Common-Mode Rejection Ratio CMRR –27.5V

INPUT IMPEDANCE

Differential 10
Common-Mode 10

OPEN-LOOP GAIN

Open-Loop Voltage Gain A

T

FREQUENCY RESPONSE

Gain-Bandwidth Product GBW 3 MHz
Slew Rate SR G = 1 ±15 V/µs
Settling Time: 0.1% G = 1, C

Total Harmonic Distortion + Noise, f = 1kHz THD+N
Overload Recovery Time V

OUTPUT

Voltage Output V

T

TJ = –40°C to +125°CI

Maximum Continuous Current Output: dc I
Short-Circuit Current I
Capacitive Load Drive C

SHUTDOWN FLAG

Thermal Shutdown Status Output

Normal Operation Sourcing 0.05 1 µA
Thermally Shutdown Sourcing 80 120 160 µA
Voltage Compliance Range V– (V+) – 1.5 V

Junction Temperature

Shutdown 160 °C
Reset from Shutdown 140 °C

POWER SUPPLY

Specified Voltage V
Operating Voltage Range ±4 ±30 V
Quiescent Current I

T

TEMPERATURE RANGE

Specified Range T
Operating Range T
Storage Range T
Thermal Resistance

SO-8 Surface Mount
DIP-8
DDPak-7
DDPak-7

NOTES: (1) All tests are high-speed tested at +25°C ambient temperature. Effective junction temperature is +25°C unless otherwise noted.

(1)

= +25°C

, RL = 3kΩ connected to ground and V

= 0V, unless otherwise noted.

OUT

= –40°C to +125°C.

J

OPA551UA, PA, FA

= –40°C to +125°C ±5 mV

J

= –40°C to +125°CR

J

OS

B

OS

n
n

CM

OL

0.01% G = 1, C

VCM = 0V, IO = 0 ±1 ±3mV

= ±4V to ±30V, VCM = 0V 10 30 µV/V

S

±20 ±100 pA

±3 ±100 pA

14 nV/√Hz

3.5 fA/√Hz

(V–) + 2.5 (V+) – 2.5 V

< VCM < +27.5V 92 102 dB

13

|| 2 Ω || pF

13

|| 6 Ω || pF

RL = 3kΩ, –28V < VO < +28V 110 126 dB

= 3kΩ, –28V < VO < +28V 100 dB

L

R

= 300Ω, –27V < VO < +27V 120 dB

L

= 100pF, 10V Step 1.3 µs

L

= 100pF, 10V Step 2 µs

VO = 15Vr ms, RL = 3kΩ, G = 3 0.0005 %

L

VO = 15Vrms, RL = 300Ω, G = 3 0.0005 %

• Gain = V

IN

= –40°C to +125°CI

J

= –40°C to +125°C ±10 mA

J

OUT

Package Dependent—See Text ±200 mA

O

SC

LOAD

S

Q

J
J

A

θ

JA

θ

JA

θ

JA

θ

JC

IO = 200mA (V–) + 3.0 (V+) – 3.0 V

= 200mA (V–) + 3.5 (V+) – 3.5 V

O

I

= 10mA (V–) + 2.0 (V+) – 2.0 V

O

= 10mA (V–) + 2.5 (V+) – 2.7 V

O

Stable Operation See Typical Curve

IO = 0 ±7 ±8.5 mA

S

–40 +125 °C
–55 +125 °C
–65 +150 °C

1 µs

±380 mA

±30 V

90 °C/W

100 °C/W

65 °C/W

3 °C/W

2

www.ti.com

OPA551, OPA552

SBOS100A

SPECIFICATIONS: VS = ±30V

OPA552

At T

J

Boldface limits apply over the specified junciton temperature range, T

PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE

Input Offset Voltage V

T
vs Temperature dV

vs Power Supply PSRR V

INPUT BIAS CURRENT

Input Bias Current I
Input Offset Current I

NOISE

Input Voltage Noise Density, f = 1kHz e
Current Noise Density, f = 1kHz i

INPUT VOLTAGE RANGE

Common-Mode Voltage Range V
Common-Mode Rejection Ratio CMRR –27.5V

INPUT IMPEDANCE

Differential 1013 || 2 Ω || pF
Common-Mode 10

OPEN-LOOP GAIN

Open-Loop Voltage Gain A

T

FREQUENCY RESPONSE

Gain-Bandwidth Product GBW 12 MHz
Slew Rate SR G = 5 ±24 V/µs
Settling Time: 0.1% G = 5, C

Total Harmonic Distortion + Noise, f = 1kHz THD+N

Overload Recovery Time V

OUTPUT

Voltage Output V

T

T

Maximum Continuous Current Output: dc I
Short-Circuit Current I
Capacitive Load Drive C

SHUTDOWN FLAG

Thermal Shutdown Status Output

Normal Operation Sourcing 0.05 1 µA
Thermally Shutdown Sourcing 80 120 160 µA
Voltage Compliance Range V– (V+) – 1.5 V

Junction Temperature

Shutdown 160 °C
Reset from Shutdown 140 °C

POWER SUPPLY

Specified Voltage V
Operating Voltage Range ±4 ±30 V
Quiescent Current I

T

TEMPERATURE RANGE

Specified Range T
Operating Range T
Storage Range T
Thermal Resistance

SO-8 Surface Mount
DIP-8
DDPak-7
DDPak-7

NOTES: (1) All tests are high-speed tested at +25°C ambient temperature. Effective junction temperature is +25°C unless otherwise noted.

(1)

= +25°C

, RL = 3kΩ connected to Ground and V

= 0V, unless otherwise noted.

OUT

= –40°C to +125°C.

J

OPA552UA, PA, FA

= –40°C to +125°C ±5 mV

J

= –40°C to +125°CR

J

OS

/dT ±7 µV/°C

OS

B

OS

n
n

CM

OL

0.01% G = 5, C

= –40°C to +125°CI

J

= –40°C to +125°CI

J

= –40°C to +125°C ±10 mA

J

OUT

LOAD

θ
θ
θ

θ

O

SC

S

Q

J
J

A

JA
JA
JA

JC

VCM = 0V, IO = 0 ±1 ±3mV

= ±4V to ±30V, VCM = 0V 10 30 µV/V

S

±20 ±100 pA

±3 ±100 pA

14 nV/√Hz

3.5 fA/√Hz

(V–) + 2.5 (V+) – 2.5 V

< VCM < +27.5V 92 102 dB

13

|| 6 Ω || pF

RL = 3kΩ, –28V < VO < +28V 110 126 dB

= 3kΩ, –28V < VO < +28V 100 dB

L

RL = 300Ω, –27V < VO < +27V 120 dB

= 100pF, 10V Step 2.2 µs

L

= 100pF, 10V Step 3 µs

VO = 15Vr ms, RL = 3kΩ, G = 5 0.0005 %

V

L

= 15Vrms, RL = 300Ω, G = 5 0.0005 %

O

• Gain = V

IN

S

1 µs

IO = 200mA (V–) + 3.0 (V+) – 3.0 V

= 200mA (V–) + 3.5 (V+) – 3.5 V

O

IO = 10mA (V–) + 2.0 (V+) – 2.0 V

= 10mA (V–) + 2.5 (V+) – 2.7 V

Package Dependent—See Text ±200 mA

O

±380 mA

Stable Operation See Typical Curve

±30 V

IO = 0 ±7 ±8.5 mA

–40 +125 °C
–55 +125 °C
–65 +150 °C

90 °C/W

100 °C/W

65 °C/W

3 °C/W

OPA551, OPA552

SBOS100A

www.ti.com

3

ABSOLUTE MAXIMUM RATINGS

Output Current ................................................................. See SOA Curve

Supply Voltage, V+ to V– ................................................................... 60V

Input Voltage Range ....................................... (V–) – 0.5V to (V+) + 0.5V

Operating Temperature ..................................................–55°C to +125°C

Storage Temperature ..................................................... –65°C to +150°C

Junction Temperature .................................................................... +150°C

Lead Temperature (soldering 10s, DIP-8) ...................................... 300°C

(soldering 3s, SO-8 and DDPAK) .................... 240°C

ESD Capability (Human Body Model) ............................................. 3000V

NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.

(1)

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada­tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.

PACKAGE/ORDERING INFORMATION

For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet.

4

www.ti.com

OPA551, OPA552

SBOS100A

TYPICAL PERFORMANCE CURVES

120

100

80

60

40

20

0

1 10 100 1k 10k 100k 1M 10M

Frequency (Hz)

PSRR (dB)

POWER SUPPLY REJECTION RATIO vs FREQUENCY

–PSRR

+PSRR

0.1

0.01

0.001

0.0001

TOTAL HARMONIC DISTORTION + NOISE

vs FREQUENCY

Frequency (Hz)

1 100 1k 10k 100k

THD+N (%)

VO = 15Vrms
R

L

= 3kΩ, 300Ω
G = 3 (OPA551)
G = 5 (OPA552)

At T

= +25°C, VS = ±30V and RL = 3kΩ, unless otherwise noted.

J

All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

OPEN-LOOP GAIN AND PHASE vs FREQUENCY

140
120
100

80
60
40

Gain (dB)

20

0

–20
–40

1 10 100 1k 10k 100k 1M 10M

COMMON-MODE REJECTION RATIO vs FREQUENCY

120

100

80

60

CMRR (dB)

40

Gain

OPA551

Phase

Frequency (Hz)

OPA551

0

–20
–40
–60
–80
–100
–120
–140
–160
–180

OPEN-LOOP GAIN AND PHASE vs FREQUENCY

140
120
100

80
60
40

Gain (dB)

Phase (°)

20

0

–20
–40

1 10 100 1k 10k 100k 1M 10M

OPA552

Gain

Frequency (Hz)

OPA552

Phase

0

–20
–40
–60
–80
–100
–120
–140
–160
–180

Phase (°)

20

0

1 10 100 1k 10k 100k 1M 10M

INPUT VOLTAGE AND CURRENT NOISE

10k

1k

100

10

Current Noise (fA/√Hz)

Voltage Noise (nV/√Hz)

1

10 100 1k 10k 100k 1M

SPECTRAL DENSITY vs FREQUENCY

Frequency (Hz)

Frequency (Hz)

i

n

e

n

OPA551, OPA552

SBOS100A

www.ti.com

5

TYPICAL PERFORMANCE CURVES (Cont.)

At T

= +25°C, VS = ±30V and RL = 3kΩ, unless otherwise noted.

J

All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

MAXIMUM OUTPUT VOLTAGE SWING

vs FREQUENCY

±30

±25

±20

OPA552

±15

±10

Maximum Output Voltage (V)

±5

Without Slew-Induced

OPA551

Distortion

0

1 10 100 1k 10k 100k 1M 10M

Frequency (Hz)

OPEN-LOOP GAIN, POWER SUPPLY REJECTION RATIO,

AND COMMON-MODE REJECTION RATIO

vs TEMPERATURE

130
125
120

A

OL

115
110
105

Gain (dB)

100

PSRR

CMRR

95
90
85
80

–75 –25 25 75 125

Ambient Temperature (°C)

(V+)

(V+)–1

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT

+85°C

(V+)–2

(V+)–3
(V–)+3

–55°C

–55°C

(V–)+2

Output Voltage Swing (V)

(V–)+1

(V–)

0 50 100 150 200 250 300 350 400

INPUT BIAS CURRENT AND INPUT OFFSET CURRENT

100k

10k

1k

100

Current (pA)

10

1

–75 0–25–50 25 50 75 100 125

+25°C

+25°C

+85°C

Output Current (mA)

vs TEMPERATURE

+I

B

Ambient Temperature (°C)

–I

B

–I

OS

QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT

vs TEMPERATURE

9
8
7
6
5

(mA)

Q

4

I

3
2
1
0

I

Q

–I

SC

+I

SC

450
430
410
390
370
350
330
310
290
270

(mA)

SC

I

Gain Bandwidth Product (MHz)

–75 –50 –25 0 25 50 75 100 125 150

Temperature (°C)

6

www.ti.com

GAIN BANDWIDTH PRODUCT vs TEMPERATURE

100

OPA552

10

OPA551

1

–80 –60 –40 –20 0 20 40 60 80 100 120 140

Temperature (°C)

OPA551, OPA552

SBOS100A

TYPICAL PERFORMANCE CURVES (Cont.)

30

25

20

15

10

5

0

–5

–30 –20 –10 0 10 20 30

Common-Mode Voltage (V)

Current (pA)

INPUT BIAS CURRENT AND INPUT OFFSET CURRENT

vs COMMON-MODE VOLTAGE

+I

B

–I

B

I

OS

OFFSET VOLTAGE

PRODUCTION DISTRIBUTION

Percent of Amplifiers (%)

Offset Voltage (mV)

< –3.0

< –2.4

< –1.8

< –1.2

< –0.6

< 0.0

< 0.6

< 1.2

< 1.8

< 2.4

< 3.0

18

15

12

9

6

3

0

Typical production
distribution of
packaged units.

At T

= +25°C, VS = ±30V and RL = 3kΩ, unless otherwise noted.

J

All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

35

30

25

20

15

Slew Rate (V/µs)

10

5

0

–60 –40 –20 0 20 40 60 80 100 120 140

QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT

7.6

7.2

6.8

SLEW RATE vs TEMPERATURE

OPA552

OPA551

Junction Temperature (°C)

vs SUPPLY VOLTAGE

–I

SC

I

Q

405

395

385

6.4

Quiescent Current (mA)

6.0
0 5 10 15 20 25 30 35

Supply Voltage (V)

OFFSET VOLTAGE DRIFT

18
16
14
12
10

8
6
4

Percent of Amplifiers (%)

2
0

< 0.0

OPA551, OPA552

SBOS100A

PRODUCTION DISTRIBUTION

< 1.5

< 3.0

< 4.50

Offset Drift µV/°C

< 6.0

< 7.5

+I

SC

Typical production
distribution of
packaged units.

< 9.0

< 10.5

< 12.0

< 13.5

375

365

< 15.0

www.ti.com

Short-Circuit Current (mA)

SETTLING TIME vs CLOSED-LOOP GAIN

100

10

Settling Time (µs)

1

1 10 100

OPA551

0.01%

OPA551

0.1%

OPA552

0.01%

OPA552

0.1%

Gain (V/V)

7

TYPICAL PERFORMANCE CURVES (Cont.)

At T

= +25°C, VS = ±30V and RL = 3Ω, unless otherwise noted.

J

All temperatures are junction temperatures unless otherwise noted. Refer to the Applications Information section to calculate junction temperatures from ambient
temperatures for a specific configuration.

SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE

60

OPA552

50

40

30

Overshoot (%)

20

10

0

0.01 10.1 10

G = –4

OPA552

G = –6

OPA552, G = –8

Load Capacitance (nF)

LARGE-SIGNAL STEP RESPONSE

OPA552, G = 5, C

L

OPA551, G = 1

OPA551

G = –1

OPA551

G = –2

= 100pF

OPA552

5V/div

LARGE-SIGNAL STEP RESPONSE

OPA551, G = 1, C

Time (1µs/div)

SMALL-SIGNAL STEP RESPONSE

OPA551, G = 1, C

= 100pF

L

= 100pF

L

OPA551

OPA551

5V/div

100mV/div

Time (1µs/div)

SMALL-SIGNAL STEP RESPONSE

OPA552, G = 5, C

Time (1µs/div)

= 100pF

L

OPA552

25mV/div

5V/div

Time (1µs/div)

SMALL-SIGNAL STEP RESPONSE

OPA551, G = –1, C

Time (1µs/div)

= 1000pF

L

OPA551

8

www.ti.com

OPA551, OPA552

SBOS100A

APPLICATIONS INFORMATION

Figure 1 shows the OPA551 connected as a basic non­inverting amplifier. The OPA551 can be used in virtually
any op amp configuration. OPA552 is designed for use in
configurations with gains of 5 or greater. Power supply
terminals should be bypassed with 0.1µF capacitors, or
greater, near the power supply pins. Be sure that the capaci­tors are appropriately rated for the power supply voltage
used. The OPA551 and OPA552 can supply output currents
up to 200mA with excellent performance.

V+

10µF

+

0.1µF

R

1

OPA551

V

IN

0.1µF

10µF

R

G = 1+

R

R

2

Flag

(optional)

+

2
1

V

O

Z

L

CURRENT LIMIT

The OPA551 and OPA552 are designed with internal cur­rent-limiting circuitry that limits the output current to ap­proximately 380mA. The current limit varies with increasing
junction temperature as shown in the typical curve “Current
Limit vs Temperature.” This, in combination with the ther­mal protection circuitry, provides protection from many
types of overload conditions including short circuit to ground.

THERMAL PROTECTION

The OPA551 and OPA552 have thermal shutdown circuitry
that protects the amplifier from damage caused by overload
conditions. The thermal protection circuitry disables the
output when the junction temperature reaches approximately
160°C, allowing the device to cool. When the junction
temperature cools to approximately 140°C, the output cir-
cuitry is automatically re-enabled.

The thermal shutdown function is not intended to replace
proper heat sinking. Activation of the thermal shutdown
circuitry is an indication of excessive power dissipation or
an inadequate heat sink. Continuously running the amplifier
into thermal shutdown can degrade reliability.

The Thermal Shutdown Indicator (“flag”) pin can be moni­tored to determine if shutdown is occurring. During normal
operation, the current output from the flag pin is typically
50nA. During shutdown, the current output from the flag pin
increases to 120µA (typical). This current output allows for
easy interfacing to external logic. See Figure 2 for two
examples implementing this function.

V–

FIGURE 1. Basic Circuit Connections.

OPA551

HCT logic has relatively well­controlled logic level. A properly
chosen resistor value can
guarantee proper logic high level
throughout the full range of flag
output current.

Interfacing with HCT Logic

FIGURE 2. Thermal Shutdown Indicator.

Flag
80µA to

160µA

27kΩ

Logic

Ground

V

OUT

+5V

HCT

Interface to virtually any CMOS
logic gate by choosing resistor
value that provides a guaranteed
logic high voltage with the
minimum (80µA) flag current. A
diode clamp to the logic supply
voltage assures that the CMOS
is not damaged by overdrive.

Interfacing with CMOS Logic

OPA551

V

OUT

HP5082-2835

47kΩ

Logic

Ground

V

LOGIC

CMOS

OPA551, OPA552

SBOS100A

www.ti.com

9

POWER SUPPLIES

The OPA551 and OPA552 may be operated from power
supplies of ±4V to ±30V, or a total of 60V with excellent
performance. Most behavior remains unchanged throughout
the full operating voltage range. Parameters that vary sig­nificantly with operating voltage are shown in the Typical
Performance Curves.

For applications that do not require symmetrical output
voltage swing, power supply voltages do not need to be
equal. The OPA551 and OPA552 can operate with as little
as 8V between the supplies or with up to 60V between the
supplies. For example, the positive supply could be set to
50V with the negative supply at –10V or vice-versa.

The SO-8 package outline shows three negative supply (V–)
pins. These pins are internally connected for improved thermal
performance. Pin 4 is to be used as the primary current

carrier for the negative supply. It is recommended that
pins 1 and 5 not be directly connected to V– but, instead
be connected to a thermal mass. DO NOT lay out the PC
board to use pins 1 and 5 as feedthroughs to the negative
supply. Doing so can result in a reduction of performance.

The tab of the DDPAK-7 package is electrically connected
to the negative supply (V–), however, this connection should
not be used to carry current. For best thermal performance,
the tab should be soldered directly to the circuit board
copper area (see heat sink text).

POWER DISSIPATION

Internal power dissipation of these op amps can be quite
large. Many of the specifications for the OPA551 and
OPA552 are for a specified junction temperature. If the
device is not subjected to internal self-heating, the junction
temperature will be the same as the ambient. However, in
practical applications, the device will self-heat and the junc­tion temperature will be significantly higher than ambient.
After junction temperature has been established, perfor­mance parameters that vary with junction temperature can be
determined from the performance curves. The following
calculation can be performed to establish junction tempera­ture as a function of ambient temperature and the conditions
of the application.

Consider the OPA551 in a circuit configuration where the
load is 600Ω and the output voltage is 15V. The supplies are
at ±30V and the ambient temperature (TA) is 40°C. The

θ

for the 8-pin DIP package is 100°C/W.
First, the internal heating of the op amp is as follows:
P

D(internal)

= IQ • VS = 7.2mA • 60V = 432mW

The output current (IO) can be calculated:

IO = V

= 15V / 600Ω = 25mA

OUT/RL

The power being dissipated (PD) in the output transistor of
the amplifier can be calculated:

P

D(output stage)

P

D(total)

= IO • (VS – VO) = 25mA • (30 – 15) = 375mW

= P

D(internal)

+ P

D(output stage)

= 432mW + 375mW = 807mW

The resulting junction temperature can be calculated:

TJ = TA + PD

θ

JA

TJ = 40°C + 807mW • 100°C/W = 120.7°C

Where,

TJ = junction temperature (°C)
TA = ambient temperature (°C)

θ

= junction-to-air thermal resistance (°C/W)

JA

For the DDPAK package, the

θ

is 65°C/W with no heat

JA

sinking, resulting in a junction temperature of 92.5°C.
To estimate the margin of safety in a complete design

(including heat sink), increase the ambient temperature until
the thermal protection is activated. Use worst-case load and
signal conditions. For good reliability, the thermal protec­tion should trigger more than +35°C above the maximum
expected ambient condition of your application. This en­sures a maximum junction temperature of +125°C at the
maximum expected ambient condition.

If the OPA551 or OPA552 is to be used in an application
requiring more than 0.5W continuous power dissipation, it
is recommended that the DDPAK package option be used.
The DDPAK has superior thermal dissipation characteris­tics and is more easily adapted to a heat sink.

Operation from a single power supply (or unbalanced power
supplies) can produce even larger power dissipation since a
larger voltage can be impressed across the conducting output
transistor. Consult Application Bulletin AB-039 for further
information on how to calculate or measure power dissipation.

Power dissipation can be minimized by using the lowest
possible supply voltage. For example, with a 200mA load,
the output will swing to within 3.5V of the power supply
rails. Power supplies set to no more than 3.5V above the
maximum output voltage swing required by the application
will minimize the power dissipation.

SAFE OPERATING AREA

The Safe Operating Area (SOA curves, Figures 3, 4, and 5)

JA

shows the permissible range of voltage and current. The
curves shown represent devices soldered to a circuit board
with no heat sink. The safe output current decreases as the
voltage across the output transistor (VS – VO) increases. For
further insight on SOA, consult Application Bulletin AB-039.

Output short circuits are a very demanding case for SOA.
A short circuit to ground forces the full power supply
voltage (V+ or V–) across the conducting transistor and
produces a typical output current of 380mA. With ±30V

10

www.ti.com

OPA551, OPA552

SBOS100A

power supplies, this creates an internal dissipation of 11.4W.

THERMAL RESISTANCE vs

CIRCUIT BOARD COPPER AREA

50

40

30

20

10

0

012345

Copper Area (inches

2

)

OPA551, OPA552

Surface-Mount Package

1oz. copper

Circuit Board Copper Area

OPA551, OPA552

Surface-Mount Package

Thermal Resistance,

JA

(°C/W)

θ

This far exceeds the maximum rating and is not recom­mended. If operation in this region is unavoidable, use the
DDPAK with a heat sink.

1000

100

10

(mA)

O

I

1

0.1
1 10 100

SAFE OPERATING AREA—8-PIN DIP

125°C

85°C

| – | VO | (V)

| V

S

25°C

FIGURE 3. DIP-8 Safe Operating Area.

1000

100

SAFE OPERATING AREA—SO-8

25°C

HEAT SINKING

Power dissipated in the OPA551 or OPA552 will cause the
junction temperature to rise. For reliable operation, the
junction temperature should be limited to +125°C. Many
applications will require a heat sink to assure that the
maximum operating junction temperature is not exceeded.
The heat sink required depends on the power dissipated and
on ambient conditions.

For heat sinking purposes, the tab of the DDPAK is typically
soldered directly to a circuit board copper area. Increasing
the copper area improves heat dissipation. Figure 6 shows
typical thermal resistance from junction-to-ambient as a
function of copper area.

Depending on conditions, additional heat sinking may be
required. Aavid Thermal Products Inc. manufactures sur­face-mountable heat sinks designed specifically for use with
DDPAK packages. Further information is available on
Aavid’s web site, www.aavid.com.

To estimate the margin of safety in a complete design
(including heat sink), increase the ambient temperature until
the thermal protection is activated. Use worst-case load and
signal conditions. For good reliability, the thermal protec­tion should trigger more than +25°C above the maximum
expected ambient condition of your application. This pro­duces a junction temperature of +125°C at the maximum
expected ambient condition.

125°C

10

(mA)

O

I

1

0.1

FIGURE 4. SO-8 Safe Operating Area.

1 10 100

| V

| – | VO | (V)

S

1000

100

10

(mA)

O

I

1

SAFE OPERATING AREA—DDPAK

125°C

125°C

1" Copper

85°C

25°C

85°C

25°C

1" Copper

0.1
1 10 100

| – | VO | (V)

| V

S

FIGURE 5. DDPAK-7 Safe Operating Area.

OPA551, OPA552

SBOS100A

FIGURE 6. DDPAK Thermal Resistance vs Circuit Board

www.ti.com

Copper Area.

11

CAPACITIVE LOADS

The dynamic characteristics of the OPA551 and OPA552
have been optimized for commonly encountered gains, loads,
and operating conditions. The combination of low closed­loop gain and capacitive load will decrease the phase margin
and may lead to gain peaking or oscillations. Figure 7 shows
a circuit that preserves phase margin with capacitive load.
Figure 8 shows the small-signal step response for the circuit
in Figure 7. Consult Application Bulletin AB-028 for more
information.

+30V

OPA551

R

G

V

4kΩ

I

C

1.8nF

S

–30V

R

F

4kΩ

C

F

220pF

10nF

FIGURE 7. Driving Large Capacitive Loads.

can be used to boost output current. The circuit in Figure 10
is capable of supplying output currents up to 1A. Alterna­tively, the OPA547, OPA548, and OPA549 series power op
amps should be considered for high output current drive,
along with programmable current limit and output disable
capability.

R

1

V

IN

NOTE: (1) RS resistors minimize the circulating
current that can flow between the two devices
due to V

errors.

OS

R

OPA551

OPA551

“SLAVE”

2

“MASTER”

R

10Ω

R

10Ω

(1)

S

(1)

S

R

L

SMALL-SIGNAL STEP RESPONSE

OPA551, G = –1, C

20mV/div

Time (2.5µs/div)

= 10nF

L

OPA551

FIGURE 8. Small-Signal Step Response for Figure 7.

INCREASING OUTPUT CURRENT

In those applications where the 200mA of output current is
not sufficient to drive the desired load, output current can be
increased by connecting two or more OPA551s or OPA552s
in parallel as shown in Figure 9. Amplifier A1 is the
“master” amplifier and may be configured in virtually an op
amp circuit. Amplifier A2, the “slave”, is configured as a
unity gain buffer. Alternatively, external output transistors

FIGURE 9. Parallel Amplifers Increase Output Current Ca-

pability.

R

1

V

IN

NOTE: (1) R
drive the load when the output is between 0.7V and –0.7V.

R

2

+30V

TIP29C

C

F

(1)

R

3

100Ω

OPA551

–30V

provides current limit and allows the amplifier to

3

R

0.2Ω

R

0.2Ω

TIP30C

4

4

LOAD

V

O

FIGURE 10. External Output Transistors Boost Output Cur-

rent Up to 1 Amp.

12

www.ti.com

OPA551, OPA552

SBOS100A

INPUT PROTECTION

R

F

1kΩ

C

S

1.88nF

NG

1

= 1 + R

F

/RG = 2

NG

2

= 1 + C

S

/CF = 10

OPA552

+30V

–30V

V

IN

V

OUT

C

F

208pF

R

G

1kΩ

The OPA551 and OPA552 feature internal clamp diodes
to protect the inputs when voltages beyond the supply rails
are encountered. However, input current should be limited
to 5mA. In some cases, an external series resistor may be
required. Many input signals are inherently current-limtied,
therefore, a limiting resistor may not be required. Please
consider that a “large” series resistor, in conjunction with
the input capacitance, can affect stability.

USING THE OPA552 IN LOW GAINS

The OPA552 family is intended for applications with
signal gains of 5 or greater, but it is possible to take
advantage of their high slew rate in lower gains using an
external compensation technique in an inverting configu­ration. This technique maintains low noise characteristics
of the OPA552 architecture at low frequencies. Depending
on the application, a small increase in high frequency
noise may result. This technique shapes the loop gain for
good stability while giving an easily controlled second­order low-pass frequency response.

Considering only the noise gain (non-inverting signal
gain) for the circuit of Figure 11, the low frequency noise
gain (NG

) will be set by the resistor ratios, while the high

1

frequency noise gain (NG2) will be set by the capacitor
ratios. The capacitor values set both the transition fre­quencies and the high frequency noise gain. If this noise
gain, determined by NG2 = 1 + CS/CF, is set to a value
greater than the recommended minimum stable gain for
the op amp and the noise gain pole, set by 1/RFCF, is
placed correctly, a very well controlled, 2nd-order low­pass frequency response will result.

To choose the values for both CS and CF, two parameters
and only three equations need to be solved. First, the
target for the high frequency noise gain (NG2) should be
greater than the minimum stable gain for the OPA552. In
the circuit in Figure 11, a target NG2 of 10 is used.
Second, the signal gain of –1 shown in Figure 11 sets the
low frequency noise gain to NG1 = 1 + RF/RG (=2 in this
example). Using these two gains, knowing the Gain Band­width Product (GBP) for the OPA552 (12MHz), and
targeting a maximally flat 2nd-order, low-pass Butterworth
frequency response (Q = 0.707), the key frequency in the
compensation can be found.

For the values shown in Figure 11, the f

–3dB

will be
approximately 956kHz. This is less than that predicted by
simply dividing the GBP by NG1. The compensation
network controls the bandwidth to a lower value while

providing the full slew rate at the output and an excep­tional distortion performance due to increased loop gain at
frequencies below NG

• Z0. The capacitor values shown

1

in Figure 11 are calculated for NG1 = 2 and NG2 = 10 with
no adjustment for parasitics.

Actual circuit values can be optimized by check the
small-signal step response with actual load conditions.
Figure 12 shows the small-signal step response of this
OPA552, G = –1 circuit with a 500pF load. It is well­behaved with no tendency to oscillate. If C

and CF were

S

removed, the circuit would be unstable.

FIGURE 11. Compensation of the OPA552 for G = 1.

SMALL-SIGNAL STEP RESPONSE

OPA552, G = –1, C

20mV/div

Time (1µs/div)

= 500pF

L

OPA552

FIGURE 12. Small-Signal Step Response for Figure 11.

OPA551, OPA552

SBOS100A

www.ti.com

13

OFFSET VOLTAGE ERROR CALCULATION

The offset voltage (VOS) of the OPA51 and OPA552 is
specified with a ±30V power supply and the common­mode voltage centered between the supplies (VS/2 =
0V). Additional specifications for power supply rejec­tion and common-mode rejection are provided to allow
the user to easily calculate worst-case excepted offset
under the conditions of a given application.

Power Supply Rejection Ratio (PSRR) is specified in
µV/V. For the OPA551 and OPA552, worst-case PSRR
is 30µV/V, which means for each volt of change in total
power supply voltage, the offset may shift by up to
30µV/V. Common-Mode Rejection Ratio (CMRR) is
specified in dB, which can be converted to µV/V using
the following equation:

CMRR in (V/V) = 10

[(CMRR in dB)/–20]

(1)

For the OPA551 and OPA552, the worst-case CMRR at
±30mV supply over the full common-mode range is
96dB, or approxmately 15.8µV/V. This means that for
every volt of change in common-mode, the offset may
shift up to 15.8µV. These numbers can be used to

calculate excursions from the specified offset voltage
under different applications conditions. For example, a
common application might configure the amplifier with
a –48 single supply with –6V common-mode. This
configuration represents a 12V variation in power sup­ply: ±30V or 60V in the offset specification versus 48V
in the application. In addition, this configuration has an
18V variation in common-mode voltage: VS/2 = –24V is
the specification for these power supplies, but the com­mon-mode voltage is –6V in the application.

Calculation of the worst-case expected offset would be
as follows:

Worst-case VOS =(2)

maximum specified V

OS

+ (power supply variation • PSRR
+ (common-mode variation • CMRR)

V

= 5mV + (12V • 30µV/V) + (18V • 15.8µV/V)

OSwc

= ±5.64mV

14

www.ti.com

OPA551, OPA552

SBOS100A

PACKAGE OPTION ADDENDUM

www.ti.com

28-Nov-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

OPA551FA OBSOLETE DDPAK KTW 7 TBD Call TI Call TI

OPA551FA/500 ACTIVE DDPAK KTW 7 500 Green (RoHS &

no Sb/Br)

OPA551FA/500G3 ACTIVE DDPAK KTW 7 500 Green (RoHS &

no Sb/Br)

OPA551FAKTWT ACTIVE DDPAK KTW 7 50 Green (RoHS &

no Sb/Br)

OPA551FAKTWTG3 ACTIVE DDPAK KTW 7 50 Green (RoHS &

no Sb/Br)
OPA551PA ACTIVE PDIP P 8 50 TBD Call TI Level-NA-NA-NA
OPA551UA ACTIVE SOIC D 8 100 Pb-Free

OPA551UA/2K5 ACTIVE SOIC D 8 2500 Pb-Free

OPA551UA/2K5G4 ACTIVE SOIC D 8 2500 Pb-Free

OPA552FA NRND DDPAK KTW 7 49 TBD Call TI Call TI

OPA552FA/500 ACTIVE DDPAK KTW 7 500 Green (RoHS &

no Sb/Br)

OPA552FA/500G3 ACTIVE DDPAK KTW 7 500 Green (RoHS &

no Sb/Br)

OPA552FAKTWT ACTIVE DDPAK KTW 7 50 Green (RoHS &

no Sb/Br)

OPA552FAKTWTG3 ACTIVE DDPAK KTW 7 50 Green (RoHS &

no Sb/Br)
OPA552PA ACTIVE PDIP P 8 50 TBD Call TI Level-NA-NA-NA
OPA552UA ACTIVE SOIC D 8 100 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU SN Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU SN Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

CU NIPDAU Level-3-260C-168 HR

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

28-Nov-2005

Addendum-Page 2

MECHANICAL DATA

MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

4

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

0.125 (3,18) MIN

0.100 (2,54)

0.010 (0,25)

Seating Plane

M

0.325 (8,26)

0.300 (7,62)

0.015 (0,38)

Gage Plane

0.010 (0,25) NOM

0.430 (10,92)
MAX

4040082/D 05/98

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPSF015 – AUGUST 2001

KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT

0.0625 (1,587)

0.0585 (1,485)

H

0.605 (15,37)

0.595 (15,11)

H

0.370 (9,40)

0.330 (8,38)

C

C

0.410 (10,41)

0.385 (9,78)

0.303 (7,70)

0.297 (7,54)

0.050 (1,27)

0.034 (0,86)

F

0.022 (0,57)

0.010 (0,25)

–A–

0.055 (1,40)

0.045 (1,14)

A

0.012 (0,305)

0.000 (0,00)

0.019 (0,48)

0.017 (0,43)

0.026 (0,66)

C

0.014 (0,36)

B

A

M

M

C

M

0.006

–B–

0.104 (2,64)

0.096 (2,44)

0.064 (1,63)

0.056 (1,42)

0.187 (4,75)

0.179 (4,55)

H

0°~3°

0.304 (7,72)

0.296 (7,52)

0.300 (7,62)

0.252 (6,40)

0.183 (4,65)

0.170 (4,32)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Lead width and height dimensions apply to the

plated lead.

D. Leads are not allowed above the Datum B.

E. Stand–off height is measured from lead tip

with reference to Datum B.

F. Lead width dimension does not include dambar

protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.

G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception

of the dimensions indicated.

4201284/A 08/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Copyright  2005, Texas Instruments Incorporated