The ISO103 isolation amplifier provides both signal
and power across an isolation barrier. The ceramic
non-hermetic hybrid package with side-brazed pins
contains a transformer-coupled DC/DC converter and
a capacitor-coupled signal channel.
Extra power is available on the isolated input side for
external input conditioning circuitry. The converter is
protected from shorts to ground with an internal current limit, and the soft-start feature limits the initial
currents from the power source. Multiple-channel synchronization can be accomplished by applying a TTL
clock signal to paralleled Sync pins. The Enable con-
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trol is used to turn off transformer drive while keeping
the signal channel demodulator active. This feature
provides a convenient way to reduce quiescent current
for low power applications.
The wide barrier pin spacing and internal insulation
allow for the generous 1500Vrms continuous rating.
Reliability is assured by 100% barrier breakdown
testing that conforms to UL1244 test methods. Low
barrier capacitance minimizes AC leakage currents.
These specifications and built-in features make the
ISO103 easy to use, as well as providing for compact
PC board layouts.
Load RegulationBalanced Load0.3✻%/mA
Line Regulation1.12✻V/V
Output Voltage vs Temperature2.5✻mV/°C
Voltage Balance Error, ±V
Voltage Ripple (800kHz)No External Capacitors50✻mVp-p
✻ Specifications same as ISO103.
NOTE: (1) Conforms to UL1244 test methods. 100% tested at 1500Vrms for 1 minute. (2) If using external synchronization with a TTL-level clock, frequency should
be between 1.2MHz and 2MHz with a duty-cycle greater than 25%.
= ±15V, ±15mA output current unless otherwise noted.
CC2
(1)
to T
MIN
MAX
to T
MIN
MAX
2121VDC160✻dB
= –10V to 10V±0.026±0.075±0.018±0.050% FSR
O
V
= –5V to 5V±0.009✻±0.025%FSR
O
= ±10V to ±18V0.9✻mV/V
CC2
= 0 to ±50mA±0.3✻mV/mA
O
400Ω/4.7nF (See Figure 4)5✻mVp-p
CC2
= ±15mA+90/–4.5✻mA
O
I
= 0mA+60/–4.5✻mA
O
C
= 1µF3✻mAp-p
IN
100mA Single-Ended Loads10✻✻V
CC1
C
= 1µF5✻mVp-p
EXT
ISO103ISO103B
1500✻Vrms
2121✻VDC
12
|| 9✻Ω || pF
±15✻V
0.05✻%
(2)
1.6✻MHz
®
ISO103
2
ABSOLUTE MAXIMUM RATINGS
Supply Without Damage .................................................................... ±18V
V
, Sense Voltage............................................................................. ±50V
IN
Com 1 to Gnd 1 or Com 2 to Gnd 2 ..............................................±200mV
Enable, Sync........................................................................... 0V to +V
Continuous Isolation Voltage ..................................................... 1500Vrms
Junction Temperature ...................................................................... 150°C
Storage Temperature...................................................... –25°C to +125°C
Lead Temperature,10s .................................................................... 300°C
Output Short to Gnd 2 Duration ............................................... Continuous
±V
to Gnd 1 Duration .......................................................... Continuous
CC1
CC2
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PIN CONFIGURATION
1
+V
C
+V
2
CC1
3
–V
CC1
–V
4
CC1
Com 2
9
V
10
OUT
Sense
11
12
Gnd 2
*Operation requires this pin be grounded or driven with TTL levels.
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/ ) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “ISO103/2K5” will get a single 2500piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
(1)
RANGEMARKINGNUMBER
(2)
MEDIA
®
3
ISO103
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