BSS FDS355, FDScomplete 56007 User Manual



MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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DSP56007/D

DSP56007

SYMPHONY  AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

Motorola designed the Symphony  family of high-performance, programmable Digital Signal Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic, ATRAC, and Lucasfilm Home THX processing. Software for these applications is licensed by Motorola for integration into products like audio/video receivers, televisions, and automotive sound systems with such user-developed features as digital equalization and sound field processing. The DSP56007 is an MPU-style general purpose DSP, composed of an efficient 24-bit Digital Signal Processor core, program and data memories, various peripherals optimized for audio, and support circuitry. As illustrated in DSP is fed by program memory, two independent data RAMs and two data ROMs, a Serial Audio Interface (SAI), Serial Host Interface (SHI), External Memory Interface (EMI), dedicated I/O lines, on-chip Phase Lock Loop (PLL), and On-Chip Emulation (OnCE DSP56007 has significantly more on-chip memory than the DSP56004.

4 9 5 29

General

Purpose

Input/

Output

Serial Audio

Interface

(SAI)

Serial

Host

Interface

(SHI)

Figure 1 , the DSP56000 core family compatible

) port. The

16-Bit Bus 24-Bit Bus

External Memory

Interface

(EMI)

Program Memory*

X Data

Memory*

Y Data

Memory*

Program Address

PAB XAB YAB

Data ALU

24 × 24 + 56 → 56-Bit MAC

Two 56-Bit Accumulators

Refer to Table 1 for memory configurations.

AA0248

24-Bit

DSP56000

Core

Internal

Switch

OnCETM Port

Clock

PLL

Gen.

Data Bus

Address

Generation

Interrupt

Control

Program Control Unit

IRQA, IRQB, NMI, RESET

Unit

Program

Decode

Controller

GDB PDB XDB

YDB

Generator

Figure 1 DSP56007 Block Diagram

SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . .1-1

SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

SECTION 4 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

SECTION 5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

FOR TECHNICAL ASSISTANCE:

Telephone: 1-800-521-6274

Email: dsphelp@dsp.sps.mot.com

Internet: http://www.motorola-dsp.com

Data Sheet Conventions

his data sheet uses the following conventions:

OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is

active when low.)

“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal

is low

“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal

is high

Examples:

Signal/Symbol Logic State Signal State Voltage

PIN True Asserted VIL/V PIN False Deasserted VIH/V PIN True Asserted VIH/V

PIN False Deasserted VIL/V

Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

ii DSP56007/D MOTOROLA

FEATURES

Digital Signal Processing Core

• Efficient, object code compatible with the 24-bit DSP56000 core family engine

• Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at 88 MHz

• Highly parallel instruction set with unique DSP addressing modes

• Two 56-bit accumulators including extension byte

DSP56007

Features

Memory

• Parallel 24

• Double precision 48

• 56-bit addition/subtraction in 1 instruction cycle

• Fractional and integer arithmetic with support for multiprecision arithmetic

• Hardware support for block floating-point Fast Fourier Transforms (FFT)

• Hardware nested DO loops

• Zero-overhead fast interrupts (2 instruction cycles)

• Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories

• Fabricated in high-density CMOS

• On-chip modified Harvard architecture, which permits simultaneous accesses to program and two data memories

• Bootstrap loading from Serial Host Interface or External Memory Interface

24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)

48-bit multiply with 96-bit result in 6 instruction cycles

Table 1 Memory Configuration (Word width is 24 bits)

Mode Program X Data Y Data

PE ROM RAM ROM RAM ROM RAM

0 6400 None 512 1024 512 2176 52 1 5120 1024 512 1024 512 1152 52

Bootstrap

ROM

MOTOROLA DSP56007/D iii

DSP56007 Features

Peripheral and Support Circuits

• Serial Audio Interface (SAI) includes two receivers and three transmitters, master or slave capability, implementation of I protocols; and two sets of SAI interrupt vectors

• Serial Host Interface (SHI) features single master capability, 10-word receive FIFO, and support for 8-, 16-, and 24-bit words

• External Memory Interface (EMI), implemented as a peripheral supporting: – Page-mode DRAMs (one or two chips): 64 K

and 4 M – SRAMs (one to four): 256 K – Data bus may be 4 or 8 bits wide – Data words may be 8, 12, 16, 20, or 24 bits wide

• Four dedicated, independent, programmable General Purpose Input/Output (GPIO) lines

• On-chip peripheral registers memory mapped in data memory space

• Three external interrupt request pins

• On-Chip Emulation (OnCE) port for unobtrusive, processor speedindependent debugging

4 bits

8 bits

S, Sony, and Matsushita audio

4, 256 K × 4,

• Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer for the core clock

• Power-saving Wait and Stop modes

• Fully static, HCMOS design for operating frequencies down to DC

• 80-pin plastic Quad Flat Pack surface-mount package; 14 (2.15–2.45 mm range); 0.65 mm lead pitch

• Complete pinout compatibility between DSP56009, DSP56004, DSP56004ROM, and DSP56007 for easy upgrades

• 5 V power supply

14 × 2.20 mm

iv DSP56007/D MOTOROLA

Product Documentation

PRODUCT DOCUMENTATION

Table 2 lists the documents that provide a complete description of the DSP56007 and

are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information).

Table 2 DSP56007 Documentation

Document Name Description of Content Order Number

DSP56007

DSP56000 Family Manual

DSP56007 User’s Manual

DSP56007 Technical Data

DSP56000 core family architecture and the 24-bit core processor and instruction set

Memory, peripherals, and interfaces DSP56007UM/AD

Electrical and timing specifications, and pin and package descriptions

DSP56KFAMUM/AD

DSP56007/D

MOTOROLA DSP56007/D v

DSP56007 Product Documentation

vi DSP56007/D MOTOROLA

SECTION 1

SIGNAL/CONNECTION DESCRIPTIONS

SIGNAL GROUPINGS

The DSP56007 input and output signals are organized into the nine functional groups, as shown in

Table 1-1 DSP56007 Functional Group Signal Allocations

Functional Group Number of Signals Detailed Description

Table 1-1 . The individual signals are illustrated in Figure 1-1 .

Power (V Ground (GND) 13 Phase Lock Loop (PLL) 3 External Memory Interface (EMI) 29

Interrupt and Mode Control 4 Serial Host Interface (SHI) 5 Serial Audio Interface (SAI) 9

General Purpose Input/Output (GPIO) 4 On-Chip Emulation (OnCE) port 4

Total 80

Table 1-2 Table 1-3 Table 1-4

Table 1-5

Table 1-6 Table 1-7 Table 1-8

Table 1-9

Table 1-10 Table 1-11 Table 1-12

and

MOTOROLA DSP56007/D 1-1

Signal/Connection Descriptions Signal Groupings

Power Inputs

CCP

CCQ

CCA

CCD

CCS

Ground

GND

PCAP

PINIT

EXTAL

MA0–MA14

MD0–MD7

MA15/MCS3 MA16/MCS2/MCAS MA17/MCS1/MRAS

MCS0

MWR

MRD

DSP56007

3 2

Port B

Serial Host

Interface

Port C

MOSI/HA0 SS/HA2

MISO/SDA SCK/SCL HREQ

Serial Audio

Interface

WSR SCKR

PLL

Rec0 Rec1

SDI0 SDI1

WST

Tran0 Tran1

Tran2

SCKT SDO0 SDO1 SDO2

Port A

External Memory

Interface

GPIO

GPIO0–GPIO3

MODC/NMI

MODB/IRQB MODA/IRQA

RESET

Mode/Interrupt Control

Reset

80 signals

OnCE™

Port

DSCK/OS1 DSI/OS0 DSO DR

AA0249G

Figure 1-1 DSP56007 SIgnals

1-2 DSP56007/D MOTOROLA

POWER

Table 1-2 Power Inputs

Power Name Description

Signal/Connection Descriptions

Power

CCP

CCQ

CCA

CCD

CCS

GROUND

PLL Power —V

provides isolated power for the Phase Lock Loop (PLL). The

CCP

voltage should be well-regulated and the input should be provided with an extremely low impedance path to the V

Quiet Power —V

provides isolated power for the internal processing logic. This

CCQ

power rail.

input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

Address Bus Power —V

provides isolated power for sections of the address bus

CCA

I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

Data Bus Power —V

provides isolated power for sections of the data bus I/O

CCD

drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

Serial Interface Power—V

provides isolated power for the SHI and SAI. This

CCS

input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

Table 1-3 Grounds

Ground Name Description

GND

PLL Ground—GNDP is ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. V

should be

CCP

bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip package.

GND

Quiet Ground—GNDQ provides isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

GND

Address Bus Ground—GNDA provides isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

GND

Data Bus Ground—GNDD provides isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

GND

Serial Interface Ground—GNDS provides isolated ground for the SHI and SAI. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

MOTOROLA DSP56007/D 1-3

Signal/Connection Descriptions Clock and PLL signals

CLOCK AND PLL SIGNALS

Note: While the PLL on this DSP is identical to the PLL described in the

Family Manual

, two of the signals have not been implemented externally.

DSP56000

Specifically, there is no PLOCK signal or CKOUT signal available. Therefore, the internal clock is not directly accessible and there is no external indication that the PLL is locked. These signals were omitted to reduce the number of pins and allow this DSP to be put in a smaller, less expensive package.

Table 1-4 Clock and PLL Signals

Signal

Name

EXTAL Input Input External Clock/Crystal—This input should be connected to an

PCAP Input Input PLL Filter Capacitor—This input is used to connect a high-

Signal

Type

State

during

Reset

Signal Description

external clock source. If the PLL is enabled, this signal is internally connected to the on-chip PLL. The PLL can multiply the frequency on the EXTAL pin to generate the internal DSP clock. The PLL output is divided by two to produce a four-phase instruction cycle clock, with the minimum instruction time being two PLL output clock periods. If the PLL is disabled, EXTAL is divided by two to produce the four-phase instruction cycle clock.

quality (high “Q” factor) external capacitor needed for the PLL filter. The capacitor should be as close as possible to the DSP with heavy, short traces connecting one terminal of the capacitor to PCAP and the other terminal to V value is specified in Table 2-6 on page 2-6.

. The required capacitor

CCP

Note: When short lock time is critical, low dielectric absorption

capacitors such as polystyrene, polypropylene, or teflon are recommended.

If the PLL is not used (i.e., it remains disabled at all times), there is no need to connect a capacitor to the PCAP pin. It may remain unconnected, or be tied to either Vcc or GND.

PINIT Input Input PLL Initialization (PINIT)—During the assertion of hardware

reset, the value on the PINIT line is written into the PEN bit of the PCTL register. When set, the PEN bit enables the PLL by causing it to derive the internal clocks from the PLL voltage controlled oscillator output. When the bit is cleared, the PLL is disabled and the DSP’s internal clocks are derived from the clock connected to the EXTAL signal. After hardware RESET is deasserted, the PINIT signal is ignored.

1-4 DSP56007/D MOTOROLA

EXTERNAL MEMORY INTERFACE (EMI)

Table 1-5 External Memory Interface (EMI) Signals

Signal/Connection Descriptions

External Memory Interface (EMI)

Signal Name

MA0–MA14 Output Table 1-6 Memory Address Lines 0–14—The MA0–MA10 lines provide

MA15

MCS3

MA16

MCS2

MCAS

MA17

Signal

Type

Output Table 1-6 Memory Address Line 15 (MA15)—This line functions as the

Output Table 1-6 Memory Address Line 16 (MA16)—This line functions as the

Output Table 1-6 Memory Address Line 17 (MA17)—This line functions as the

State during

Reset

Signal Description

the multiplexed row/column addresses for DRAM accesses. Lines MA0–MA14 provide the non-multiplexed address lines 0–14 for SRAM accesses.

non-multiplexed address line 15.

Memory Chip Select 3 (MCS3)—For SRAM accesses, this line functions as memory chip select 3.

non-multiplexed address line 16 or as memory chip select 2 for SRAM accesses.

Memory Chip Select 2 (MCS2)—For SRAM access, this line functions as memory chip select 2.

Memory Column Address Strobe (MCAS)—This line functions as the Memory Column Address Strobe (MCAS) during DRAM accesses.

non-multiplexed address line 17.

MCS1

MRAS

MCS0 Output Table 1-6 Memory Chip Select 0—This line functions as memory chip

MWR Output Table 1-6 Memory Write Strobe—This line is asserted when writing to

MRD Output Table 1-6 Memory Read Strobe—This line is asserted when reading

Memory Chip Select 1 (MCS1)—This line functions as chip select 1 for SRAM accesses.

Memory Row Address Strobe (MRAS)—This line also functions as the Memory Row Address Strobe during DRAM accesses.

select 0 for SRAM accesses.

external memory.

MOTOROLA DSP56007/D 1-5

Signal/Connection Descriptions External Memory Interface (EMI)

Table 1-5 External Memory Interface (EMI) Signals (Continued)

Signal Name

Signal

Type

MD0–MD7 Bidi-

rectional

State during

Reset

Signal Description

Tri-stated Data Bus—These signals provide the bidirectional data bus for

EMI accesses. They are inputs during reads from external memory, outputs during writes to external memory, and tristated if no external access is taking place. If the data bus width is defined as four bits wide, only signals MD0–MD3 are active, while signals MD4–MD7 remain tri-stated. While tri-stated, MD0–MD7 are disconnected from the pins and do not require external pull-ups.

Table 1-6 EMI States during Reset and Stop States

Operating Mode

Signal

Hardware Reset Software Reset Individual Reset Stop Mode

MA0–MA14 Driven High Previous State Previous State Previous State MA15

MCS3 MA16

Driven High

Driven High Driven High

Driven High

Driven High Driven High

Previous State

Driven High

Previous State

Driven High

Previous State

MCS2

Driven High

MCAS: DRAM refresh disabled DRAM refresh enabled

MA17

MCS1

Driven High Driven High

Driven High

Driven High Driven High

Driven High

Driven Low

Previous State

Driven High

Driven High Driven High

Previous State

Driven High

MRAS:

DRAM refresh disabled

DRAM refresh enabled

Driven High Driven High

Driven High

Driven Low

Driven High Driven High

MCS0 Driven High Driven High Driven High Driven High MWR Driven High Driven High Driven High Driven High MRD Driven High Driven High Driven High Driven High

1-6 DSP56007/D MOTOROLA

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the DSP’s operating mode as it comes out of hardware reset and receives interrupt requests from external sources after reset.

Table 1-7 Interrupt and Mode Control Signals

Signal/Connection Descriptions

Interrupt and Mode Control

Signal Name

MODA

IRQA

Signal

Type

Input Input (MODA) Mode Select A—This input signal has three functions:

State during

Reset

Signal Description

• to work with the MODB and MODC signals to select the DSP’s initial operating mode,

• to allow an external device to request a DSP interrupt after internal synchronization, and

• to turn on the internal clock generator when the DSP is in the Stop processing state, causing the DSP to resume processing.

MODA is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODA signal changes to the external interrupt request IRQA. The DSP operating mode can be changed by software after reset.

External Interrupt Request A (IRQA)—The IRQA input is a synchronized external interrupt request. It may be programmed to be level-sensitive or negative-edgetriggered. When the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQA will generate multiple interrupts also increases.

While the DSP is in the Stop mode, asserting IRQA gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. Hardware reset causes this input to function as MODA.

MOTOROLA DSP56007/D 1-7

Signal/Connection Descriptions Interrupt and Mode Control

Table 1-7 Interrupt and Mode Control Signals (Continued)

Signal Name

MODB

IRQB

Signal

Type Input Input (MODB) Mode Select B—This input signal has two functions:

State during

Reset

Signal Description

• to work with the MODA and MODC signals to select the DSP’s initial operating mode, and

• to allow an external device to request a DSP interrupt after internal synchronization.

MODB is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODB signal changes to the external interrupt request IRQB software after reset.

External Interrupt Request B (IRQB)—The IRQB input is a synchronized external interrupt request. It may be programmed to be level-sensitive or negative-edgetriggered. When the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases. Hardware reset causes this input to function as MODB.

. The DSP operating mode can be changed by

1-8 DSP56007/D MOTOROLA

Signal/Connection Descriptions

Interrupt and Mode Control

Table 1-7 Interrupt and Mode Control Signals (Continued)

Signal Name

MODC

NMI

Signal

Type

Input,

edge-

triggered

State during

Reset

Input (MODC) Mode Select C—This input signal has two functions:

• to work with the MODA and MODB signals to select the DSP’s initial operating mode, and

• to allow an external device to request a DSP interrupt after internal synchronization.

MODC is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODC signal changes to the Non-Maskable Interrupt request, NMI changed by software after reset.

Non-Maskable Interrupt Request—The NMI input is a negative-edge-triggered external interrupt request. This is a level 3 interrupt that can not be masked out. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on NMI will generate multiple interrupts also increases. Hardware reset causes this input to function as MODC.

Signal Description

. The DSP operating mode can be

RESET input active RESET—This input causes a direct hardware reset of the

processor. When RESET is asserted, the DSP is initialized and placed in the Reset state. A Schmitt-trigger input is used for noise immunity. When the reset signal is deasserted, the initial DSP operating mode is latched from the MODA, MODB, and MODC signals. The DSP also samples the PINIT signal and writes its status into the PEN bit of the PLL Control Register. When the DSP comes out of the Reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal. However, the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal.

For proper hardware reset to occur, the clock must be active, since a number of clock ticks are required for proper propagation of the hardware Reset state.

MOTOROLA DSP56007/D 1-9

Signal/Connection Descriptions Serial Host Interface (SHI)

SERIAL HOST INTERFACE (SHI)

Signal Name

SCK

SCL

The Serial Host Interface (SHI) has five I/O signals, which may be configured to

operate in either SPI or I

C mode. Table 1-8 lists the SHI signals.

Table 1-8 Serial Host Interface (SHI) signals

Signal

Type

Input or

Output

Input or

Output

State

during

Reset

Tri-stated SPI Serial Clock (SCK)—The SCK signal is an output

when the SPI is configured as a master, and a Schmitttrigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the Slave Select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol.

I2C Serial Clock (SCL)—SCL carries the clock for bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave, and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. The maximum allowed internally generated bit clock frequency is I2C mode where F maximum allowed externally generated bit clock frequency is I2C mode. This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state).

Signal Description

Fosc

/4 for the SPI mode and

is the clock on EXTAL. The

osc

Fosc

/3 for the SPI mode and

Fosc

/6 for the

Fosc

/5 for the

1-10 DSP56007/D MOTOROLA

Signal/Connection Descriptions

Serial Host Interface (SHI)

Table 1-8 Serial Host Interface (SHI) signals (Continued)

Signal Name

MISO

SDA

Signal

Type

Input or

Output

Input or

Output

State

during

Signal Description

Reset

Tri-stated SPI Master-In-Slave-Out (MISO)—When the SPI is

configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS

is deasserted.

I2C Serial Data and Acknowledge (SDA)—In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of Start and Stop events. A high-to-low transition of the SDA line while SCL is high is an unique situation, and is defined as the Start event. A low-to-high transition of SDA while SCL is high is an unique situation, and is defined as the Stop event.

MOSI

HA0

Input or

Output

Input

Note: This line is tri-stated during hardware reset, software

reset, or individual reset (no need for external pull-up in this state).

Tri-stated SPI Master-Out-Slave-In (MOSI)—When the SPI is

configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode.

I2C Slave Address 0 (HA0)—This signal uses a Schmitttrigger input when configured for the I2C mode. When configured for I2C Slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when the SHI is configured for the I2C Master mode.

Note: This signal is tri-stated during hardware reset,

software reset, or individual reset (no need for external pull-up in this state).

MOTOROLA DSP56007/D 1-11

Signal/Connection Descriptions Serial Host Interface (SHI)

Table 1-8 Serial Host Interface (SHI) signals (Continued)

Signal Name

HA2

Signal

Type

Input

State

during

Reset

Tri-stated

Signal Description

SPI Slave Select (SS)—This signal is an active low

Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI Master mode, this signal should be kept deasserted. If it is asserted while configured as SPI master, a bus error condition will be flagged.

C Slave Address 2 (HA2)—This signal uses a

Schmitt-trigger input when configured for the I

mode. When configured for the I

C Slave mode, the

HA2 signal is used to form the slave device address.

HA2 is ignored in the I

C Master mode. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state.

Note: This signal is tri-stated during hardware reset,

software reset, or individual reset (no need for external pull-up in this state).

HREQ Input or

Output

Tri-stated Host Request—This signal is an active low Schmitt-

trigger input when configured for the Master mode, but an active low output when configured for the Slave mode. When configured for the Slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the Master mode, HREQ is an input and when asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer.

Note: This signal is tri-stated during hardware, software,

individual reset, or when the HREQ[1:0] bits (in the HCSR) are cleared (no need for external pull-up in this state).

1-12 DSP56007/D MOTOROLA

SERIAL AUDIO INTERFACE (SAI)

The SAI is composed of separate receiver and transmitter sections.

SAI Receiver Section

Table 1-9 Serial Audio Interface (SAI) Receiver signals

Signal/Connection Descriptions

Serial Audio Interface (SAI)

Signal

Name

SDI0 Input Tri-stated Serial Data Input 0—While in the high impedance

SDI1 Input Tri-stated Serial Data Input 1—While in the high impedance

SCKR Input or

Signal

Type

Output

State during

Reset

state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. SDI0 is the serial data input for receiver 0.

Note: This signal is high impedance during hardware or

software reset, while receiver 0 is disabled (R0EN = 0), or while the DSP is in the Stop state.

state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. SDI1 is the serial data input for receiver 1.

Note: This signal is high impedance during hardware or

software reset, while receiver 1 is disabled (R1EN = 0), or while the DSP is in the Stop state.

Tri-stated Receive Serial Clock—SCKR is an output if the

receiver section is programmed as a master, and a Schmitt-trigger input if programmed as a slave. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary.

Signal Description

Note: SCKR is high impedance if all receivers are

disabled (individual reset) and during hardware or software reset, or while the DSP is in the Stop state.

MOTOROLA DSP56007/D 1-13

Signal/Connection Descriptions Serial Audio Interface (SAI)

Table 1-9 Serial Audio Interface (SAI) Receiver signals (Continued)

Signal

Name

Signal

Type

WSR Input or

Output

State during

Reset

Signal Description

Tri-stated Word Select Receive (WSR)—WSR is an output if the

receiver section is configured as a master, and a Schmitt-trigger input if configured as a slave. WSR is used to synchronize the data word and to select the left/right portion of the data sample.

Note: WSR is high impedance if all receivers are disabled

(individual reset), during hardware reset, during software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the signal and no external pull-up is necessary.

1-14 DSP56007/D MOTOROLA

SAI Transmitter Section

Table 1-10 Serial Audio Interface (SAI) Transmitter signals

Signal/Connection Descriptions

Serial Audio Interface (SAI)

Signal

Name

Signal

Type

State

during

Reset

SDO0 Output Driven

High

SDO1 Output Driven

High

SDO2 Output Driven

High

SCKT Input or

Tri-stated Serial Clock Transmit (SCKT)—This signal provides the

Output

Signal Description

Serial Data Output 0 (SDO0)—SDO0 is the serial output for

transmitter 0. SDO0 is driven high if transmitter 0 is disabled, during individual reset, hardware reset, and software reset, or when the DSP is in the Stop state.

Serial Data Output 1 (SDO1)—SDO1 is the serial output for transmitter 1. SDO1 is driven high if transmitter 1 is disabled, during individual reset, hardware reset and software reset, or when the DSP is in the Stop state.

Serial Data Output 2 (SDO2)—SDO2 is the serial output for transmitter 2. SDO2 is driven high if transmitter 2 is disabled, during individual reset, hardware reset and software reset, or when the DSP is in the Stop state.

clock for the SAI. SCKT can be an output if the transmit section is configured as a master, or a Schmitt-trigger input if the transmit section is configured as a slave. When the SCKT is an output, it provides an internally generated SAI transmit clock to external circuitry. When the SCKT is an input, it allows external circuitry to clock data out of the SAI.

Note: SCKT is high impedance if all transmitters are disabled

(individual reset), during hardware reset, software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary.

WST Input or

Output

Tri-stated Word Select Transmit (WST)—WST is an output if the

transmit section is programmed as a master, and a Schmitttrigger input if it is programmed as a slave. WST is used to synchronize the data word and select the left/right portion of the data sample.

Note: WST is high impedance if all transmitters are disabled

(individual reset), during hardware or software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary.

MOTOROLA DSP56007/D 1-15

Signal/Connection Descriptions General Purpose I/O

GENERAL PURPOSE I/O

Table 1-11 General Purpose I/O (GPIO) Signals

Signal

Name

GPIO0– GPIO3

Signal

Type

Standard

Output,

Open-drain

Output, or

Input

State during

Reset

Disconnected GPIO lines can be used for control and handshake

ON-CHIP EMULATION (OnCE

There are four signals associated with the OnCE port controller and its serial interface.

Table 1-12 On-Chip Emulation Port Signals

Signal

Name

Signal

Type

State during

Reset

) PORT

Signal Description

functions between the DSP and external circuitry. Each GPIO line can be configured individually as disconnected, open-drain output, standard output, or an input.

Note: Hardware reset or software reset configures all

the GPIO lines as disconnected (external circuitry connected to these pins may need pullups until the pins are configured for operation).

Signal Description

DSI

OS0

Input

Output

Output,

Driven Low

Debug Serial Input (DSI)—The DSI signal is the signal through which serial data or commands are provided to the OnCE port controller. The data received on the DSI signal will be recognized only when the DSP has entered the Debug mode of operation. Data must have valid TTL logic levels before the serial clock falling edge. Data is always shifted into the OnCE port Most Significant Bit (MSB) first.

Operating Status 0 (OS0)—When the DSP is not in the Debug mode, the OS0 signal provides information about the DSP status if it is an output and used in conjunction with the OS1 signal. When switching from output to input, the signal is tri-stated.

Note: If the OnCE port is in use, an external pull-down resistor

should be attached to the DSI/OS0 signal. If the OnCE port is not in use, the resistor is not required.

1-16 DSP56007/D MOTOROLA

Signal/Connection Descriptions

On-Chip Emulation (OnCETM) Port

Table 1-12 On-Chip Emulation Port Signals (Continued)

Signal Name

DSCK

OS1

DSO Output Driven High Debug Serial Output (DSO)—The DSO line provides the

Signal

Type

Input

Output

State during

Reset

Output,

Driven Low

Debug Serial Clock (DSCK)—The DSCK/OS1 signal, when an input, is the signal through which the serial clock is supplied to the OnCE port. The serial clock provides pulses required to shift data into and out of the OnCE port. Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE port on the rising edge.

Operating Status 1 (OS1)—If the OS1 signal is an output and used in conjunction with the OS0 signal, it provides information about the DSP status when the DSP is not in the Debug mode. The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. The signal is tri-stated when it is changing from input to output.

Note: If the OnCE port is in use, an external pull-down resistor

data contained in one of the OnCE port controller registers as specified by the last command received from the command controller. The Most Significant Bit (MSB) of the data word is always shifted out of the OnCE port first. Data is clocked out of the OnCE port on the rising edge of DSCK.

Signal Description

should be attached to the DSCK/OS1 pin. If the OnCE port is not in use, the resistor is not required.

The DSO line also provides acknowledge pulses to the external command controller. When the DSP enters the Debug mode, the DSO line will be pulsed low to indicate that the OnCE port is waiting for commands. After receiving a read command, the DSO line will be pulsed low to indicate that the requested data is available and the OnCE port is ready to receive clock pulses in order to deliver the data. After receiving a write command, the DSO line will be pulsed low to indicate that the OnCE port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided.

Note: During hardware reset and when idle, the DSO line is

held high.

MOTOROLA DSP56007/D 1-17

Signal/Connection Descriptions On-Chip Emulation (OnCETM) Port

Table 1-12 On-Chip Emulation Port Signals (Continued)

Signal

Name

DR Input Input Debug Request (DR)—The debug request input provides a

Signal

Type

State during

Reset

Signal Description

means of entering the Debug mode of operation. This signal, when asserted (pulled low), will cause the DSP to finish the current instruction being executed, to save the instruction pipeline information, to enter the Debug mode, and to wait for commands to be entered from the debug serial input line. While the DSP is in the Debug mode, the user can reset the OnCE port controller by asserting DR acknowledge pulse on DSO, and then deasserting DR. It may be necessary to reset the OnCE port controller in cases where synchronization between the OnCE port controller and external circuitry is lost. Asserting DR when the DSP is in the Wait or the Stop mode, and keeping it asserted until an acknowledge pulse in the DSP is produced, puts the DSP into the Debug mode. After receiving the acknowledge pulse, DR must be deasserted before sending the first OnCE port command. For more information, see Methods Of Entering The Debug Mode in the

Manual

Note: If the OnCE port is not in use, an external pull-up resistor

should be attached to the DR

, waiting for an

DSP56000 Family

line.

1-18 DSP56007/D MOTOROLA

SECTION 2

SPECIFICATIONS

INTRODUCTION

The DSP56007 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs.

MAXIMUM RATINGS

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or V

Note: In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist.

CAUTION

MOTOROLA DSP56007/D 2-1

+ 58 hidden pages

BSS FDS355, FDScomplete 56007 User Manual

TABLE OF CONTENTS

FEATURES

SIGNAL/CONNECTION DESCRIPTIONS

SPECIFICATIONS