BSS FDS355, FDScomplete 56007 User Manual

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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DSP56007/D

DSP56007

SYMPHONY  AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

Motorola designed the Symphony  family of high-performance, programmable Digital Signal Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic, ATRAC, and Lucasfilm Home THX processing. Software for these applications is licensed by Motorola for integration into products like audio/video receivers, televisions, and automotive sound systems with such user-developed features as digital equalization and sound field processing. The DSP56007 is an MPU-style general purpose DSP, composed of an efficient 24-bit Digital Signal Processor core, program and data memories, various peripherals optimized for audio, and support circuitry. As illustrated in DSP is fed by program memory, two independent data RAMs and two data ROMs, a Serial Audio Interface (SAI), Serial Host Interface (SHI), External Memory Interface (EMI), dedicated I/O lines, on-chip Phase Lock Loop (PLL), and On-Chip Emulation (OnCE DSP56007 has significantly more on-chip memory than the DSP56004.

4 9 5 29

General

Purpose

Input/

Output

Serial Audio

Interface

(SAI)

Serial

Host

Interface

(SHI)

Figure 1 , the DSP56000 core family compatible

) port. The

16-Bit Bus 24-Bit Bus

External Memory

Interface

(EMI)

Program Memory*

X Data

Memory*

Y Data

Memory*

Program Address

PAB XAB YAB

Data ALU

24 × 24 + 56 → 56-Bit MAC

Two 56-Bit Accumulators

Refer to Table 1 for memory configurations.

AA0248

24-Bit

DSP56000

Core

Internal

Switch

OnCETM Port

Clock

PLL

Gen.

Data Bus

Address

Generation

Interrupt

Control

Program Control Unit

IRQA, IRQB, NMI, RESET

Unit

Program

Decode

Controller

GDB PDB XDB

YDB

Generator

Figure 1 DSP56007 Block Diagram

SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . .1-1

SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

SECTION 4 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

SECTION 5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

FOR TECHNICAL ASSISTANCE:

Telephone: 1-800-521-6274

Email: dsphelp@dsp.sps.mot.com

Internet: http://www.motorola-dsp.com

Data Sheet Conventions

his data sheet uses the following conventions:

OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is

active when low.)

“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal

is low

“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal

is high

Examples:

Signal/Symbol Logic State Signal State Voltage

PIN True Asserted VIL/V PIN False Deasserted VIH/V PIN True Asserted VIH/V

PIN False Deasserted VIL/V

Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

ii DSP56007/D MOTOROLA

FEATURES

Digital Signal Processing Core

• Efficient, object code compatible with the 24-bit DSP56000 core family engine

• Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at 88 MHz

• Highly parallel instruction set with unique DSP addressing modes

• Two 56-bit accumulators including extension byte

DSP56007

Features

Memory

• Parallel 24

• Double precision 48

• 56-bit addition/subtraction in 1 instruction cycle

• Fractional and integer arithmetic with support for multiprecision arithmetic

• Hardware support for block floating-point Fast Fourier Transforms (FFT)

• Hardware nested DO loops

• Zero-overhead fast interrupts (2 instruction cycles)

• Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories

• Fabricated in high-density CMOS

• On-chip modified Harvard architecture, which permits simultaneous accesses to program and two data memories

• Bootstrap loading from Serial Host Interface or External Memory Interface

24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)

48-bit multiply with 96-bit result in 6 instruction cycles

Table 1 Memory Configuration (Word width is 24 bits)

Mode Program X Data Y Data

PE ROM RAM ROM RAM ROM RAM

0 6400 None 512 1024 512 2176 52 1 5120 1024 512 1024 512 1152 52

Bootstrap

ROM

MOTOROLA DSP56007/D iii

DSP56007 Features

Peripheral and Support Circuits

• Serial Audio Interface (SAI) includes two receivers and three transmitters, master or slave capability, implementation of I protocols; and two sets of SAI interrupt vectors

• Serial Host Interface (SHI) features single master capability, 10-word receive FIFO, and support for 8-, 16-, and 24-bit words

• External Memory Interface (EMI), implemented as a peripheral supporting: – Page-mode DRAMs (one or two chips): 64 K

and 4 M – SRAMs (one to four): 256 K – Data bus may be 4 or 8 bits wide – Data words may be 8, 12, 16, 20, or 24 bits wide

• Four dedicated, independent, programmable General Purpose Input/Output (GPIO) lines

• On-chip peripheral registers memory mapped in data memory space

• Three external interrupt request pins

• On-Chip Emulation (OnCE) port for unobtrusive, processor speedindependent debugging

4 bits

8 bits

S, Sony, and Matsushita audio

4, 256 K × 4,

• Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer for the core clock

• Power-saving Wait and Stop modes

• Fully static, HCMOS design for operating frequencies down to DC

• 80-pin plastic Quad Flat Pack surface-mount package; 14 (2.15–2.45 mm range); 0.65 mm lead pitch

• Complete pinout compatibility between DSP56009, DSP56004, DSP56004ROM, and DSP56007 for easy upgrades

• 5 V power supply

14 × 2.20 mm

iv DSP56007/D MOTOROLA

Product Documentation

PRODUCT DOCUMENTATION

Table 2 lists the documents that provide a complete description of the DSP56007 and

are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information).

Table 2 DSP56007 Documentation

Document Name Description of Content Order Number

DSP56007

DSP56000 Family Manual

DSP56007 User’s Manual

DSP56007 Technical Data

DSP56000 core family architecture and the 24-bit core processor and instruction set

Memory, peripherals, and interfaces DSP56007UM/AD

Electrical and timing specifications, and pin and package descriptions

DSP56KFAMUM/AD

DSP56007/D

MOTOROLA DSP56007/D v

DSP56007 Product Documentation

vi DSP56007/D MOTOROLA

SECTION 1

SIGNAL/CONNECTION DESCRIPTIONS

SIGNAL GROUPINGS

The DSP56007 input and output signals are organized into the nine functional groups, as shown in

Table 1-1 DSP56007 Functional Group Signal Allocations

Functional Group Number of Signals Detailed Description

Table 1-1 . The individual signals are illustrated in Figure 1-1 .

Power (V Ground (GND) 13 Phase Lock Loop (PLL) 3 External Memory Interface (EMI) 29

Interrupt and Mode Control 4 Serial Host Interface (SHI) 5 Serial Audio Interface (SAI) 9

General Purpose Input/Output (GPIO) 4 On-Chip Emulation (OnCE) port 4

Total 80

Table 1-2 Table 1-3 Table 1-4

Table 1-5

Table 1-6 Table 1-7 Table 1-8

Table 1-9

Table 1-10 Table 1-11 Table 1-12

and

MOTOROLA DSP56007/D 1-1

Signal/Connection Descriptions Signal Groupings

Power Inputs

CCP

CCQ

CCA

CCD

CCS

Ground

GND

PCAP

PINIT

EXTAL

MA0–MA14

MD0–MD7

MA15/MCS3 MA16/MCS2/MCAS MA17/MCS1/MRAS

MCS0

MWR

MRD

DSP56007

3 2

Port B

Serial Host

Interface

Port C

MOSI/HA0 SS/HA2

MISO/SDA SCK/SCL HREQ

Serial Audio

Interface

WSR SCKR

PLL

Rec0 Rec1

SDI0 SDI1

WST

Tran0 Tran1

Tran2

SCKT SDO0 SDO1 SDO2

Port A

External Memory

Interface

GPIO

GPIO0–GPIO3

MODC/NMI

MODB/IRQB MODA/IRQA

RESET

Mode/Interrupt Control

Reset

80 signals

OnCE™

Port

DSCK/OS1 DSI/OS0 DSO DR

AA0249G

Figure 1-1 DSP56007 SIgnals

1-2 DSP56007/D MOTOROLA

POWER

Table 1-2 Power Inputs

Power Name Description

Signal/Connection Descriptions

Power

CCP

CCQ

CCA

CCD

CCS

GROUND

PLL Power —V

provides isolated power for the Phase Lock Loop (PLL). The

CCP

voltage should be well-regulated and the input should be provided with an extremely low impedance path to the V

Quiet Power —V

provides isolated power for the internal processing logic. This

CCQ

power rail.

input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

Address Bus Power —V

provides isolated power for sections of the address bus

CCA

I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

Data Bus Power —V

provides isolated power for sections of the data bus I/O

CCD

drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

Serial Interface Power—V

provides isolated power for the SHI and SAI. This

CCS

input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.

Table 1-3 Grounds

Ground Name Description

GND

PLL Ground—GNDP is ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. V

should be

CCP

bypassed to GNDP by a 0.47 µF capacitor located as close as possible to the chip package.

GND

Quiet Ground—GNDQ provides isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

GND

Address Bus Ground—GNDA provides isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

GND

Data Bus Ground—GNDD provides isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

GND

Serial Interface Ground—GNDS provides isolated ground for the SHI and SAI. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.

MOTOROLA DSP56007/D 1-3

Signal/Connection Descriptions Clock and PLL signals

CLOCK AND PLL SIGNALS

Note: While the PLL on this DSP is identical to the PLL described in the

Family Manual

, two of the signals have not been implemented externally.

DSP56000

Specifically, there is no PLOCK signal or CKOUT signal available. Therefore, the internal clock is not directly accessible and there is no external indication that the PLL is locked. These signals were omitted to reduce the number of pins and allow this DSP to be put in a smaller, less expensive package.

Table 1-4 Clock and PLL Signals

Signal

Name

EXTAL Input Input External Clock/Crystal—This input should be connected to an

PCAP Input Input PLL Filter Capacitor—This input is used to connect a high-

Signal

Type

State

during

Reset

Signal Description

external clock source. If the PLL is enabled, this signal is internally connected to the on-chip PLL. The PLL can multiply the frequency on the EXTAL pin to generate the internal DSP clock. The PLL output is divided by two to produce a four-phase instruction cycle clock, with the minimum instruction time being two PLL output clock periods. If the PLL is disabled, EXTAL is divided by two to produce the four-phase instruction cycle clock.

quality (high “Q” factor) external capacitor needed for the PLL filter. The capacitor should be as close as possible to the DSP with heavy, short traces connecting one terminal of the capacitor to PCAP and the other terminal to V value is specified in Table 2-6 on page 2-6.

. The required capacitor

CCP

Note: When short lock time is critical, low dielectric absorption

capacitors such as polystyrene, polypropylene, or teflon are recommended.

If the PLL is not used (i.e., it remains disabled at all times), there is no need to connect a capacitor to the PCAP pin. It may remain unconnected, or be tied to either Vcc or GND.

PINIT Input Input PLL Initialization (PINIT)—During the assertion of hardware

reset, the value on the PINIT line is written into the PEN bit of the PCTL register. When set, the PEN bit enables the PLL by causing it to derive the internal clocks from the PLL voltage controlled oscillator output. When the bit is cleared, the PLL is disabled and the DSP’s internal clocks are derived from the clock connected to the EXTAL signal. After hardware RESET is deasserted, the PINIT signal is ignored.

1-4 DSP56007/D MOTOROLA

EXTERNAL MEMORY INTERFACE (EMI)

Table 1-5 External Memory Interface (EMI) Signals

Signal/Connection Descriptions

External Memory Interface (EMI)

Signal Name

MA0–MA14 Output Table 1-6 Memory Address Lines 0–14—The MA0–MA10 lines provide

MA15

MCS3

MA16

MCS2

MCAS

MA17

Signal

Type

Output Table 1-6 Memory Address Line 15 (MA15)—This line functions as the

Output Table 1-6 Memory Address Line 16 (MA16)—This line functions as the

Output Table 1-6 Memory Address Line 17 (MA17)—This line functions as the

State during

Reset

Signal Description

the multiplexed row/column addresses for DRAM accesses. Lines MA0–MA14 provide the non-multiplexed address lines 0–14 for SRAM accesses.

non-multiplexed address line 15.

Memory Chip Select 3 (MCS3)—For SRAM accesses, this line functions as memory chip select 3.

non-multiplexed address line 16 or as memory chip select 2 for SRAM accesses.

Memory Chip Select 2 (MCS2)—For SRAM access, this line functions as memory chip select 2.

Memory Column Address Strobe (MCAS)—This line functions as the Memory Column Address Strobe (MCAS) during DRAM accesses.

non-multiplexed address line 17.

MCS1

MRAS

MCS0 Output Table 1-6 Memory Chip Select 0—This line functions as memory chip

MWR Output Table 1-6 Memory Write Strobe—This line is asserted when writing to

MRD Output Table 1-6 Memory Read Strobe—This line is asserted when reading

Memory Chip Select 1 (MCS1)—This line functions as chip select 1 for SRAM accesses.

Memory Row Address Strobe (MRAS)—This line also functions as the Memory Row Address Strobe during DRAM accesses.

select 0 for SRAM accesses.

external memory.

MOTOROLA DSP56007/D 1-5

Signal/Connection Descriptions External Memory Interface (EMI)

Table 1-5 External Memory Interface (EMI) Signals (Continued)

Signal Name

Signal

Type

MD0–MD7 Bidi-

rectional

State during

Reset

Signal Description

Tri-stated Data Bus—These signals provide the bidirectional data bus for

EMI accesses. They are inputs during reads from external memory, outputs during writes to external memory, and tristated if no external access is taking place. If the data bus width is defined as four bits wide, only signals MD0–MD3 are active, while signals MD4–MD7 remain tri-stated. While tri-stated, MD0–MD7 are disconnected from the pins and do not require external pull-ups.

Table 1-6 EMI States during Reset and Stop States

Operating Mode

Signal

Hardware Reset Software Reset Individual Reset Stop Mode

MA0–MA14 Driven High Previous State Previous State Previous State MA15

MCS3 MA16

Driven High

Driven High Driven High

Driven High

Driven High Driven High

Previous State

Driven High

Previous State

Driven High

Previous State

MCS2

Driven High

MCAS: DRAM refresh disabled DRAM refresh enabled

MA17

MCS1

Driven High Driven High

Driven High

Driven High Driven High

Driven High

Driven Low

Previous State

Driven High

Driven High Driven High

Previous State

Driven High

MRAS:

DRAM refresh disabled

DRAM refresh enabled

Driven High Driven High

Driven High

Driven Low

Driven High Driven High

MCS0 Driven High Driven High Driven High Driven High MWR Driven High Driven High Driven High Driven High MRD Driven High Driven High Driven High Driven High

1-6 DSP56007/D MOTOROLA

INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the DSP’s operating mode as it comes out of hardware reset and receives interrupt requests from external sources after reset.

Table 1-7 Interrupt and Mode Control Signals

Signal/Connection Descriptions

Interrupt and Mode Control

Signal Name

MODA

IRQA

Signal

Type

Input Input (MODA) Mode Select A—This input signal has three functions:

State during

Reset

Signal Description

• to work with the MODB and MODC signals to select the DSP’s initial operating mode,

• to allow an external device to request a DSP interrupt after internal synchronization, and

• to turn on the internal clock generator when the DSP is in the Stop processing state, causing the DSP to resume processing.

MODA is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODA signal changes to the external interrupt request IRQA. The DSP operating mode can be changed by software after reset.

External Interrupt Request A (IRQA)—The IRQA input is a synchronized external interrupt request. It may be programmed to be level-sensitive or negative-edgetriggered. When the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQA will generate multiple interrupts also increases.

While the DSP is in the Stop mode, asserting IRQA gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. Hardware reset causes this input to function as MODA.

MOTOROLA DSP56007/D 1-7

Signal/Connection Descriptions Interrupt and Mode Control

Table 1-7 Interrupt and Mode Control Signals (Continued)

Signal Name

MODB

IRQB

Signal

Type Input Input (MODB) Mode Select B—This input signal has two functions:

State during

Reset

Signal Description

• to work with the MODA and MODC signals to select the DSP’s initial operating mode, and

• to allow an external device to request a DSP interrupt after internal synchronization.

MODB is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODB signal changes to the external interrupt request IRQB software after reset.

External Interrupt Request B (IRQB)—The IRQB input is a synchronized external interrupt request. It may be programmed to be level-sensitive or negative-edgetriggered. When the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases. Hardware reset causes this input to function as MODB.

. The DSP operating mode can be changed by

1-8 DSP56007/D MOTOROLA

Signal/Connection Descriptions

Interrupt and Mode Control

Table 1-7 Interrupt and Mode Control Signals (Continued)

Signal Name

MODC

NMI

Signal

Type

Input,

edge-

triggered

State during

Reset

Input (MODC) Mode Select C—This input signal has two functions:

• to work with the MODA and MODB signals to select the DSP’s initial operating mode, and

• to allow an external device to request a DSP interrupt after internal synchronization.

MODC is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODC signal changes to the Non-Maskable Interrupt request, NMI changed by software after reset.

Non-Maskable Interrupt Request—The NMI input is a negative-edge-triggered external interrupt request. This is a level 3 interrupt that can not be masked out. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on NMI will generate multiple interrupts also increases. Hardware reset causes this input to function as MODC.

Signal Description

. The DSP operating mode can be

RESET input active RESET—This input causes a direct hardware reset of the

processor. When RESET is asserted, the DSP is initialized and placed in the Reset state. A Schmitt-trigger input is used for noise immunity. When the reset signal is deasserted, the initial DSP operating mode is latched from the MODA, MODB, and MODC signals. The DSP also samples the PINIT signal and writes its status into the PEN bit of the PLL Control Register. When the DSP comes out of the Reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal. However, the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal.

For proper hardware reset to occur, the clock must be active, since a number of clock ticks are required for proper propagation of the hardware Reset state.

MOTOROLA DSP56007/D 1-9

Signal/Connection Descriptions Serial Host Interface (SHI)

SERIAL HOST INTERFACE (SHI)

Signal Name

SCK

SCL

The Serial Host Interface (SHI) has five I/O signals, which may be configured to

operate in either SPI or I

C mode. Table 1-8 lists the SHI signals.

Table 1-8 Serial Host Interface (SHI) signals

Signal

Type

Input or

Output

Input or

Output

State

during

Reset

Tri-stated SPI Serial Clock (SCK)—The SCK signal is an output

when the SPI is configured as a master, and a Schmitttrigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the Slave Select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol.

I2C Serial Clock (SCL)—SCL carries the clock for bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave, and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. The maximum allowed internally generated bit clock frequency is I2C mode where F maximum allowed externally generated bit clock frequency is I2C mode. This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state).

Signal Description

Fosc

/4 for the SPI mode and

is the clock on EXTAL. The

osc

Fosc

/3 for the SPI mode and

Fosc

/6 for the

Fosc

/5 for the

1-10 DSP56007/D MOTOROLA

Signal/Connection Descriptions

Serial Host Interface (SHI)

Table 1-8 Serial Host Interface (SHI) signals (Continued)

Signal Name

MISO

SDA

Signal

Type

Input or

Output

Input or

Output

State

during

Signal Description

Reset

Tri-stated SPI Master-In-Slave-Out (MISO)—When the SPI is

configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS

is deasserted.

I2C Serial Data and Acknowledge (SDA)—In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of Start and Stop events. A high-to-low transition of the SDA line while SCL is high is an unique situation, and is defined as the Start event. A low-to-high transition of SDA while SCL is high is an unique situation, and is defined as the Stop event.

MOSI

HA0

Input or

Output

Input

Note: This line is tri-stated during hardware reset, software

reset, or individual reset (no need for external pull-up in this state).

Tri-stated SPI Master-Out-Slave-In (MOSI)—When the SPI is

configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode.

I2C Slave Address 0 (HA0)—This signal uses a Schmitttrigger input when configured for the I2C mode. When configured for I2C Slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when the SHI is configured for the I2C Master mode.

Note: This signal is tri-stated during hardware reset,

software reset, or individual reset (no need for external pull-up in this state).

MOTOROLA DSP56007/D 1-11

Signal/Connection Descriptions Serial Host Interface (SHI)

Table 1-8 Serial Host Interface (SHI) signals (Continued)

Signal Name

HA2

Signal

Type

Input

State

during

Reset

Tri-stated

Signal Description

SPI Slave Select (SS)—This signal is an active low

Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI Master mode, this signal should be kept deasserted. If it is asserted while configured as SPI master, a bus error condition will be flagged.

C Slave Address 2 (HA2)—This signal uses a

Schmitt-trigger input when configured for the I

mode. When configured for the I

C Slave mode, the

HA2 signal is used to form the slave device address.

HA2 is ignored in the I

C Master mode. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state.

Note: This signal is tri-stated during hardware reset,

software reset, or individual reset (no need for external pull-up in this state).

HREQ Input or

Output

Tri-stated Host Request—This signal is an active low Schmitt-

trigger input when configured for the Master mode, but an active low output when configured for the Slave mode. When configured for the Slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the Master mode, HREQ is an input and when asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer.

Note: This signal is tri-stated during hardware, software,

individual reset, or when the HREQ[1:0] bits (in the HCSR) are cleared (no need for external pull-up in this state).

1-12 DSP56007/D MOTOROLA

SERIAL AUDIO INTERFACE (SAI)

The SAI is composed of separate receiver and transmitter sections.

SAI Receiver Section

Table 1-9 Serial Audio Interface (SAI) Receiver signals

Signal/Connection Descriptions

Serial Audio Interface (SAI)

Signal

Name

SDI0 Input Tri-stated Serial Data Input 0—While in the high impedance

SDI1 Input Tri-stated Serial Data Input 1—While in the high impedance

SCKR Input or

Signal

Type

Output

State during

Reset

state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. SDI0 is the serial data input for receiver 0.

Note: This signal is high impedance during hardware or

software reset, while receiver 0 is disabled (R0EN = 0), or while the DSP is in the Stop state.

state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. SDI1 is the serial data input for receiver 1.

Note: This signal is high impedance during hardware or

software reset, while receiver 1 is disabled (R1EN = 0), or while the DSP is in the Stop state.

Tri-stated Receive Serial Clock—SCKR is an output if the

receiver section is programmed as a master, and a Schmitt-trigger input if programmed as a slave. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary.

Signal Description

Note: SCKR is high impedance if all receivers are

disabled (individual reset) and during hardware or software reset, or while the DSP is in the Stop state.

MOTOROLA DSP56007/D 1-13

Signal/Connection Descriptions Serial Audio Interface (SAI)

Table 1-9 Serial Audio Interface (SAI) Receiver signals (Continued)

Signal

Name

Signal

Type

WSR Input or

Output

State during

Reset

Signal Description

Tri-stated Word Select Receive (WSR)—WSR is an output if the

receiver section is configured as a master, and a Schmitt-trigger input if configured as a slave. WSR is used to synchronize the data word and to select the left/right portion of the data sample.

Note: WSR is high impedance if all receivers are disabled

(individual reset), during hardware reset, during software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the signal and no external pull-up is necessary.

1-14 DSP56007/D MOTOROLA

SAI Transmitter Section

Table 1-10 Serial Audio Interface (SAI) Transmitter signals

Signal/Connection Descriptions

Serial Audio Interface (SAI)

Signal

Name

Signal

Type

State

during

Reset

SDO0 Output Driven

High

SDO1 Output Driven

High

SDO2 Output Driven

High

SCKT Input or

Tri-stated Serial Clock Transmit (SCKT)—This signal provides the

Output

Signal Description

Serial Data Output 0 (SDO0)—SDO0 is the serial output for

transmitter 0. SDO0 is driven high if transmitter 0 is disabled, during individual reset, hardware reset, and software reset, or when the DSP is in the Stop state.

Serial Data Output 1 (SDO1)—SDO1 is the serial output for transmitter 1. SDO1 is driven high if transmitter 1 is disabled, during individual reset, hardware reset and software reset, or when the DSP is in the Stop state.

Serial Data Output 2 (SDO2)—SDO2 is the serial output for transmitter 2. SDO2 is driven high if transmitter 2 is disabled, during individual reset, hardware reset and software reset, or when the DSP is in the Stop state.

clock for the SAI. SCKT can be an output if the transmit section is configured as a master, or a Schmitt-trigger input if the transmit section is configured as a slave. When the SCKT is an output, it provides an internally generated SAI transmit clock to external circuitry. When the SCKT is an input, it allows external circuitry to clock data out of the SAI.

Note: SCKT is high impedance if all transmitters are disabled

(individual reset), during hardware reset, software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary.

WST Input or

Output

Tri-stated Word Select Transmit (WST)—WST is an output if the

transmit section is programmed as a master, and a Schmitttrigger input if it is programmed as a slave. WST is used to synchronize the data word and select the left/right portion of the data sample.

Note: WST is high impedance if all transmitters are disabled

(individual reset), during hardware or software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary.

MOTOROLA DSP56007/D 1-15

Signal/Connection Descriptions General Purpose I/O

GENERAL PURPOSE I/O

Table 1-11 General Purpose I/O (GPIO) Signals

Signal

Name

GPIO0– GPIO3

Signal

Type

Standard

Output,

Open-drain

Output, or

Input

State during

Reset

Disconnected GPIO lines can be used for control and handshake

ON-CHIP EMULATION (OnCE

There are four signals associated with the OnCE port controller and its serial interface.

Table 1-12 On-Chip Emulation Port Signals

Signal

Name

Signal

Type

State during

Reset

) PORT

Signal Description

functions between the DSP and external circuitry. Each GPIO line can be configured individually as disconnected, open-drain output, standard output, or an input.

Note: Hardware reset or software reset configures all

the GPIO lines as disconnected (external circuitry connected to these pins may need pullups until the pins are configured for operation).

Signal Description

DSI

OS0

Input

Output

Output,

Driven Low

Debug Serial Input (DSI)—The DSI signal is the signal through which serial data or commands are provided to the OnCE port controller. The data received on the DSI signal will be recognized only when the DSP has entered the Debug mode of operation. Data must have valid TTL logic levels before the serial clock falling edge. Data is always shifted into the OnCE port Most Significant Bit (MSB) first.

Operating Status 0 (OS0)—When the DSP is not in the Debug mode, the OS0 signal provides information about the DSP status if it is an output and used in conjunction with the OS1 signal. When switching from output to input, the signal is tri-stated.

Note: If the OnCE port is in use, an external pull-down resistor

should be attached to the DSI/OS0 signal. If the OnCE port is not in use, the resistor is not required.

1-16 DSP56007/D MOTOROLA

Signal/Connection Descriptions

On-Chip Emulation (OnCETM) Port

Table 1-12 On-Chip Emulation Port Signals (Continued)

Signal Name

DSCK

OS1

DSO Output Driven High Debug Serial Output (DSO)—The DSO line provides the

Signal

Type

Input

Output

State during

Reset

Output,

Driven Low

Debug Serial Clock (DSCK)—The DSCK/OS1 signal, when an input, is the signal through which the serial clock is supplied to the OnCE port. The serial clock provides pulses required to shift data into and out of the OnCE port. Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE port on the rising edge.

Operating Status 1 (OS1)—If the OS1 signal is an output and used in conjunction with the OS0 signal, it provides information about the DSP status when the DSP is not in the Debug mode. The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. The signal is tri-stated when it is changing from input to output.

Note: If the OnCE port is in use, an external pull-down resistor

data contained in one of the OnCE port controller registers as specified by the last command received from the command controller. The Most Significant Bit (MSB) of the data word is always shifted out of the OnCE port first. Data is clocked out of the OnCE port on the rising edge of DSCK.

Signal Description

should be attached to the DSCK/OS1 pin. If the OnCE port is not in use, the resistor is not required.

The DSO line also provides acknowledge pulses to the external command controller. When the DSP enters the Debug mode, the DSO line will be pulsed low to indicate that the OnCE port is waiting for commands. After receiving a read command, the DSO line will be pulsed low to indicate that the requested data is available and the OnCE port is ready to receive clock pulses in order to deliver the data. After receiving a write command, the DSO line will be pulsed low to indicate that the OnCE port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided.

Note: During hardware reset and when idle, the DSO line is

held high.

MOTOROLA DSP56007/D 1-17

Signal/Connection Descriptions On-Chip Emulation (OnCETM) Port

Table 1-12 On-Chip Emulation Port Signals (Continued)

Signal

Name

DR Input Input Debug Request (DR)—The debug request input provides a

Signal

Type

State during

Reset

Signal Description

means of entering the Debug mode of operation. This signal, when asserted (pulled low), will cause the DSP to finish the current instruction being executed, to save the instruction pipeline information, to enter the Debug mode, and to wait for commands to be entered from the debug serial input line. While the DSP is in the Debug mode, the user can reset the OnCE port controller by asserting DR acknowledge pulse on DSO, and then deasserting DR. It may be necessary to reset the OnCE port controller in cases where synchronization between the OnCE port controller and external circuitry is lost. Asserting DR when the DSP is in the Wait or the Stop mode, and keeping it asserted until an acknowledge pulse in the DSP is produced, puts the DSP into the Debug mode. After receiving the acknowledge pulse, DR must be deasserted before sending the first OnCE port command. For more information, see Methods Of Entering The Debug Mode in the

Manual

Note: If the OnCE port is not in use, an external pull-up resistor

should be attached to the DR

, waiting for an

DSP56000 Family

line.

1-18 DSP56007/D MOTOROLA

SECTION 2

SPECIFICATIONS

INTRODUCTION

The DSP56007 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs.

MAXIMUM RATINGS

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or V

Note: In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist.

CAUTION

MOTOROLA DSP56007/D 2-1

Specifications Thermal characteristics

Table 2-1 Maximum Ratings (GND = 0 V

Rating Symbol Value Unit

Supply Voltage V All Input Voltages V Current Drain per Pin excluding V

and GND I 10 mA

Operating Temperature Range:

• 50 and 66 MHz

• 88 MHz

Storage Temperature T

THERMAL CHARACTERISTICS

Table 2-2 Thermal Characteristics

Characteristic Symbol QFP Value

Junction-to-ambient thermal resistance Junction-to-case thermal resistance

)

STG

(GND – 0.25) to (V

61.5 37

11.8 —

–0.3 to +7.0 V

+ 0.25) V

–40 to +125 –40 to +110

–55 to +125

QFP Value

Unit

C/W

° C ° C

° C

Thermal characterization parameter

Notes: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided

Printed Circuit Board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111)

2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G3088, with the exception that the cold plate temperature is used for the case temperature.

3. These are measured values. See note 1 for test board conditions.

4. These are measured values; testing is not complete. Values were measured on a non-standard four-layer thermal test board (two internal planes) at one watt in a horizontal configuration.

2.7 —

C/W

2-2 DSP56007/D MOTOROLA

DC ELECTRICAL CHARACTERISTICS

Table 2-3 DC Electrical Characteristics

50 MHz 66 MHz 88 MHz

Characteristics Symbol

Min Typ Max Min Typ Max Min Typ Max

Specifications

DC Electrical Characteristics

Unit

Supply voltage V Input high voltage

• EXTAL

• RESET

• MODA, MODB,

V V

MODC

• SHI inputs

• All other inputs

Input low voltage

• EXTAL

• MODA, MODB, MODC

• SHI inputs

• All other inputs

Input leakage current

• EXTAL, RESET, MODA, MODB, MODC, DR

• Other Input Pins (@ 2.4 V/0.4 V)

High impedance (off-state) input current (@ 2.4 V / 0.4 V)

IHM

IHC

IHR

IHS

ILC

ILM

ILS

TSI

4.75 5.0 5.25 4.75 5.0 5.25 4.75 5.0 5.25 V

— — —

—

— —

—

V V V

0.3

4.0

2.5

3.5

0.7 V

2.0

–0.5 –0.5

–0.5

—

–1

–10——110

CC CC CC

0.4

2.0

0.8

0.7 V

–0.5 –0.5

–0.5

— — —

—

— —

—

V V V

0.4

2.0

0.3

4.0

2.5

3.5

2.0

—

0.8

–1

–10——110

4.0

2.5

3.5

0.7

2.0

–0.5 –0.5

–0.5

–1

–10——110

—

V V V

0.4

2.0

0.3 V

0.8

CC CC CC

— —

—

— —

—

–10 — 10 –10 — 10 –10 — 10 µ A

V V V

V V

µ A

Output high voltage (I

= –0.4 mA)

Output low voltage (I

= 3.2 mA)

SCK/SCL I MISO/SDA I HREQ I

= 6.7 mA

2.4 — — 2.4 — — 2.4 — — V

— — 0.4 — — 0.4 — — 0.4 V

Internal Supply Current

• Normal mode

• Wait mode

• Stop mode

CCI

CCW

CCS

— — —

80 14

105

110

— — —

110

130

110

—

147

—

169

110

mA mA

µ A

MOTOROLA DSP56007/D 2-3

Specifications AC Electrical Characteristics

Table 2-3 DC Electrical Characteristics (Continued)

50 MHz 66 MHz 88 MHz

Characteristics Symbol

Min Typ Max Min Typ Max Min Typ Max

PLL supply current — 0.7 1.1 — 1.0 1.5 — 1.3 2.2 mA Input capacitance

Notes: 1. The SHI inputs are: MOSI/HA0, SS/HA2, MISO/SDA, SCK/SCL, and HREQ.

2. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signals are

3. Periodically sampled and not 100% tested

4. Maximum values are derived using the methodology described in

disabled during Stop state.

application dependent and may vary widely from these numbers.

—10— —10— —10— pF

Section 4

. Actual maximums are

Unit

AC ELECTRICAL CHARACTERISTICS

The timing waveforms in the AC Electrical Characteristics are tested with a V maximum of 0.5 V and a V MODA, MODB, MODC, and SHI pins (MOSI/HA0, SS SCL, HREQ

). These pins are tested using the input levels set forth in the DC Electrical

minimum of 2.4 V for all pins, except EXTAL, RESET,

/HA2, MISO/SDA, SCK/

Characteristics. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal’s transition. DSP56007 output levels are measured with the production test machine V

and V

reference levels set at 0.8 V and 2.0 V, respectively.

All output delays are given for a 50 pF load unless otherwise specified. For load capacitance greater than 50 pF, the drive capability of the output pins typically decreases linearly:

1. At 1.5 ns per 10 pF of additional capacitance at all output pins except MOSI/HA0, MISO/SDA, SCK/SCL, HREQ

2. At 1.0 ns per 10 pF of additional capacitance at output pins MOSI/HA0, MISO/SDA, SCK/SCL, HREQ

(in SPI mode only)

2-4 DSP56007/D MOTOROLA

INTERNAL CLOCKS

Specifications

Internal Clocks

For each occurrence of T

, TL, TC, or I

, substitute with the numbers in Table 2-4.

CYC

Table 2-4 Internal Clocks

Characteristics Symbol Expression

Internal Operation Frequency f — Internal Clock High Period

• with PLL disabled

• with PLL enabled and MF ≤ 4

• with PLL enabled and MF > 4

Internal Clock Low Period

• with PLL disabled

• with PLL enabled and MF ≤ 4

• with PLL enabled and MF > 4

Internal Clock Cycle Time T Instruction Cycle Time I

CYC

(Min) 0.48 × T (Max) 0.52 × T

(Min) 0.467 × T

(Max) 0.533 × T

(Min) 0.48 × T (Max) 0.52 × T

(Min) 0.467 × T

(Max) 0.533 × T

(DF /MF) × ET

2 × T

C C

EXTERNAL CLOCK (EXTAL PIN)

The DSP56007 system clock is externally supplied via the EXTAL pin. Timings shown in this document are valid for clock rise and fall times of 3 ns maximum.

Table 2-5 External Clock (EXTAL Pin)

50 MHz 66 MHz 88 MHz

No. Characteristics Sym.

Min Max Min Max Min Max

— Frequency of External Clock (EXTAL Pin) Ef 0 50 0 66 0 88 MHz

1 External Clock Input High—EXTAL Pin1

• with PLL disabled

9.3

7.1

5.3

(46.7%–53.3% duty cycle)

• with PLL enabled

8.5∞235500

6.4∞235500

4.8∞235500

(42.5%–57.5% duty cycle)

Unit

MOTOROLA DSP56007/D 2-5

Specifications Phase Lock Loop (PLL) Characteristics

Table 2-5 External Clock (EXTAL Pin) (Continued)

No. Characteristics Sym.

50 MHz 66 MHz 88 MHz

Unit

Min Max Min Max Min Max

2 External Clock Input Low—EXTAL Pin1

• with PLL disabled

9.3

7.1

5.4

(46.7%–53.3% duty cycle)

• with PLL enabled

8.5∞235500

6.4∞235500

4.8∞235500

(42.5%–57.5% duty cycle)

3 External Clock Cycle Time

• with PLL disabled

• with PLL enabled

4 Instruction Cycle Time = I

• with PLL disabled

• with PLL enabled

Note: 1. External Clock Input High and External Clock Input Low are measured at 50% of the input transition.

= 2 × T

cyc

20 20∞409600

cyc

40 40∞819200

15.15

15.15∞409600

30.3

30.3∞819200

11.4

11.4∞409600nsns

22.7

22.7∞819200nsns

EXTAL

1 2

AA0250

Figure 2-1 External Clock Timing

PHASE LOCK LOOP (PLL) CHARACTERISTICS

Table 2-6 Phase Lock Loop (PLL) Characteristics

Characteristics Expression Min Max Unit

VCO frequency when PLL enabled MF × Ef 10 f PLL external capacitor

(PCAP pin to V

CCP

)

MF × C

@ MF ≤ 4

@ MF > 4

Note: 1. Cpcap is the value of the PLL capacitor (connected between PCAP pin and V

The recommended value for Cpcap is 400 pF for MF ≤ 4 and 540 pF for MF > 4. The maximum VCO frequency is limited to the internal operation frequency, defined in Table 2-4.

PCAP

MF × 340 MF × 380

2-6 DSP56007/D MOTOROLA

MF × 480 MF × 970

) for MF = 1.

CCP

MHz

pF pF

Specifications

RESET, Stop, Mode Select, and Interrupt Timing

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (CL = 50 pF + 2 TTL Loads)

No. Characteristics Min Max Unit

10 Minimum RESET assertion width:

• PLL disabled

• PLL enabled

14 Mode Select Setup Time 21 — ns 15 Mode Select Hold Time 0 — ns 16 Minimum Edge-triggered Interrupt Request Assertion

Width

16a Minimum Edge-triggered Interrupt Request

Deassertation Width

18 Delay from IRQA

, IRQB, NMI Assertion to GPIO Valid

Caused by First Interrupt Instruction Execution

22 Delay from General Purpose Output Valid to Interrupt

Request Deassertation for Level Sensitive Fast Interrupts—If Second Interrupt Instruction is: 2

• Single Cycle

• Two Cycles 25 Duration of IRQA Assertion for Recovery from Stop State 12 — ns 27 Duration for Level Sensitive IRQA Assertion to ensure

interrupt service (when exiting “STOP”)

• Stable External Clock, OMR Bit 6 = 1

• Stable External Clock, PCTL Bit 17 = 1

Note: 1. This timing requirement is sensitive to the quality of the external PLL capacitor connected to the PCAP

pin. For capacitor values less than or equal to 2 nF, asserting RESET will ensure proper processor initialization for capacitors with a deltaC/C less than 0.5%. (This is typical for ceramic capacitors.) For capacitor values greater than 2 nF, asserting RESET requirement will ensure proper processor initialization for capacitors with a deltaC/C less than 0.01%. (This is typical for Teflon, polystyrene, and polypropylene capacitors.) However, capacitors with values greater than 2 nF with a deltaC/C greater than 0.01% may require longer RESET proper initialization.

2. When using fast interrupts and IRQA prevent multiple interrupt service. To avoid these timing restrictions, the Negative Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.

and IRQB are defined as level-sensitive, then timing 22 applies to

25 × T

2500 × ET

— —

ns ns

13 — ns

12 × TC + TH —ns

TL – 31

(2 × TC) + TL – 31nsns

6 × TC + T

according to this timing requirement

— —

according to this timing

assertion to ensure

ns ns

IHR

RESET

AA0251

Figure 2-2 Reset Timing

MOTOROLA DSP56007/D 2-7

Specifications RESET, Stop, Mode Select, and Interrupt Timing

RESET

MODA, MODB

MODC

IRQA, IRQB,

NMI

IRQA, IRQB,

NMI

General

Purpose

I/O

(Output)

IRQA IRQB

NMI

IHM

ILM

Figure 2-3 Operating Mode Select Timing

16A

Figure 2-4 External Interrupt Timing (Negative Edge-triggered)

2218

General Purpose I/O

IRQA, IRQB, NMI

IHR

AA0252

AA0253

AA0254

Figure 2-5 External Level-sensitive Fast Interrupt Timing

IRQA

AA0255

Figure 2-6 Recovery from Stop State Using IRQA

IRQA

AA0256

Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service

2-8 DSP56007/D MOTOROLA

External Memory Interface (EMI) DRAM Timing

EXTERNAL MEMORY INTERFACE (EMI) DRAM TIMING

(CL = 50 pF + 2 TTL Loads)

Table 2-8 External Memory Interface (EMI) DRAM Timing

Specifications

No. Characteristics Symbol

41 Page Mode Cycle Time t

42 RAS or RD Assertion to

Data Valid

43 CAS Assertion to Data

RAC

CAC

Valid

44 Column Address Valid

to Data Valid

45 CAS Assertion to Data

CLZ

Active

46 RAS Assertion Pulse

Width

RASP

(Page Mode Access Only)

47 RAS Assertion Pulse

RAS

Width (Single Access Only)

48 RAS or CAS

Deassertation to RAS

tRP,

CRP

Assertion

49 CAS Assertion Pulse

CAS

Width

50 Last CAS Assertion to

RSH

RAS Deassertation (Page Mode Access Only)

RAS or WR Assertion to CAS Deassertation

52 RAS Assertion to CAS

T T

CSH

CWL

RCD

Assertion

53 RAS Assertion to

RAD

Column Address Valid

Timing

Mode

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

50 MHz 66 MHz 88 MHz

Expression

Min Max Min Max Min Max

4 × T 3 × T

× T × T

C C

– 16 – 16——

8060——6146——45.5

34.1——nsns

12484——9060——63.5

3 × TC – 10

2 × TC – 10——5030——3520——

3 ×TC + TL – 7

——6343——4630——32.8

2 × TC + TL –

7 0 0—0—0—ns

3 ×TC –11

+ n × 4 × T

2 × TC –11

+ n × 3 ×T

7 × TC – 11

5 × TC – 11

5 × TC – 5 3 × TC – 59555——7040——

3 × TC – 10

2 × TC – 105030——3520—— 3 × TC – 15

2 × TC – 154525——3015——

7 × TC – 15 5 × TC – 15

4 ×TC – 13

3 × TC – 136747——4732——

3 ×TC + TH –

209

149——

156

110——

12989——9565——68.5

12585——9161——64.5

5737——4025——26.8

114

79.9——nsns

45.8——nsns

51.8

29.1——nsns

24.1

12.7——nsns

19.1

7.7——nsns

41.8——nsns

32.5

21.1——nsns

2 ×TC + TH –

15.4——nsns

Unit

40.8nsns

24.1

12.7nsns

21.4nsns

MOTOROLA DSP56007/D 2-9

Specifications External Memory Interface (EMI) DRAM Timing

Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued)

No. Characteristics Symbol

54 CAS Deassertation Pulse

Width (Page Mode Access Only)

55 Row Address Valid to

ASR

RAS Assertion (Row Address Setup Time)

56 RAS

Assertion to ROW

RAH

Address Not Valid (Row Address Hold Time)

57 Column Address Valid

ASC

to CAS Assertion (Column Address Setup Time)

58 CAS Assertion to

CAH

Column Address Not Valid (Column Address Hold Time)

Last CAS Assertion to

CAH

Column Address Not Valid (Column Address Hold Time)

60 RAS Assertion to

Column Address Not Valid

61 Column Address Valid

RAL

to RAS Deassertation

62 CAS, RAS, RD, or WR

Deassertation to WR or

RCH

RRH

RD Assertion

63 CAS or RD

Deassertation to Data

OFF

tGZ

Not Valid (Data Hold Time)

Timing

Mode

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

50 MHz 66 MHz 88 MHz

Expression

Min Max Min Max Min Max

TC – 5 15 — 10 — 6.4 — ns

TL – 6 4—2—0.1—ns

3 × TC + TH –

5636——3924——25.8

2 × TC + TH –

14.4——nsns

TL – 6 4—2—0.1—ns

3 × TC + TH –

5636——3924——25.8

2 × TC + TH –

14.4——nsns

7 × TC + TH –

13676——10054——71.2

4 × T

+ TH –

37.1——nsns

7 × TC + TH –

13696——10069——71.2

5 × TC + TH –

48.5——nsns

3 × TC + TL –

6343——4630——32.8

21.2——nsns

2 × TC + TL –

5 × TC – 11 3 × TC – 118949——6535——

45.8

23.1——nsns

0 0—0—0—ns

Unit

2-10 DSP56007/D MOTOROLA

Specifications

External Memory Interface (EMI) DRAM Timing

Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued)

Timing

Mode

slow

fast

Expression

12 × T

8 × T

No. Characteristics Symbol

64 Random Read or Write

t Cycle Time (Single Access Only)

65 WR Deassertation to

CAS Assertion

66 CAS Assertion to WR

Deassertation

67 Data Valid to CAS

RCS

WCH

slow

fast

slow

fast

9 × TC – 11 6 × TC – 11

3 × TC – 13 2 × TC – 134727——3217——

TL – 6 4—2—0.1—ns Assertion (Data Setup Time)

68 CAS Assertion to Data

Not Valid (Data Hold Time)

slow

fast

3 × TC + TH –

2 × TC + TH –

69 RAS Assertion to Data

Not Valid

DHR

slow

fast

7 × TC + TH –

5 × TC + TH –

70 WR Assertion to CAS

Assertion

71 WR Assertion Pulse

Width (Single Cycle

WCS

slow

fast

slow

fast

4 × TC – 14 3 × TC – 146646——4731——

7 × TC – 9 5 × TC – 9

Only)

RAS Assertion to WR Deassertation

WCR

slow

fast

7 × TC – 15 5 × TC – 15

(Single Cycle Only)

73 WR Assertion to Data

Active

slow

fast

3 × TC + TH –

2 × TC + TH –

74 RD or WR Assertion to

RAS Deassertation

ROH

RWL

slow

fast

7 × TC – 13 5 × TC – 13

(Single Cycle Only)

Note: 1. n is the number of successive accesses. n = 2, 3, 4, or 6.

50 MHz 66 MHz 88 MHz

Min Max Min Max Min Max

240

98.8——

169 109——

182 121——

136.4

91.0——nsns

12580——91.3

57.2——nsns

21.1

9.7——nsns

5636——3924——25.8

14.4——nsns

13696——10069——71.2

48.5——nsns

31.4

20.1——nsns

13191——9767——70.5

47.8——nsns

12585——9161——64.5

41.8——nsns

5737——4025——26.8

15.4——nsns

12787——9363——66.5

43.8——nsns

Unit

MOTOROLA DSP56007/D 2-11

Specifications External Memory Interface (EMI) DRAM Timing

MRAS

MCAS

MA0–MA10

MWR

MRD

4748

53 59

Row Address Last Column Address

50 49

6257

MD0–MD7

42 63

Data In

AA0257

Figure 2-8 DRAM Single Read Cycle

2-12 DSP56007/D MOTOROLA

Specifications

External Memory Interface (EMI) DRAM Timing

MRAS

MCAS

MA0–MA10

MWR

MRD

48 46

60 50

65 41 54

Col. AddressRow Address Col. Address Last Column Address

59585853

4444

MD0–MD7

42 63 63 63

4545 45

Data

InDataIn Data In

Figure 2-9 DRAM Page Mode Read Cycle

AA0263

MOTOROLA DSP56007/D 2-13

Specifications External Memory Interface (EMI) DRAM Timing

MRAS

MCAS

47 4848

52 50

MA0–MA10

MWR

MRD

MD0–MD7

Row Address Column Address

Data Out

Figure 2-10 DRAM Single Write Cycle

AA0264

2-14 DSP56007/D MOTOROLA

Specifications

External Memory Interface (EMI) DRAM Timing

MRAS

MCAS

MA0–MA10

MWR

48 46

60 50

65 41 54

Col. AddressRow Address Col. Address Last Column Address

59585853

MRD

MD0–MD7

Data Out Data Out

Data Out

Figure 2-11 DRAM Page Mode Write Cycle

68 67

AA0265

MOTOROLA DSP56007/D 2-15

Specifications External Memory Interface (EMI) DRAM Refresh Timing

EXTERNAL MEMORY INTERFACE (EMI) DRAM REFRESH TIMING

(CL = 50pF + 2 TTL Loads)

Table 2-9 External Memory Interface (EMI) DRAM Refresh Timing

50 MHz 66 MHz 88 MHz

Min Max Min Max Min Max

11373——84———61.2———ns

260

180——

13191——97———70.5———ns

No. Characteristics Sym.

CPN

RAS Deassertation to

Assertion

RAS

82 CAS

Deassertation to

CAS Assertion

83 Refresh Cycle Time t

84 RAS Assertion Pulse

RAS

Width

85 RAS Deassertation to

RAS Assertion for Refresh Cycle

86 CAS Assertion to RAS

CSR

Timing

Mode

slow

fast

slow

fast

slow

fast

slow

fast

slow

fast

Exp.

6 × TC – 7

4 × TC – 7

5 × TC – 7 3 × TC – 79353——71———

13 × T

9 × T

7 × TC – 9 5 × TC – 9

5 × TC – 5 3 × TC – 59555——70———

TC – 7 13 — 8 — 4.4 — ns Assertion on Refresh Cycle

87 RAS Assertion to CAS

Deassertation on

CHR

slow

fast

7 × TC – 15 5 × TC – 15

12585——91———64.5———ns

Refresh Cycle

88 RAS Deassertation to

CAS Assertion on a

RPC

slow

fast

5 × TC – 11

3 × TC – 118949——65———

Refresh Cycle

89 CAS Deassertation to

OFF

0 0—0—0—ns

Data Not Valid

Note: 1. Fast mode is not available for operating frequencies above 50 MHz.

2. This happens when a Refresh Cycle is followed by an Access Cycle.

Unit

49.8———ns ns

197———147.7———ns

51.8———ns ns

45.8———ns ns

2-16 DSP56007/D MOTOROLA

MRAS

Specifications

External Memory Interface (EMI) SRAM Timing

81 84 85

88 82

MCAS

MD0–MD7

Data In

Figure 2-12 CAS

before RAS Refresh Cycle

EXTERNAL MEMORY INTERFACE (EMI) SRAM TIMING

(CL = 50pF + 2 TTL Loads)

Table 2-10 External Memory Interface (EMI) SRAM Timing

50 MHz 66 MHz 88 MHz

No. Characteristics Symbol Expression

Min Max Min Max Min Max

Address Valid and CS Assertion Pulse Width

92 Address Valid to RD or WR

Assertion

93 RD or WR Assertion Pulse

Width

94 RD or WR Deassertation to

RD or WR Assertion

95 RD or WR Deassertation to

Address not Valid

96 Address Valid to Input Data

Valid

97 RD Assertion to Input Data

Valid

98 RD Deassertation to Data

Not Valid (Data Hold Time)

tRC, t

4 × TC – 11 +

Ws × T

69 — 50 — 34.5 — ns

TC + TL – 13 17 — 10 — 4.4 — ns

2 × TC – 5 +

Ws × T

35 — 23 — 17.7 — ns

—2 × TC – 11 29 — 19 — 11.7 — ns

tAA, t

OHZ

TH – 6 4—2—0.1— ns

3 × TC + TL –15 +

Ws × T

2 × TC – 15 +

Ws × T

— 55 — 38 — 24.8 ns

—25—15—7.7 ns

0 0—0—0—ns

AA0266

Unit

MOTOROLA DSP56007/D 2-17

Specifications External Memory Interface (EMI) SRAM Timing

Table 2-10 External Memory Interface (EMI) SRAM Timing

No. Characteristics Symbol Expression

50 MHz 66 MHz 88 MHz

Unit

Min Max Min Max Min Max

99 Address Valid to WR

Deassertation

100 Data Setup Time to WR

Deassertation

101 Data Hold Time from WR

TCW, t

3 × TC + TL –14 +

Ws × T

tDS (tDW)T

+ TL – 5 +

Ws × T

TH – 6 4—2—0.1— ns

56 — 39 — 25.8 — ns

25 — 18 — 12.0 — ns

Deassertation 102 WR Assertion to Data Valid — TH + 4 — 14 — 12 — 9.7 ns 103 WR

Deassertation to Data

high impedance

104 WR Assertion to Data

—T

+ 10 — 20 — 18 — 15.7 ns

– 6 4—2—0.1— ns

Active

Note: 1. This value is periodically sampled and not 100% tested.

MA0–MA14

MCS3

MA15/

MA16/MCS2/MCAS MA17/MCS1/MRAS

MCS0

9897

MD0–MD7

Data In

AA0267

Figure 2-13 SRAM Read Cycle

2-18 DSP56007/D MOTOROLA

Specifications

External Memory Interface (EMI) SRAM Timing

MA0–MA14

MCS3

MA15/ MA16/MCS2/MCAS MA17/MCS1/MRAS

MCS0

MD0–MD7

100

102

Data Out

104 101

Figure 2-14 SRAM Write Cycle

103

AA0268

MOTOROLA DSP56007/D 2-19

Specifications Serial Audio Interface (SAI) Timing

SERIAL AUDIO INTERFACE (SAI) TIMING

(CL = 50pF + 2 TTL Loads)

Table 2-11 Serial Audio Interface (SAI) Timing

No. Characteristics Mode Expression

50 MHz 66 MHz 81 MHz

Unit

Min Max Min Max Min Max

111 Minimum Serial Clock Cycle =

(min)

SAICC

112 Serial Clock High Period master

113 Serial Clock Low Period master

114 Serial Clock Rise/Fall Time master

115 Data In Valid to SCKR edge

(Data In Set-up Time)

116 SCKR Edge to Data In Not

Valid (Data In Hold Time)

117 SCKR Edge to Word Select Out

master

slave

master

slave

master

slave

4 × T

3 × TC + 5

0.5 × t

× t

0.35

× t

0.5

0.35 × t

0.15 × t

SAICC

4 0

– 8

8065——6151——45.5

3223——2218——14.7

3223——2218——14.8

——810——88——8.0

264——264——264——ns

014——014——014——ns

master 20 — 20 — 20 — 20 ns

Valid (WSR Out Delay Time)

118 Word Select In Valid to SCKR

slave 12 12 — 12 — 12 — ns

Edge (WSR In Set-up Time)

119 SCKR Edge to Word Select In

slave 12 12 — 12 — 12 — ns

Not Valid (WSR In Hold Time)

121 SCKT Edge to Data Out Valid

(Data Out Delay Time) master

122 SCKT Edge to Word Select Out

slave

master 19 — 19 — 19 — 19 ns

13 40

TH + 34

— — —

13 40 44

— — —

Valid (WST Out Delay Time)

123 Word Select In Valid to SCKT

slave 12 12 — 12 — 12 — ns

Edge (WST In Set-up Time)

124 SCKT Edge to Word Select In

slave 12 12 — 12 — 12 — ns

Not Valid (WST In Hold Time)

Note: 1. When the Frequency Ratio between Parallel and Serial clocks is 1:4 or greater

2. When the Frequency Ratio between Parallel and Serial clocks is 1:3 – 1:4

39.1——nsns

13.7——nsns

—

5.9nsns

13 40

39.7

ns ns ns

2-20 DSP56007/D MOTOROLA

SCKR

(RCKP = 1)

SCKR

(RCKP = 0)

115

Specifications

Serial Audio Interface (SAI) Timing

111

112

114 114

113

111

113

114 114

112

116

SDI0–SDI1

(Data Input)

WSR

(Input)

WSR

(Output)

Valid

119

118

Valid

117

AA0269

Figure 2-15 SAI Receiver Timing

MOTOROLA DSP56007/D 2-21

Specifications Serial Audio Interface (SAI) Timing

SCKT

KP = 1)

SCKT

KP = 0)

SDO0–SDO2

(Data Output)

WST

(Input)

111

112

114 114

113

111

113

114 114

112

121

124

123

Valid

WST

(Output)

122

AA0270

Figure 2-16 SAI Transmitter Timing

2-22 DSP56007/D MOTOROLA

Serial Host Interface (SHI) SPI Protocol Timing

SERIAL HOST INTERFACE (SHI) SPI PROTOCOL TIMING

Specifications

(CL = 50 pF; V

= 0.7 × VCC, V

IHS

Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing

No. Characteristics Mode

Tolerable Spike Width on Clock or Data In

141 Minimum Serial Clock

Cycle = t For frequency below 33

MHz For frequency above 33

MHz

CPHA = 0, CPHA = 12

CPHA = 1

142 Serial Clock High Period

CPHA = 0, CPHA = 12

CPHA = 1

143 Serial Clock Low Period

CPHA = 0, CPHA = 1

CPHA = 1

144 Serial Clock Rise/Fall

Time

SPICC

(min)

master

slave

master

slave

master

slave

master

slave

Filter

Mode

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

= 0.3 × VCC)

ILS

Expression

4 × T 6 × T

1000 2000

3 × T 3 × TC + 25 3 × TC + 85 3 × TC + 79

3 × TC + 431

3 × TC + 1022

0.5 × t

SPICC

TC + 8 TC + 31 TC + 43

TC + TH + 40 TC + TH + 216 TC + TH + 511

0.5 × t

SPICC

TC + 8 TC + 31 TC + 43

TC + TH + 40 TC + TH + 216 TC + TH + 511

2000

50 MHz 66 MHz 88 MHz

Min Max Min Max Min Max

—

100

—

100

—

120

—

1000

—

–10

2000

85 145 139 491

1082

70 246 541

— — — — — — —

—

— — — — — —

—

— — — — — —

1000 2000

1067

70 130 124 476

63 239 534

— — — — — — — —

—

— — — — — —

—

— — — — — —

——10

2000——102000——102000nsns

— — —

—

68.2 1000 2000

34.1

59.1

119.1

113.1

465.1

1056.1

24.1

19.4

42.4

54.4

57.0

233.0

528.0

24.1

19.4

42.4

54.4

57.0

233.0

528.0

100

—

— — — — — — — — —

—

— — — — — —

—

— — — — — —

Unit

ns ns ns

ns ns ns ns ns ns ns ns ns

ns ns ns ns ns ns

MOTOROLA DSP56007/D 2-23

Specifications Serial Host Interface (SHI) SPI Protocol Timing

Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued)

No. Characteristics Mode

146 SS Assertion to First

slave

SCK Edge CPHA = 0

CPHA = 1

147 Last SCK Edge to SS Not

slave

slave Asserted CPHA = 0 CPHA = 1

148 Data In Valid to SCK

slave

master Edge (Data In Set-up Time)

slave

149 SCK Edge to Data In Not

master Valid (Data In Hold Time)

slave

150 SS Assertion to Data Out

slave 4 4—4— 4 —ns

Active

151 SS Deassertation to Data

high impedance

152 SCK Edge to Data Out

slave 24 — 24 — 24 — 24 ns

master Valid (Data Out Delay Time) CPHA = 0, CPHA = 12

CPHA = 1

slave

Filter

Mode

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

Expression

TC + TH + 35 TC + TH + 35 TC + TH + 35

6 0 0

TC + 6

+ 70

TC + 197

193

0 MAX {(37 –TC), 0} MAX {(52 –TC), 0}

0 MAX {(38 –TC), 0} MAX {(53 –TC), 0}

2 × TC + 17 2 × TC + 18 2 × TC + 28 2 × TC + 17 2 × TC + 18 2 × TC + 28

41 214 504

TC + TH + 40 TC + TH + 216 TC + TH + 511

50 MHz 66 MHz 88 MHz

Min Max Min Max Min Max

—

— 65 65

6 0 0

26 90

217

193

33 57

58 68 57 58 68

— — — — — — — — —

— — — — —

— — — — — —

— —

—

— —

— — — — —

41 214 504

70 246 541

58 58

6 0 0

21 85

212

193

38 47

48 58 47 48 58

— — — — — — — — —

— — — — —

— — — — — —

— —

—

— —

— — — — —

41 214 504

63 239 534

52.0

17.4

81.4

208.4

193

25.6

40.6

26.6

41.6

39.7

40.7

50.7

39.7

40.7

50.7

— — — — — — — — —

— — —

—

— —

— — —

— —

—

— —

— — — — —

41 214 504

57.0 233 528

Unit

ns ns ns ns ns ns

ns ns

ns ns ns ns ns

ns ns ns ns ns ns ns ns ns

2-24 DSP56007/D MOTOROLA

Specifications

Serial Host Interface (SHI) SPI Protocol Timing

Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued)

50 MHz 66 MHz 88 MHz

Min Max Min Max Min Max

—

163

— — — — —

163

— — — — — —

163

— — — — — —

Unit

ns ns ns ns ns ns

No. Characteristics Mode

153 SCK Edge to Data Out

master Not Valid (Data Out Hold Time)

slave

154 SS Assertion to Data Out

slave TC + TH + 35 — 65 — 58 — 52.0 ns

Filter

Mode

bypassed

narrow

wide

bypassed

narrow

wide

Expression

163

Valid CPHA = 0

157 First SCK Sampling

Edge to HREQ

Output

Deassertation

158 Last SCK Sampling Edge

to HREQ Output Not Deasserted

slave bypassed

narrow

wide

slave bypassed

narrow

wide

3 × TC + TH + 32 3 × TC + TH + 209 3 × TC + TH + 507

2 × TC + TH + 6

2 × TC + TH + 63 2 × TC + TH + 169

— — —

56 113 219

102 279 577

— — —

44 101 207

85 262 560

—

— — —

34.4

91.4

197.4

71.8

248.8

546.8 —

— —

ns ns ns

CPHA = 1

159 SS Deassertation to

slave 2 × TC + TH + 7 57 45 35.4 ns

HREQ Output Not Deasserted CPHA = 0

160 SS Deassertation Pulse

slave TC + 4 24 — 19 — 15.4 — ns

Width CPHA = 0

161 HREQ In Assertion to

First SCK Edge

162 HREQ In Deassertation

master 0.5 × t

SPICC

106 — 82 — 62.8 — ns

2 × TC + 6

master 0 0—0— 0 —ns to Last SCK Sampling Edge (HREQ In Set-up Time) CPHA = 1

163 First SCK Edge to HREQ

master 0 0—0— 0 —ns In Not Asserted (HREQ In Hold Time)

Note: 1. For an Internal Clock frequency below 33 MHz, the minimum permissible Internal Clock to Serial Clock frequency

ratio is 4:1. For an Internal Clock frequency above 33 MHz, the minimum permissible Internal Clock to Serial Clock frequency ratio is 6:1.

2. In CPHA = 1 mode, the SPI slave supports data transfers at t written at least transfers at t SCK of each word.

3. When CPHA = 1, the SS

4. Periodically sampled, not 100% tested

5. Refer to the modes.

ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave supports data

= 3 × TC, if the user assures that the HTX is written at least T

SPICC

line may remain active low between successive transfers.

DSP56007 User’s Manual

for a detailed description of how to use the different filtering

SPICC

= 3 × T

, if the user assures that the HTX is

ns before the first edge of

MOTOROLA DSP56007/D 2-25

Specifications Serial Host Interface (SHI) SPI Protocol Timing

(Input)

143

142

SCK (CPOL = 0)

(Output)

141

144 144

SCK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

HREQ

(Input)

161

142

143

144

148

149

MSB

Valid

148

152 153

MSB LSB

163

Figure 2-17 SPI Master Timing (CPHA = 0)

141

144

149

LSB

Valid

AA0271

2-26 DSP56007/D MOTOROLA

(Input)

SCK (CPOL = 0)

(Output)

142

143

Specifications

Serial Host Interface (SHI) SPI Protocol Timing

141

144 144

SCK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

HREQ

(Input)

142

143

144

148 148

149

MSB Valid

152 153

MSB LSB

161

162

163

Figure 2-18 SPI Master Timing (CPHA = 1)

141

144

149

LSB

Valid

AA0272

MOTOROLA DSP56007/D 2-27

Specifications Serial Host Interface (SHI) SPI Protocol Timing

(Input)

143

142

SCK (CPOL = 0)

(Input)

144 144

141

147

160

SCK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

HREQ

(Output)

150

146

154

142

153

143

152

144

153

MSB LSB

148

149

MSB Valid

Figure 2-19 SPI Slave Timing (CPHA = 0)

141

144

151

149

LSB

Valid

159157

AA0273

2-28 DSP56007/D MOTOROLA

(Input)

Specifications

Serial Host Interface (SHI) SPI Protocol Timing

SCK (CPOL = 0)

(Input)

SCK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

HREQ

(Output)

150

143

146

152

142

143

152

144 144

144

153

MSB LSB

148

149

MSB LSB Valid Valid

157

Figure 2-20 SPI Slave Timing (CPHA = 1)

141

148

147

144

151

149

158

AA0274

MOTOROLA DSP56007/D 2-29

Specifications Serial Host Interface (SHI) I2C Protocol Timing

SERIAL HOST INTERFACE (SHI) I2C PROTOCOL TIMING

= 0.7 × VCC, V

IHS

= 0.3 × VCC)

ILS

= 0.8 × VCC, V

OHS

(min) = 1.5 kΩ)

= 0.2 × VCC)

OLS

Table 2-13 SHI I

C Protocol Timing

Standard I2C

(CL = 400 pF, RP = 2 kΩ, 100 kHz)

No. Characteristics Symbol

— Tolerable Spike Width on SCL or SDA

Filters Bypassed Narrow Filters Enabled

Wide Filters Enabled 171 Minimum SCL Serial Clock Cycle t 172 Bus Free Time t 173 Start Condition Set-up Time t 174 Start Condition Hold Time t 175 SCL Low Period t 176 SCL High Period t

SCL

BUF

SU;STA

HD;STA

LOW

HIGH

177 SCL and SDA Rise Time t 178 SCL and SDA Fall Time t 179 Data Set-up Time t 180 Data Hold Time t 182 SCL Low to Data Out Valid t 183 Stop Condition Set-up Time t

Note: Refer to the

modes.

DSP56007 User’s Manual

for a detailed description of how to use the different filtering

SU;DAT

HD;DAT

VD;DAT

SU;STO

All frequencies

Unit

Min Max

— — —

100

ns ns ns

10.0 — µs

4.7 — µs

4.0 — µs

4.7 — µs

4.0 — µs

— 1.0 µs — 0.3 µs

250 — ns

0.0 — ns

— 3.4 µs

4.0 — µs

2-30 DSP56007/D MOTOROLA

Specifications

Serial Host Interface (SHI) I2C Protocol Timing

The Programmed Serial Clock Cycle, t

, is specified by the value of the HDM5–

I2CCP

HDM0 and HRS bits of the HCKR (SHI Clock control Register).

The expression for t

I2CCP

is:

I2CCP

Tc 2× HDM[5:0] 1+()× 7 1 HRS–()× 1+()×[]=

where

• HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-byeight prescaler is operational. When HRS is set, the prescaler is bypassed.

• HDM5–HDM0 are the Divider Modulus Select bits.

• A divide ratio from 1 to 64 (HDM5–HDM0 = 0 to $3F) may be selected.

C mode, you may select a value for the Programmed Serial Clock Cycle from

In I

6 × 1024 ×

The DSP56007 provides an improved I 100 kHz I kHz. The actual maximum frequency is limited by the bus capacitances (C up resistors (R

(HDM5–HDM0 = 2, HRS = 1) to

(HDM5–HDM0 = $3F, HRS = 0).

C bus protocol, the SHI in I2C mode supports data transfers at up to 1000

), (which affect the rise and fall time of SDA and SCL, (see table

C bus protocol. In addition to supporting the

),the pull-

below)), and by the input filters.

Consideration for programming the SHI Clock Control Register (HCKR)—Clock Divide Ratio: the master must generate a bus free time greater than T172 slave when

operating with a DSP56007 SHI I

The table below describes a few examples

C slave.

Table 2-14 Considerations for Programming the SHI Clock control Register (HCKR)

Conditions to be Considered Resulting Limitations

Bus Load

CL = 50 pF,

RP = 2 kΩ

Master

Oper-

ating Freq.

88 MHz 88 MHz Bypassed

Slave

Oper-

ating Freq.

Master

Filter

Mode

Narrow

Wide

Slave Filter

Mode

Bypassed

Narrow

Wide

T172

Slave

36 ns 60 ns 95 ns

Min.

Perm-

issible

I2CCP

56 × T 60 × T 66 × T

C C C

T172

Master

41 ns 66 ns

103 ns

Maximum

I2C Serial

Frequency

1010 kHz

825 kHz 634 kHz

MOTOROLA DSP56007/D 2-31

Specifications Serial Host Interface (SHI) I2C Protocol Timing

Example: for CL = 50 pF, RP = 2 kΩ, f = 88 MHz, Bypassed Filter mode: The master, when operating with a DSP56007 SHI I must generate a bus free time greater than 36 ns (T172 slave). Thus, the minimum permissible t

is 56 × TC which gives a bus free time of at least 41 ns (T172 master).

I2CCP

This implies a maximum I

In general, bus performance may be calculated from the C Input Filter modes and operating frequencies of the master and the slave. Table 2-15 contains the expressions required to calculate all relevant performance timing for a given C

and RP.

Table 2-15 SHI Improved I

Improved I2C (CL = 50 pF, RP = 2 kΩ)

No. Char. Sym. Mode

— Tolerable Spike

Width on SCL or SDA

171 SCL Serial Clock

Cycle

172 Bus Free Time t

SCL

BUF

master

slave

master

slave

C slave with an 88 MHz operating frequency,

C serial frequency of 1010 kHz.

C Protocol Timing

Filter

Mode

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

Expression

100

+ 3 × TC+

I2CCP

72 + t

I2CCP

+ 3 × TC +

245 + t

+ 3 × TC +

535 + t

4 × TC + TH +

172 + t

4 × TC + TH +

366 + t

4 × TC + TH +

648 + t

0.5 × t

I2CCP

42 – t

I2CCP

42 – t

I2CCP

42 – t

0.5 × t

0.5 × t 2 × TC + 11

2 × TC + 35 2 × TC + 70

–

and RP of the bus, the

50 MHz266 MHz388 MHz4U

Min Max Min Max Min Max

—

0 — —

1050

1263

1593

500

694

976

100

51 75

110

100

—

— — —

— —

1007

1225

1591

478

672

954

102

41 65

100

—

— — —

981

1199

1557

461

655

937

38.2

60.9

33.7

57.7

92.7

100

—

— — —

i t

ns ns ns

173 Start Condition

Set-up Time

SU;STA

slave bypassed

narrow

wide

12 50

150

12 50

150

— — —

12 50

150

— — —

12 50

150

2-32 DSP56007/D MOTOROLA

— — —

ns ns ns

Table 2-15 SHI Improved I2C Protocol Timing (Continued)

Improved I2C (CL = 50 pF, RP = 2 kΩ)

No. Char. Sym. Mode

174 Start Condition

Hold Time

HD;STA

master

slave

Filter

Mode

bypassed

narrow

wide

bypassed

narrow

wide

Specifications

Serial Host Interface (SHI) I2C Protocol Timing

50 MHz266 MHz388 MHz4U

Expression

Min Max Min Max Min Max

332

—

318

340

378

59 138 238

—

— — —

49.4

0.5 × t

12 – t

0.5 × t

12 – t

0.5 × t

12 – t

I2CCP

2 × TC + TH + 21 2 × TC + TH + 100 2 × TC + TH + 200

352

372

71 150 250

—

— — —

310

333

367

128 228

—

— — —

i t

ns ns ns

175 SCL Low Period t

176 SCL High Period t

177 SCL Rise Time

Output

Input

178 SCL Fall Time

Output

Input

LOW

HIGH

master

slave

master

slave

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

bypassed

narrow

wide

0.5 × t

18 – t

0.5 × t

18 – t

0.5 × t

18 – t

I2CCP

2 × TC + 74 + t 2 × TC + 286 + t 2 × TC + 586 + t

0.5 × t

I2CCP

+ 2 ×

TC + 19

0.5 × t

I2CCP

2 × TC + 144

0.5 × t

I2CCP

2 × TC + 356

2 × TC + TH – 1

2 × TC + TH + 18 2 × TC + TH + 30

1.7 × RP ×

(CL + 20)

2000

20 + 0.1 ×

(CL– 50)

2000

r r

338

—

324

—

316

358

378

352 564 864

379

544

776

49 68 80

——238

2000——

— — — — —

—

— — —

346

384

342 554 854

375

523

773

37 56 68

— —

339 — —

373 —

335

534

847 —

360

—

507

—

754

—

27.4

—

46.4

—

58.4

238

2000——

——20

2000——202000——202000nsns

—

238

2000nsns

179 Data Set-up Time t

SU;DAT

bypassed

narrow

wide

TC + 8 TC + 60 TC + 74

28 80 94

— — —

23 75 89

— — —

19.4

71.4

85.4

MOTOROLA DSP56007/D 2-33

— — —

ns ns ns

Specifications Serial Host Interface (SHI) I2C Protocol Timing

Table 2-15 SHI Improved I2C Protocol Timing (Continued)

Improved I2C (CL = 50 pF, RP = 2 kΩ)

No. Char. Sym. Mode

Filter

Mode

Expression

50 MHz266 MHz388 MHz4U

Min Max Min Max Min Max

i t

180 Data Hold Time t

182 SCL Low to Data

Out Valid

183 Stop Condition

Set-up Time

184 HREQ In

Deassertation to Last SCL Edge (HREQ In Set-up Time)

186 First SCL

Sampling Edge to HREQ Output Deassertation

HD;DAT

VD;DAT

SU;STO

bypassed

narrow

wide

bypassed

narrow

wide

master

bypassed

narrow

wide

slave

bypassed

narrow

wide

master bypassed

narrow

wide

slave bypassed

narrow

wide

0 0 0

2 × TC + 71 + t

2 × TC + 244 + t 2 × TC + 535 + t

0.5 × t

I2CCP

TC + TH + 11

0.5 × t

I2CCP

TC + TH + 69

0.5 × t

I2CCP

TC + TH + 183

11 50

150

0 0 0

3 × TC + TH + 32 3 × TC + TH + 209 3 × TC + TH + 507

—

349

—

339

—

332

—

522

—

512

—

505

—

813

—

803

—

— — —

85 262 560

—

346

427

575

11 50

150

0 0 0

— — —

381

—

359

459

—

440

613

—

592

—

150

—

150

—

102

—

279

—

577

—

796

—

— — —

72 249 547

ns ns

ns ns ns

187 Last SCL Edge to

HREQ Output Not Deasserted

188 HREQ In

Assertion to First SCL Edge

189 First SCL Edge

slave bypassed

narrow

wide

master bypassed

narrow

wide

2 × TC + TH + 6

2 × TC + TH + 63

2 × TC + TH + 169

+ 2 × TC + 6

I2CCP

+ 2 × TC + 6

I2CCP

+ 2 × TC + 6

I2CCP

56 113 219

726 766 846

— — —

44 101 207

688 733 809

— — —

34.4

91.4

197.4 665

711 779

master 0 0—0— 0 —ns to HREQ In Not Asserted (HREQ In Hold Time)

2-34 DSP56007/D MOTOROLA

— — —

ns ns ns

Specifications

Serial Host Interface (SHI) I2C Protocol Timing

Table 2-15 SHI Improved I

Improved I2C (CL = 50 pF, RP = 2 kΩ)

No. Char. Sym. Mode

Note: 1. CL is in pF, RP is in kΩ, and result is in ns.

2. A t Bypassed Filter mode. A t Narrow Filter mode. A t Filter mode.

3. A t Bypassed Filter mode. A t Narrow Filter mode. A t Filter mode.

4. A t Bypassed Filter mode. A t Narrow Filter mode. A t Filter mode.

5. Refer to the modes.

I2CCP

of 34 × T of 36 × T of 40 × T of 43 × T of 46 × T of 51 × T of 56 × T of 60 × T of 66 × T

(the maximum permitted for the given bus load) was used for the calculations in the

(the maximum permitted for the given bus load) was used for the calculations in the Wide

(the maximum permitted for the given bus load) was used for the calculations in the

(the maximum permitted for the given bus load) was used for the calculations in the Wide

(the maximum permitted for the given bus load) was used for the calculations in the

(the maximum permitted for the given bus load) was used for the calculations in the Wide

DSP56007 User’s Manual

Filter

Mode

C Protocol Timing (Continued)

50 MHz266 MHz388 MHz4U

Expression

Min Max Min Max Min Max

for a detailed description of how to use the different filtering

i t

SCL

SDA

HREQ

171

173 176 175

177

172

179

Stop

Start

174

189

188

Figure 2-21 I2C Timing

178

180

ACKMSB LSB

186 182 183

184

187

Stop

AA0275

MOTOROLA DSP56007/D 2-35

Specifications General Purpose I/O (GPIO) Timing

GENERAL PURPOSE I/O (GPIO) TIMING

(CL = 50 pF + 2 TTL Loads)

Table 2-16 GPIO Timing

50/66/88 MHz

No. Characteristics Expression

Min Max

201 EXTAL Edge to GPIO Out Valid (GPIO Out Delay Time) 26 — 26 ns

Unit

202 EXTAL Edge to GPIO Out Not Valid (GPIO Out Hold

Time) 203 GPIO In Valid to EXTAL Edge (GPIO In Set-up Time) 10 10 — ns 204 EXTAL Edge to GPIO In Not Valid (GPIO In Hold Time) 6 6 — ns

EXTAL

(Input)

(Note 1)

GPIO(0:3)

(Output)

204203

GPIO(0:3)

(Input)

Note: 1. Valid when the ratio between EXTAL frequency and internal clock frequency equals 1

Valid

22—ns

201

202

AA0276

Figure 2-22 GPIO Timing

2-36 DSP56007/D MOTOROLA

ON-CHIP EMULATION (OnCE) TIMING

(CL = 50 pF + 2 TTL Loads)

Table 2-17 OnCE Timing

No. Characteristics

Specifications

On-Chip Emulation (OnCE) Timing

50/66/88 MHz

Unit

Min Max

230 DSCK Low 231 DSCK High 40 — ns

232 DSCK Cycle Time 200 — ns 233 DR 234 DSCK High to DSO Valid — 42 ns 235 DSCK High to DSO Invalid 3 — ns 236 DSI Valid to DSCK Low (Set-up) 15 — ns 237 DSCK Low to DSI Invalid (Hold) 3 — ns 238 Last DSCK Low to OS0–OS1, ACK Active 3 TC + T 239 DSO (ACK) Asserted to First DSCK High 2 T 240 DSO (ACK) Assertion Width 4 TC + TH – 3 5 TC + 7 ns 241 DSO (ACK) Asserted to OS0–OS1 High

242 OS0–OS1 Valid to EXTAL Transition #2 TC – 21 — ns

Asserted to DSO (ACK) Asserted 5 T

Impedance

40 — ns

—0ns

—ns

—ns —ns

243 EXTAL Transition #2 to OS0–OS1 Invalid 0 — ns 244 Last DSCK Low of Read Register to First DSCK

High of Next Command 245 Last DSCK Low to DSO Invalid (Hold) 3 — ns 246 DR Assertion to EXTAL Transition #2 for Wake

Up from WAIT State 247 EXTAL Transition #2 to DSO After Wake Up from

WAIT State

7 TC + 10 — ns

10 TC – 10 ns

17 T

—ns

MOTOROLA DSP56007/D 2-37

Specifications On-Chip Emulation (OnCE) Timing

Table 2-17 OnCE Timing (Continued)

No. Characteristics

248 DR Assertion Width

• to recover from WAIT

• to recover from WAIT and enter Debug mode

50/66/88 MHz

Min Max

13 TC + 15

12 TC – 15

—

Unit

ns ns

249 DR Assertion to DSO (ACK) Valid (Enter Debug

mode) After Asynchronous Recovery from WAIT State

250A DR

Assertion Width to Recover from STOP2

• Stable External Clock, OMR Bit 6 = 0

• Stable External Clock, OMR Bit 6 = 1

• Stable External Clock, PCTL Bit 17 = 1

250B DR Assertion Width to Recover from STOP and

enter Debug mode

• Stable External Clock, OMR Bit 6 = 0

• Stable External Clock, OMR Bit 6 = 1

• Stable External Clock, PCTL Bit 17 = 1

251 DR Assertion to DSO (ACK) Valid (Enter Debug

mode) After Recovery from STOP State

• Stable External Clock, OMR Bit 6 = 0

• Stable External Clock, OMR Bit 6 = 1

• Stable External Clock, PCTL Bit 17 = 1

Note: 1. Maximum T

2. Periodically sampled, not 100% tested

17 T

15 15 15

65549 TC + T

21 TC + T 14 TC + T

65553 TC + T

25 TC + T 18 TC + T

L L L

—ns

65548 TC + T

20 TC + T 13 TC + T

— — —

L L

ns ns

ns ns ns

246 246

230

DSCK (input)

231

232

AA0277

Figure 2-23 DSP56007 OnCE Serial Clock Timing

2-38 DSP56007/D MOTOROLA

(Input)

Specifications

On-Chip Emulation (OnCE) Timing

233 240

DSO

(Output)

Figure 2-24 DSP56007 OnCE Acknowledge Timing

DSCK

(Input)

DSO

(Output)

236 237 238

DSI

(Input)

Note: 1. High Impedance, external pull-down resistor

(Last)

Figure 2-25 DSP56007 OnCE Data I/O to Status Timing

DSCK

(Input)

DSO

(Output)

234

235 245

(Last)

ACK

(Note 1)

(OS1)

ACK)

(

(OS0)

(Note 1)

(OS0)

AA0278

AA0279

Note: 1. High Impedance, external pull-down resistor

AA0280

Figure 2-26 DSP56007 OnCE Read Timing

240

239

(Note 1)

(DSCK Input)

(DSO Output)

(DSI Input)

AA0281

OS1

(Output)

241

DSO

(Output)

OS0

(Output)

241 236 237

Note: 1. High Impedance, external pull-down resistor

Figure 2-27 DSP56007 OnCE Data I/O Status Timing

MOTOROLA DSP56007/D 2-39

Specifications On-Chip Emulation (OnCE) Timing

EXTAL

(Note 2)

242

OS0–OS1

(Output)

(Note 1)

243

Note: 1. High Impedance, external pull-down resistor

2. Valid when the ratio between EXTAL frequency and clock frequency equals 1

Figure 2-28 DSP56007 OnCE EXTAL to Status Timing

DSCK (Input)

(Next Command)

244

Figure 2-29 DSP56007 OnCE DSCK Next Command After Read Register Timing

EXTAL

T0, T2 T1, T3

AA0282

AA0283

(Input)

DSO

(Output)

(Input)

DSO

(Output)

248

246 247

AA0284

Figure 2-30 Synchronous Recovery from WAIT State

248

249

AA0285

Figure 2-31 Asynchronous Recovery from WAIT State

2-40 DSP56007/D MOTOROLA

(Input)

DSO

(Output)

Specifications

On-Chip Emulation (OnCE) Timing

250

251

AA0286

Figure 2-32 Asynchronous Recovery from STOP State

MOTOROLA DSP56007/D 2-41

Specifications On-Chip Emulation (OnCE) Timing

2-42 DSP56007/D MOTOROLA

SECTION 3

PACKAGING

PIN-OUT AND PACKAGE INFORMATION

This section provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56007 is available in an 80-pin Quad Flat Pack (QFP) package.

MOTOROLA DSP56007/D 3-1

Packaging Pin-out and Package Information

QFP Package Description

Top and bottom views of the QFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs.

DR MD7 MD6 MD5 MD4

GND

MD3 MD2 MD1

CCD

MD0

GND GPIO3 GPIO2 GPIO1 GPIO0

MRD

MWR MA17/MCS1/MRAS MA16/MCS2/MCAS

DSCK/OS1

DSI/OS0

DSO

SDI0

SDI1

WSR

GNDSV

CCQ

GNDQSCKR

(Top View)

Orientation Mark

GND

MCS0

MA14

MA13

CCA

MA12

GND

CCQ

GND

WST

SCKT

MA11

MA10

CCS

MA9

SDO0

SDO1

MA8

GND

SDO2

GNDSHREQ

CCA

MA7

MA6

SS/HA2

MA5

MOSI/HA0

MA4

CCS

MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA GND

CCP

PCAP GND

PINIT GND

CCQ

EXTAL SCK/SCL MA0 MA1 MA2 MA3 GND

MA15/MCS3

Note: An OVERBAR indicates the signal is asserted when the

voltage = ground (active low). To simplify locating the pins, each fifth pin is shaded in the illustration.

Figure 3-1 Top View

3-2 DSP56007/D MOTOROLA

GND

HREQ

SS/HA2

MOSI/HA0

SDO1

SDO2

CCS

SDO0

WST

SCKT

GND

SCKR

CCQ

GND

SDI1

WSR

Packaging

Pin-out and Package Information

DSCK/OS1

DSI/OS0

DSO

SDI0

CCS

MODC/NMI MODB/IRQB MODA/IRQA

RESET

MISO/SDA

GND

CCP

PCAP

GNDP

PINIT

GND

CCQ

EXTAL

SCK/SCL

MA0 MA1 MA2 MA3

GND

Note: An OVERBAR indicates the signal is asserted when the

DR MD7

(Bottom View)

MD6 MD5 MD4 GND

MD3 MD2 MD1 V

CCD

MD0 GND

GPIO3 GPIO2 GPIO1 GPIO0 MRD

Orientation Mark

MA4

MA5

MA6

CCA

MA7

GND

MA8

MA9

MA11

MA10

GND

CCQ

MA12

GND

CCA

MA14

MA13

MCS0

MWR MA17/MCS1/MRAS MA16/MCS2/MCAS

GND

MA15/MCS3

voltage = ground (active low). To simplify locating the pins, each fifth pin is shaded in the illustration.

Figure 3-2 Bottom View

MOTOROLA DSP56007/D 3-3

Packaging Pin-out and Package Information

Table 3-1 DSP56007 Pin Identification by Pin Number

Pin # Signal Name Pin # Signal Name Pin # Signal Name

1 GND

2 MCS0 29 GND

28 V

CCQ

55 WSR

56 SDI1 3 MA15/MCS3 30 PINIT 57 SDI0 4 MA14 31 GND

58 DSO 5 MA13 32 PCAP 59 DSI/OS0 6V

CCA

7 MA12 34 GND 8 GND 9V 10 GND

CCQ

33 V

CCP

60 DSCK/OS1

61 DR

35 MISO/SDA 62 MD7 36 RESET 63 MD6

37 MODA/IRQA 64 MD5 11 MA11 38 MODB/IRQB 65 MD4 12 MA10 39 MODC/NMI 66 GND 13 MA9 40 V

CCS

67 MD3

14 MA8 41 MOSI/HA0 68 MD2 15 GND

16 MA7 43 HREQ 70 V 17 V

CCA

18 MA6 45 SDO2 72 GND

42 SS/HA2 69 MD1

CCD

44 GND

71 MD0

19 MA5 46 SDO1 73 GPIO3 20 MA4 47 SDO0 74 GPIO2 21 GND

48 V

CCS

75 GPIO1 22 MA3 49 SCKT 76 GPIO0 23 MA2 50 WST 77 MRD 24 MA1 51 SCKR 78 MWR 25 MA0 52 GND

79 MA17/MCS1/

MRAS

26 SCK/SCL 53 V

CCQ

80 MA16/MCS2/

MCAS

27 EXTAL 54 GND

3-4 DSP56007/D MOTOROLA

Packaging

Pin-out and Package Information

Table 3-2 DSP56007 Pin Identification by Signal Name

Signal Name Pin # Signal Name Pin # Signal Name Pin #

DR 61 MA5 19 MRD 77

DSCK 60 MA6 18 MWR 78

DSI 59 MA7 16 NMI 39

DSO 58 MA8 14 OS0 59

EXTAL 27 MA9 13 OS1 60

GND

GPIO0 76 MD0 71 SS 42 GPIO1 75 MD1 69 V GPIO2 74 MD2 68 V GPIO3 73 MD3 67 V

HA0 41 MD4 65 V HA2 42 MD5 64 V

HREQ 43 MD6 63 V

IRQA 37 MD7 62 V

IRQB 38 MISO 35 V

MA0 25 MODA 37 V MA1 24 MODB 38 WSR 55 MA2 23 MODC 39 WST 50 MA3 22 MOSI 41 MA4 20 MRAS 79

1 MA10 12 PCAP 32

8 MA11 11 PINIT 30 15 MA12 7 RESET 36 21 MA13 5 SCK 26 66 MA14 4 SCKR 51 72 MA15 3 SCKT 49 31 MA16 80 SCL 26 10 MA17 79 SDA 35 29 MCAS 80 SDI0 57 52 MCS0 2 SDI1 56 34 MCS1 79 SDO0 47 44 MCS2 80 SDO1 46 54 MCS3 3 SDO2 45

CCA CCA CCD

CCP CCQ CCQ CCQ

CCS

17 70 33

28 53 40 48

MOTOROLA DSP56007/D 3-5

Packaging Pin-out and Package Information

Table 3-3 DSP56007 Power Supply Pins

Pin # Signal Name Circuit Supplied

CCA

17 1 GND

8 15 21 70 V 66 GND

CCD

72 9V

CCQ

28 53 10 GND

29 52

Address Bus Buffers

Data Bus Buffers

Internal Logic

33 V

CCP

31 GND 40 V

CCS

48 34 GND 44 54

PLL

Serial Ports

3-6 DSP56007/D MOTOROLA

Packaging

Pin-out and Package Information

-C-

SEATING PLANE

DATUM PLANE

-A-

-H-

S S

-B-

C A-B D

DETAIL A

120

-DA

0.20 A-B D

0.05

A-B

S SM

A-B

0.05

0.20

0.20 A-B D

DETAIL C

DATUM

-H-

PLANE

0.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE

BOTTOM OF THE PARTING LINE.

4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-.

5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.

H A-B D

MSS

0.20

B B

DETAIL A

SECTION B-B

CASE 841B-01

DIM

A B C D E F

H J K L

N P

R S T U V

A-B D

ISSUE O

MILLIMETERS

MIN MAX

13.90

2.15

0.22

2.00

0.22

0.65 BSC

0.13

0.65

12.35 BSC

0.13

0.325 BSC

0.13

16.95

0.13 05

16.95

0.35

1.6 REF

-A,B,D-

S S

14.10

2.45

0.38

2.40

0.33

0.25

0.23

0.95 105

0.17 75

0.30

17.45

0.45

Figure 3-3 80-pin Quad Flat Pack (QFP) Mechanical Information

MOTOROLA DSP56007/D 3-7

Packaging Ordering Drawings

ORDERING DRAWINGS

Complete mechanical information regarding DSP56007 packaging is available by facsimile through Motorola's Mfax™ system. Call the following number to obtain information by facsimile:

The Mfax automated system requests the following information:

• The receiving facsimile telephone number including area code or country code

• The caller’s Personal Identification Number (PIN)

Note: For first time callers, the system provides instructions for setting up a PIN,

which requires entry of a name and telephone number.

(602) 244-6591

• The type of information requested: – Instructions for using the system – A literature order form – Specific part technical information or data sheets – Other information described by the system messages

A total of three documents may be ordered per call.

The DSP56007 80-pin QFP package mechanical drawing is referenced as 841B-01.

3-8 DSP56007/D MOTOROLA

SECTION 4

DESIGN CONSIDERATIONS

THERMAL DESIGN CONSIDERATIONS

An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:

Equation 1:

TJTAPDR

×()+=

θJA

Where:

= ambient temperature ˚C

= package junction-to-ambient thermal resistance ˚C/W

θJA

= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:

Equation 2:

θJA

θJCRθCA

Where:

= package junction-to-ambient thermal resistance ˚C/W

θJA

= package junction-to-case thermal resistance ˚C/W

θJC

= package case-to-ambient thermal resistance ˚C/W

θCA

is device-related and cannot be influenced by the user. The user controls the

θJC

thermal environment to change the case-to-ambient thermal resistance, R

θCA

. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool.

MOTOROLA DSP56007/D 4-1

Design Considerations Thermal Design Considerations

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from

do not satisfactorily answer whether the thermal performance is adequate, a

θJA

system level model may be appropriate.

A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages:

• To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink.

• To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case.

• If the temperature of the package case (T

) is determined by a thermocouple,

the thermal resistance is computed using the value obtained by the equation

– TT)/PD.

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, Thermal Characterization Parameter or Ψ

, has been defined to be (TJ – TT)/PD. This value gives a better

estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

4-2 DSP56007/D MOTOROLA

ELECTRICAL DESIGN CONSIDERATIONS

CAUTION

This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or V

Use the following list of recommendations to assure correct DSP operation:

Design Considerations

Electrical Design Considerations

• Provide a low-impedance path from the board power supply to each V

pin on the DSP, and from the board ground to each GND pin.

• Use at least four 0.01–0.1 µF bypass capacitors positioned as close as

possible to the four sides of the package to connect the V

power source

to GND.

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

and GND pins are less than 0.5 in per capacitor

lead.

• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V

and GND.

• Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA

, IRQB, and NMI pins. Maximum Printed Circuit Board (PCB) trace lengths on the order of 6 inches are recommended.

• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the V

and GND circuits.

• All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except as noted in Section 1.

• Take special care to minimize noise levels on the V

and GNDP pins.

CCP

• If multiple DSP56007 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices.

MOTOROLA DSP56007/D 4-3

Design Considerations Power Consumption Considerations

POWER CONSUMPTION CONSIDERATIONS

Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is Alternating Current (AC), which is charging and discharging the capacitances of the pins and internal nodes.

Current consumption is described by the formula:

Equation 3:

I CVf××=

where: C = node/pin capacitance in farads

V = voltage swing f = frequency of node/pin toggle in hertz

Example 4-1 Current Consumption

For an I/O pin loaded with 50 pF capacitance, operating at 5.25 V, and with a 88 MHz clock, toggling at its maximum possible rate (22 MHz), the current consumption is:

Equation 4:

I5010

The Maximum Internal Current (I

12–

× 5.25× 22× 106× 5.78mA==

max) value reflects the typical possible

CCI

switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The Typical Internal Current (I

CCItyp

) value

reflects the average switching of the internal buses on typical operating conditions.

For applications that require very low current consumption:

• Minimize the number of pins that are switching.

• Minimize the capacitive load on the pins.

• Connect the unused inputs to pull-up or pull-down resistors.

• Disable unused peripherals.

• Disable unused pin activity.

4-4 DSP56007/D MOTOROLA

Current consumption test code:

org p:RESET

jmp MAIN org p:MAIN movep #$180000,x:$FFFD move #0,r0 move #0,r4 move #$00FF,m0 move #$00FF,m4 nop rep #256 move r0,x:(r0)+ rep #256 mov r4,y:(r4)+ clr a move l:(r0)+,a rep #30 mac x0,y0,a x:(r0)+,x0 y:(r4)+,y0 move a,p:(r5) jmp TP1

TP1 nop

jmp MAIN

Design Considerations

Power Consumption Considerations

MOTOROLA DSP56007/D 4-5

Design Considerations Power-Up Considerations

POWER-UP CONSIDERATIONS

To power-up the device properly, ensure that the following conditions are met:

• Stable power is applied to the device according to the specifications in Table 2-3 (DC Electrical Characteristics).

• The external clock oscillator is active and stable.

• RESET Mode Select, and Interrupt Timing).

• The following input pins are driven to valid voltage levels: DR MODA, MODB, and MODC.

Care should be taken to ensure that the maximum ratings for all input voltages obey the restrictions on Table 2-1 (Maximum Ratings), at all phases of the power-up procedure. This may be achieved by powering the external clock, hardware reset, and mode selection circuits from the same power supply that is connected to the power supply pins of the chip.

At the beginning of the hardware reset procedure, the device might consume significantly more current than the specified typical supply current. This is because of contentions among the internal nodes being affected by the hardware reset signal until they reach their final hardware reset state.

is asserted according to the specifications in Table 2-7 (Reset, Stop,

, PINIT,

4-6 DSP56007/D MOTOROLA

SECTION 5

ORDERING INFORMATION

Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order.

Table 5-1 Ordering Information

Part

DSPB56007

DSPE56007

Note: 1. The DSPB56007 includes a generic factory-programmed ROM and may be used for RAM-based

applications. For additional information on future part development, or to request specific ROMbased support, call your local Motorola Semiconductor sales office or authorized distributor.

2. The DSPE56007 includes factory-programmed ROM containing support for Dolby Pro Logic and Lucasfilm THX applications. This part can be used only be customers licensed for Dolby Pro Logic and Lucasfilm THX. To request specific support for this chip, call your local Motorola Semiconductor sales office or authorized distributor.

Supply

Voltage

5 V Quad Flat Pack

Package Type Pin Count

(QFP)

80 50 DSPB56007FJ50

80 50 DSPE56007FJ50

Frequency

(MHz)

66 DSPB56007FJ66 88 DSPB56007FJ88

66 DSPE56007FJ66 88 DSPE56007FJ88

Order Number

MOTOROLA DSP56007/D 5-1

OnCE, Mfax, and Symphony are trademarks of Motorola, Inc.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

USA/Europe/Locations Not Listed :

Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 303-675-2140 1 (800) 441-2447

Mfax™ :

RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 US & Canada ONLY (800) 774-1848

Asia/Pacific :

Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298

Technical Resource Center:

1 (800) 521-6274

DSP Helpline

dsphelp@dsp.sps.mot.com

Japan :

Nippon Motorola Ltd. Tatsumi-SPD-JLDC 6F Seibu-Butsuryu-Center 3-14-2 Tatsumi Koto-Ku Tokyo 135, Japan 81-3-3521-8315

Internet :

http://www.motorola-dsp.com

BSS FDS355, FDScomplete 56007 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

TABLE OF CONTENTS

FEATURES

SIGNAL/CONNECTION DESCRIPTIONS

SPECIFICATIONS

PACKAGING

DESIGN CONSIDERATIONS

ORDERING INFORMATION