Benq U102 Schematics
A
ZZZ1
ZZZ1
PCB
PCB
1 1
PJP1
PJP1
45@
45@
DCIN
DCIN
B
C
D
E
Compal Confidential
2 2
KTV00 Schematics Document
Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M
3 3
2009-05-07
REV: 1.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2008/09/20
2006/08/18 2008/09/20
2006/08/18 2008/09/20
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
139Thursday, May 07, 2009
139Thursday, May 07, 2009
139Thursday, May 07, 2009
E
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1.0
1.0
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of
A
B
C
D
E
Compal Confidential
Model Name : KTV00
File Name : LA-5241P
1 1
Thermal Sensor
EMC1402
2 2
Power ON/OFF
& LED & LID
3 3
page 26
DC IN
page 31
BATT IN
page 32
CHARGER
page 33
page 2
DC/DC Interface
3VALW/5VALW
page 29
page 34
1.05VP/1.8VP
page 35
2.5VSP/0.9VSP/1.5VSP
page 36
CPU_CORE
page 37
CRT Conn
page 14
LCD Conn.
page 13
MINI Card x1
page 19
RGB
LVDS
PCI-Express
10/100 Ethernet
RTL 8103EL
page 24
Transformer
page 24
RJ45
page 24
Int.KBD
Diamondville SC
FCBGA8
437Pins
22x22mm
H_A#(3..31) H_D#(0..63)
FSB
400/533MHz
page 4,5
Calistoga GSE
FCBGA998
27x27mm
page 6,7,8,9,10
DMI
X2 mode
ICH7M
BGA652
31x31mm
page 15,16,17,18
LPC BUS
page 27
ENE KBC
KB926 rev.D3
Touch Pad
page 27
SPI
page 25
SPI ROM
Memory BUS(DDRII)
1.8V DDRII 400/533
SATA
SATA HDD CONN
page 22
page 25
Clock Generator
CK505
DDRII-SO-DIMM
USB
HDA
HDA Codec
AMP & INT
Speaker
page 21
page 12
page 11
ALC272
page 20
INT MIC HeadPhone &
page 20
MIC Jack
page 21
USB Port X1
page 28
USB Board X2
page 28
USB Card
Reader X1
RTS5159E
page 23
CMOS CAM
page22
WLAN Card
page19
3G Card
page19
Blue tooth
page19
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2008/09/20
2006/08/18 2008/09/20
2006/08/18 2008/09/20
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
239Thursday, May 07, 2009
239Thursday, May 07, 2009
239Thursday, May 07, 2009
E
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1.0
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of
of
A
1 1
B
C
D
E
Voltage Rails
S5
Power Plane
VIN
B+
+CPU_CORE
+0.9VS
+VCCP
+1.5VS
+1.8V
+2.5VS
+3VALW
2 2
+3VS
+5VALW
+5VS
+VSB
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
3 3
S4 (Suspend to Disk)
S5 (Soft OFF)
Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
0.9V switched power rail for DDR terminator
VCCP switched power rail
1.5V switched power rail
1.8V power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
RTC power
SIGNAL
SLP_S3#
SLP_S4#
SLP_S5#
HIGH HIGH HIGH
HIGH
LOW
LOW LOW
LOWLOW
HIGHHIGHHIGH
HIGH
HIGH
LOW
+VALW
ON
ON
ON
ON
ON
S3S1
N/AN/AN/A
N/A N/A N/A
OFF
OFF
ON
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFFOFF
OFFOFF
ON
OFF
OFF
OFF
ON ON*
OFF
OFF
ON ON*
OFF
OFF
ON ON*
ONON
+V +VS Clock
ON
ON
ON
OFF
OFF
ON
OFF
OFF
OFF
ONON
LOW
OFF
OFF
OFF
External PCI Devices
DEVICE REQ/GNT #
IDSEL #
No PCI Device
EC SM Bus1 address
Device
Smart Battery
Address
EC SM Bus2 address
Device
EMC1402
PIRQ
Address
1001 100X b0001 011X b
ICH7M SM Bus address
BOARD ID Table(Page 25)
ID
0
1
2
3
4 4
BRD ID
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
A
Ra
NC
100K
100K
100K
Rb Vab
0
8.2K
18K
NC
0V
0.25V
0.50V
3.3V
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2008/09/20
2006/08/18 2008/09/20
2006/08/18 2008/09/20
C
Device
Clock Generator
(SLG8SP556VTR)
DDR DIMMA
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Address
1101 001Xb
1010 000Xb
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Notes List
Notes List
Notes List
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
339Thursday, May 07, 2009
339Thursday, May 07, 2009
339Thursday, May 07, 2009
of
of
E
of
1.0
1.0
1.0
5
H_A#[3..16]<6>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
D D
H_ADSTB#0<6>
H_REQ#[0..4]<6>
H_A#[17..31]<6>
H_ADSTB#1<6>
C C
B B
A A
H_A20M#<16>
H_FERR#<16>
H_IGNNE#<16>
H_STPCLK#<16>
H_INTR<16>
H_NMI<16>
H_SMI#<16>
+VCCP
+VCCP
+VCCP
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_AP0
T4
@T4
@
PAD
PAD
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_AP1
T3 PAD@T3 PAD@
H_A20M#
H_FERR#
H_IGNNE# CLK_CPU_BCLK#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
R304 1K_0402_5%
R304 1K_0402_5%
1 2
R307 1K_0402_5%
R307 1K_0402_5%
1 2
R305 1K_0402_5%
R305 1K_0402_5%
1 2
R312 1K_0402_5%
R312 1K_0402_5%
1 2
R6 1K_0402_5%
R6 1K_0402_5%
1 2
R42 1K_0402_5%
R42 1K_0402_5%
1 2
This shall place near CPU
R11 56_0402_5%
R11 56_0402_5%
1 2
R7 56_0402_5% R7 56_0402_5%
1 2
R12 56_0402_5%@R12 56_0402_5%@
1 2
R8 56_0402_5% R8 56_0402_5%
1 2
R313 68_0402_5%
R313 68_0402_5%
1 2
Modify schematic by 10/21
R9 56_0402_5%
R9 56_0402_5%
1 2
R10 56_0402_5%
R10 56_0402_5%
1 2
5
U19A
U19A
P21
A[3]#
H20
A[4]#
N20
A[5]#
R20
A[6]#
J19
A[7]#
N19
A[8]#
G20
A[9]#
M19
A[10]#
H21
A[11]#
L20
A[12]#
M20
A[13]#
K19
A[14]#
J20
A[15]#
L21
A[16]#
K20
ADSTB[0]#
D17
AP0
N21
REQ[0]#
J21
REQ[1]#
G19
REQ[2]#
P20
REQ[3]#
R19
REQ[4]#
C19
A[17]#
F19
A[18]#
E21
A[19]#
A16
A[20]#
D19
A[21]#
C14
C18
C20
E20
D20
B18
C15
B16
B17
C16
A17
B14
B15
A14
B19
M18
U18
T16
J4
R16
T15
R15
U17
D6
G6
H6
K4
K5
M15
L16
ADDR GROUP 1
ADDR GROUP 1
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
AP1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
AU80586GE025512_FCBGA437
AU80586GE025512_FCBGA437
N270@
N270@
H_A#32
H_A#33
H_A#34
H_A#35
H_A20M#
H_IGNNE#
ITP_TMS
ITP_TDI
PREQ#
ITP_TDO
VR_TT#
ITP_TCK
ITP_TRST#
ADDR
GROUP
0
ADDR
GROUP
0
DEFER#
CONTROL
CONTROL
RESET#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PROCHOT#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
THRMDA
THRMDC
THERM
THERM
THERMTRIP#
BCLK[0]
BCLK[1]
H CLK
H CLK
NC
NC
ADS#
BNR#
BPRI#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
BR1#
RSVD3
RSVD2
RSVD1
V19
Y19
U21
T21
T19
Y18
T20
F16
V16
W20
D15
W18
Y17
U20
W19
AA17
V20
K17
J18
H15
J15
K18
J16
M17
N16
TDI
M16
L17
K16
V15
G17
E4
E5
H17
V11
V12
C21
C1
A3
.
.
4
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_IERR#
H_INIT#_R
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
PREQ#
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
H_PROCHOT#_R
H_THERMDA
H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK
+CPU_GTLREF
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
R314 22_0402_5%
R314 22_0402_5%
C67
C67
Close to CPU pin
within 500mils.
Zo=55ohm
4
H_ADS# <6>
H_BNR# <6>
H_BPRI# <6>
H_DEFER# <6>
H_DRDY# <6>
H_DBSY# <6>
H_BR0# <6>
R51 1K_0402_5%
R51 1K_0402_5%
1 2
H_LOCK# <6>
H_RESET# <6> H_RS#[0..2] <6>
H_TRDY# <6>
H_HIT# <6>
H_HITM# <6>
Close to CPU
H_THERMTRIP# <6,16>
CLK_CPU_BCLK <12>
CLK_CPU_BCLK# <12>
+VCCP
12
R38
R38
1K_0402_1%
1K_0402_1%
12
1
R36
R36
2K_0402_1%
2K_0402_1%
2
<BOM Structure>
<BOM Structure>
+VCCP +VCCP
12
R31
R31
56_0402_5%
56_0402_5%
Close to CPU
VR_TT# <37>
+CPU_EXTBGREF
C68
C68
1U_0402_6.3V4Z
1U_0402_6.3V4Z
Close to CPU pin
within 500mils.
Zo=55ohm
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
R50
R50
330_0402_5%
330_0402_5%
+VCCP
1
2
<BOM Structure>
<BOM Structure>
Issued Date
Issued Date
Issued Date
12
12
3
U19
U19
AU80586GF028512 _FCBGA437
AU80586GF028512 _FCBGA437
N280@
N280@
H_INIT# <16>
+CPU_GTLREF
+CPU_EXTBGREF
R37
R37
1K_0402_1%
1K_0402_1%
R41
R41
2K_0402_1%
2K_0402_1%
3
2
H_D#[0..15]<6>
H_DSTBN#0<6>
H_DSTBP#0<6>
H_DINV#0<6>
H_D#[16..31]<6>
H_DSTBN#1<6>
H_DSTBP#1<6>
H_DINV#1<6>
R47 1K_0402_5%@R47 1K_0402_5%@
1 2
R48 1K_0402_5%@R48 1K_0402_5%@
1 2
CPU_BSEL0<12>
CPU_BSEL1<12>
CPU_BSEL2<12>
+VCCP
12
R39
1
C69
C69
2
<BOM Structure>
<BOM Structure>
12
R39
1K_0402_1%
1K_0402_1%
R40
R40
2K_0402_1%
2K_0402_1%
+CPU_CMREF
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to CPU pin
within 500mils.
Zo=55ohm
Compal Secret Data
Compal Secret Data
2006/08/18 2008/09/20
2006/08/18 2008/09/20
2006/08/18 2008/09/20
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
H_D#0
Y11
H_D#1
W10
H_D#2
Y12
H_D#3
AA14
H_D#4
AA11
H_D#5
W12
H_D#6
AA16
H_D#7
Y10
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_DP#0
@
T5 PAD@T5 PAD
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1 H_DSTBN#3
H_DSTBP#1
H_DINV#1
H_DP#1
T7 PAD@T7 PAD@
ACLKPH
DCLKPH
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
1 2
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C76
C76
2200P_0402_50V7K
2200P_0402_50V7K
2
Y9
Y13
W15
AA13
Y16
W13
AA9
W9
Y14
Y15
W16
V9
AA5
Y8
W3
U1
W7
W6
Y7
AA6
Y3
W2
V3
U2
T3
AA8
V2
W4
Y4
Y5
Y6
R4
A7
U5
V5
T17
R6
M6
N15
N6
P17
T6
J6
H5
G5
1
C75
C75
2
U19B
U19B
D[0]#
D[1]#
D[2]#
DATA GRP 0 DATA GRP 1
DATA GRP 0 DATA GRP 1
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1
GTLREF
ACLKPH
DCLKPH
BINIT#
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]
AU80586GE025512_FCBGA437
AU80586GE025512_FCBGA437
N270@
N270@
DATA GRP 2
DATA GRP 2
DSTBN[2]#
DSTBP[2]#
DATA GRP 3
DATA GRP 3
DSTBN[3]#
DSTBP[3]#
MISC
MISC
DPRSTP#
PWRGOOD
CORE_DET
CMREF[1]
Layout note:
COMP0,2 connect with Zo=27.4ohm +/-15%, make
trace length shorter than 0.5"
COMP1,3 connect with Zo=55ohm +/-15%, make
trace length shorter than0.5"
CPU THERMAL SENSOR
U2
U2
1
H_THERMDA
H_THERMDC
VDD
2
DP
3
DN
4
THERM#
EMC1402-1-ACZL-TR_MSOP8
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DINV[2]#
DP#2
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DINV[3]#
DP#3
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPSLP#
DPWR#
SLP#
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
H_D#33
R2
H_D#34
P1
H_D#35
N1
H_D#36
M2
H_D#37
P2
H_D#38
J3
H_D#39
N3
H_D#40
G3
H_D#41
H2
H_D#42
N2
H_D#43
L2
H_D#44
M3
H_D#45
J2
H_D#46
H1
H_D#47
J1
H_DSTBN#2
K2
H_DSTBP#2
K3
H_DINV#2
L1
H_DP#2
M4
H_D#48
C2
H_D#49
G2
H_D#50
F1
H_D#51
D3
H_D#52
B4
H_D#53
E1
H_D#54
A5
H_D#55
C3
H_D#56
A6
H_D#57
F2
H_D#58
C6
H_D#59
B6
H_D#60
B3
H_D#61
C4
H_D#62
C7
H_D#63
D2
E2
H_DSTBP#3
F3
H_DINV#3
C5
H_DP#3
D4
COMP0
T1
T2
F20
F21
R18
R17
U4
V17
N18
A13
B7
SMCLK
SMDATA
ALERT#
1 2
COMP1
1 2
COMP2
COMP3
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
EC_SMB_CK2
8
EC_SMB_DA2
7
6
5
GND
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Diamondville(1/2)
Diamondville(1/2)
Diamondville(1/2)
H_D#32
R3
H_D#[32..47] <6>
H_DSTBN#2 <6>
H_DSTBP#2 <6>
H_DINV#2 <6>
@
T8PAD@T8PAD
H_D#[48..63] <6>
H_DSTBN#3 <6>
H_DSTBP#3 <6>
H_DINV#3 <6>
@
T6PAD@T6PAD
R46 27.4_0402_1%
R46 27.4_0402_1%
R45 54.9_0402_1% R45 54.9_0402_1%
R13 27.4_0402_1% R13 27.4_0402_1%
12
R5 54.9_0402_1%
R5 54.9_0402_1%
12
H_DPRSTP# <16,37>
H_DPSLP# <16>
H_DPWR# <6>
H_PWRGOOD <16>
H_CPUSLP# <6>
+CPU_CMREF
EC_SMB_CK2 <25>
EC_SMB_DA2 <25>
R52
R52
12
10K_0402_5%
10K_0402_5%
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
439Thursday, May 07, 2009
439Thursday, May 07, 2009
439Thursday, May 07, 2009
1
+3VS
of
of
of
1.0
1.0
1.0
5
4
3
2
1
C63
C63
C49
C49
1
2
1
2
+VCCP
1
+
+
C351
C351
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
+1.5VS
1
C66
C66
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C50
C50
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C27
C27
C342
C342
2
10U_0805_6.3V6M
10U_0805_6.3V6M
Deciphered Date
Deciphered Date
Deciphered Date
+CPU_CORE
12
12
1
C46
C46
2
1
2
R28
R28
100_0402_1%
100_0402_1%
R27
R27
100_0402_1%
100_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C39
C39
2
1U_0402_6.3V6K
1U_0402_6.3V6K
VCCSENSE <37>
VSSSENSE <37>
1
C31
C31
C34
C34
2
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
2
Length match within 25 mils
The trace space 7 mils,
Zo=27.4ohm
+CPU_CORE
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C51
C51
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
Date: Sheet of
Compal Electronics, Inc.
330uF(9mohm/2)
1
+
+
C343
C343
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
2
12/29 Remove C331-->330U
Diamondville(2/2)
Diamondville(2/2)
Diamondville(2/2)
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
539Thursday, May 07, 2009
539Thursday, May 07, 2009
539Thursday, May 07, 2009
1
1.0
1.0
1.0
of
of
U19D
U19D
A2
VSS1
A4
VSS2
A8
VSS4
A15
VSS5
A18
VSS6
A19
VSS7
A20
VSS8
B1
VSS9
B2
VSS10
D D
C C
B B
A A
B5
VSS11
B8
VSS12
B13
VSS13
B20
VSS14
B21
VSS15
C8
VSS16
C17
VSS17
D1
VSS18
D5
VSS19
D8
VSS20
D14
VSS21
D18
VSS22
D21
VSS23
E3
VSS24
E6
VSS25
E7
VSS26
E8
VSS27
E15
VSS28
E16
VSS29
E19
VSS30
F4
VSS31
F5
VSS32
F6
VSS33
F7
VSS34
F17
VSS35
F18
VSS36
G1
VSS37
G4
VSS38
G7
VSS39
G9
VSS41
G13
VSS42
G21
VSS45
H3
VSS46
H4
VSS48
H7
VSS49
H9
VSS51
H13
VSS52
H16
VSS53
H18
VSS54
H19
VSS55
J5
VSS56
J7
VSS57
J9
VSS58
J13
VSS59
J17
VSS60
K1
VSS61
K6
VSS62
K7
VSS63
K9
VSS64
K13
VSS65
K15
VSS66
K21
VSS67
L3
VSS68
L4
VSS69
L5
VSS70
L6
VSS71
L7
VSS72
L9
VSS73
L13
VSS74
L15
VSS75
L18
VSS76
L19
VSS77
M1
VSS78
M5
VSS79
M7
VSS80
M9
VSS81
M13
VSS82
M21
VSS83
N4
VSS84
AU80586GE025512_FCBGA437
AU80586GE025512_FCBGA437
N270@
N270@
5
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20
+CPU_CORE
+CPU_CORE
+VCCP
1
C35
C35
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C23
C23
2
10U_0805_6.3V6M
10U_0805_6.3V6M
4
U19C
U19C
V10
VCCF
A9
VCCQ1
B9
VCCQ2
A10
VCCP1
A11
VCCP2
A12
VCCP3
B10
VCCP4
B11
VCCP5
B12
VCCP6
C10
VCCP7
C11
VCCP8
C12
VCCP9
D10
VCCP10
D11
VCCP11
D12
VCCP12
E10
VCCP13
E11
VCCP14
E12
VCCP15
F10
VCCP16
F11
VCCP17
F12
VCCP18
G10
VCCP19
G11
VCCP20
G12
VCCP21
H10
VCCP22
H11
VCCP23
H12
VCCP24
J10
VCCP25
J11
VCCP26
J12
VCCP27
K10
VCCP28
K11
VCCP29
K12
VCCP30
L10
VCCP31
L11
VCCP32
L12
VCCP33
M10
VCCP34
M11
VCCP35
M12
VCCP36
N10
VCCP37
N11
VCCP38
N12
VCCP39
P10
VCCP40
P11
VCCP41
P12
VCCP42
R10
VCCP43
R11
VCCP44
R12
VCCP45
AU80586GE025512_FCBGA437
AU80586GE025512_FCBGA437
N270@
N270@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C53
C53
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C25
C25
C26
C26
2
10U_0805_6.3V6M
10U_0805_6.3V6M
C52
C52
1
2
1
2
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VCCPC64
VCCPC63
VCCPC62
VCCPC61
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14
F14
F13
E14
E13
D7
F15
D16
E18
G15
G16
E17
G18
C13
D13
+1.5VS
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
VCCSENSE
VSSSENSE
0.1U_0402_16V7K
C22
C22
0.1U_0402_16V7K
0.1U_0402_16V7K
1
C33
C33
2
CPU_VID0 <37>
CPU_VID1 <37>
CPU_VID2 <37>
CPU_VID3 <37>
CPU_VID4 <37>
CPU_VID5 <37>
CPU_VID6 <37>
1
C64
C64
2
1U_0402_6.3V6K
1U_0402_6.3V6K
130mA
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
PLACE IN CAVITY
0.1U_0402_16V7K
PLACE IN CAVITY
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C38
C38
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C56
C56
2
10U_0805_6.3V6M
10U_0805_6.3V6M
PLACE IN CORRIDOR AND CLOSE TO CPU
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C37
C37
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0805_6.3V6M
10U_0805_6.3V6M
1
C55
C55
C344
C344
2
Issued Date
Issued Date
Issued Date
C36
C36
1
2
1
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C45
C45
1U_0402_6.3V6K
1U_0402_6.3V6K
C58
C58
1
C47
C47
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
C57
C57
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
2006/08/18 2008/09/20
2006/08/18 2008/09/20
2006/08/18 2008/09/20
3
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C48
C48
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C24
C24
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
5
H_D#[0..15]<4> H_A#[3..16] <4>
D D
H_D#[16..31]<4>
H_D#[32..47]<4>
C C
H_D#[48..63]<4>
+VCCP
12
12
R297
R297
R311
R311
54.9_0402_1%
54.9_0402_1%
54.9_0402_1%
54.9_0402_1%
B B
A A
12
R298
R298
R306
R306
24.9_0402_1%
24.9_0402_1%
Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.
+VCCP
12
R16
R16
100_0402_1%
100_0402_1%
+H_VREF
12
R15
R15
1
C11
C11
2
200_0402_1%
200_0402_1%
5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
+H_SWNG0
H_YRCOMP
H_YSCOMP
+H_SWNG1
12
24.9_0402_1%
24.9_0402_1%
C50 be placed <100mils
from GMCH pin
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AB4
AB8
AA9
AA8
AB1
AB7
AA2
AB5
A10
C15
C4
F6
H9
H6
F7
E3
C2
C3
K9
F5
J7
K7
H8
E5
K8
J8
J2
J3
N1
M5
K5
J5
H3
J4
N3
M4
M3
N8
N6
K3
N9
M1
V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3
W2
W1
V2
W4
W7
W5
V5
W8
A6
J1
K1
H1
U18A
U18A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
QG82945GSE SLB2R A3_FCBGA998
QG82945GSE SLB2R A3_FCBGA998
H_ADSTB#_0
H_ADSTB#_1
H_BREQ0#
H_CPURST#
HOST
HOST
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPWR#
H_DRDY#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_SLPCPU#
+VCCP
12
R1
R1
12
R3
R3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_ADS#
H_VREF0
H_BNR#
H_BPRI#
H_VREF1
HCLKN
HCLKP
H_DBSY#
H_HIT#
H_HITM#
H_LOCK#
H_RS#_0
H_RS#_1
H_RS#_2
H_TRDY#
221_0402_1%
221_0402_1%
100_0402_1%
100_0402_1%
4
F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17
F10
C12
H16
E2
B9
C7
G8
B10
E1
AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3
C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10
+H_SWNG0
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADS#
H_ADSTB#0
H_ADSTB#1
+H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_RESET#
+H_VREF
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DBSY#
H_DEFER#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DPWR#
H_DRDY#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#
H_TRDY#
C4
C4
+VCCP
R20
R20
R19
R19
12
221_0402_1%
221_0402_1%
12
100_0402_1%
100_0402_1%
H_A#[17..31] <4>
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_RESET# <4>
CLK_MCH_BCLK# <12>
CLK_MCH_BCLK <12>
H_DBSY# <4>
H_DEFER# <4>
H_DINV#0 <4>
H_DINV#1 <4>
H_DINV#2 <4>
H_DINV#3 <4>
H_DPWR# <4>
H_DRDY# <4>
H_DSTBN#0 <4>
H_DSTBN#1 <4>
H_DSTBN#2 <4>
H_DSTBN#3 <4>
H_DSTBP#0 <4>
H_DSTBP#1 <4>
H_DSTBP#2 <4>
H_DSTBP#3 <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_REQ#[0..4] <4>
H_RS#[0..2] <4>
H_CPUSLP# <4>
H_TRDY# <4>
+H_SWNG1
1
C12
C12
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3
0211 Add C427, C428, C429 for power noise
Change C427 from 100p to 330p 0319
Change C428 C429 from 100p to 220p 0319
C427 close to U18
C428 close to U18
C429 close to U12
MCH_CLKSEL0
1
C427
C427
330P_0402_50V7K
330P_0402_50V7K
2
MCH_CLKSEL1
1
C428
C428
220P_0402_50V7K
220P_0402_50V7K
2
MCH_CLKSEL2
1
C429
C429
220P_0402_50V7K
220P_0402_50V7K
2
+1.8V
R44 80.6_0402_1%
R44 80.6_0402_1%
R43 80.6_0402_1%
+DIMM_VREF
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R43 80.6_0402_1%
3
DMI_TXN0<17>
DMI_TXN1<17>
DMI_TXP0<17>
DMI_TXP1<17>
DMI_RXN0<17>
DMI_RXN1<17>
DMI_RXP0<17>
DMI_RXP1<17>
M_CLK_DDR0<11>
M_CLK_DDR1<11>
M_CLK_DDR#0<11>
M_CLK_DDR#1<11>
DDR_CKE0<11>
DDR_CKE1<11>
DDR_CS0#<11>
DDR_CS1#<11>
M_ODT0<11>
M_ODT1<11>
1 2
1 2
1
1
C61
C61
C54
C54
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2006/08/18 2008/09/20
2006/08/18 2008/09/20
2006/08/18 2008/09/20
DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1
DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR#1
DDR_CKE0
DDR_CKE1
DDR_CS0#
DDR_CS1#
M_ODT0
M_ODT1
15mil
SMRCOMPN
SMRCOMPP
10uA
Layout Note:
+DIMM_VREF trace
width and spacing
is 20/20.
SMRCOMPN and
SMRCOMPP trace
width 15mil
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
AF33
AG1
AM30
AG33
AF1
AK1
AN30
AN21
AN22
AF26
AF25
AG14
AF12
AK14
AH12
AJ21
AF11
AE12
AF14
AJ14
AJ12
AN12
AN14
AA33
AE1
Y29
Y32
Y28
Y31
V28
V31
V29
V32
AJ1
2
U18B
U18B
DMI_RXN_0
DMI_RXN_1
DMI_RXP_0
DMI_RXP_1
DMI_TXN_0
DMI_TXN_1
DMI_TXP_0
DMI_TXP_1
DMI
DMI
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_OCDCOMP_0
DDR2 MUXING
DDR2 MUXING
SM_OCDCOMP_1
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMPN
SM_RCOMPP
SM_VREF_0
SM_VREF_1
QG82945GSE SLB2R A3_FCBGA998
QG82945GSE SLB2R A3_FCBGA998
2
CFG_0
CFG_1
CFG_2
CFG_3
CFG_5
CFG_6
RESERVED1
RESERVED2
RESERVED7
RESERVED8
RESERVED9
CFG/RSVD
CFG/RSVD
PM_ICHSYNC#
PM_BMBUSY#
PM_EXTTS#_0
PM
PM
PM_EXTTS#_1
THRMTRIP#
PWROK
RSTIN#
D_REFCLKN
D_REFCLKP
CLK
CLK
D_REFSSCLKN
D_REFSSCLKP
CLKREQ#
1
MCH_CLKSEL0
C18
MCH_CLKSEL1
E18
MCH_CLKSEL2
G20
CFG3
G18
CFG5
J20
J18
K32
K31
C17
F18
A3
0210 Add C414 for noise
E31
G21
F26
H26
J15
AB29
W27
A27
A26
J33
H33
J22
1 2
CFG6
R23 2.2K_0402_5%
R23 2.2K_0402_5%
H_THERMTRIP#
C414
靠近北橋
Change C414 from 100p to 220p 0319
MCH_ICH_SYNC#
PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
R26 0_0402_5%
R26 0_0402_5%
H_THERMTRIP#
ICH_POK
PLTRST_R#
1 2
R33 100_0402_5%
R33 100_0402_5%
0210 Add C416 for noise
PLTRST#
C416靠近R33
Change C416 from 100p to 220p 0319
MCH_CLKSEL0 <12>
MCH_CLKSEL1 <12>
MCH_CLKSEL2 <12>
T1PAD@ T1PAD@
T2PAD@ T2PAD@
0120 Add C400 for noise
DPRSLPVR
1
C400
C400
100P_0402_50V8J
100P_0402_50V8J
2
1
C414
C414
220P_0402_50V7K
220P_0402_50V7K
2
U18
MCH_ICH_SYNC# <15>
PM_BMBUSY# <17>
PM_EXTTS#0 <11>
1
2
12
C416
C416
220P_0402_50V7K
220P_0402_50V7K
DPRSLPVR <17,37>
H_THERMTRIP# <4,16>
ICH_POK <17,25>
PLTRST# <15,17,19,24,25>
CLK_MCH_DREFCLK# <12>
CLK_MCH_DREFCLK <12>
MCH_SSCDREFCLK# <12>
MCH_SSCDREFCLK <12>
MCH_CLKREQ# <12>
Strap Pin Table
CFG5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Low = DMI x 2
High = DMI x 4
PM_EXTTS#0
PM_EXTTS#1
Calistoga(1/5)-GTL/DMI/DDR
Calistoga(1/5)-GTL/DMI/DDR
Calistoga(1/5)-GTL/DMI/DDR
R17 10K_0402_5%
R17 10K_0402_5%
R25 10K_0402_5%
R25 10K_0402_5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
1 2
@
@
1 2
1
*
+3VS
of
of
of
639Thursday, May 07, 2009
639Thursday, May 07, 2009
639Thursday, May 07, 2009
1.0
1.0
1.0
5
4
3
2
1
D D
C C
B B
DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>
DDR_A_DM[0..7]<11>
DDR_A_DQS[0..7]<11>
DDR_A_DQS#[0..7]<11>
DDR_A_MA[0..13]<11>
DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>
T10 PAD@T10 PAD
@
@
T9 PAD@T9 PAD
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_CAS#
DDR_A_RAS#
SA_RCVENIN#
SA_RCVENOUT#
DDR_A_WE#
AK12
AH11
AG17
AB30
AL31
AF30
AK26
AL9
AG7
AK5
AH3
AC28
AJ30
AK33
AL25
AN9
AH8
AM2
AE3
AC29
AK30
AJ33
AM25
AN8
AJ8
AM3
AE2
AJ15
AM17
AM15
AH15
AK15
AN15
AJ18
AF19
AN17
AL17
AG16
AL18
AG18
AL14
AJ17
AK18
AN28
AM28
AH17
AH21
AJ20
AE27
AN20
AL21
AK21
AK22
AL22
AH22
AG22
AF21
AM21
AE21
AL20
AE22
AE26
AE20
U18C
U18C
SA_BS_0
SA_BS_1
SA_BS_2
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
SB_BS_0
SB_BS_1
SB_BS_2
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
DDR2 SYSTEM MEMORY
DDR2 SYSTEM MEMORY
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SB_CAS#
SB_RAS#
SB_WE#
QG82945GSE SLB2R A3_FCBGA998
QG82945GSE SLB2R A3_FCBGA998
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5
AG19
AG21
AG20
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_D0
AC31
DDR_A_D[0..63] <11>
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2008/09/20
2006/08/18 2008/09/20
2006/08/18 2008/09/20
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
Calistoga(2/5)-DDR2
Calistoga(2/5)-DDR2
Calistoga(2/5)-DDR2
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
739Thursday, May 07, 2009
739Thursday, May 07, 2009
739Thursday, May 07, 2009
1
1.0
1.0
1.0
of
of
of
5
D D
4
3
2
1
U18F
U18F
H27
SDVO_CTRLDATA
J27
GMCH_CRT_R
R301 150_0402_1%
R301 150_0402_1%
R299 150_0402_1%
R299 150_0402_1%
R300 150_0402_1%
R300 150_0402_1%
Layout Note:
CRT_IREF trace
width 10mil ,
PEGCOMP trace
width 15mil
C C
+3VS
B B
12
12
12
Close to U4.H25
1 2
R14 10K_0402_5%
R14 10K_0402_5%
1 2
R4 10K_0402_5%
R4 10K_0402_5%
GMCH_CRT_G
GMCH_CRT_B
12
R18 255_0402_1%
R18 255_0402_1%
R21 100K_0402_5%
R21 100K_0402_5%
LCTLA_CLK
LCTLB_DATA
L_BKLTCTL<13>
GMCH_ENBKL<25>
R22 1.5K_0402_1%
R22 1.5K_0402_1%
CLK_MCH_3GPLL#<12>
CLK_MCH_3GPLL<12>
GMCH_CRT_CLK<14>
GMCH_CRT_DATA<14>
GMCH_CRT_B<14>
GMCH_CRT_G<14>
GMCH_CRT_R<14>
GMCH_CRT_VSYNC<14>
GMCH_CRT_HSYNC<14>
12
LVDS_SCL<13>
LVDS_SDA<13>
GMCH_ENVDD<13>
12
LVDS_ACLK#<13>
LVDS_ACLK<13>
LVDS_A0#<13>
LVDS_A1#<13>
LVDS_A2#<13>
LVDS_A0<13>
LVDS_A1<13>
LVDS_A2<13>
CLK_MCH_3GPLL#
CLK_MCH_3GPLL
GMCH_CRT_CLK
GMCH_CRT_DATA
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R
CRT_IREF
10mil
LCTLA_CLK
LCTLB_DATA
LVDS_SCL
LVDS_SDA
GMCH_ENVDD
L_IBG
LVDS_ACLK#
LVDS_ACLK
LVDS_A0#
LVDS_A1#
LVDS_A2#
LVDS_A0
LVDS_A1
LVDS_A2
AA26
Y26
H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25
H30
G29
F28
E28
G28
H28
K30
K27
J29
J30
K29
D30
C30
A30
A29
G31
F32
D31
H31
G32
C31
F33
D33
F30
E33
D32
F29
SDVO_CTRLCLK
G_CLKN
G_CLKP
CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_VSYNC
CRT_HSYNC
CRT_IREF
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CTLBDATA
L_DDC_CLK
L_DDC_DATA
L_VDDEN
L_IBG
L_VBG
L_VREFH
L_VREFL
LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP
LA_DATAN_0
LA_DATAN_1
LA_DATAN_2
LA_DATAP_0
LA_DATAP_1
LA_DATAP_2
LB_DATAN_0
LB_DATAN_1
LB_DATAN_2
LB_DATAP_0
LB_DATAP_1
LB_DATAP_2
EXP_A_COMPI
EXP_A_ICOMPO
SDVO_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
MISC
MISC
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
SDVO
SDVO
SDVO_RED#
SDVO_GREEN#
SDVO_BLUE#
SDVO_CLKN
SDVO_RED
SDVO_GREEN
SDVO_BLUE
SDVO_CLKP
TV_DACA
TV_DACB
TV_DACC
TV_IREF
TV_IRTNA
TV
TV
TV_IRTNB
LVDS VGA
LVDS VGA
TV_IRTNC
TV_DCONSEL0
TV_DCONSEL1
QG82945GSE SLB2R A3_FCBGA998
QG82945GSE SLB2R A3_FCBGA998
R28
M28
N30
R30
T29
M30
P30
T30
P28
N32
P32
T32
N28
M32
P33
R32
A21
C20
E20
G23
B21
C21
D21
G26
J26
15mil
PEGCOMP
+1.5VS
1 2
Disable TV
R30
R30
24.9_0402_1%
24.9_0402_1%
+1.5VS_PCIE
A A
Security Classification
Security Classification
Security Classification
2006/08/18 2008/09/20
2006/08/18 2008/09/20
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2008/09/20
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet of
Compal Electronics, Inc.
Calistoga(3/5)-VGA/LVDS/TV
Calistoga(3/5)-VGA/LVDS/TV
Calistoga(3/5)-VGA/LVDS/TV
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
839Thursday, May 07, 2009
839Thursday, May 07, 2009
839Thursday, May 07, 2009
of
1
of
1.0
1.0
1.0
5
+VCCP
D D
C C
+VCCP
B B
A A
5
AB10
AA10
M25
N24
M24
W22
U22
R22
N22
M22
W21
U21
R21
N21
M21
W20
U20
R20
N20
M20
N19
M19
N18
M18
N17
M17
N16
M16
N15
M15
W14
U14
R14
N14
M14
R10
N10
M10
T25
R25
P25
N25
P24
Y22
V22
T22
P22
Y21
V21
T21
P21
Y20
V20
T20
P20
Y19
P19
Y18
P18
Y17
P17
Y16
P16
Y15
P15
Y14
V14
T14
P14
T10
P10
L10
D1
A18
U18H
U18H
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
RSVD_3
RSVD_4
RSVD_5
RSVD_6
NCTF
NCTF
QG82945GSE SLB2R A3_FCBGA998
QG82945GSE SLB2R A3_FCBGA998
4
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
CFG_19
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25
4
AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1
K28
K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15
+1.5VS
3
U18E
U18E
AH33
VSS_1
Y33
VSS_2
V33
VSS_3
R33
VSS_4
G33
VSS_5
AK32
VSS_6
AG32
VSS_7
AE32
VSS_8
AC32
VSS_9
AA32
VSS_10
U32
VSS_11
H32
VSS_12
E32
VSS_13
C32
VSS_14
AM31
VSS_15
AJ31
VSS_16
AA31
VSS_17
U31
VSS_18
T31
VSS_19
R31
VSS_20
P31
VSS_21
N31
VSS_22
M31
VSS_23
J31
VSS_24
F31
VSS_25
AL30
VSS_26
AG30
VSS_27
AE30
VSS_28
AC30
VSS_29
AA30
VSS_30
Y30
VSS_31
V30
VSS_32
U30
VSS_33
G30
VSS_34
E30
VSS_35
B30
VSS_36
AA29
VSS_37
U29
VSS_38
R29
VSS_39
P29
VSS_40
N29
VSS_41
M29
VSS_42
H29
VSS_43
E29
VSS_44
B29
VSS_45
AK28
VSS_46
AH28
VSS_47
AE28
VSS_48
AA28
VSS_49
U28
VSS_50
T28
VSS_51
J28
VSS_52
D28
VSS_53
AM27
VSS_54
AF27
VSS_55
AB27
VSS_56
AA27
VSS_57
Y27
VSS_58
U27
VSS_59
T27
VSS_60
R27
VSS_61
P27
VSS_62
N27
VSS_63
M27
VSS_64
G27
VSS_65
E27
VSS_66
C27
VSS_67
B27
VSS_68
AL26
VSS_69
AH26
VSS_70
W26
VSS_71
U26
VSS_72
AN25
VSS_73
AK25
VSS_74
AG25
VSS_75
AE25
VSS_76
J25
VSS_77
G25
VSS_78
A25
VSS_79
H23
VSS_80
F23
VSS_81
B23
VSS_82
AM22
VSS_83
AJ22
VSS_84
AF22
VSS_85
G22
VSS_86
E22
VSS_87
J21
VSS_88
H21
VSS_89
F21
VSS_90
AM20
VSS_91
AK20
VSS_92
AH20
VSS_93
AF20
VSS_94
D20
VSS_95
W19
VSS_96
R19
VSS_97
AM18
VSS_98
AH18
VSS_99
AF18
VSS_100
U18
VSS_101
H18
VSS_102
D18
VSS_103
AK17
VSS_104
V17
VSS_105
T17
VSS_106
F17
VSS_107
B17
VSS_108
AH16
VSS_109
U16
VSS_110
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2006/08/18 2008/09/20
2006/08/18 2008/09/20
2006/08/18 2008/09/20
3
VSS
VSS
QG82945GSE SLB2R A3_FCBGA998
QG82945GSE SLB2R A3_FCBGA998
J16
VSS_111
AL15
VSS_112
AG15
VSS_113
W15
VSS_114
R15
VSS_115
F15
VSS_116
D15
VSS_117
AM14
VSS_118
AH14
VSS_119
AE14
VSS_120
H14
VSS_121
B14
VSS_122
F13
VSS_123
D13
VSS_124
AL12
VSS_125
AG12
VSS_126
H12
VSS_127
B12
VSS_128
AN11
VSS_129
AJ11
VSS_130
AE11
VSS_131
AM9
VSS_132
AJ9
VSS_133
AB9
VSS_134
W9
VSS_135
R9
VSS_136
M9
VSS_137
J9
VSS_138
F9
VSS_139
C9
VSS_140
A9
VSS_141
AL8
VSS_142
AG8
VSS_143
AE8
VSS_144
U8
VSS_145
AA7
VSS_146
V7
VSS_147
R7
VSS_148
N7
VSS_149
H7
VSS_150
E7
VSS_151
B7
VSS_152
AL6
VSS_153
AG6
VSS_154
AE6
VSS_155
AB6
VSS_156
W6
VSS_157
T6
VSS_158
M6
VSS_159
K6
VSS_160
AN5
VSS_161
AJ5
VSS_162
B5
VSS_163
AA4
VSS_164
V4
VSS_165
R4
VSS_166
N4
VSS_167
K4
VSS_168
H4
VSS_169
E4
VSS_170
AL3
VSS_171
AD3
VSS_172
W3
VSS_173
T3
VSS_174
B3
VSS_175
AK2
VSS_176
AH2
VSS_177
AF2
VSS_178
AB2
VSS_179
M2
VSS_180
K2
VSS_181
H2
VSS_182
F2
VSS_183
V1
VSS_184
R1
VSS_185
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
2
1
U18G
U18G
W33
NC1
AM33
NC2
AL33
NC3
C33
NC4
B33
NC5
AN32
NC6
A32
NC7
AN31
NC8
W28
NC9
V27
NC10
W29
NC11
J24
NC12
H24
NC13
W32
NC14
G24
NC15
F24
NC16
E24
NC17
D24
NC18
K33
NC19
A31
NC20
E21
NC21
C23
NC22
AN19
NC23
AM19
NC24
AL19
NC25
AK19
NC26
AJ19
NC27
AH19
NC28
AN3
NC29
Y9
NC30
J19
NC31
H19
NC32
G19
NC33
F19
NC34
E19
NC35
D19
NC36
C19
NC37
B19
NC38
A19
NC39
Y8
NC40
G16
NC41
F16
NC42
E16
NC43
D16
NC44
C16
NC45
B16
NC46
AN2
NC47
A16
NC48
Y7
NC49
AM4
NC50
AF4
NC51
AD4
NC52
AL4
NC53
AK4
NC54
W31
NC55
AJ4
NC56
AH4
NC57
AG4
NC58
AE4
NC59
AM1
NC60
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
NC
NC
RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
RESERVED38
RESERVED39
RESERVED40
RESERVED41
RESERVED42
QG82945GSE SLB2R A3_FCBGA998
QG82945GSE SLB2R A3_FCBGA998
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Calistoga(4/5)-PWR/GND
Calistoga(4/5)-PWR/GND
Calistoga(4/5)-PWR/GND
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
1
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72
W30
Y6
AL1
Y5
Y10
W10
W25
V24
U24
V10
U10
K18
Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17
of
of
of
939Thursday, May 07, 2009
939Thursday, May 07, 2009
939Thursday, May 07, 2009
1.0
1.0
1.0
2940mA
1
1
+
+
C20
C20
2
2
10U_0805_10V4Z
10U_0805_10V4Z
+VCCP
D1
@D1
@
RB751V-40_SOD323-2
RB751V-40_SOD323-2
1 2
12
+2.5VS
@
@
5
C40
C40
10U_0805_10V4Z
10U_0805_10V4Z
5
1
2
1
C21
C21
C42
C42
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.47U_0603_16V4Z
0.47U_0603_16V4Z
1
1
C41
C41
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1250mA
C334
C334
1 2
0.47U_0603_16V4Z
0.47U_0603_16V4Z
C333
C333
1 2
10mil
0.47U_0603_16V4Z
0.47U_0603_16V4Z
1
C332
C332
2
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
C43
C43
780mA
10mil
C345
C345
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
10mil
2
1
C59
C59
1
2
+1.5VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VCCP
1
2
U4_A14
U4_A7
U4_AA1
U4_F1
2
C338
C338
0.47U_0603_16V4Z
0.47U_0603_16V4Z
1
10mil
M26
W18
W17
W16
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18
AF17
AE17
AF16
AE16
AF15
AE15
AD9
AD8
AD7
AD6
T26
R26
P26
N26
V19
U19
T19
V18
T18
R18
U17
R17
V16
T16
R16
V15
U15
T15
J14
J10
H10
AE9
U9
A14
D10
P9
L9
D9
P8
L8
D8
P7
L7
D7
A7
P6
L6
G6
D6
U5
P5
L5
G5
D5
Y4
U4
P4
L4
G4
D4
Y3
U3
P3
L3
G3
D3
Y2
U2
P2
L2
G2
D2
AA1
F1
+VCCP
C30
C30
220U_B2_2.5VM_R35
D D
C C
B B
A A
220U_B2_2.5VM_R35
R29
R29
10_0402_5%
10_0402_5%
U18D
U18D
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40
4
VCCATVDACA0
VCCATVDACA1
VCCATVDACB0
VCCATVDACB1
VCCATVDACC0
VCCATVDACC1
VCCATVBG
VSSATVBG
VCCDTVDAC
VCCDQTVDAC
VCCDLVDS0
VCCDLVDS1
VCCDLVDS2
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCAMPLL
VCCAHPLL
VCCADPLLA
VCCADPLLB
POWER
POWER
VCCDHMPLL1
VCCDHMPLL2
VCCTXLVDS0
VCCTXLVDS1
VCC3G0
VCC3G1
VCCA3GPLL
VCCA3GBG
VSSA3GBG
VCCSYNC
VCCACRTDAC0
VCCACRTDAC1
VSSACRTDAC
VCCALVDS
VSSALVDS
VTT41
VTT42
VTT43
VTT44
QG82945GSE SLB2R A3_FCBGA998
QG82945GSE SLB2R A3_FCBGA998
4
VTT45
B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32
P1
L1
G1
U1
Y1
+1.5VS
400mA
2mA
10mA
144mA
20mA
40mA
10mil
10mil
10mil
+1.5VS_MPLL
+1.5VS_HPLL
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS
+2.5VS
+1.5VS_3GPLL
+2.5VS
+2.5VS_CRTDAC
+2.5VS
U4_AB33
U4_AM32
3
2
Disable TV
+1.5VS
+3VS
10mil
C352
C352
150mA
60mA
10mil
1
1
C350
C350
C355
C355
U4_AN18
U4_AH1
1U_0603_10V6K
1U_0603_10V6K
2
2
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
1
C72
C72
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
U4_AN4
1
C73
C73
2
1
1U_0603_10V6K
1U_0603_10V6K
2
45mA
45mA
50mA
50mA
Route +2.5VS from GMCH pinN33 to
decoupling cap <200mil to the edge.
1
1
C2
C2
2
2
C10
C10
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C77
C77
C71
C71
2
2
1U_0603_10V6K
1U_0603_10V6K
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
+1.8V
533 MTS=1720mA
1
C60
C60
2
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
C18
C18
400mA
CRTDAC: Route FB
70mA
70mA
1
+VCCP
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C8
C8
2
2
0.022U_0402_16V7K
0.022U_0402_16V7K
3
within 3" of Calistoga
R2
R2
12
10_0603_5%
10_0603_5%
1
C5
C5
C6
C6
2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
2006/08/18 2008/09/20
2006/08/18 2008/09/20
2006/08/18 2008/09/20
+2.5VS
1
1
C329
C329
2
2
C328
C328
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+2.5VS
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+2.5VS
1
C13
C13
C15
C15
2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+1.5VS_MPLL
+1.5VS_PCIE
1
C28
C28
C19
C19
2
@
@
1
10U_0805_10V4Z
10U_0805_10V4Z
2
2
PCI-E/MEM/PSB PLL decoupling
R32
R32
0_0603_5%
0_0603_5%
+1.5VS
+1.5VS +1.5VS
+1.5VS
close pin C29/D29
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+1.5VS
12
+1.5VS_HPLL
C62
C62
+1.5VS_DPLLA+1.5VS_DPLLB
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+2.5VS
1
C9
C9
C327
C327
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
Calistoga(5/5)-PWR/GND
Calistoga(5/5)-PWR/GND
Calistoga(5/5)-PWR/GND
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
C346
C346
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1
C349
C349
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C14
C14
1
2
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
1
1
+
+
C70
C70
2
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
+1.5VS_3GPLL
1
1
C29
C29
C32
C32
2
2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
45mA Max.
R315
R315
0_0603_5%
0_0603_5%
12
1
2
10U_0805_10V4Z
10U_0805_10V4Z
L2
L2
1 2
FBMA-L10-160808-301LMT_2P
FBMA-L10-160808-301LMT_2P
1
+
+
C74
C74
2
Change C249 and C13 size to B2 ; Terry 0106
R34
R34
12
0_0805_5%
0_0805_5%
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
1
@
@
1
C65
C65
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C7
C7
1
2
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
1
2
1
+1.5VS+1.5VS_3GPLL
1
C44
C44
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
45mA Max.
R35
R35
0_0603_5%
0_0603_5%
12
1
2
10U_0805_10V4Z
10U_0805_10V4Z
40mA Max.40mA Max.
L1
L1
1 2
FBMA-L10-160808-301LMT_2P
FBMA-L10-160808-301LMT_2P
1
+
+
C3
C3
2
+2.5VS
1
1
C331
C331
C330
C330
close pin B31
2
2
0.01U_0402_25V7K
0.01U_0402_25V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
of
of
of
10 39Thursday, May 07, 2009
10 39Thursday, May 07, 2009
10 39Thursday, May 07, 2009
+1.5VS
1.0
1.0
1.0
5
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DM[0..7]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..13]<7>
D D
+1.8V
2
2
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C367
C367
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C101
C101
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.9VS
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
2
C370
C370
C368
C368
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
1
C369
C369
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C102
C102
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RP5
RP5
18
27
36
45
RP4
RP4
18
27
36
45
RP1
RP1
18
27
36
45
56_0804_8P4R_5%
56_0804_8P4R_5%
2
C364
C364
C366
C362
C362
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
+
+
@
@
C C
+0.9VS
1
C82
C82
B B
A A
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C358
C358
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
1
C84
C84
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M_ODT0
DDR_A_MA0
DDR_A_RAS#
DDR_A_BS1
DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_CAS#
DDR_A_WE#
DDR_A_BS0
M_ODT1
DDR_CS1#
DDR_A_BS2
DDR_CKE0
C363
C363
2
1
C86
C86
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
5
C366
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
1
C365
C365
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
1
C80
C80
C98
C98
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
RP6
RP6
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
56_0804_8P4R_5%
RP2
RP2
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
56_0804_8P4R_5%
RP3
RP3
1 8
2 7
3 6
4 5
56_0804_8P4R_5%
56_0804_8P4R_5%
R56
R56
1 2
56_0402_5%
56_0402_5%
R55
R55
1 2
56_0402_5%
56_0402_5%
2
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
C81
C81
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_CS0#
DDR_A_MA13
DDR_A_MA2
DDR_A_MA4
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_CKE1
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA10
C97
C97
Layout Note:
Place near JDIM1
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
+1.8V
12
R53
R53
1K_0402_1%
1K_0402_1%
12
R54
R54
1K_0402_1%
1K_0402_1%
+DIMM_VREF
Share +DIMM_VREF for
1.DDRII VREF
2.GMCH SM_VREF_0
SM_VREF_1
20mils
1
C90
C90
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
For EMI DDR issue
+1.8V
1 2
C88 0.1U_0402_16V4Z@C88 0.1U_0402_16V4Z@
1 2
C87 0.1U_0402_16V4Z@C87 0.1U_0402_16V4Z@
+3VS
1 2
C372 0.1U_0402_16V4Z@C372 0.1U_0402_16V4Z@
1
1
1
C96
C96
C99
C99
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4
1
C85
C85
C83
C83
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+DIMM_VREF
+1.5VS
C371
C371
3
1
C91
C91
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
+3VS
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
3
2
+1.8V +1.8V
JDIM1
JDIM1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
201
GND
FOX_AS0A426-N4SN-7F
FOX_AS0A426-N4SN-7F
CONN@
CONN@
DDR_A_CAS#<7>
CLK_SMBDATA<12>
CLK_SMBCLK<12>
DDR_CKE0<6>
DDR_A_BS2<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_CS1#<6>
+DIMM_VREF
M_ODT1<6>
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1#
M_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
CLK_SMBDATA
CLK_SMBCLK
+3VS
DIMMA
Compal Secret Data
Compal Secret Data
2006/08/18 2008/09/20
2006/08/18 2008/09/20
2006/08/18 2008/09/20
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
GND
1
2
VSS
A11
BA1
S0#
SA0
SA1
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
R59
R59
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0#
M_ODT0
DDR_A_MA13
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R326 10K_0402_5% R326 10K_0402_5%
1 2
R325 10K_0402_5% R325 10K_0402_5%
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>
1 2
0_0402_5%
0_0402_5%
DDR_CKE1 <6>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0# <6>
M_ODT0 <6>
M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>
DDRII-SODIMMA
DDRII-SODIMMA
DDRII-SODIMMA
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
1
PM_EXTTS#0 <6>
11 39Thursday, May 07, 2009
11 39Thursday, May 07, 2009
11 39Thursday, May 07, 2009
of
of
of
1.0
1.0
1.0
5
PCI
SRC
CPU
CLKSEL1
0
FSA
CLKSEL0
MHz
266
MHz
1000
MHz
MHz
33.30
14.318 96.0 48.0
DOT_96
MHz
USB
MHz
FSC FSB REF
CLKSEL2
0 1000 133 33.31 14.318 96.0 48.0
0 1001 200 33.30 14.318 96.0 48.0
0 1001 166 33.31 14.318 96.0 48.0
D D
1 1000 333 33.30 14.318 96.0 48.0
1 1000 100 33.31 14.318 96.0 48.0
1 1001 400 33.30 14.318 96.0 48.0
111
+VCCP
R222
R222
R203
R203
2.2K_0402_5%
2.2K_0402_5%
FSA
CPU_BSEL0<4>
C C
CPU_BSEL1<4>
CPU_BSEL2<4>
B B
1 2
R208
R208
0_0402_5%
0_0402_5%
1 2
R216
R216
0_0402_5%
0_0402_5%
R237
R237
10K_0402_5%
10K_0402_5%
FSC
1 2
R235
R235
0_0402_5%
0_0402_5%
56_0402_5%
56_0402_5%
1 2
1 2
12
@
@
R218
R218
1K_0402_5%
@
@
@
@
N280@
N280@
N270@
N270@
12
+VCCP
+VCCP
1K_0402_5%
12
R205
R205
1K_0402_5%
1K_0402_5%
@
@
R213
R213
1K_0402_5%
1K_0402_5%
1 2
1 2
R214
R214
1K_0402_5%
1K_0402_5%
12
R215
R215
0_0402_5%
0_0402_5%
R234
R234
1K_0402_5%
1K_0402_5%
@
@
1 2
1 2
R233
R233
1K_0402_5%
1K_0402_5%
12
R236
R236
0_0402_5%
0_0402_5%
FSB
Reserved
MCH_CLKSEL0 <6>
MCH_CLKSEL1 <6>
EMI
MCH_CLKSEL2 <6>
0211 Add C426 for power noise
H_STP_PCI#_R
1
C426
C426
100P_0402_50V8J
100P_0402_50V8J
2
C426 close to U12
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#
Pin28/29 : LCDCLK / LCDCLK#
For PCI2_TME:0=Overclocking of CPU and SRC allowed
(ICS only) 1=Overclocking of CPU and SRC NOT allowed
Change Y2 part number from SJ114P3M720 to SJ100003B00
Change Y2 footprint from Y_6X1430004201_2P to Y_7A14300083_2P
Change Y2 value from 14.31818MHZ X5H01431AFG1H-X to 14.31818MHZ X5H01431AFG1H-X
A A
C244 27P_0402_50V8J
C244 27P_0402_50V8J
14.31818MHZ X5H01431AFG1H-X
14.31818MHZ X5H01431AFG1H-X
C243 27P_0402_50V8J
C243 27P_0402_50V8J
Routing the trace at least 10mil
5
Y1
Y1
CLK_XTAL_IN
12
CLK_XTAL_OUT
4
<EMI>
<EMI>
+3VS
FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603
L15
L15
12
47P_0402_50V8J <RF>
47P_0402_50V8J <RF>
C240
C240
Close to L11
+VCCP
<EMI>
<EMI>
FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603
12
L14
L14
47P_0402_50V8J
47P_0402_50V8J
Close to L12
L15
L15
0_0603_5%
0_0603_5%
@
@
L14
L14
0_0603_5%
0_0603_5%
@
@
0118 change L14 & L15 to 0_0603
+3VS
1 2
R174 10K_0402_5%@R174 10K_0402_5%@
0120 Add C403 for noise
Change C403 from 100p to 330p 0319
VGATE
CLK_SD_48M<23>
CLK_ICH_48M<17>
CLK_ICH_14M<17>
C222
C222
CLK_SD_48M
33P_0402_50V8J@<RF>
33P_0402_50V8J@<RF>
C233
C233
CLK_ICH_48M
33P_0402_50V8J@<RF>
33P_0402_50V8J@<RF>
C242
C242
CLK_ICH_14M
12
10P_0402_50V8J
10P_0402_50V8J
C246
C246
CLK_PCI_LPC
33P_0402_50V8J@<RF>
33P_0402_50V8J@<RF>
C247
C247
CLK_PCI_ICH
33P_0402_50V8J@<RF>
33P_0402_50V8J@<RF>
CLK_PCI_LPC<25>
CLK_PCI_ICH<15>
1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS
R227
R227
10K_0402_5%
10K_0402_5%
@
@
1 2
ITP_EN PCI4_SEL PCI2_TME
R228
R228
10K_0402_5%
10K_0402_5%
1 2
4
H_STP_PCI#_R
1
C403
C403
330P_0402_50V7K
330P_0402_50V7K
2
+3VS+3VS +3VS
1 2
1 2
R232
R232
10K_0402_5%
10K_0402_5%
@
@
R231
R231
10K_0402_5%
10K_0402_5%
3
+3VM_CK505
C204
C204
1
2
1
2
<RF>
<RF>
1
C237
C237
10U_0805_10V4Z
10U_0805_10V4Z
2
+1.05VM_CK505
1
C198
C198
10U_0805_10V4Z
10U_0805_10V4Z
2
1
C210
C210
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C214
C214
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C234
C234
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C208
C208
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
SA000020K00 (Silego : SLG8SP556VTR )
SA000020H10 (ICS : ICS9LPRS387AKLFT)
H_STP_CPU#<17>
H_STP_PCI#_R<17>
+1.05VM_CK505
1 2
1 2
1 2
VGATE<17,25,37>
1 2
1 2
R229
R229
10K_0402_5%
10K_0402_5%
1 2
@
@
R230
R230
10K_0402_5%
10K_0402_5%
1 2
R19612_0402_5% R19612_0402_5%
R20212_0402_5% R20212_0402_5%
R21733_0402_5%
R21733_0402_5%
H_STP_CPU#
H_STP_PCI#_R
CLK_XTAL_IN
CLK_XTAL_OUT
R21933_0402_5%
R21933_0402_5%
R22033_0402_5%
R22033_0402_5%
+3VM_CK505
FSA
FSB
FSC
VGATE
PCI2_TME
PCI4_SEL
ITP_EN
U12
U12
55
VDD_SRC
6
VDD_REF
12
VDD_PCI
72
VDD_CPU
19
VDD_48
27
VDD_PLL3
66
VDD_CPU_IO
31
VDD_PLL3_IO
62
VDD_SRC_IO
52
VDD_SRC_IO
23
VDD_IO
38
VDD_SRC_IO
20
USB_0/FS_A
2
FS_B/TEST_MODE
7
REF_0/FS_C/TEST_
8
REF_1
1
CKPWRGD/PD#
11
NC
53
CPU_STOP#
54
PCI_STOP#
5
XTAL_IN
4
XTAL_OUT
13
PCI_1
14
PCI_2
15
PCI_3
16
PCI_4/SEL_LCDCL
17
PCIF_5/ITP_EN
18
VSS_PCI
3
VSS_REF
22
VSS_48
26
VSS_IO
69
VSS_CPU
30
VSS_PLL3
34
VSS_SRC
59
VSS_SRC
42
VSS_SRC
73
VSS
SLG8SP556VTR_QFN72_10X10
SLG8SP556VTR_QFN72_10X10
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
1
C238
C238
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C239
C239
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C206
C206
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
SRC_0/DOT_96
SRC_0#/DOT_96#
LCDCLK#/27M_SS
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
CLKREQ_11#
USB_1/CLKREQ_A#
2007/10/15 2008/09/20
2007/10/15 2008/09/20
2007/10/15 2008/09/20
SDA
CPU_0
CPU_0#
CPU_1
CPU_1#
LCDCLK/27M
SRC_2
SRC_2#
SRC_3
SRC_3#
SRC_4
SRC_4#
SRC_6
SRC_6#
SRC_7
SRC_7#
SRC_9
SRC_9#
SRC_10
SRC_10#
SRC_11
SRC_11#
CLKREQ_3#
CLKREQ_4#
CLKREQ_6#
CLKREQ_7#
CLKREQ_9#
SLKREQ_10#
1
2
9
10
SCL
71
70
68
67
24
25
28
29
32
33
35
36
39
40
57
56
61
60
64
63
44
45
50
51
48
47
37
41
58
65
43
49
46
21
Compal Secret Data
Compal Secret Data
Compal Secret Data
1
2
C217
C217
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CLK_SMBDATA
CLK_SMBCLK
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_ICH
CLK_PCIE_ICH#
MCH_CLKREQ#
WLAN_CLKREQ#
LAN_CLKREQ#
SATA_CLKREQ#
Deciphered Date
Deciphered Date
Deciphered Date
C235
C235
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C221
C221
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
1
C218
C218
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C228
C228
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
CLK_SMBDATA <11>
CLK_SMBCLK <11>
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
CLK_MCH_DREFCLK <6>
CLK_MCH_DREFCLK# <6>
MCH_SSCDREFCLK <6>
MCH_SSCDREFCLK# <6>
CLK_PCIE_SATA <16>
CLK_PCIE_SATA# <16>
CLK_MCH_3GPLL <8>
CLK_MCH_3GPLL# <8>
CLK_PCIE_WLAN <19>
CLK_PCIE_WLAN# <19>
CLK_PCIE_LAN <24>
CLK_PCIE_LAN# <24>
CLK_PCIE_ICH <17>
CLK_PCIE_ICH# <17>
MCH_CLKREQ# <6>
WLAN_CLKREQ# <19>
LAN_CLKREQ# <24>
SATA_CLKREQ# <17>
1
+3VS
R239
R239
2.2K_0402_5%
2.2K_0402_5%
R238 0_0402_5%
R238 0_0402_5%
1 2
@
@
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
ICH_SMBDATA<17>
ICH_SMBCLK<17>
6 1
Q4A
Q4A
3
1 2
@
@
2
5
Q4B
Q4B
4
+3VS
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
R226 0_0402_5%
R226 0_0402_5%
SRC PORT LIST
PORT
SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11
LAN_CLKREQ#
MCH_CLKREQ#
SATA_CLKREQ#
WLAN_CLKREQ#
0120 Add C393 C398 for power noise
Change C393 from 100p to 220p 0319.
LAN_CLKREQ# MCH_CLKREQ#
0210 Add C425 for power noise
SATA_CLKREQ#
1
2
1
2
C425 靠近U12
DEVICE
MCH_DREFCLK
SATA HDD
MCH_3GPLL
PCIE_WLAN
PCIE_LAN
PCIE_ICH
R259 10K_0402_5%
R259 10K_0402_5%
R181 10K_0402_5%
R181 10K_0402_5%
R212 10K_0402_5%
R212 10K_0402_5%
R186 10K_0402_5%
R186 10K_0402_5%
C393
C393
220P_0402_50V7K
220P_0402_50V7K
C425
C425
100P_0402_50V8J
100P_0402_50V8J
12
12
12
12
REQ PORT LIST
REQ_3#
REQ_4#
REQ_6#
REQ_7#
REQ_9#
REQ_10#
REQ_11#
REQ_A#
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Clock Generator CK505
Clock Generator CK505
Clock Generator CK505
MCH_3GPLL
PCIE_WLAN
PCIE_LAN
SATA
KTV00 LA-5241P
KTV00 LA-5241P
KTV00 LA-5241P
1
DEVICEPORT
+3VS
1
C398
C398
100P_0402_50V8J
100P_0402_50V8J
2
of
12 39Thursday, May 07, 2009
of
12 39Thursday, May 07, 2009
of
12 39Thursday, May 07, 2009
R225
R225
2.2K_0402_5%
2.2K_0402_5%
CLK_SMBDATA
CLK_SMBCLK
1.0
1.0
1.0
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