VERY PRECISE ADJUSTABLE OUTPUT
OVERVOLTAGEPROTECTION
MICROPOWERSTART-UPCURRENT (50µATYP.)
VERYLOW OPERATINGSUPPLY CURRENT
(4mA TYP.)
INTERNALSTART-UP TIMER
CURRENT SENSEFILTER ON CHIP
DISABLEFUNCTION
1% PRECISION (@ T
=25°C) INTERNAL
j
REFERENCEVOLTAGE
TRANSITIONMODE OPERATION
TOTEMPOLE OUTPUTCURRENT: ±400mA
DIP8/SO8PACKAGES
DESCRIPTION
L6561 is the improved version of the L6560
standard Power Factor Corrector. Fully compatible with the standard version, it has a superior
performant multiplier making the device capable
of working in wide input voltage range applications (from 85V to 265V) with an excellent THD.
Furthermore the start up current has been reduced at few tens of µA and a disable function
has been implemented on the ZCD pin, guaranteeing lower current consumption in stand by
mode.
L6561
POWER FACTOR CORRECTOR
Minidip SO8
ORDERING NUMBERS:
L6561 (Minidip)
L6561D
Realisedin mixedBCD technology,the chip gives
the followingbenefits:
- micro powerstart up current
- 1% precisioninternal referencevoltage
(Tj= 25°C)
- Soft Output Over Voltage Protection
- noneedforexternallowpas sfilt eronthecurr e n t
sense
- verylowoperatingquiescentcurrentminimises
powerdissipation
The totem pole output stage is capable of driving
a Power MOS or IGBT with source and sink currents of +/- 400mA. The device is operating in
transition mode and it is optimised for Electronic
Lamp Ballast application, AC-DC adaptors and
SMPS.
(SO8)
BLOCK DIAGRAM
April 1999
INV
V
COMP MULT CS
1
VOLTAGE
REGULATOR
8
CC
20V
R1
R2
2.3V
1.8V
6
GND
INTERNAL
SUPPLY 7V
+
-
V
REF2
2.5V
OVER-VOLTAGE
5
ZCD
23 4
-
+
DETECTION
UVLO
ZERO
-
+
CURRENT
DETECTOR
DISABLE
MULTIPLIER
+-
RSQ
STARTER
5pF
40K
DRIVER
D97IN547B
V
CC
7
GD
1/11
L6561
ABSOLUTE MAXIMUM RATINGS
Symbol Pin Parameter Value Unit
I
cc
V
I
GD
INV, COMP
8ICC+I
Z
7 Output Totem Pole Peak Current (2µs) ±700 mA
1, 2, 3 Analog Inputs & Outputs -0.3 to 7 V
MULT
CS 4 Current Sense Input -0.3 to 7 V
ZCD 5 Zero Current Detector 50 (source)
P
tot
Power Dissipation @T
=50°C (Minidip)
amb
(SO8)
T
j
T
stg
Junction Temperature Operating Range -25 to 150
Storage Temperature -55 to 150
PIN CONNECTION
30 mA
-10 (sink)
1
0.65
mA
mA
W
C
°
C
°
THERMAL DATA
Symbol Parameter SO 8 MINIDIP Unit
R
th j-amb
ThermalResistance Junction-ambient
150 100 °C/W
PIN FUNCTIONS
N. Name Function
1 INV Inverting input ofthe error amplifier. A resistivedivider is connected betweenthe output
2 COMP Output of error amplifier. A feedback compensation network is placed between thispin and
3 MULT Input of themultiplier stage. A resistive dividerconnects to this pinthe rectified mains. A
4 CS Input to thecomparator ofthe control loop. The current is sensedby a resistor and the
5 ZCD Zero current detectioninput. If it is connected to GND, the device isdisabled.
6 GND Current return for driver and control circuits.
7 GD Gate driver output. A push pull output stage isable to drivethe Power MOS with peak current
8V
CC
2/11
regulated voltage and this point, to provide voltage feedback.
the INV pin.
voltage signal, proportional to the rectified mains, appears on this pin.
resulting voltage is applied to this pin.
of 400mA (source and sink).
Supply voltage of driver and control circuits.
L6561
ELECTRICALCHARACTERISTICS(VCC= 14.5V; T
= -25°C to 125°C;unless otherwisespecified)
amb
SUPPLY VOLTAGE SECTION
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
V
CC
V
CC ON
CC OFF 8 Turn-off Threshold 8.7 9.5 10.3 V
V
8 Operating Range after turn-on 11 18 V
8 Turn-on Threshold 11 12 13 V
Hys 8 Hysteresis 2.2 2.5 2.8 V
SUPPLY CURRENT SECTION
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
START-U 8 Start-up Current before turn-on (V
I
q 8 Quiescent Current 2.6 4 mA
I
CC Operating Supply Current C
I
= 1nF @ 70KHz 4 5.5 mA
L
in OVP condition V
V
PIN5
PIN5
150mV, V
≤
150mV, V
≤
I
q
V
Z
Quiescent Current V
8 Zener Voltage ICC= 25mA 18 20 22 V
=11V) 20 50 90 µA
CC
= 2.7V 1.4 2.1 mA
pin1
CC>VCC off
CC<VCC off
20 50 90
1.4 2.1 mA
ERROR AMPLIFIER SECTION
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
V
INV
1 Voltage Feedback Input
Threshold
Line Regulation V
I
INV
G
V
1 Input Bias Current -0.1 -1 µA
Voltage Gain Open loop 60 80 dB
GB Gain Bandwidth 1 MHz
COMP 2 Source Current V
I
Sink Current V
V
COMP
2 Upper Clamp Voltage I
Lower Clamp Voltage I
T
=25°C 2.465 2.5 2.535 V
amb
12V< V
CC
COMP
COMP
SOURCE
Sink
<18V 2.44 2.56
CC
= 12 to18V 2 5 mV
= 4V, V
= 4V, V
= 2.4V -2 -4 -8 mA
INV
= 2.6V 2.5 4.5 mA
INV
= 0.5mA 5.8 V
= 0.5mA 2.25 V
A
µ
MULTIPLIERSECTION
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
V
MULT
∆V
CS
V
∆
mult
K Gain V
3 Linear Operating Voltage 0to3 0 to3.5 V
Output Max. Slope V
= from0V to 0.5V
MULT
V
= UpperClamp Voltage
COMP
=1V V
MULT
1.65 1.9
= 4V 0.45 0.6 0.75 1/V
COMP
CURRENT SENSECOMPARATOR
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
V
CS
4 Current Sense Reference
Clamp
CS 4 Input Bias Current V
I
t
d (H-L)
4 Delay to Output 200 450 ns
4 Current Sense Offset 0 15 mV
V
= 2.5V
MULT
V
= Upper Clamp Voltage
COMP
= 0 -0.05 -1 µA
OS
1.6 1.7 1.8 V
3/11
L6561
ELECTRICALCHARACTERISTICS
(continued)
ZERO CURRENT DETECTOR
Symbol Pin Parameter Test Condition Min. Typ. Max. Unit
V
V
V
V
I
I
I
V
I
ZCD
ZCD
ZCD
ZCD
ZCD
ZCD
ZCD
DIS
ZCD
5 Input Threshold Voltage
Rising Edge
Hysteresis (1) 0.3 0.5 0.7 V
5 Upper Clamp Voltage IZCD =20µA 4.5 5.1 5.9 V
5 Upper Clamp Voltage I
5 Lower Clamp Voltage I
5 Sink Bias Current 1V≤V
5 Source Current Capability -3 -10 mA
5 Sink CurrentCapability 3 10 mA
5 Disable threshold 150 200 250 mV
5 Restart Current After Disable V
(1) 2.1 V
= 3mA 4.7 5.2 6.1 V
ZCD
= –3mA 0.3 0.65 1 V
ZCD
4.5V 2
≤
ZCD
< Vdis; VCC>V
ZCD
CCOFF
-100 -200 -300 µA
OUTPUT SECTION
V
GD
r 7 Output VoltageRise Time CL = 1nF 40 100 ns
t
f 7 Output Voltage Fall Time CL = 1nF 40 100 ns
t
I
GD off
7 Dropout Voltage I
7IGDSink Current VCC=3.5V VGD= 1V 5 10 - mA
GDsource
I
GDsource
I
GDsink
GDsink = 20mA 0.3 V
I
= 200mA 1.2 2 V
= 20mA 0.7 1 V
= 200mA 1.5 V
OUTPUT OVERVOLTAGE SECTION
I
OVP
2 OVP Triggering Current 35 40 45 µA
Static OVP Threshold 2.1 2.25 2.4 V
RESTART TIMER
t
START
(1) Parameter guaranteed by design, not testedin production.
Start Timer 70 150 400 µs
A
µ
OVER VOLTAGEPROTECTION OVP
The output voltage is expected to be kept by the
operation of the PFC circuit close to its nominal
value. This is set by the ratio of the two external
resistors R
1 and R2 (see fig. 2), taking into con-
sideration that the non inverting input of the error
amplifier isbiased inside the L6561at 2.5V.
In steady state conditions, the current throughR1
and R2 is:
I
R1sc
V
out
=
R1
= I
R2
=
2.5V
R2
− 2.5
and, if the external compensation network is
comp
made only with a capacitor C
throughC
comp equalszero.
, the current
When the output voltage increases abruptly the
current throughR1 becomes:
V
4/11
+∆V
outsc
=
I
R1
R1
OUT
− 2.5
I
R1sc
+∆
I
R1
=
Since the current through R2 does not change,
∆
R1
I
must flow through the capacitor C
comp
and
enter theerror amplifier.
Thiscurrentis monitoredinsidethe L6561andwhen
reachesabout37µA the outputvoltageof themulti-
plieris forcedto decrease,thusreducing theenergy
drawn from the mains . If the current exceeds 40µA,
the OVP protectionis triggered(Dynami cOVP),and
the externalpowertransistoris switched offuntilthe
currentfallsapproximatelybelow10µA.
However, if the overvoltage persists, an internal
comparator(Static OVP) confirms theOVP condition keeping the external power switch turned off
(see fig.1).
Finally, the overvoltage that triggers the OVP
functionis:
1 ⋅
∆
Vout = R
Typical values for R
1,R2and C are shown in the
40µA.
applicationcircuits. Theovervoltagecanbe setindependentlyfrom the average outputvoltage.The precision in setting the overvoltage threshold is 7% of
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