BBK DW9937S Service Manual

SERVICE MANUAL

DW9937S

Ver 0.0

PREFACE

INDEX

FEATURES
FRONT PANEL&REAR PANEL
REMOTE CONTROL

........................................................................................................................

.................................................................................................................

BLOCK DIAGRAM

BLOCK DIAGRAM

.............................................................................................................

EXPLODED VIEW

EXPLODED VIEW

......................................................................................................................

PARTS SPECIFICATIONS

SST39VF16 0 ............................................................................................................................... 6

M13S128168A ............................................................................................................................

TSB41AB1
TVP5146
CS4360

CS5333 ......................................................................................................................................... 15

74HC/HCT14 ............................................................................................................................. 17

74ALVT16373 ...................................................................................................................... 18

MM1313 ............................................................................................................................................ 19-30

MAX4051 .......................................................................................................................................... 31-50

FSDM07652RB ................................................................................................................................ 51-70

LP2995

PQXXXEZ02Z .......................................................................................................................... 72

TUNER .............................................................................................................. 73

..................................................................................................................................

...................................................................................................................... 9

........................................................................................................................................ 13

................................................................................................................

........................................................................................................................

1
2
3

4

5

7

8

71

SCHEMA

TIC DIAGRAM&PCB SILKSCREEN

MAIN BOARD SCHEMATIC AND PCB LAYOUT

AV BOARD SCHEMATIC ..................................................................................................... 85-95

KEY BOARD SCHEMATIC .......................................................................................................

POWER BOARD SCHEMATIC ........................................................................................... 97

VCR MODLE 98-100

PARTSLIST

MAIN BOARD .............................................................................................................................. 101-102

MAIN PANEL BOARDKEY

POWER BOARD .............................................................................................................. 105-107

AV BOARD 108-110

............................................................................

.........................................................................................................................

......................................................................................................................

....................................................................................................................................

74-84

96

103-104

1

2

3

BLOCK DIAGRAM

POWER SUPPLY

Power board Video signal(s) Main pannel board

Audio signal(s)

Control signal(s)

wake up signal

Power on/off signal

VCR

VCR CVBS signal

HC4052

VCR L&R audio signals

MSP3415

CD4052

AV Channel

VMM1313

Switch

audio Signals outputs (except mixed L/R Audio) (except CVBS )

CVBS &mixed Audio inputs Video inputs Audio outputs Video outputs

key matrix

µPD16316

VFD-DISP

Video ADC

5146

DNM8602

Audio ADC

CS5333

CS4360

Audio

DVD L&R audio signals

DVD CVBS signal

Main board

4

AV board

EXPLODED VIEW

55

FUNCTIONAL BLOCK DIAGRAM

A19 - A

0

CE#
OE#

WE#

X-Decoder

Address Buffer & Latches

Control Logic

16 Megabit Multi-Purpose Flash

SST39VF160Q / SST39VF160

Advance Information

16,777,216 bit

EEPROM
Cell Array

Y-Decoder

I/O Buffers and Data Latches

DQ15 - DQ

V

0

DDQ

329 ILL B1.2

A15
A14
A13
A12
A11
A10

A19

WE#

A18
A17

1
2
3
4
5
6

A9

7

A8

8
9

NC

10
11

NC

12

NC

13

NC

14

NC

15
16
17

A7

18

A6

19

A5

20

A4

21

A3

22

A2

23

A1

24

Standard Pinout

T op Vie w

Die Up

SST39VF160Q

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

329 ILL F01.2

A16
V
V
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
CE#
A0

FIGURE 1: PIN ASSIGNMENTS FOR 48-PIN TSOP PACKAGES

123456

A

A3 A7 NC WE# A9 A13

B

A4 A17 NC NC A8 A12

C

A2 A6 A18 NC A10 A14

D

A1 A5 NC A19 A11 A15

E

A0 DQ0 DQ2 DQ5 DQ7 A16

F

CE# DQ8 DQ10 DQ12 DQ14 V

G

OE# DQ9 DQ11 V

H

V

DQ1 DQ3 DQ4 DQ6 V

SS

SST39VF160Q

DD

DQ13 DQ15

DDQ

SS

329 ILL F02.4

DDQ
SS

DD

SS

A15
A14
A13
A12
A11
A10

A19

WE#

A18
A17

NC

NC
NC
NC
NC

A9
A8

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Standard Pinout

T op Vie w

Die Up

SST39VF160

123456

A

A3 A7 NC WE# A9 A13

B

A4 A17 NC NC A8 A12

C

A2 A6 A18 NC A10 A14

D

A1 A5 NC A19 A11 A15

E

A0 DQ0 DQ2 DQ5 DQ7 A16

F

CE# DQ8 DQ10 DQ12 DQ14 NC

G

OE# DQ9 DQ11 V

H

V

DQ1 DQ3 DQ4 DQ6 V

SS

SST39VF160

DD

DQ13 DQ15

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

329 ILL F01a.0

SS

329 ILL F02a.0

A16
NC
V

SS

DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V

DD

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V

SS

CE#
A0

FIGURE 2: PIN ASSIGNMENTS FOR 48-PIN TFBGA

6

ESMT



 



M13S128168A

45

45









;(


 




 
 







































45-45







  

2

2












































































































































66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)



























































































 

























































































Elite Semiconductor Memory Technology Inc.

7

Publication Date : Nov. 2002

Revision : 0.2

Revision : 0.2






   


SLLS423D – JUNE 2000 – REVISED SEPTEMBER 2002

description (continued)

required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is
in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it
to normal operation.

When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a
low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB1 disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the port (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt
enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a
port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify
the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected
on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes
active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high
when the TSB41AB1 is in the low-power mode.

The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet
addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output
when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON
output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON
to be active.

PHP package terminal diagram

SYSCLK

CTL0
CTL1

D0
D1
D2
D3
D4
D5
D6
D7

PD

LREQ

DGND

DGND

47 46 45 44 4348 42 40 39 3841

1
2
3
4
5
6
7
8
9
10
11
12

14 15

LPS

DGND

C/LKON

16

13

PHP PACKAGE

(TOP VIEW)

DDDVDD

DV

XO

XI

TSB41AB1

17 18 19 20

ISO

PC1

PC2

PC0

DD

PLLGND

PLLV

FILTER1

22 23 24

21

DD

CPS

DV

TESTM

FILTER0

RESET

37

SE

SM

36
35
34
33
32
31
30
29
28
27
26
25

AGND
AV

DD

R1
R0
AGND
TPBIAS
TPA+
TPA–
TPB+
TPB–
AGND
AV

DD

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1.5 Functional Block Diagram

TVP5146

CVBS/

Pb/B/C

CVBS/

Y/G

CVBS/
Pr/R/C

CVBS/Y

VI_1_A
VI_1_B

VI_1_C

VI_2_A
VI_2_B

VI_2_C

VI_3_A
VI_3_B

VI_3_C

VI_4_A

Protection

Detector

Analog Front End

ADC1

ADC2

ADC3

ADC4

Sampling
Clock

Copy

M
U
X

Timing Processor

with Sync Detector

CVBS/Y/G

CVBS/Y

C

Y/G

Pb/B

Pr/R

VBI

Data

Slicer

Composite and S-Video Processor

Y/C

Separation

5-line

Adaptive

Comb

Gain/Offset

Y

C

Component

Luma

Processing

Chroma

Processing

Processor

Color

Space

Conversion

YCbCr

YCbCr

Host

Interface

Output

Formatter

Y[9:0]

C[9:0]

FSS

GPIO

XTAL1

XTAL2

PWDN

RESETB

AVID

DATACLK

FID

VS/VBLK

GLCO

HS/CS

DRDGDB

Figure 1–1. Functional Block Diagram

FSO

SCL

SDA

1–4

9

1.6 Terminal Assignments

VI_1_A

CH1_A18GND

CH1_A18VDD

PLL_A18GND

PLL_A18VDD

XTAL2

XTAL1

PFP PACKAGE

(TOP VIEW)

VS/VBLK/GPIO

HS/CS/GPIO

FID/GPIO

C_0/GPIO

C_1/GPIO

DGND

DVDD

C_2/GPIO

C_3/GPIO

C_4/GPIO

C_5/GPIO

IOGND

IOVDD

TVP5146

VI_1_B
VI_1_C

CH1_A33GND

CH1_A33VDD
CH2_A33VDD

CH2_A33GND

VI_2_A
VI_2_B
VI_2_C

CH2_A18GND

CH2_A18VDD
A18VDD_REF

A18GND_REF

CH3_A18VDD

CH3_A18GND

VI_3_A
VI_3_B
VI_3_C

CH3_A33GND

CH3_A33VDD

79 78 77 76 7580 74 72 71 7073

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

22 23

24

VI_4_A

CH4_A33VDD

CH4_A33GND

25 26 27 28

SCL

AGND

DGND

CH4_A18VDD

CH4_A18GND

29

30 31 32 33

SDA

INTREQ

69 682167 66 65 64

34 35 36 37 38 39 40

DVDD

DGND

PWDN

RESETB

FSS/GPIO

63 62 61

IOVDD

AVID/GPIO

GLCO/I2CA

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

IOGND

DATACLK

C_6/GPIO/RED
C_7/GPIO/GREEN
C_8/GPIO/BLUE
C_9/GPIO/FSO
DGND
DVDD
Y_0
Y_1
Y_2
Y_3
Y_4
IOGND
IOVDD
Y_5
Y_6
Y_7
Y_8
Y_9
DGND
DVDD

Figure 1–2. Terminal Assignments Diagram

10

1–5

TVP5146

1.7 Terminal Functions

Table 1–1. Terminal Functions

TERMINAL

NAME NUMBER

Analog Video

VI_1_A
VI_1_B
VI_1_C
VI_2_A
VI_2_B
VI_2_C
VI_3_A
VI_3_B
VI_3_C
VI_4_A

Clock Signals

DATACLK 40 O Line-locked data output clock.

XTAL1 74 I

XTAL2 75 O External clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator.

Digital Video

C[9:0]/
GPIO[9:0]

D_BLUE 58 I Digital BLUE input from overlay device
D_GREEN 59 I Digital GREEN input from overlay device
D_RED 60 I Digital RED input from overlay device
FSO 57 I Fast-switch overlay between digital RGB and any video

Y[9:0]

Miscellaneous Signals

FSS/GPIO 35 I/O

GLCO/I2CA 37 I/O

INTREQ 30 O Interrupt request

PWDN 33 I

RESETB 34 I Reset input, active low

80

1
2
7
8

9
16
17
18
23

57, 58,
59, 60,
63, 64,
65, 66,

69, 70

43, 44,
45, 46,
47, 50,
51, 52,

53, 54

I/O

VI_1_x: Analog video input for CVBS/Pb/B/C
VI_2_x: Analog video input for CVBS/Y/G
VI_3_x: Analog video input for CVBS/Pr/R/C
VI_4_A: Analog video input for CVBS/Y

I

Up to 10 composite, 4 S-video, and 2 composite or 3 component video inputs (or a combination thereof)
can be supported.

The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 µF.
The possible input configurations are listed in the input select register at I2C subaddress 00h (see

Section 2.11.1).

External clock reference input. It may be connected to an external oscillator with a 1.8-V compatible clock
signal or a 14.31818-MHz crystal oscillator.

Digital video output of CbCr, C[9] is MSB and C[0] is LSB. Unused outputs can be left unconnected. Also,
these terminals can be programmable general-purpose I/O.

O

For the 8-bit mode, the two LSBs are ignored.

Digital video output of Y/YCbCr, Y[9] is MSB and Y[0] is LSB.

O

For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected.

Fast-switch (blanking) input. Switching signal between the synchronous component video (YPbPr/RGB)
and the composite video input.

Programmable general-purpose I/O
Genlock control output (GLCO). Two Genlock data formats are available: TI format and real time control

(RTC) format.
During reset, this terminal is an input used to program the I2C address LSB.

Power down input:
1 = Power down
0 = Normal mode

DESCRIPTION

1–6

11

Table 1–1. Terminal Functions (Continued)

TVP5146

TERMINAL

NAME NUMBER

Host Interface

SCL 28 I I2C clock input
SDA 29 I/O I2C data bus

Power Supplies

AGND 26 I Analog ground. Connect to analog ground.
A18GND_REF 13 I Analog 1.8-V return
A18VDD_REF 12 I Analog power for reference 1.8 V
CH1_A18GND

CH2_A18GND
CH3_A18GND
CH4_A18GND

CH1_A18VDD
CH2_A18VDD
CH3_A18VDD
CH4_A18VDD

CH1_A33GND
CH2_A33GND
CH3_A33GND
CH4_A33GND

CH1_A33VDD
CH2_A33VDD
CH3_A33VDD
CH4_A33VDD

DGND

DVDD

IOGND 39, 49, 62 I Digital power return
IOVDD 38, 48, 61 I Digital power. Connect to 3.3 V or less for reduced noise.
PLL_A18GND 77 I Analog power return
PLL_A18VDD 76 I Analog power. Connect to 1.8 V.

Sync Signals

HS/CS/GPIO 72 I/O

VS/VBLK/GPIO 73 I/O

FID/GPIO 71 I/O

AVID/GPIO 36 I/O

79
10
15
24

78

11
14
25

3

6
19
22

4

5
20
21

27, 32, 42,

56, 68

31, 41, 55,

67

I/O

I Analog 1.8-V return

I Analog power. Connect to 1.8 V.

I Analog 3.3-V return

I Analog power. Connect to 3.3 V.

I Digital return

I Digital power. Connect to 1.8 V.

Horizontal sync output or digital composite sync output
Programmable general-purpose I/O

Vertical sync output (for modes with dedicated VSYNC) or VBLK output
Programmable general-purpose I/O

Odd/even field indicator output. This terminal needs a pulldown resistor.
Programmable general-purpose I/O

Active video indicator output
Programmable general-purpose I/O

DESCRIPTION

121413151416151716

1–7

Philips SemiconductorsProduct specification

Hex inverting Schmitt trigger 74HC/HCT14

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 3, 5, 9, 11, 13 1A to 6A data inputs
2, 4, 6, 8, 10, 12 1Y to 6Y data outputs
7 GND ground (0 V)
14 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

FUNCTION TABLE

INPUT OUTPUT

nA nY

L

H

Notes

1. H = HIGH voltage level
L = LOW voltage level

APPLICATIONS

• Wave and pulse shapers

• Astable multivibrators

• Monostable multivibrators

Fig.4 Functional diagram. Fig.5 Logic diagram

(one Schmitt trigger).

H

L

17

Philips Semiconductors Product specification

74ALVT163732.5V/3.3V 16-bit transparent D-type latch (3-State)

LOGIC SYMBOL

47 46 44 43

1

1D0 1D1 1D2 1D3

1LE
1OE

1Q0 1Q1 1Q2651Q3

32

36 35 33 32

2D02D21 2D2 2D3

2LE
2OE

2Q0 2Q1 2Q2 2Q3

1413 1716

48

25
24

41 40 38 37

1D4 1D5 1D6 1D7

1Q4 1Q5 1Q6

30 29 27 26

2D4 2D5 2D6 2D7

2Q4 2Q5 2Q6 2Q7

98

2019 2322

1Q7

1211

SA00044

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

47, 46, 44, 43, 41, 40, 38, 37,
36, 35, 33, 32, 30, 29, 27, 26

2, 3, 5, 6, 8, 9, 11, 12, 13,

14, 16, 17, 19, 20, 22, 23

1, 24 1OE, 2OE

48, 25 1LE, 2LE

4, 10, 15, 21, 28, 34, 39, 45 GND Ground (0V)

7, 18, 31, 42 V

1D0 – 1D7
2D0 – 2D7

1Q0 – 1Q7
2Q0 – 2Q7

CC

Data inputs

Data outputs

Output enable
inputs
(active-Low)

Enable inputs
(active-High)

Positive
supply voltage

LOGIC SYMBOL (IEEE/IEC)

1OE
1LE
2OE
2LE

1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1

2D2
2D3
2D4
2D5
2D6
2D7
2D8

1
48
24
25

47
46
44
43
41
40
38
37
36

35
33
32
30
29
27
26

1EN
C3
2EN
C4

3D

4D

PIN CONFIGURATION

1

1OE

2

1Q0

1Q1

3

GND

4

1Q2

5
6

1Q3

7

V

CC

8

1Q4
1Q5

9

GND

10

1Q6

11

1Q7

12

2Q0

13

2Q1

14

GND

15
16

2Q2
2Q3

17
18

V

CC

2Q4

19
20

2Q5

21

GND

22

2Q6

23

2Q7

24

2OE

1 ∇

2 ∇

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

SA00043

1LE
1D0
1D1
GND
1D2
1D3

V

CC

1D4
1D5

GND
1D6
1D7
2D0
2D1
GND
2D2

2D3
V

CC

2D4
2D5
GND

2D6
2D7
2LE

2

1Q1

3

1Q2

5

1Q3

6

1Q4

8

1Q5

9

1Q6

11

1Q7

12

1Q8

13

2Q1

14

2Q2

16

2Q3

17

2Q4

19

2Q5

20

2Q6

22

2Q7

23

2Q8

SW00010

18

2

C BUS Control 5-Input 2-Output AV Switch MM1313

MITSUMI

I

I2C BUS Control 5-Input 2-Output AV Switch

Monolithic IC MM1313

Outline

This IC is a 5-input 2-output AV switch with I2C control, developed for use in televisions. Two outputs enable
it to support two screens or "picture-in-picture".

Features

1. Serial control by I2C bus.

2. 5-inputs, 2-outputs.

3. Video and audio system switches can be controlled independently.

4. 6dB amplifier built in to video system.

5. Built-in Y/C MIX circuit.

6. Slave address can be changed : 90H or 92H.

7. Audio muting possible by external pin.

8. Maintains high impedance even when I

9. Built-in 3 value discrimination function.

10.On-chip power ON reset function.

11.Two types of audio input impedance : 60kΩ and 30kΩ.
MM1313AD : 60kΩ MM1313BD : 30kΩ

12.Supports 2-screen or P-IN-P TV.

2

C BUS line (SDA, SCL) power supply is off.

Package

SDIP-42A (MM1313AD, MM1313BD)

Applications

1. Televisions

2. Other video equipment

19

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Equivalent Block Diagram

2

C BUS Control 5-Input 2-Output AV Switch MM1313

I

20

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Pin Function

2

C BUS Control 5-Input 2-Output AV Switch MM1313

I

Pin No.

Name

41 MTV-V

1 V1

7 V2

13 V3

27 STV

3 V1

9 V2

31 Y

5 V1-C

11 V2

29 C

42 MTV-L

2 V1

8 V2
14 V3
25 STV
40 MTV

4 V1
10 V2
16 V3
26 STV

-

-

-

-

-

IN1

-

IN1

-

-

-

-

-

-

Internal equivalent circuit diagram

Pin No.

Name

Internal equivalent circuit diagram

33 LOUT1

V

V

V

-

V

22 L

32 R

24 R

OUT2

OUT1

OUT2

Y

Y

36 BIAS

C

19 SCL

L
L
L

-

L

-

R
R
R
R

-

R

34 VOUT1

23 V

OUT2

37 YOUT1

39 C

OUT1

20 SDA

6 S1

12 S2

21 ADR

28 Mute

21

MITSUMI

2

C BUS Control 5-Input 2-Output AV Switch MM1313

I

Absolute Maximum Ratings

Item Symbol Ratings Units

Storage temperature T

Operating temperature T

Power supply voltage V

Allowable power dissipation Pd 850 mW

Electrical Characteristics

Item Symbol

Operating power supply voltage

Current consumption I

V

OUT1 output

Voltage gain G

Frequency characteristics F

Differential gain DG

Differential phase DP

Input dynamic range D

V

OUT2 output

Voltage gain G

Frequency characteristics F

Differential gain DG

Differential phase DP

Input dynamic range D

YOUT1 output

Voltage gain

Frequency characteristics

Differential gain DGY TP2

Differential phase DPY TP2

(Ta=25°C, VCC=9V)

VCC 8910V

CC 38 VCC=9V, no signal, no load 40 52 mA

V1 TP1 Sine wave 1.0VP-P, 100kHz 5.5 6.0 6.5 dB

V1 TP1

V1 TP1

V1 TP1

V1 SG1~3 Maximum input for total higher 1.6 1.9 VP-P

V2 TP6 Sine wave 1.0VP-P, 100kHz 5.5 6.0 6.5 dB

V2 TP6

V2 TP6

V2 TP6

V2 SG1~3 Maximum input for total higher 1.6 1.9 VP-P

G

Y1 TP2

G

Y2 TP2

Y1 TP2

F

F

Y2 TP2

(Ta=25°C)

Measure
ment pin

STG

OPR

CC 12 V

-

40~+125

-

20~+75

Conditions (unless otherwise indicated,

Measurement Circuit Figure 1)

Sine wave 1.0V

Vn-V : Staircase 1V

P-P

, 10MHz/100kHz-1.0 0 1.0 dB

P-P

°

C

°

C

Min. Typ. Max. Units

APL=10~90%

Vn-Y : Staircase (luminance signal) 1V

Vn-C : Chroma signal 0.3V

P-P

P-P

-

30 3 %

APL=10~90%

Vn-V : Staircase 1V

P-P

APL=10~90%

Vn-Y : Staircase (luminance signal) 1V

Vn-C : Chroma signal 0.3V

P-P

P-P

-

3 0 3 deg

APL=10~90%

Sine wave 100kHz

harmonic distortion factor < 1.0%

Sine wave 1.0V

10MHz/100kHz

Vn-V : Staircase 1V

P-P

P-P

-

1.0 0 1.0 dB

APL=10~90%

Vn-Y : Staircase (luminance signal) 1V

Vn-C : Chroma signal 0.3V

P-P

P-P

-

30 3 %

APL=10~90%

Vn-V : Staircase 1V

P-P

APL=10~90%

Vn-Y : Staircase (luminance signal) 1V

Vn-C : Chroma signal 0.3V

P-P

P-P

-

3 0 3 deg

APL=10~90%

Sine wave 100kHz

harmonic distortion factor < 1.0%

Vn-Y : Sine wave 1.0V

YIN1 : Sine wave 2.0V

-

Y : Sine wave 1.0VP

Vn

10MHz/100kHz

Y

IN1 : Staircase 2.0VP-P

10MHz/100kHz

Vn-Y : Staircase 1V

APL=10~90%

Y

IN1: Staircase 2VP-P

P-P

, 100kHz

P-P

, 100kHz-0.5 0 0.5

-

P

P-P

5.5 6.0 6.5

-

1.0 0 1.0

-

1.0 0 1.0

-

30 3 %

APL=10~90%

Vn-Y : Staircase 1V

APL=10~90%

IN1 : Staircase 2VP-P

Y

P-P

-

3 0 3 deg

APL=10~90%

dB

dB

22

MITSUMI

2

C BUS Control 5-Input 2-Output AV Switch MM1313

I

Item Symbol

D

Measure

ment pin

Y1 SG2 Maximum input for total higher 1.6 1.9

Input dynamic range

DY2 SG4 Maximum input for total higher 3.2 3.8

Output impedance Z

C

OUT1 output

Voltage gain

OYC150Ω

C1 TP3

G
G

C2 TP3

F

C1 TP3

Frequency characteristics

C2 TP3

F

Differential gain DG

Differential phase DP

C TP3

C TP3

D

C1 SG3 Maximum input for total higher 2.75 3.25

Input dynamic range

C2 SG5 Maximum input for total higher 5.5 6.5

D

Input impedance Z

Output impedance Z

OUT1 output

L

Voltage gain

Frequency characteristics F

Total higher harmonic distortion

Input dynamic range D

IC Vn

OC150Ω

G

L11 TP4 b7=0, Sine wave 2.5VP-P, 1kHz

G

L12 TP4 b7=1, Sine wave 2.5VP-P, 1kHz

L1 TP4 Sine wave 2.5VP-P, 1MHz/1kHz

1 TP4 Sine wave 2.5VP

THDL

L1 SG6 Maximum input for total higher 2.6 2.8 Vrms

Output offset voltage VOFFL133

Input impedance Z

Output impedance Z

L

OUT2 output

Voltage gain G

Frequency characteristics F

Total higher harmonic distortion

Input dynamic range D

IL1 426078kΩ

OL1 120 Ω

L2 TP7 Sine wave 2.5VP-P, 1kHz

L2 TP7 Sine wave 2.5VP-P, 1MHz/1kHz

THDL2 TP7 Sine wave 2.5VP

L2 SG6 Maximum input for total higher 2.6 2.8 Vrms

Output offset voltage VOFFL222

Output impedance Z

R

OUT1 output

Voltage gain

Frequency characteristics F

Total higher harmonic distortion

Input dynamic range D

OL2 120 Ω

R11 TP5 b7=0, Sine wave 2.5VP-P, 1kHz

G
G

R12 TP5 b7=1, Sine wave 2.5VP-P, 1kHz

R1 TP5 Sine wave 2.5VP-P, 1MHz/1kHz

R1 TP5 Sine wave 2.5VP-P, 1kHz 0.03 0.1 %

THD

R1 SG7 Maximum input for total higher 2.6 2.8 Vrms

Output offset voltage VOFFR132

Input impedance Z

Output impedance Z

IR1 426078kΩ

OR1 120 Ω

Conditions (unless otherwise indicated,

Measurement Circuit Figure 1)

Min. Typ. Max. Units

Vn-Y : Sine wave 100kHz

harmonic distortion factor < 1.0%

V

IN1 : Sine wave 100kHz

harmonic distortion factor < 1.0%

Vn-C : Sine wave 1.0V

CIN1 : Sine wave 2.0V

-

C : Sine wave 1.0VP

Vn

10MHz/100kHz

C

IN1 : Sine wave 2.0VP-P

10MHz/100kHz

IN1 : Staircase 2VP-P

C

APL=10~90%

C

IN1 : Staircase 2VP-P

APL=10~90%

P-P

, 100kHz

P-P

, 100kHz-0.5 0 0.5

-

P

5.5 6.0 6.5

-

1.0 0 1.0

-

1.0 0 1.0

-

30 3 %

-

3 0 3 deg

Vn-C : Sine wave 100kHz

harmonic distortion factor < 1.0%

CIN1: Sine wave 100kHz

harmonic distortion factor < 1.0%

-

C, CIN1 101520kΩ

-

6.5-6.0-5.5

-

0.5 0.0 0.5

-

3.0 0 1.0 dB

-

P, 1kHz 0.03 0.1 %

Sine wave 1kHz

harmonic distortion factor < 0.5%

L

OUT1 pin DC difference during

SW switching

-

0.5 0.0 0.5 dB

-

3.0 0 1.0 dB

-

P, 1kHz 0.03 0.1 %

Sine wave 1kHz

harmonic distortion factor < 0.5%

OUT2 pin DC difference during

L

SW switching

-

6.5-6.0-5.5

-

0.5 0.0 0.5

-

3.0 0 1.0 dB

Sine wave 1kHz

harmonic distortion factor < 0.5%

R

OUT1 pin DC difference during

SW switching

P-P

V

dB

dB

V

P-P

dB

0 ±15 mV

0 ±15 mV

dB

0 ±15 mV

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MITSUMI

SDA

SCL

t

BUF

P PS

tHD:STA tHD:DAT tHIGH tSU:DAT tSU:STA tSU:STD

tLOW

Sr

t

R tF

2

C BUS Control 5-Input 2-Output AV Switch MM1313

I

Item Symbol

Measure
ment pin

ROUT2 output

Voltage gain G

Frequency characteristics F

Total higher harmonic distortion

Input dynamic range D

R2 TP8 Sine wave 2.5VP-P, 1kHz

R2 TP8 Sine wave 2.5VP-P, 1MHz/1kHz

THDR2 TP8 Sine wave 2.5VP

R2 SG7 Maximum input for total higher 2.6 2.8 Vrms

Output offset voltage VOFFR224

Output impedance Z

OR2 120 Ω

Crosswalk

V

OUT 1 CTV1 TP1
OUT 2 CTV2 TP2

V
Y

OUT 1 CTY1 TP3

OUT 1 CTC1 TP6

C

L

OUT 1 CTL1 TP4
OUT 2 CTL2 TP5 Measurement Circuit Figure 2

L

R

OUT 1 CTR1 TP7 1kHz, 2.5VP-P

R

OUT 2 CTR2 TP8

Video I/O Pin Voltage

Input pin voltage V

VIP No signal, no load 4.6 4.9 5.2 V

VOP

V

Output pin voltage

V

SOP

Audio I/O Pin Voltage

Input pin voltage V

Output pin voltage V

AIP No signal, no load 4.0 4.3 4.6 V

AOP No signal, no load 3.9 4.2 4.5 V

Logic section (Refer to figure below)

Input voltage L V

Input voltage H V

Low level output voltage (SDA)

High level input current I

Low level input current I

Clock frequency f

Data transmission waiting time

SCL start hold time t

SCL low level hold time t

SCL high level hold time t

SCL start set-up time t

SDA data hold time t

SDA data set-up time t

SCL rise time t

SCL fall time t

SCL stop set-up time t

IL I

IH

VOL SDA for 3mA inflow 0.0 0.4 V

IH when SDA, SCL=4.5V impressed
IL when SDA, SCL=0.4V impressed

SCL 100 kHz

BUF 4.7 µS

t

HD;STA 4.0 µS

LOW 4.7 µS

HIGH 4.0 µS

SU;STA 4.7 µS

HD;DAT 200 nS

SD;DAT 250 nS

R 1000 nS

F 300 nS

SU;STO 4.0 µS

Conditions (unless otherwise indicated,

Measurement Circuit Figure 1)

-

P, 1kHz 0.03 0.1 %

Min. Typ. Max. Units

-

0.5 0.0 0.5 dB

-

3.0 0 1.0 dB

Sine wave 1kHz

harmonic distortion factor < 0.5%

R

OUT2 pin DC difference during

switching

Measurement Circuit Figure 2
for SG1 input : 4.43MHz, 1V
for SG2 input : 4.43MHz, 0.5V

VOUT1 pin, VOUT2 pin

No signal, no load

YOUT1 pin, COUT1 pin

No signal, no load

2

C logic low level discrimination value 0.0 1.5 V

2

I

Clogic high level discrimination value 3.0 5.0 V

P-P

P-P

4.1 4.4 4.7 V

3.3 3.6 3.9 V

-

-

0 ±15 mV

-

60-53 dB

-

60-53 dB

-

60-53 dB

-

60-53 dB

-

90-80 dB

-

90-80 dB

-

90-80 dB

-

90-80 dB

10 +10 µA
10 +10 µA

I2C BUS BUS Control Signal

24

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Measurement Circuit

Measurement Circuit 1

2

C BUS Control 5-Input 2-Output AV Switch MM1313

I

25

MITSUMI

Measurement Circuit 2 (Crosstalk measurement)

2

C BUS Control 5-Input 2-Output AV Switch MM1313

I

26

2

SDA

SCL

S

123456 78A123 8A P

S:Start Condition
P:Stop Condition
A:Acknowledge

C BUS Control 5-Input 2-Output AV Switch MM1313

MITSUMI

I

I2C BUS

The I2C BUS is a BUS system developed by Philips for internal use in equipment. Data transmission is carried
out by the two SDA and SCL lines, in byte units, with the MSB first from start condition.

[Control Register]

The control register contains data sent from the master in order to determine the status of each switch.

S

Slave address

1001000/10

R/W

A

Control register 1

b7 b6 b5 b4 b3 b2 b1 b0

A

Control register 2

b7 b6 b5 b4 b3 b2 b1 b0

AP

Address byte Control data

The data format is set as shown in the figure above. The first 7 bits in the address byte are allocated to the
slave address, and the remaining 1 bit is allocated to the read/write bit. The read/write bit is set at 0 when
using as a control register.
The MM1313 slave address can be selected as 90H/92H depending on the status of the ADR pin. When ADR
pin is low it is 90H.
The relationship between the control register bits and switch control is as shown below.

b7 b6 b5 b4 b3 b2 b1 b0

Audio

S/Comp

Video-Select Audio-Select

Gain Select

The control register bits are reset to 0 when power is applied.
MM1313 control is carried out by the 3-byte structure of the 1 address byte and 2 control data bytes. The first
byte in the control data is control data for output 1, and the remaining 1 byte is control data for output 2.
All of the remaining data (fourth byte and after) are ignored.
Refer to the separate tables for details on switch control.

27

2

Reset released

Reset status

Undefined

0.6V 4.3V 5.4V V

CC

C BUS Control 5-Input 2-Output AV Switch MM1313

MITSUMI

I

[Status Register]

The status register contains data for sending device status to the master.

S

A

Slave address R/W

Status register

NA P

1001000/11 b7b6b5b4b3b2b1b0

Address byte Status data

The data format is set as shown in the figure above. The first 7 bits in the address byte are allocated to the
slave address, and the remaining 1 bit is allocated to the read/write bit. The read/write bit is set at 1 when
using as a status register.
The MM1313 slave address can be selected as 91H/93H depending on the status of the ADR pin. When the
ADR pin is low it is 91H. However, the confirmation response after completion of the status register should be
non-acknowledge.
The status register output data as shown below.

b7 b6 b5 b4 b3 b2 b1 b0

P-ON S1 S1 S2 S2

RESET

OPEN SEL OPEN SEL

P-ON RESET : Returns 1 for power on reset. However once data read begins, 0 is returned next.
S1/S2 OPEN : Returns 0 when the S1/S2 pin is not open, and returns 1 when the S1/S2 pin is open
S1/S2 SEL : Returns 0 when the S1/S2 pin is not grounded, and returns 1 when the S1/S2 pin is grounded.

S1/S2 OPEN, SEL have 3-value discrimination, and the combinations are as shown below.

S1/S2 pin DC voltage S1/S2 OPEN S1/S2 SEL

0.8V or less 01

1.3V or more, 3.5V or less

00

4.5V or more 10

[Power On Reset]

Power on reset is built in to reset each control register to 0 when power is turned on.
Power on reset threshold has hysteresis as shown in the figure below. The IC power on reset status can be
discriminated by reading the status register P-ON RESET.

28