BBK DW9916S Service Manual
A
4 4
B
C
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FIGARO - 2
DMN8602MK Main Codec Board (DDR SDRAM)
BBK AV ELECTRONICS CORP.,LTD.
REVISION HISTORY
VER REV DATE DESCRIPTION
Initial Draft08/20/2003A0
1: Correct net name E5_SDRAM_DQ0(U27_M18) and E5_SDRAM_DQ1(U27_M19).09/27/2003A1
2: Change net I2C_SCL to IDC_SCL.
3 3
10/26/20031A BBK MODIFY BY FENGHONGJUN
SCHEMATICS CONTENTS
TITLE
FIGARO-2 COVER PAGE
E5.1
TERM AT E5 & DDR & VREF/VTT
2 (8M x 16) DDR SDRAM
RST, IR, AV IO/ELink-3 Connector, UART
FLASH, ATA, EEPROM, IR
1394 PHY & USB
2 2
POWER CONN
VIDEO IN
VIDEO OUT DRIVER
PAGE DESCRIPTION
1
2
3
4
5
6
7
8
9
10
1 1
LSI Logic Corporation
560 Cottonwood Drive
Milpitas, CA 95035
U.S.A.
Title
FIGARO-2 COVER PAGE
Size Document Number Rev
<Doc> A1
C
112Thursday, September 15, 2005
Date: Sheet
A
B
C
D
E
of
A
V33
R1
R11 10K
AO_SCLK11
AO_FSYNC11
AO_IEC9585
AO_MCLKO11
RDS_DATA7
AI_SCLK11
AI_FSYNC11
AI_MCLKO11
E5_GPIOx355,9
10K
AO_D111
AO_D211
AO_D311
AI_D011
TMS
TDI
TDO
TCK
C1
27P
13.5MHZ
C2
27P
TRST_L
GND
Y1
GND
VI_D[9..0]9
4 4
3 3
VI_VSYNC9
VI_CLK09
E5_GPIOx2
E5_GPIOx1
E5_GPIOx3
E5_GPIOx4
E5_GPIOx5
E5_GPIOx6
E5_GPIOx7
R36 10K
R37 10K
R38 10K
R39 10K
R40 10K
R41 10K
R42 10K
V33
(BIO_PHY_PD)
(VI_AVID)
(MIC_DET)
(MUTE)
(INT_VI)
(/RST_VI)
R2
10K
TP1
1
TP2
1
(Reset_Audio)
GND
VI_VSYNC
VI_CLK0
R4
R3
10K
10K
AO_D0
1
E5_GPIOx33
(Input Only)
E5_GPIOx32
CLKI
CLKX
TCK
TDI
TDO
TMS
TRST_L
VI_D0
VI_D1
VI_D2
VI_D3
VI_D4
VI_D5
VI_D6
VI_D7
VI_D8
VI_D9
E5_GPIOx07
E5_GPIOx112
E5_GPIOx212
E5_GPIOx39
E5_GPIOx412
E5_GPIOx511
E5_GPIOx69
E5_GPIOx79
GND
R19 22
R21 22
R23 22
R24 22
R26 22
R29 22
R30 22
R33 22
R34 22
R35 22
E5_GPIOx35
(SCART_GPIO)
(SCART_GPIO)
(SCART_GPIO)
E5_GPIO6
E5_GPIOx0
E5_GPIOx1
E5_GPIOx2
E5_GPIOx3
E5_GPIOx4
E5_GPIOx5
E5_GPIOx6
E5_GPIOx7
AO_1
AO_2
AO_3
AOSCLK
AOFSYNC
AOIEC
AOMCLKO
AISCLK
AIFSYNC
AIMCLKO
2 2
CVBS10
Y10
C10
Y/G10
Pb/B10
Pr/R10
V18_E5_DAC_DVDD
GND
V33_E5_DAC_AVDD
+
CA2
T47u/16
C6
C7
104
103
12
D2
IN4148
12
D3
C10
C9
C8
104
104
IN4148
103
VO_GND
VO_GND GND
1 1
A17
B15
B16
B17
B14
A14
B13
A13
A15
C14
D14
A12
D13
C13
A16
E1
F1
H1
G1
B7
A7
C6
B6
D6
B10
C10
B11
C11
D11
D10
B12
C12
D12
A11
A10
A9
D7
C7
D8
C8
B8
D9
C9
B9
A8
A1
A2
A3
A4
A5
A6
D5
B2
B3
C5
B4
B5
E5_SDRAM_A03
E5_SDRAM_A13
E5_SDRAM_A23
E5_SDRAM_A33
E5_SDRAM_A43
E5_SDRAM_A53
E5_SDRAM_A63
E5_SDRAM_A73
E5_SDRAM_A83
E5_SDRAM_A93
E5_SDRAM_A103
E5_SDRAM_A113
E5_SDRAM_A123
E5_SDRAM_A143
E5_SDRAM_A153
E5_SDRAM_CS03
E5_SDRAM_CAS#3
E5_SDRAM_RAS#3
E5_SDRAM_CLKE3
E5_SDRAM_WE#3
E5_SDRAM_CLK03
E5_SDRAM_CLK#03
E5_SDRAM_CLK13
E5_SDRAM_CLK#13
AO_D0
AO_D1
AO_D2
AO_D3
AO_SCLK
AO_FSYNC
AO_IEC958
AO_MCLKI
AO_MCLKO
AI_D0
AI_D1
AI_SCLK
AI_FSYNC
AI_MCLKI
AI_MCLKO
3.3v only
CLKI
CLKX
CLKO
BYPASS_PLL
TCK
TDI
TDO
TMS
TRST_L
VI_D0
VI_D1
VI_D2
VI_D3
VI_D4
VI_D5
VI_D6
VI_D7
VI_D8
VI_D9
VI_VSYNC0
VI_CLK0
VO_D0
VO_D1
VO_D2
VO_D3
VO_D4
VO_D5
VO_D6
VO_D7
VO_CLK
VDENC
012
SEL
DAC1
CPST Y -
DAC2
Y CPST -
DAC3
C CPST -
DAC4
G/Y Y -
DAC5
B/Pb C CPST
DAC6
R/Pr C CPST
DAC_Dvdd (1.8v)
DAC_Vdd0(3.3v)
DAC_Vdd1(3.3v)
DAC_Dvss
DAC1bar
DAC0bar
V33_E5_USB
+
C11
GND
10UF/1206
VREF3,4
GPIO[6]
GPIO[7]
AOUT
CS[9]-
CS[8]-
DACO
GPIOx[31]
GPIOx[34]
GPIOx[33]
GPIOx[32]
GPIOx[35]
JTAG
PEC
GPIOx[45]
GPIOx[29]
2nd 24-bit
VI_D0
VI_D1
VI_D2
VI_D3
VI_D4
VI_D5
VI_D6
VI_D7
VI_D8
VI_D9
voutvin
VO_D16
VO_D17
VO_D18
VO_D19
VO_D20
VO_D21
VO_D22
VO_D23
GPIOx[0]
GPIOx[1]
GPIOx[2]
GPIOx[3]
GPIOx[4]
GPIOx[5]
GPIOx[6]
GPIOx[7]
GPIOx[8]
GPIOx[9]
GPIOx[10]
GPIOx[11]
GPIOx[12]
GPIOx[13]
GPIOx[14]
GPIOx[15]
GPIOx[30]
20-bit
vin
VI_D10
VI_D11
VI_D12
VI_D13
VI_D14
VI_D15
VI_D16
VI_D17
VI_D18
VI_D19
3.3V ONLY
USB 1394
POWER
3.3V
GND
Dplus_0
USB_Avdd0(3.3v)
USB_VSS0
G3G4H2
F3
F4
C12
104
USB_D0-
USB_D0+
VREF
D16
SDRAM_VREF
Dminus_0
Host_PO_0
USB_PO0
VIN
H3
USB_OC0
L20
K20
E20
D20
SDRAM_CLK1
SDRAM_CLK_L0
SDRAM_CLK_L1
AIN
SYSTEM
2nd
vout
VO_D0
VO_D1
VO_D2
VO_D3
VO_D4
VO_D5
VO_D6
VO_D7
VOUT
GPIOx[43]
GPIOx[44]
Host_OC_0
7
7
7
C14
102
N18
N19
SDRAM_CLK0
SDRAM_WE_L
VIO
GPIOx[36]
7
GND
SSTL2_VDD
GND
SDRAM_CKE
BIO_PHY_DATA7
N17
C?
101
P20
SDRAM_CAS_L
SDRAM_RAS_L
BIO_PHY_DATA5
BIO_PHY_DATA6
C15
102
E5_SDRAM_CS1
E5_SDRAM_A15
R20
P19
P18
SDRAM__A17
SDRAM__A16
SDRAM__A15
BIO_PHY_DATA1
BIO_PHY_DATA2
BIO_PHY_DATA3
BIO_PHY_DATA4
L2L4L3J1K4K3K2
BIO_PHY_DATA1
A
B
E5_SDRAM_A9
E5_SDRAM_A7
E5_SDRAM_A6
E5_SDRAM_A5
E5_SDRAM_A4
E5_SDRAM_A2
E5_SDRAM_A14
Y20
SDRAM__A14
E5_SDRAM_A12
U20
*SDRAM__A13
E5_SDRAM_A11
V19
SDRAM__A12
E5_SDRAM_A10
U18
SDRAM__A11
W20
SDRAM__A10
E5_SDRAM_A8
U19
SDRAM__A8
SDRAM__A9
E5_SDRAM_A0
E5_SDRAM_A3
E5_SDRAM_A1
R17
T19
P17
R19
R18
T18
T20
V20
SDRAM__A0
SDRAM__A1
SDRAM__A2
SDRAM__A3
SDRAM__A4
SDRAM__A5
SDRAM__A6
SDRAM__A7
SDRAM I/F
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
PADS CORE
3.3V 1.8V 3.3V
BIO_PHY_DATA0
BIO_PHY_CTL0
BIO_PHY_CTL1
BIO_LREQ
BIO_LPS
BIO_LINK_ON
BIO_PHY_CLK
VDD_PAD1
VDD_PAD2
VDD_PAD3
VDD_PAD4
VDD_PAD5
VDD_PAD6
7
J5K5E11
E5_VPAD
7
7
7
7
7
C18
104
C53
103
E12
T12
7
E5_AVDD
VDD_PAD7
T11
7
C19
104
J2
J3K1N1M1J4L1H4
BIO_LPS
BIO_LREQ
BIO_PHY_CLK
BIO_LINK_ON
BIO_PHY_CTL1
BIO_PHY_CTL0
BIO_PHY_DATA0
C16
C17
102
104
E5_VDDREF E5_VDDX
C51
C52
103
104
GND GND GND
B
E5_SDRAM_DQ[31..0] 3
3
3
E5_SDRAM_DQS3
E5_SDRAM_DQ29
E5_SDRAM_DQ31
E5_SDRAM_DQ30
E5_SDRAM_DQM3
C19
B19
C20
C18
D18
SDRAM_DQ29
SDRAM_DQ30
SDRAM_DQ31
SDRAM_DQS3
SDRAM_DQM3
E5_SDRAM_DQS2
E5_SDRAM_DQ25
E5_SDRAM_DQ26
E5_SDRAM_DQ23
E5_SDRAM_DQ27
E5_SDRAM_DQ28
E5_SDRAM_DQ24
E5_SDRAM_DQM2
E17
A18
B18
A20
A19
B20
F19
F20
SDRAM_DQ24
SDRAM_DQ25
SDRAM_DQ27
SDRAM_DQ26
SDRAM_DQ28
SDRAM_DQS2
SDRAM_DQM2
3
3
E5_SDRAM_DQS1
E5_SDRAM_DQ20
E5_SDRAM_DQ21
E5_SDRAM_DQ22
F17
E19
E18
SDRAM_DQ20
SDRAM_DQ21
SDRAM_DQ22
SDRAM_DQ23
E5_SDRAM_DQ15
E5_SDRAM_DQ18
E5_SDRAM_DQ19
E5_SDRAM_DQ17
E5_SDRAM_DQ16
E5_SDRAM_DQM1
G20
G19
G18
G17
F18
J20
H20
SDRAM_DQ16
SDRAM_DQ17
SDRAM_DQ18
SDRAM_DQ19
SDRAM_DQS1
SDRAM_DQM1
3
3
E5_SDRAM_DQ8
E5_SDRAM_DQ9
E5_SDRAM_DQS0
E5_SDRAM_DQ12
E5_SDRAM_DQ14
E5_SDRAM_DQ11
E5_SDRAM_DQ10
E5_SDRAM_DQ13
E5_SDRAM_DQM0
J19
J18
H17
H19
H18
J17
K17
M20
K19
SDRAM_DQ9
SDRAM_DQ8
SDRAM_DQ15
SDRAM_DQ12
SDRAM_DQ14
SDRAM_DQ10
SDRAM_DQ13
SDRAM_DQ11
SDRAM_DQM0
3
E5_SDRAM_DQ0
E5_SDRAM_DQ3
E5_SDRAM_DQ6
E5_SDRAM_DQ2
E5_SDRAM_DQ7
E5_SDRAM_DQ1
E5_SDRAM_DQ4
E5_SDRAM_DQ5
N20
M19
M18
M17
L19
L18
L17
K18
SDRAM_DQ2
SDRAM_DQ1
SDRAM_DQ3
SDRAM_DQ4
SDRAM_DQ5
SDRAM_DQ6
SDRAM_DQ7
SDRAM_DQS0
DATAADDRCONTROL
E5.1-BGA-308-A
U1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
POWER GND
SDRAM
SDR
3.3V
DDR
2.5V 5V
VDD_CORE8
VDD_CORE2
VDD_CORE3
C55
104
VDD_CORE4
VDD_CORE5
T10E9E10
C21
104
VDD_CORE6
D19
VDD_CORE7
T17
V17
SSTL2_VDD
C56
102
VDD_CORE9
VDD_25V1
VDD_25V2
VDD_25V3
VDD_25V4
VDD_25V5
C16
D17
J16
K16
L16
E5_V5BIAS
E5_AVDD
E5_VDDX
C22
C23
+
104
T47u/16
VDD_CORE1
L5M5T9
E5_VCORE
C20
104
C54
103
M16
104
C13
VDD_25V6
5V_BIAS0
D15
GND
+
C24
10UF/1206
BIAS
PLL PLL
AVDD1
AVDD2
AVDD0
AVDD3
VDDX
AGND1
C4E4D3D2E2C3D4E3D1
AGND2
AGND0
AGND3
GNDX
VSS_PC2_CTR1
VSS_PC2_CTR2
VSS_PC2_CTR3
C15
C17H8H9
F2
3
SDRAM_DQ0
VSS_PC2_CTR4
VSS_PC2_CTR5
H10
C33
102
C46
102
C
Y15
SPI_CLK
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
VSS_PC2_CTR6
VSS_PC2_CTR7
VSS_PC2_CTR8
H11
H12
H13J8J9
C
E5_GPIOx25
E5_GPIOx24
W17
W18
W16
V16
Y16
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
CS10-
CS11-GPIOx[25]
GPIOx[24]
DIGITAL
VSS_PC2_CTR9
VSS_PC2_CTR10
VSS_PC2_CTR11
VSS_PC2_CTR12
VSS_PC2_CTR13
VSS_PC2_CTR14
J10
J11
J12
J13K8K9
C35
C34
102
102
C47
C48
102
102
E5_GPIOx42
E5_GPIOx41
U17
U15
W19
UART1_CTS
UART1_RTS
GPIOx[42]
GPIOx[41]
SIO
VSS_PC2_CTR15
VSS_PC2_CTR16
VSS_PC2_CTR17
K10
K11
D
R235
10K
OPEN FOR DW9916
DI 9
DO 9
CL 9
R236
10K
R237 22
R238 22
R239 22
R240 22
/DTACK
R20 22
MCONFIG
R27 22
R28 22
E5_GPIO0
E5_GPIO1
E5_GPIO2
E5_GPIO3
E5_GPIO4
E5_GPIO5
R31 22
R32 22
/WAIT
/E5_CS2
Y8
W15
G2
Y11
Y9
V14
V6
V12
W9
V8
W8
U10
Y7
U8
U9
W3
Y2
Y6
Y4
Y5
Y3
V4
V5
W4
U5
W5
U6
W7
W6
U7
V7
V10
W11
Y10
V9
V11
Y12
W10
W12
Y13
U11
V13
W13
Y14
U12
U13
W14
V3
T4
V1
U2
U4
W2
U1
R4
R1
P3
P1
N2
M2
M3
M4
N3
N4
P2
P4
R3
T1
Y1
T2
W1
T3
V2
U3
R2
CE 9
CN8
5P1.0
DI
1
DO
2
CL
3
CE
4
5
GND
E5_ALE 5,6
/SYS_RST 5,6
GND
/E5_OE 5,6
/E5_UDS 5
E5_GPIO0 12
E5_GPIO1 7
E5_GPIO2 5
E5_GPIO3 11
E5_GPIO4 12
E5_GPIO5 12
/E5_WEL 5,6
/WAIT 5
E5_/DTACK 5
/E5_CS1 5
/E5_CS0 6
E5_MA22 6
E5_MA5 5,6
E5_MA4 5,6
E5_MA3 5,6
E5_MA2 5,6
E5_MA1 5,6
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
HD7
HD6
HD5
HD4
HD3
HD2
HD1
HD0
AtapiAddr0 6
AtapiAddr1 6
AtapiAddr2 6
AtapiAddr3 6
AtapiAddr4 6
ATAPI_DATA15 6
ATAPI_DATA14 6
ATAPI_DATA13 6
ATAPI_DATA12 6
ATAPI_DATA11 6
ATAPI_DATA10 6
ATAPI_DATA9 6
ATAPI_DATA8 6
ATAPI_DATA7 6
ATAPI_DATA6 6
ATAPI_DATA5 6
ATAPI_DATA4 6
ATAPI_DATA3 6
ATAPI_DATA2 6
ATAPI_DATA1 6
ATAPI_DATA0 6
ATAPI_RESET 6
ATAPI_DMAACK_L 6
ATAPI_DMARQ 6
ATAPI_IORDY 6
ATAPI_INTRQ 6
ATAPI_DIOR_L 6
ATAPI_DIOW_L 6
(FP D_HOST)
(/RST_PHY)
(/ETHER_IRQ)
(RST_CS4360)
(AUDIO_SEL0)
(AUDIO_SEL1)
HD[15..0]5,6
/DTACK
MCONFIG
/E5_CS0
/E5_CS1
/E5_CS2
E5_GPIO0
E5_GPIO1
E5_GPIO2
E5_GPIO3
E5_GPIO4
E5_GPIO5
/WAIT
E5_UART2_TX
E5_UART2_RX
1.8V
V18
2.5V
V25
3.3V
V33
5V
VCC
VCC
R234
R233
10K
10K
E5_GPIOx25 12
E5_GPIOx24 12
E5_GPIOx41 12
E5_GPIOx42 12
U16
V18
Y19
UART2_TX
UART1_TX
UART2_RX
UART1_RX
GPIOx[38]
GPIOx[37]
(RDY_FM)
(ATN_FM)
(FP SCLK)
(FP D_FM)
IRTX1
1
V15
Y18
Y17
U14
IRRX
IRTX1
IDC_CLK
IDC_DAT
CS7-
CS6-
GPIOx[39]
GPIOx[40]
IDCUART1 UART2SPI IR
GPIOx[23]
GPIOx[22]
GPIOx[21]
GPIOx[20]
GPIOx[19]
GPIOx[18]
GPIOx[17]
GPIOx[16]
CD_C2PO
CD_BCK
CD_LRCK
ATAPI I/F
CD_DATA
SD/CD SBP
SPI_MOSI
SPI_MISO
SPI_SCK
SPI_CS2
E5_UART2_TX 5
E5_UART2_RX 5
SDA 6,7,9,11,12
SCL 6,7,9,11,12
E5_VDDX
R6
D1
*10K
*1N6263
1 2
R10 *0
RSTÂMCONFIG
CS-
RD-
LDS-
DMAREQ
UDSÂHINTÂA0
A1
A2
PCMCIA_IOW-
PCMCIA_IORÂRD
WRÂWAITÂDTACKÂD31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
HOST I/F
D17
D16
D15
MA[21]
D14
MA[20]
D13
MA[19]
D12
MA[18]
D11
MA[17]
D10
MA[16]
D9
MA[15]
D8
MA[14]
D7
MA[13]
D6
MA[12]
D5
MA[11]
D4
MA[10]
D3
MA[9]
D2
MA[8]
D1
MA[7]
D0
MA[6]
SBP_FRAME
SBP_ACK
SBP_RD
SBP_REQ
SBP_CLK
SBP_D[7]
SBP_D[6]
SBP_D[5]
SBP_D[4]
SBP_D[3]
SBP_D[2]
SBP_D[1]
SBP_D[0]
SD_D[7]
SD_D[6]
SD_D[5]
SD_D[4]
SD_D[3]
SD_D[2]
SD_D[1]
SD_D[0]
SD_SECSTART
SD_ERROR
SD_CLK
SD_ACK
SD_RDREQ
SD_WRREQ
MASTERSLAVE
MCONFIG
CS0_8BIT
AtapiAddr0
AtapiAddr1
AtapiAddr2
AtapiAddr3
AtapiAddr4
ATAPI_DATA15
ATAPI_DATA14
ATAPI_DATA13
ATAPI_DATA12
ATAPI_DATA11
ATAPI_DATA10
ATAPI_DATA9
ATAPI_DATA8
ATAPI_DATA7
ATAPI_DATA6
ATAPI_DATA5
ATAPI_DATA4
ATAPI_DATA3
ATAPI_DATA2
ATAPI_DATA1
ATAPI_DATA0
ATAPI_RESET_L
ATAPI_DMAACK_L
ATAPI_DMARQ
ATAPI_IORDY
ATAPI_INTRQ
ATAPI_DIOR_L
ATAPI_DIOW_L
RST-
UWEÂGPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
LWE-
WAIT-
DTACK-
CS5ÂCS4ÂCS3ÂCS2ÂCS1-
CS0ÂMA[26]
MS[25]
MA[24]
MA[23]
MA[22]
MA[5]
MA[4]
MA[3]
MA[2]
MA[1]
ALE
OE-
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IR_FMUTE 11,12
CONTROL
VREF
ADDRDATA
ATAPI2 I/F
VDD_REF
R_REF
VSS_REF
VSS_PC2_CTR37
VSS_PC2_CTR18
VSS_PC2_CTR19
VSS_PC2_CTR20
VSS_PC2_CTR21
VSS_PC2_CTR22
VSS_PC2_CTR23
VSS_PC2_CTR24
VSS_PC2_CTR25
VSS_PC2_CTR26
VSS_PC2_CTR27
VSS_PC2_CTR28
VSS_PC2_CTR29
K12
K13L8L9
L10
VSS_PC2_CTR30
L11
L12
L13M8M9
M10
M11
M12
GNDGND
VSS_PC2_CTR31
VSS_PC2_CTR32
M13N8N9
VSS_PC2_CTR38
VSS_PC2_CTR33
VSS_PC2_CTR34
VSS_PC2_CTR35
VSS_PC2_CTR36
N12
N13
N10
N11
C2C1B1
E5_VDDREF
R43
1.18K 1%
GND
R5 10K
R7 10K
R8 10K
R9 10K
R12 10K
R13 10K
R14 10K
R15 10K
R16 *10K
R18 10K
R22 10K
R25 10K
E5_VCORE
C5
104
GND
+
T47u/16
E
V33
TX1
1
RX1
1
V18_E5_DAC_DVDD
FB1
C3
104
GND
L1 601
L2 601
L3 601
L4 601
601
SSTL2_VDD
V33_E5_USB
E5_VDDX
E5_AVDD
E5_VDDREF
V33_E5_DAC_AVDD
E5_VPAD
E5_V5BIAS
CA1
+
T47u/16
C4
General decoupling cap placement:
Caps with smaller capacitance values to be
closer to respective power pins compared to
those of larger values. All should be as
close as possible.
C28
C29
C26
C25
+
C37
C36
103
103
C49
103
10UF/1206
C38
+
C50
104
10UF/1206
+
10UF/1206
C39
+
10UF/1206
C27
104
104
C40
C41
104
104
C30
104
104
C42
C43
104
104
E5_VPAD
C31
C32
104
104
GND
E5_VCORE
C44
C45
104
104
GND
D
BBK AV ELECTRONICS CORP.,LTD.
Title
E5.1
Size Document Number Rev
Date: Sheet of
HDW-10-310000-1 A1
2
12Thursday, September 15, 2005
E
A
B
C
D
E
TERMINATION
AT E5.1
C79
103
C92
103
SSTL2_VDD
C57
104
C61
104
SSTL2_VDD
C64
104
C70
104
SSTL2_VDD
C80
104
C93
104
VREF
4 4
E5_SDRAM_DQ0
E5_SDRAM_DQ1
E5_SDRAM_DQ2
E5_SDRAM_DQ3
E5_SDRAM_DQ4
E5_SDRAM_DQ5
E5_SDRAM_DQ6
E5_SDRAM_DQ7
E5_SDRAM_DQ8
E5_SDRAM_DQ9
E5_SDRAM_DQ10
E5_SDRAM_DQ11
E5_SDRAM_DQ12
E5_SDRAM_DQ13
E5_SDRAM_DQ14
E5_SDRAM_DQ15
E5_SDRAM_DQ16
E5_SDRAM_DQ17
E5_SDRAM_DQ18
E5_SDRAM_DQ19
E5_SDRAM_DQ20
E5_SDRAM_DQ21
E5_SDRAM_DQ22
3 3
2 2
E5_SDRAM_DQ23
E5_SDRAM_DQ24
E5_SDRAM_DQ25
E5_SDRAM_DQ26
E5_SDRAM_DQ27
E5_SDRAM_DQ31
E5_SDRAM_DQ28
E5_SDRAM_DQ30
E5_SDRAM_DQ29
E5_SDRAM_DQM0 2
E5_SDRAM_DQM1 2
E5_SDRAM_DQM2 2
E5_SDRAM_DQM3 2
E5_SDRAM_A1 2
E5_SDRAM_A6 2
E5_SDRAM_A3 2
E5_SDRAM_A15 2
E5_SDRAM_A8 2
E5_SDRAM_A0 2
E5_SDRAM_A4 2
E5_SDRAM_A2 2
E5_SDRAM_A7 2
E5_SDRAM_A14 2
E5_SDRAM_A9 2
E5_SDRAM_A12 2
E5_SDRAM_A11 2
E5_SDRAM_A10 2
E5_SDRAM_A5 2
E5_SDRAM_DQS0 2
E5_SDRAM_DQS1 2
E5_SDRAM_DQS2 2
E5_SDRAM_DQS3 2
E5_SDRAM_CLK0 2
E5_SDRAM_CLK1 2
E5_SDRAM_CLK#0 2
E5_SDRAM_CLK#1 2
E5_SDRAM_RAS# 2
E5_SDRAM_CLKE 2
E5_SDRAM_CAS# 2
E5_SDRAM_WE# 2
E5_SDRAM_CS0 2
RP1 51/RP
RP3 51/RP
1 8
2 7
3 6
4 5
RP5 51/RP
RP7 51/RP
RP9 51/RP
RP11 51/RP
1 8
2 7
3 6
4 5
RP12 51/RP
RP14 51/RP
1 8
2 7
3 6
4 5
RP16 22/RP
1 8
2 7
3 6
4 5
RP18 22/RP
RP20 22/RP
1 8
2 7
3 6
4 5
RP22 22/RP
RP24 22/RP
1 8
2 7
3 6
4 5
R44 51
R45 51
R47 51
R49 51
R52 22
R53 22
R55 22
R57 22
RP26 22/RP
1 8
2 7
3 6
4 5
R65 22
SDRAM_DQ0
18
SDRAM_DQ1 SDRAM_DQ0
27
SDRAM_DQ2
36
SDRAM_DQ3
45
SDRAM_DQ4
SDRAM_DQ5
SDRAM_DQ6
SDRAM_DQ7
SDRAM_DQ8
18
SDRAM_DQ9
27
SDRAM_DQ10
36
SDRAM_DQ11
45
SDRAM_DQ12
18
SDRAM_DQ13
27
SDRAM_DQ14
36
SDRAM_DQ15
45
SDRAM_DQ16
18
SDRAM_DQ17
27
SDRAM_DQ18
36
SDRAM_DQ19
45
SDRAM_DQ20
SDRAM_DQ21
SDRAM_DQ22
SDRAM_DQ23
SDRAM_DQ24
45
SDRAM_DQ25
36
SDRAM_DQ26
27
SDRAM_DQ27
18
SDRAM_DQ31
SDRAM_DQ28
SDRAM_DQ30
SDRAM_DQ29
SDRAM_DQM0
SDRAM_DQM1
SDRAM_DQM2
SDRAM_DQM3
SDRAM_A1
18
SDRAM_A6
27
SDRAM_A3
36
SDRAM_A15
45
SDRAM_A8
SDRAM_A0
SDRAM_A4
SDRAM_A2
SDRAM_A7
18
SDRAM_A14
27
SDRAM_A9
36
SDRAM_A12
45
SDRAM_A11
SDRAM_A10
SDRAM_A5
SDRAM_DQS0
SDRAM_DQS1
SDRAM_DQS2
SDRAM_DQS3
SDRAM_CLK0
SDRAM_CLK1
SDRAM_CLK#0
SDRAM_CLK#1
SDRAM_RAS#
SDRAM_CLKE
SDRAM_CAS#
SDRAM_WE#
SDRAM_CS0
SDRAM_DQ[31..0]4E5_SDRAM_DQ[31..0] 2
C78
C77
C76
103
104
104
C91
C90
C89
103
104
104
DDR TERMINATION VOLTAGE REGULATOR
VREF needs to be decoupled
to both SSTL2_VDD and SSTL2_GND with balanced
decoupling capacitors.
VREF should be routed over a
reference plane and isolated, and possibly
shielded with both SSTL2_VDD and SSTL2_GND
VREF2,4
The VTT side of the terminaton resistors should be placed
on a wide VTT island on the surface layer. The island is
located at each end of the bus, so it does not interfere
with the signal routing.
C59
103
C63
103
C66
103
C72
103
C60
103
C67
103
C73
103
C84
C83
102
102
C97
C96
102
102
1
2
3
4 5
C68
C69
104
104
C74
C75
104
104
C85
104
C98
104
U2
NC
GND
VSENSE
VREF VDDQ
LP2995
GND_SSTL2
PVIN
AVIN
C81
104
C94
104
C58
104
C62
104
C65
104
C71
104
C82
102
C95
102
C107
104
VTT
GND_SSTL2
VTT
VREF
GND_SSTL2
VTT
GND_SSTL2
VTT
VTT
8
7
6
+
CA4
220u/16
VREF 2,4
VTT
+
SSTL2_VDD
TERMINATION
AT DDR
SDRAM_DQ[31..0]4
SSTL2_VDD
CA3
220u/16
C106
104
C86
104
C99
104
GND_SSTL2
+
C87
102
C100
102
C102
10u/16
C88
102
C101
102
C104
104
+
T47u/16
C103
VREF
VREF 2,4
C105
104
SDRAM_DQ1
SDRAM_DQ2
SDRAM_DQ3
SDRAM_DQ4
SDRAM_DQ5
SDRAM_DQ6
SDRAM_DQ7
SDRAM_DQ8
SDRAM_DQ9
SDRAM_DQ10
SDRAM_DQ11
SDRAM_DQ12
SDRAM_DQ13
SDRAM_DQ14
SDRAM_DQ15
SDRAM_DQ16
SDRAM_DQ17
SDRAM_DQ18
SDRAM_DQ19
SDRAM_DQ20
SDRAM_DQ21
SDRAM_DQ22
SDRAM_DQ23
SDRAM_DQ24
SDRAM_DQ25
SDRAM_DQ26
SDRAM_DQ27
SDRAM_DQ28
SDRAM_DQ29
SDRAM_DQ30
SDRAM_DQ31
SDRAM_A0 4
SDRAM_A1 4
SDRAM_A2 4
SDRAM_A3 4
SDRAM_A7 4
SDRAM_A6 4
SDRAM_A5 4
SDRAM_A4 4
SDRAM_A12 4
SDRAM_A11 4
SDRAM_A9 4
SDRAM_A8 4
SDRAM_RAS# 4
SDRAM_A14 4
SDRAM_A15 4
SDRAM_A10 4
SDRAM_DQS0 4
SDRAM_DQS1 4
SDRAM_DQS2 4
SDRAM_DQS3 4
SDRAM_DQM0 4
SDRAM_DQM1 4
SDRAM_DQM2 4
SDRAM_DQM3 4
SDRAM_CLK#0 4
SDRAM_CLK#1 4
SDRAM_CLK0 4
SDRAM_CLK1 4
SDRAM_CLKE 4
SDRAM_WE# 4
SDRAM_CAS# 4
SDRAM_CS0 4
RP2 51/RP
RP4 51/RP
RP6 51/RP
4 5
3 6
2 7
1 8
RP8 51/RP
4 5
3 6
2 7
1 8
RP10 51/RP
RP13 51/RP
RP15 51/RP
RP17 51/RP
RP19 51/RP
RP21 51/RP
1 8
2 7
3 6
4 5
RP23 51/RP
1 8
2 7
3 6
4 5
RP25 51/RP
R46 51
R48 51
R50 51
R51 51
R54 51
R56 51
R58 51
R59 51
R60 51
R61 51
R62 51
R63 51
R64 51
R66 51
R67 51
R68 51
VTT
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
18
27
36
45
1 1
BBK AV ELECTRONICS CORP.,LTD.
Title
TERM AT E5
Size Document Number Rev
C
A
B
C
D
Date: Sheet
E
312Thursday, September 15, 2005
of
D0
A
B
C
D
E
C119
104
LAYOUT
NOTE:
PLACEMENT
E5
C110
104
C120
102
C111
102
C121
102
SDRAM_CS0
SDRAM_CLK1
SDRAM_CLK0
C112
102
C122
102
M2
U25
M1
U22
C113
102
C123
102
C114
+
10UF/1206
SDRAM_DQ[31..0]3
SDRAM_A03
SDRAM_A13
SDRAM_A23
SDRAM_A33
4 4
SDRAM_A43
SDRAM_A53
SDRAM_A63
SDRAM_A73
SDRAM_A83
SDRAM_A93
SDRAM_A103
SDRAM_A113
SDRAM_A123
SDRAM_A143
SDRAM_A153
SDRAM_CS03
SDRAM_CLKE3
SDRAM_RAS#3
SDRAM_CAS#3
SDRAM_WE#3
SDRAM_DQM03
SDRAM_DQM13
SDRAM_DQS03
SDRAM_DQS13
SDRAM_CLK03
SDRAM_CLK#03
VREF2,3
SDRAM_A0
SDRAM_A1
SDRAM_A2
SDRAM_A3
SDRAM_A4
SDRAM_A5
SDRAM_A6
SDRAM_A7
SDRAM_A8
SDRAM_A9
SDRAM_A10
SDRAM_A11
SDRAM_A12
SDRAM_A14
SDRAM_A15
DDR_VDD
3 3
29
30
31
32
35
36
37
38
39
40
28
41
42
26
27
24
44
23
22
21
20
47
16
51
45
46
49
18
33
15
55
61
U3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
BA0
BA1
CS#
CKE
RAS#
CAS#
WE#
LDM
UDM
LDQS
UDQS
CLK
CLK#
VREF
1
VCC
VCC
VCC
3
VCCQ
9
VCCQ
VCCQ
VCCQ
VCCQ
8MX16 DDR
+
C124 10UF/1206
D10
D11
D12
D13
D14
D15
NC
NC
NC
NC
NC
NC
NC
GND
GND
GND
GNDQ
GNDQ
GNDQ
GNDQ
GNDQ
2
D0
4
D1
5
D2
7
D3
8
D4
10
D5
11
D6
13
D7
54
D8
56
D9
57
59
60
62
63
65
14
17
19
25
43
50
53
34
48
66
6
12
52
58
64
GND
SDRAM_DQ0
SDRAM_DQ1
SDRAM_DQ2
SDRAM_DQ3
SDRAM_DQ4
SDRAM_DQ5
SDRAM_DQ6
SDRAM_DQ7
SDRAM_DQ8
SDRAM_DQ9
SDRAM_DQ10
SDRAM_DQ11
SDRAM_DQ12
SDRAM_DQ13
SDRAM_DQ14
SDRAM_DQ15
SSTL2_VDD
FB2
B601
V33
Option for DDR with 3.3V VDD
FB3
*B601
CA5
+
T47u/16
SSTL2_VDD
C115
104
C116
104
DDR_VDD
C108
104
GND
C117
104
C109
104
C118
104
GND
SDRAM_A03
SDRAM_A13
SDRAM_A23
SDRAM_A33
SDRAM_A43
SDRAM_A53
SDRAM_A63
SDRAM_A73
SDRAM_A83
SDRAM_A93
SDRAM_A103
SDRAM_A113
SDRAM_A123
2 2
SDRAM_DQM23
SDRAM_DQM33
SDRAM_DQS23
SDRAM_DQS33
SDRAM_CLK13
SDRAM_CLK#13
SDRAM_A143
SDRAM_A153
SDRAM_CS03
SDRAM_A0
SDRAM_A1
SDRAM_A2
SDRAM_A3
SDRAM_A4
SDRAM_A5
SDRAM_A6
SDRAM_A7
SDRAM_A8
SDRAM_A9
SDRAM_A10
SDRAM_A11
SDRAM_A12
SDRAM_A14
SDRAM_A15
DDR_VDD
SSTL2_VDD
29
30
31
32
35
36
37
38
39
40
28
41
42
26
27
24
44
23
22
21
20
47
16
51
45
46
49
18
33
15
55
61
U4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
BA0
BA1
CS#
CKE
RAS#
CAS#
WE#
LDM
UDM
LDQS
UDQS
CLK
CLK#
VREF
1
VCC
VCC
VCC
3
VCCQ
9
VCCQ
VCCQ
VCCQ
VCCQ
8MX16 DDR
+
C141 10UF/1206
D10
D11
D12
D13
D14
D15
NC
NC
NC
NC
NC
NC
NC
GND
GND
GND
GNDQ
GNDQ
GNDQ
GNDQ
GNDQ
GND
SDRAM_DQ16
SDRAM_DQ17
SDRAM_DQ18
SDRAM_DQ19
SDRAM_DQ20
SDRAM_DQ21
SDRAM_DQ22
SDRAM_DQ23
SDRAM_DQ24
SDRAM_DQ25
SDRAM_DQ26
SDRAM_DQ27
SDRAM_DQ28
SDRAM_DQ29
SDRAM_DQ30
SDRAM_DQ31
2
D0
4
D1
5
D2
7
D3
8
D4
10
D5
11
D6
13
D7
54
D8
56
D9
57
59
60
62
63
65
14
17
19
25
43
50
53
34
48
66
6
12
52
58
64
DDR_VDD
C125
104
GND
SSTL2_VDD
C132
104
GND
C126
104
C133
104
C127
104
C134
104
C128
102
C135
104
C129
102
C136
104
C130
102
C137
102
+
C131
T47u/16
C138
102
C139
102
C140
102
GND_SSTL2
GND
1 1
BBK AV ELECTRONICS CORP.,LTD.
Title
2 (8M x 16) DDR SDRAM
Size Document Number Rev
Custom
A
B
C
D
Date: Sheet
E
of
412Thursday, September 15, 2005
A1
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