BBK DV985S Service Manual
SERVICE MANUAL
DV985S
CONTENTS
SAFETY PRECAUTIONS
PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY
SENSITIVE(ES)DEVICES
CONTROL BUTTON LOCATIONS AND EXPLANATIONS
PREVERTION OF STATIC ELECTRICITY DISCHARGE
ASSEMBLING AND DISASSEMBLING THE MECHANISM UNIT
OPTICAL PICKUP UNIT EXPLOSED VIEW AND PART LIST
BRACKET EXPLOSED VIEW AND PART LIST
MISCELLANEOUS
ELECTRICAL CONFIRMATION
VI DEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION
VI DEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION
1
1
2
3
4
4
6
7
8
8
9
MPEG BOARD CHECK WAVEFORM
FLI2300 DIGITAL VIDEO CONVERTER DATE SHEET
AM29LV160D
HY57V641620HG
SiI 164 PANELLINK TRANSMITTER
MT1389
SCHEMATIC & PCB WIRING DIAGRAM
SPARE PARTS LIST
10
11
19
24
27
41
44
60
1.1 GENERAL GUIDELINES
1. SAFETY PREAUTIONS
2.PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO
ELECTROSTATICALLY SENSITIVE(ES)DEVICES
1
1. When servicing, observe the original lead dress. if a short circuit is found, replace all parts which have
been overheated or damaged by the short circuit.
2. After servicing, see to it that all the protective devices such as insulation barrier, insulation papers
shields are properly installed.
3. After servicing, make the following leakage current checks to prevent the customer from being exposed
to shock hazards.
Some semiconductor(solid state)devices can be damaged easily by static electricity. Such components
commonly are called Electrostatically Sensitive(ES)Devices. Examples of typical ES devices are integrated
circuits and some field-effect transistors and semiconductor chip components. The following techniques
should be used to help reduce the incidence of component damage caused by electro static discharge(ESD).
1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain
off any ESD on your body by touching a known earth ground. Alternatively, obtain and wear a commercially
availabel discharging ESD wrist strap, which should be removed for potential shock reasons prior to
applying power to the unit under test.
2. After removing an electrical assembly equipped with ES devices,place the assembly on a conductive
surface such as alminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.
4. Use only an anti-static solder removal device. Some solder removal devices not classified as anti-static
(ESD protected)can generate electrical charge sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ES
devices.
6. Do not remove a replacement ES device from its protective package until immediately before you are
ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by
conductive foam, alminum foil or comparable conductive material).
7. Immediately before removing the protective material from the leads of a replacement ES device, touch
the protective material to the chassis or circuit assembly into which the device will be installed.
Caution
Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can
generate static electricity(ESD).
notice (1885x323x2 tiff)
Front Panel Illustration
2
POWER switch
Disc tray
2
2
4
IR SENSOR
5
Display window
3
4
5
7
STOP button
6
7
3
OPEN/CLOSE button
6
PLAY/PAUSE button
The laser diode in the traverse unit (optical pickup)may brake down due to static electricity of clothes or human
body. Use due caution to electrostatic breakdown when servicing and handling the laser diode.
Some devices such as the DVD player use the optical pickup(laser diode)and the optical pickup will be damaged
by static electricity in the working environment.Proceed servicing works under the working environment where
1. Put a conductive material(sheet)or iron sheet on the area where the optical pickup is placed,and ground the
3. The flexible cable may be cut off if an excessive force is applied to it.Use caution when handling the cable.
3
4.PREVENTION OF STATIC ELECTRICITY DISCHARGE
4.1.Grounding for electrostatic breakdown prevention
grounding works is completed.
4.1.1. Worktable grounding
sheet.
4.1.2.Human body grounding
1 Use the anti-static wrist strap to discharge the static electricity from your body.
safety_3 (1577x409x2 tiff)
4.1.3.Handling of optical pickup
1. To keep the good quality of the optical pickup maintenance parts during transportation and before
installation, the both ends of the laser diode are short-circuited.After replacing the parts with new ones,
remove the short circuit according to the correct procedure. (See this Technical Guide).
2. Do not use a tester to check the laser diode for the optical pickup .Failure to do so willdamage the laser
diode due to the power supply in the tester.
4.2. Handling precautions for Traverse Unit (Optical Pickup)
1. Do not give a considerable shock to the traverse unit(optical pickup)as it has an extremely high-precise
structure.
2. When replacing the optical pickup, install the flexible cable and cut is short land with a nipper. See the
optical pickup replacement procedure in this Technical Guide. Before replacing the traverse unit, remove
the short pin for preventingstatic electricity and install a new unit.Connect the connector as short times as
possible.
4. The half-fixed resistor for laser power adjustment cannot be adjusted. Do not turn the resistor.
5.1 Optical pickup Unit Explosed View and Part List
5. Assembling and disassembling the mechanism unit
4
Pic (1)
Materials to Pic (1)
5
No. PARTS CODE PARTS NAME Q ty
14692200 SF-HD60 1
1
1EA0311A06300 ASSY, CHASSIS, COMPLETE 1
2
Or
3
4
5
6
7
8
9
10
11
21
Or
31
32
1EA0M10A15500 ASSY, MOTOR, SLED 1
1EA0M10A15501 ASSY, MOTOR, SLED 1
1EA2451A24700 HOLDER, SHAFT 3
1EA2511A29100 GEAR, RACK 1
1EA2511A29200 GEAR, DRIVE 1
1EA2511A29300 GEAR, MIDDLE, A 1
1EA2511A29400 GEAR, MIDDLE, B 1
1EA2744A03000 SHAFT, SLIDE 1
1EA2744A03100 SHAFT, SLIDE, SUB 1
1EA2812A15300 SPRING, COMP, TYOUSEI 3
1EA2812A15400 SPRING, COMP, RACK 1
1EA0B10B20100 ASSY, PWB 1
1EA0B10B20200 ASSY, PWB 1
SEXEA25700--- SPECIAL SCREW BIN+-M2X11 3
SEXEA25900--- SPECIAL SCREW M1.7X2.2 2
33
34
35
Note : This parts list is not for service parts supply.
SFBPN204R0SE- SCR S-TPG PAN 2X4 2
SFSFN266R0SE- SCR S-TPG FLT 2.6X6 1
SWXEA15400--- SPECIAL WASHER 1.8X4 X0.25 2
5.2 Bracket Explosed View and Part List
6
Pic (2)
Materials to Pic(2)
1.bracket 14. front silicon rubber
2.belt 15. Back silicon rubber
3.screw 16. Pick-up
4.belt wheel 17. Pick-up
5.gearwheel 18. switch
6.iron chip 19. Five-pin flat plug
7. Immobility mechanism equipment 20. screw
8. Magnet 21. PCB
9. Platen 22. motor
10. Bridge bracket 23. Motor wheel
11. screw 24. screw
12. screw 25.tray
13. Big bracket
Before going process with disassembly and installation, please carefully both
peruse the chart and confirm the materials.
5.3 MISCELLANEOUS
7
5.3.1 Protection of the LD(Laser diode)
Short the parts of LD circuit pattern by soldering.
5.3.2 Cautions on assembly and adjustment
Make sure that the workbenches,jigs,tips,tips of soldering irons and measuring instruments are
grounded,and that personnel wear wrist straps for ground.
Open the LD short lands quickly with a soldering iron after a circuit is connected.
Keep the power source of the pick-up protected from internal and external sources of electrical
noise.
Refrain from operation and storage in atmospheres containing corrosive gases (such as H2S,SO2,
NO2 and Cl2)or toxic gases or in locations containing substances(especially from the organic silicon,cyan,
formalin and phenol groups)which emit toxic gases.It is particularly important to ensure that none of the
above substances are present inside the unit.Otherwise,the motor may no longer run.
6.1. Video Output (Luminance Signal) Confirmation
6.Electrical Confirmation
8
DO this confirmation after replacing a P.C.B.
Measurement point
Video output terminal
Measuring equipment,tools
200mV/dir,10 sec/dir
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohms.
2.Confirm that luminance signal(Y+S)level is 1000mVp-p±30mV
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
Mode Disc
Color bar 75%
Confirmation value
1000mVp-p±30mV
DVDT-S15
or
DVDT-S01
Do the confirmation after replacing P.C.B.
Screwdriver,Oscilloscope
6.2 Video Output(Chrominance Signal) Confirmation
9
Measurement point
Video output terminal
Measuring equipment,tools Confirmation value
200mV/dir,10 sec/dir
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohme.
2.Confirm that the chrominance signal(C)level is 621 mVp-p±30mV
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
Mode Disc
Color bar 75%
621mVp-p±30mV
DVDT-S15
or
DVDT-S01
7.MPEG BOARD CHECK WAVEFORM
7.1 27MHz WAVEFORM
7.2 IC5L0380R PIN.2 WAVEFORM DIAGRAM
10
FLI2300 Digital Video Converter Data Sheet
11
1 DESCRIPTION
The FLI2300 is a highly integrated digital video
format converter for CRT-TV applications using
patented deinterlacing and post processing algorithms
from Faroudja Laboratories, coupled with highly
flexible scaling, a wide variety of aspect ratio
conversions, and other special video enhancing
features to produce the highest quality image.
1.1 Inputs
• Input all industry standard and non-standard
video resolutions, including 480i (NTSC), 576i
(PAL/SECAM), 480p, 720p, 1080i, and VGA to
XGA
• Digital input, 8-bit Y/Cr/Cb (ITU-R BT656), 8-
bit Y/Pr/Pb, 16-bit Y Cr/Cb (ITU-R BT601), 24bit RGB, YCrCb, YPrPb
• Input pixel rate up to 75MHz maximum
1.2 Outputs
• Output resolutions include 480p, 576p, 720p,
1080i, 1080p, and VGA to SXGA
• Interlaced or Progressive output
• The output can be either analog YUV/RGB
through the integrated 10-bit Digital-To-Analog
Converter (DAC), or digital 24-bit RGB, YCrCb,
YPrPb (4:4:4), or digital 16/20-bit Y Cr/Cb
(4:2:2) Output pixel rate up to 150 MHz
maximum
1.3 Formats
• Input color manipulation matrix supports all
color spaces: RGB, YPrPb, 4:4:4 YCrCb, 4:2:2
YCr/Cb, ITU-R BT656, ITU-R BT601
• Output supports analog RGB, YPrPb, and
YCrCb;
• Output supports digital RGB, YPrPb, 4:4:4
YCrCb and 4:2:2 YCr/Cb
1.4 Frame Rate Conversion
• Tearless Frame Rate Conversion
50/60/72/75/100/120 Hz
1.5 Front End Processing
• Motion Adaptive Noise Reduction - Improves
picture quality for off-air material.
• Cross Color Suppressor (CCS) - Removes cross
color artifacts in composite video signals due to
poor Y/C separation in standard 2-D video
decoders, eliminating the need for expensive 3-D
video decoders.
1.6 Deinterlacing
• Per-pixel Motion Adaptive Deinterlacing
• Patented FilmMode Processing - Used for proper
de-interlacing of 3:2 and 2:2 pulldown material.
• Edit Correction - Film content is continuously
monitored for any break in sequence caused by
“bad edits” and quickly compensates for the
most effective reduction in artifacts.
• DCDi™ by Faroudja - Video is analyzed on a
single pixel granularity to detect presence or
absence of angled lines and edges, which are
then processed to produce a smooth and natural
looking image without visible artifacts or
“jaggies”.
1.7 Scaling
• High Quality Fully Programmable Two
Dimensional Scaler
• Aspect Ratio Conversion for “Anamorphic” or
“Panoramic” (non-linear)
• Display 4:3 images on 16:9 displays and vice
versa, including Letterbox to Fullscreen,
Pillarbox, and Subtitle Display Modes
• Pixel and line dropper to generate PIP windows
1.8 TrueLife™ Enhancer
• Two dimensional, non-linear, luma and chroma
video enhancer brings out details in the picture,
producing a more life-like image.
1.9 Memory
• 32-bit wide SDRAM (i.e. one 2M x 32-bit)
controller, up to 166 MHz operation, for external
SDRAM
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
t
12
2 BLOCK DIAGRAMS
Port 2
8-bit
656 Input
Port 1
8/16/24-bit
RGB/YCrCb
Input
Input Processor
with Auto Sync
and auto Adjust
Generation
Clock
PLLs
FLI2300 Digital Video Converter Data Sheet
Figure 2.1: FLI2300– Simplified Internal Block Diagram
Noise Reducer,
Deinterlacer, Frame
Rate Converter and
SDRAM interface
Vertical and
Horizontal
Scalers
2Mx32
SDRAM
(external)
Vertical and
Horizontal
Enhancers
Output
Processor with
Sync Generation
and DACs
16/20/24-bi
RBG/YCrCb
Digital Outputs
RBG/YCrCb
Analog Outputs
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
13
3 PIN INFORMATION
3.1 Pin Diagram
FIELD ID_PORT2
HSYNC_PORT2
VSYNC_PORT2
D1_IN_7
D1_IN_6
D1_IN_5
D1_IN_4
D1_IN_3
D1_IN_2
FLI2300 Digital Video Converter Data Sheet
Figure 3.1: Pinout Information
IN_CLK_PORT2
XTAL IN
XTAL OUT
VDD9
D1_IN_1
VDDcore8
VSScore
TEST2
VSS
D1_IN_0
TEST1
TEST0
DAC_PVDD
DAC_GR_AVDD
DAC_GR_AVSS
DAC_VREFIN
DAC_AVSS
DAC_AVDD
DAC_VREFOUT
DAC_COMP
DAC_RSET
DAC_AVDDR
DAC_AVSSR
DAC_R_OUT
DAC_G_OUT
DAC_AVDDG
DAC_AVSSG
DAC_AVSSB
DAC_B_OUT
DAC_AVDDB
DAC_VSS
DAC_PVSS
DAC_VDD
AVDD_PLL_FE
AVDD_PLL_SDI
AVSS_PLL_FE
AVSS_PLL_SDI
AVSS_PLL_BE2
AVDD_PLL_BE2
AVSS_PLL_BE1
AVDD_PLL_BE1
PLL_PVDD
PLL_PVSS
HSYNC1_PORT1
VSYNC1_PORT1
FIELD ID1_PORT1
IN_CLK1_PORT1
HSYNC2_PORT1
VSYNC2_PORT1
FIELD ID2_PORT1
VDD1
VSS
IN_CLK2_PORT1
B/Cb/D1_0
B/Cb/D1_1
B/Cb/D1_2
B/Cb/D1_3
B/Cb/D1_4
VDDcore1
VSScore
B/Cb/D1_5
B/Cb/D1_6
B/Cb/D1_7
R/Cr/Cb Cr_0
R/Cr/Cb Cr_1
R/Cr/Cb Cr_2
R/Cr/Cb Cr_3
R/Cr/Cb Cr_4
R/Cr/Cb Cr_5
R/Cr/Cb Cr_6
R/Cr/Cb Cr_7
G/Y/Y_0
VDD2
VSS
G/Y/Y_1
G/Y/Y_2
G/Y/Y_3
G/Y/Y_4
VDDcore2
VSScore
G/Y/Y_5
G/Y/Y_6
G/Y/Y_7
IN_SEL
TEST
DEV_ADDR1
DEV_ADDR0
SCLK
SDATA
RESET_N
VDD3
VSS
SDRAM DATA(0)
SDRAM DATA(1)
SDRAM DATA(2)
1 0 0
1 6 0
1 5 5
1 5 0
1 4 5
1 4 0
1 3 5
1 3 0
1 2 5
1 2 0
1 1 5
1 1 0
1 0 5
OE
G/Y/Y_OUT_7
G/Y/Y_OUT_6
G/Y/Y_OUT_5
G/Y/Y_OUT_4
G/Y/Y_OUT_3
G/Y/Y_OUT_2
G/Y/Y_OUT_1
G/Y/Y_OUT_0
VSS
VDD8
R/V/Pr_OUT_7
R/V/Pr_OUT_6
R/V/Pr_OUT_5
R/V/Pr_OUT_4
R/V/Pr_OUT_3
R/V/Pr_OUT_2
VSScore
VDDcore7
R/V/Pr_OUT_1
R/V/Pr_OUT_0
B/U/Pb_OUT_7
B/U/Pb_OUT_6
B/U/Pb_OUT_5
B/U/Pb_OUT_4
B/U/Pb_OUT_3
B/U/Pb_OUT_2
VSS
VDD7
B/U/Pb_OUT_1
B/U/Pb_OUT_0
CLKOUT
VSScore
VDDcore6
CTLOUT4
CTLOUT3
CTLOUT2
CTLOUT1
CTLOUT0
TEST OUT1
TEST OUT0
TEST3
SDRAM CLKIN
VSS
VDD6
SDRAM CLKOUT
SDRAM DQM
SDRAM CSN
SDRAM BA0
SDRAM BA1
SDRAM CASN
SDRAM RASN
1
2 0 5
2 0 0
1 9 5
1 9 0
1 8 5
1 8 0
1 7 5
1 7 0
1 6 5
5
1 0
1 5
2 0
2 5
3 0
3 5
4 0
4 5
5 0
5 5
6 0
6 5
7 0
7 5
8 0
8 5
9 0
9 5
SDRAM DATA(3)
SDRAM DATA(5)
SDRAM DATA(4)
SDRAM DATA(7)
SDRAM DATA(6)
Package: 208-pin PQFP
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
VSS
VDD4
SDRAM DATA(8)
SDRAM DATA(9)
SDRAM DATA(10)
SDRAM DATA(12)
SDRAM DATA(11)
VSScore
VDDcore3
SDRAM DATA(18)
SDRAM DATA(21)
SDRAM DATA(17)
SDRAM DATA(16)
SDRAM DATA(14)
SDRAM DATA(13)
SDRAM DATA(15)
SDRAM DATA(20)
SDRAM DATA(19)
SDRAM DATA(22)
VSScore
VDDcore4
SDRAM DATA(24)
SDRAM DATA(26)
SDRAM DATA(27)
SDRAM DATA(25)
SDRAM DATA(23)
*** Genesis Microchip Confidential ***
VSS
VDD5
TEST IN
SDRAM DATA(31)
SDRAM DATA(28)
SDRAM DATA(30)
SDRAM DATA(29)
SDRAM ADDR(9)
SDRAM ADDR(10)
VSScore
VDDcore5
SDRAM ADDR(6)
SDRAM ADDR(5)
SDRAM ADDR(7)
SDRAM ADDR(8)
SDRAM ADDR(4)
SDRAM WEN
SDRAM ADDR(3)
SDRAM ADDR(0)
SDRAM ADDR(1)
SDRAM ADDR(2)
FLI2300 Digital Video Converter Data Sheet
14
3.2 Pin details
Table 3.1: FLI2300 pin details
Internal
Pull up/
Pulldown
Pin
No
1
HSYNC1_PORT1 Input 5v
2
VSYNC1_PORT1 Input 5v
FIELD ID1_PORT1
3
IN_CLK1_PORT1
4
5
HSYNC2_PORT1 Input 5v
6
VSYNC2_PORT1 Input 5v
FIELD ID2_PORT1
7
VDD1
8
VSS
9
IN_CLK2_PORT1
10
B/Cb/D1_0
11
B/Cb/D1_1
12
B/Cb/D1_2
13
B/Cb/D1_3
14
B/Cb/D1_4
15
VDDcore1
16
VSScore
17
B/Cb/D1_5
18
B/Cb/D1_6
19
B/Cb/D1_7
20
R/Cr/Cb Cr_0
21
R/Cr/Cb Cr_1
22
R/Cr/Cb Cr_2
23
R/Cr/Cb Cr_3
24
R/Cr/Cb Cr_4
25
R/Cr/Cb Cr_5
26
R/Cr/Cb Cr_6
27
R/Cr/Cb Cr_7
28
G/Y/Y_0
29
VDD2
30
VSS
31
G/Y/Y_1
32
G/Y/Y_2
33
G/Y/Y_3
34
G/Y/Y_4
35
VDDcore2
36
VSScore
37
G/Y/Y_5
38
G/Y/Y_6
39
G/Y/Y_7
40
41
IN_SEL Output 5v 8 mA
42 TEST Input 5v
43
DEV_ADDR1 Input 5v
Pin Name I/O Type
Input 5v
Input 5v
Input 5v
Power 3.3 V - Power pin for IO
Ground Ground
Input 5v
Input 5v
Input 5v
Input 5v
Input 5v
Input 5v
Power 1.8 V - Power pin for core
Ground Ground
Input 5v
Input 5v
Input 5v
Input 5v
Input 5v
Input 5v
Input 5v
Input 5v
Input 5v
Input 5v
Input 5v
Input 5v
Power 3.3 V - Power pin for IO
Ground Ground
Input 5v
Input 5v
Input 5v
Input 5v
Power 1.8 V - Power pin for core
Ground Ground
Input 5v
Input 5v
Input 5v
Voltage
Tolerance
Drive
Description
Horizontal sync or reference -CTL1 of Port 1
Vertical sync or reference -CTL1 of Port 1
Odd/Even Field identification -CTL1 of Port 1
Data Clock input -CTL1 of Port 1
Horizontal sync or reference –CTL2 of Port 1
Vertical sync or reference –CTL2 of Port 1
Odd/Even Field identification –CTL2 of Port 1
Data Clock input –CTL2 of Port 1
Port 1 – Digital video input (Blue/Cb/D1)
Port 1 – Digital video input (Blue/Cb/D1)
Port 1 – Digital video input (Blue/Cb/D1)
Port 1 – Digital video input (Blue/Cb/D1)
Port 1 – Digital video input (Blue/Cb/D1)
Port 1 – Digital video input (Blue/Cb/D1)
Port 1 – Digital video input (Blue/Cb/D1)
Port 1 – Digital video input (Blue/Cb/D1)
Port 1 – Digital video input (Red/Cr/CrCb)
Port 1 – Digital video input (Red/Cr/CrCb)
Port 1 – Digital video input (Red/Cr/CrCb)
Port 1 – Digital video input (Red/Cr/CrCb)
Port 1 – Digital video input (Red/Cr/CrCb)
Port 1 – Digital video input (Red/Cr/CrCb)
Port 1 – Digital video input (Red/Cr/CrCb)
Port 1 – Digital video input (Red/Cr/CrCb)
Port 1 – Digital video input (Green/Y)
Port 1 – Digital video input (Green/Y)
Port 1 – Digital video input (Green/Y)
Port 1 – Digital video input (Green/Y)
Port 1 – Digital video input (Green/Y)
Port 1 – Digital video input (Green/Y)
Port 1 – Digital video input (Green/Y)
Port 1 – Digital video input (Green/Y)
Output to select external video mux
Connect to Ground
Device address setting 1
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
FLI2300 Digital Video Converter Data Sheet
15
Pin
No
44
DEV_ADDR0 Input 5v
45 SCLK
46 SDATA
47 RESET_N
48 VDD3
49 VSS
50 SDRAM DATA(0)
51 SDRAM DATA(1)
52 SDRAM DATA(2)
53 SDRAM DATA(3)
54 SDRAM DATA(4)
55 SDRAM DATA(5)
56 SDRAM DATA(6)
57 SDRAM DATA(7)
58 SDRAM DATA(8)
59 SDRAM DATA(9)
60 SDRAM DATA(10)
61 SDRAM DATA(11)
62 VDD4
63 VSS
64 SDRAM DATA(12)
65 SDRAM DATA(13)
66 SDRAM DATA(14)
67 SDRAM DATA(15)
68 VDDcore3
69 VSScore
70 SDRAM DATA(16)
71 SDRAM DATA(17)
72 SDRAM DATA(18)
73 SDRAM DATA(19)
74 SDRAM DATA(20)
75 SDRAM DATA(21)
76 SDRAM DATA(22)
77 SDRAM DATA(23)
78 SDRAM DATA(24)
79 SDRAM DATA(25)
80 VDDcore4
81 VSScore
82 SDRAM DATA(26)
83 SDRAM DATA(27)
84 SDRAM DATA(28)
85 SDRAM DATA(29)
86 SDRAM DATA(30)
87 SDRAM DATA(31)
88 VDD5
Pin Name I/O Type
I/O
I/O
Input
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Ground
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Tristate I/O
Power
Voltage
Tolerance
5v 8 mA 2-wire serial control bus clock
5v 8 mA 2-wire serial control bus data
5v PU Reset
3.3 V – Power pin for IO
Ground
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
3.3 V – Power pin for IO
Ground
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
1.8 V - Power pin for core
Ground
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
1.8 V – Power pin for core
Ground
5v 4 mA PD SDRAM data bus *
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
5v 4 mA PD
3.3 V – Power pin for IO
Drive
Internal
Pull up/
Pulldown
Device address setting 0
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
SDRAM data bus *
Description
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
FLI2300 Digital Video Converter Data Sheet
16
Pin
No
89 VSS
90 TEST IN
91 SDRAM ADDR(10)
92 SDRAM ADDR(9)
93 SDRAM ADDR(8)
94 SDRAM ADDR(7)
95 SDRAM ADDR(6)
96 VDDcore5
97 VSScore
98 SDRAM ADDR(5)
99 SDRAM ADDR(4)
100 SDRAM ADDR(3)
101 SDRAM ADDR(2)
102 SDRAM ADDR(1)
103 SDRAM ADDR(0)
104 SDRAM WEN
105 SDRAM RASN
106 SDRAM CASN
107 SDRAM BA1
108 SDRAM BA0
109 SDRAM CSN
110 SDRAM DQM
111 SDRAM CLKOUT
112 VDD6
113 VSS
114 SDRAM CLKIN
115 TEST3
116 TEST OUT0
117 TEST OUT1
118 CTLOUT0
119 CTLOUT1
120 CTLOUT2
121 CTLOUT3
122 CTLOUT4
123 VDDcore6
124 VSScore
125 CLKOUT
126 B/U/Pb_OUT_0
127 B/U/Pb_OUT_1
128 VDD7
129 VSS
Pin Name I/O Type
Ground
Input
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Power
Ground
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Output
Power
Ground
Input
Input
Output
Output
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Power
Ground
Tristate O/P
Tristate O/P
Tristate O/P
Power
Ground
Voltage
Tolerance
Ground
5V Test input-Connect to ground
5v 8 mA SDRAM address bus *
5v 8 mA SDRAM address bus *
5v 8 mA SDRAM address bus *
5v 8 mA SDRAM address bus *
5v 8 mA SDRAM address bus *
1.8 V – Power pin for core
Ground
5v 8 mA SDRAM address bus *
5v 8 mA SDRAM address bus *
5v 8 mA SDRAM address bus *
5v 8 mA SDRAM address bus *
5v 8 mA SDRAM address bus *
5v 8 mA SDRAM address bus *
5v 8 mA SDRAM write enable *
5v 8 mA SDRAM row address select *
5v 8 mA SDRAM column address select *
5v 8 mA SDRAM bank select 1*
5v 8 mA SDRAM bank select 0*
5v 4 mA SDRAM CS *
5v 8 mA SDRAM DQM *
5v 12 mA Clock out to SDRAM *
3.3 V - Power pin for IO
Ground
5v Trace delayed SDRAM Clock in
Test input – Connect to ground
12 mA Test output – leave open
8 mA Test output – leave open
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
1.8 V - Power pin for core
Ground
5v 12 mA Output data rate clock
5v 8 mA
5v 8 mA
3.3 V – Power pin for IO
Ground
Drive
Internal
Pull up/
Pulldown
Description
Control signal output selectable as HSync1/
CSync/HRef/Monitor coast
Control signal output selectable as
VSync1/CRef/VRef/Film Indicator
Control signal output selectable as Monitor
coast/HRef/VDD_en / HSync2
Control signal output selectable as Film
Indicator/VRef/backlight_en/VSync2
Control signal output selectable as CRef/Field
ID/CSync/Monitor coast
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
FLI2300 Digital Video Converter Data Sheet
17
Pin
No
130 B/U/Pb_OUT_2
131 B/U/Pb_OUT_3
132 B/U/Pb_OUT_4
133 B/U/Pb_OUT_5
134 B/U/Pb_OUT_6
135 B/U/Pb_OUT_7
136 R/V/Pr_OUT_0
137 R/V/Pr_OUT_1
138 VDDcore7
139 VSScore
140 R/V/Pr_OUT_2
141 R/V/Pr_OUT_3
142 R/V/Pr_OUT_4
143 R/V/Pr_OUT_5
144 R/V/Pr_OUT_6
145 R/V/Pr_OUT_7
146 VDD8
147 VSS
148 G/Y/Y_OUT_0
G/Y/Y_OUT_1
149
G/Y/Y_OUT_2
150
G/Y/Y_OUT_3
151
G/Y/Y_OUT_4
152
G/Y/Y_OUT_5
153
G/Y/Y_OUT_6
154
G/Y/Y_OUT_7
155
156 OE
157 PLL_PVDD
158 PLL_PVSS
159 AVSS_PLL_BE1
160 AVDD_PLL_BE1
161 AVDD_PLL_BE2
162 AVSS_PLL_BE2
163 AVSS_PLL_SDI
164 AVDD_PLL_SDI
165 AVDD_PLL_FE
166 AVSS_PLL_FE
167 DAC_PVSS
168 DAC_VDD
169 DAC_VSS
170 DAC_BOUT
171
DAC_AVDDB
172 DAC_AVSSB
173 DAC_GOUT
174 DAC_AVDDG
Pin Name I/O Type
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Power
Ground
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Power
Ground
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Tristate O/P
Input
Power
Ground
Ground
Power
Power
Ground
Ground
Power
Power
Ground
Ground
Power
Ground
Output
Power
Ground
Output
Power
Voltage
Tolerance
5v 8 mA Digital video output – Blue/U/Pb
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA Digital video output – Red/V/Pr
5v 8 mA Digital video output – Red/V/Pr
1.8 V – Power pin for core
Ground
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
3.3 V – Power pin for IO
Ground
5v 8 mA Digital video output – Green/Y
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
5v 8 mA
5v Output data enable for Digital video output
1.8 V – Power pin for PLL pads
Ground for PLL pads
PLL Ground
1.8 V – Power pin for PLL
1.8 V – Power pin for PLL
PLL Ground
PLL Ground
1.8 V – Power pin for PLL
1.8 V – Power pin for PLL
PLL Ground
Ground for DAC pads
1.8 V – Digital power pin for DAC
DAC digital Ground
34 mA Analog B/U output
3.3 V – Analog power pin for B channel
Analog Ground for B channel
34 mA Analog G/Y output
3.3 V – Analog power pin for G channel
Drive
Internal
Pull up/
Pulldown
Description
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
Digital video output – Blue/U/Pb
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
Digital video output – Red/V/Pr
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
Digital video output – Green/Y
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
FLI2300 Digital Video Converter Data Sheet
18
Pin
No
175 DAC_AVSSG
176 DAC_ROUT
177 DAC_AVDDR
178 DAC_AVSSR
179 DAC_COMP
180 DAC_RSET
181 DAC_VREFOUT
182 DAC_VREFIN
183 DAC_AVDD
184 DAC_AVSS
185 DAC_GR_AVSS
186 DAC_GR_AVDD
187 DAC_PVDD
188 TEST0
189 TEST1
190 TEST2
191 XTAL IN
192 XTAL OUT
193 VDD9
194 VSS
195 IN_CLK_PORT 2
196 D1_IN_0
197 VDDcore8
198 VSScore Ground Ground
199 D1_IN_1 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input
200 D1_IN_2 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input
201 D1_IN_3 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input
202 D1_IN_4 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input
203 D1_IN_5 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input
204 D1_IN_6 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input
205 D1_IN_7 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input
206 FIELD ID_PORT 2
207 VSYNC_ PORT 2
208 HSYNC_PORT 2
Note: 1) * - The connection of these pins depends on the type of external SDRAM used. See Appendix 3
Pin Name I/O Type
Ground
Output
Power
Ground
Output
Output
Output
Input
Power
Ground
Ground
Power
Power
Input
Input
Input
Input
Output
Power
Ground
Input
Input
Power
Input
Input
Input
2) For 16/20 bit Y and muxed C output modes see Appendix 2 for pin configuration
Voltage
Tolerance
Analog Ground for G channel
34 mA Analog R/V output
3.3 V – Analog power pin for R channel
Analog Ground for R channel
Compensation for video DACs
Current setting resistor for video DACs
External Voltage reference for video DACs
3.3 V – Analog power pin for DAC
Analog Ground for DAC
Ground for DAC Guard ring
3.3 V – Power pin for DAC Guard ring
3.3 V –Power pin for DAC pads
5v Test pin – connect to ground
5v Test pin – connect to ground
5v Test pin – connect to ground
External parallel crystal oscillator
External parallel crystal oscillator
3.3 V - Power pin for IO
Ground
5v 4 mA Port 2 - Data Clock input
5v 4 mA Port 2 - ITU-R BT656 digital data input
1.8 V – Power pin for core
5v 4 mA Port 2 - Odd/Even Field identification
5v 4 mA Port 2 - Vertical sync or reference
5v 4 mA Port 2 - Horizontal sync or reference
Drive
Internal
Pull up/
Pulldown
Description
1.28 V Internally generated voltage reference for
video DACs
*** Genesis Microchip Confidential ***
PRELIMINARY INFORMATION -- SUBJECT TO CHANGE
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
19
8. Am29LV160D
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supp ly operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3. 0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Manufactured on 0.23 µm process technology
— Fully compatible with 0.32 µm Am29L V160B de vice
■ High performan c e
— Access times as fast as 70 ns
■ Ultra low power consumption (typical values at
5MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
thirty-one 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect f eature allows code
changes in previously locked sectors
■ Unlock Bypass Program Command
— Reduces overall pr ogramming time when issuing
multiple program command sequences
■ Top or bottom boot block configurations
available
■ Minimum 1,000,000 write cycle guarantee
per sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
■ CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detec ting program
or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completi on (not av ailable
on 44-pin SO)
■ Erase Suspend/Erase Resume
— Suspends an erase operation t o read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the devic e to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modificat ions due to changes in technical specif ic ations.
Publication# 22358 Rev: B Amendment/+3
Issue Date: November 10, 2000
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