2. PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY
SENSITIVE(ES)DEVICES
3. CONTROL BUTTON LOCATIONS AND EXPLANATIONS
4. PREVERTION OF STATIC ELECTRICITY DISCHARGE
5. ASSEMBLING AND DISASSEMBLING THE MECHANISM UNIT
5.1 OPTICAL PICKUP UNIT EXPLOSED VIEW AND PART LIST
5.2 BRACKET EXPLOSED VIEW AND PART LIST
5.3 MISCELLANEOUS
6. ELECTRICAL CONFIRMATION
6.1 VIDEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION
6.2 VIDEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION
1
1
2
3
4
4
6
7
8
8
9
7. MPEG BOARD CHECK WAVEFORM
8. HY29LV800
10
11
8.1 IC42S1610116
8.2 MT1389
9. SCHEMATIC & PCB WIRING DIAGRAM
22
10. SPARE PARTS LIST
Page 3
1.1 GENERAL GUIDELINES
1. SAFETY PREAUTIONS
2.PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO
ELECTROSTATICALLY SENSITIVE(ES)DEVICES
1
1. When servicing, observe the original lead dress. if a short circuit is found, replace all parts which have
been overheated or damaged by the short circuit.
2. After servicing, see to it that all the protective devices such as insulation barrier, insulation papers
shields are properly installed.
3. After servicing, make the following leakage current checks to prevent the customer from being exposed
to shock hazards.
Some semiconductor(solid state)devices can be damaged easily by static electricity. Such components
commonly are called Electrostatically Sensitive(ES)Devices. Examples of typical ES devices are integrated
circuits and some field-effect transistors and semiconductor chip components. The following techniques
should be used to help reduce the incidence of component damage caused by electro static discharge(ESD).
1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain
off any ESD on your body by touching a known earth ground. Alternatively, obtain and wear a commercially
availabel discharging ESD wrist strap, which should be removed for potential shock reasons prior to
applying power to the unit under test.
2. After removing an electrical assembly equipped with ES devices,place the assembly on a conductive
surface such as alminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.
4. Use only an anti-static solder removal device. Some solder removal devices not classified as anti-static
(ESD protected)can generate electrical charge sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ES
devices.
6. Do not remove a replacement ES device from its protective package until immediately before you are
ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by
conductive foam, alminum foil or comparable conductive material).
7. Immediately before removing the protective material from the leads of a replacement ES device, touch
the protective material to the chassis or circuit assembly into which the device will be installed.
Caution
Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can
generate static electricity(ESD).
notice (1885x323x2 tiff)
Page 4
2
2
ECHOVOL
3
5
4
67
8
15
9
POWER switch
Disc tray
2
3
OPEN/CLOSE button
4
PLAY button
5
PAUSE button
11 12
6
STOP button
7
REV button
8
FWD button
MIC 1 jack
9
MIC 2 jack
10
13
11
MIC VOLUME knob
ECHO adjustment knob
12
13
IR SENSOR
LED display window
14
15
Headphone jack
1410
Page 5
The laser diode in the traverse unit (optical pickup)may brake down due to static electricity of clothes or human
body. Use due caution to electrostatic breakdown when servicing and handling the laser diode.
Some devices such as the DVD player use the optical pickup(laser diode)and the optical pickup will be damaged
by static electricity in the working environment.Proceed servicing works under the working environment where
1. Put a conductive material(sheet)or iron sheet on the area where the optical pickup is placed,and ground the
3. The flexible cable may be cut off if an excessive force is applied to it.Use caution when handling the cable.
3
4.PREVENTION OF STATIC ELECTRICITY DISCHARGE
4.1.Grounding for electrostatic breakdown prevention
grounding works is completed.
4.1.1. Worktable grounding
sheet.
4.1.2.Human body grounding
1 Use the anti-static wrist strap to discharge the static electricity from your body.
safety_3 (1577x409x2 tiff)
4.1.3.Handling of optical pickup
1. To keep the good quality of the optical pickup maintenance parts during transportation and before
installation, the both ends of the laser diode are short-circuited.After replacing the parts with new ones,
remove the short circuit according to the correct procedure. (See this Technical Guide).
2. Do not use a tester to check the laser diode for the optical pickup .Failure to do so willdamage the laser
diode due to the power supply in the tester.
4.2. Handling precautions for Traverse Unit (Optical Pickup)
1. Do not give a considerable shock to the traverse unit(optical pickup)as it has an extremely high-precise
structure.
2. When replacing the optical pickup, install the flexible cable and cut is short land with a nipper. See the
optical pickup replacement procedure in this Technical Guide. Before replacing the traverse unit, remove
the short pin for preventingstatic electricity and install a new unit.Connect the connector as short times as
possible.
4. The half-fixed resistor for laser power adjustment cannot be adjusted. Do not turn the resistor.
Page 6
5.1Optical pickup Unit Explosed View and Part List
5. Assembling and disassembling the mechanism unit
4
Pic (1)
Page 7
Materials to Pic (1)
5
No. PARTS CODE PARTS NAME Qty
14692200 SF-HD60 1
1
1EA0311A06300 ASSY, CHASSIS, COMPLETE 1
2
Or
3
4
5
6
7
8
9
10
11
21
Or
31
32
1EA0M10A15500 ASSY, MOTOR, SLED 1
1EA0M10A15501 ASSY, MOTOR, SLED 1
1EA2451A24700 HOLDER, SHAFT 3
1EA2511A29100 GEAR, RACK 1
1EA2511A29200 GEAR, DRIVE 1
1EA2511A29300 GEAR, MIDDLE, A 1
1EA2511A29400 GEAR, MIDDLE, B 1
1EA2744A03000 SHAFT, SLIDE 1
1EA2744A03100 SHAFT, SLIDE, SUB 1
1EA2812A15300 SPRING, COMP, TYOUSEI 3
1EA2812A15400 SPRING, COMP, RACK 1
1EA0B10B20100 ASSY, PWB 1
1EA0B10B20200 ASSY, PWB 1
SEXEA25700--- SPECIAL SCREW BIN+-M2X11 3
SEXEA25900--- SPECIAL SCREW M1.7X2.2 2
33
34
35
Note : This parts list is not for service parts supply.
SFBPN204R0SE- SCR S-TPG PAN 2X4 2
SFSFN266R0SE- SCR S-TPG FLT 2.6X6 1
SWXEA15400--- SPECIAL WASHER 1.8X4 X0.25 2
Page 8
5.2 BracketExplosed View and Part List
6
Pic (2)
Materials to Pic(2)
1.bracket 14. front silicon rubber
2.belt 15. Back silicon rubber
3.screw 16. Pick-up
4.belt wheel 17. Pick-up
5.gearwheel 18. switch
6.iron chip 19. Five-pin flat plug
7. Immobility mechanism equipment 20. screw
8. Magnet 21. PCB
9. Platen 22. motor
10. Bridge bracket 23. Motor wheel
11. screw 24. screw
12. screw 25.tray
13. Big bracket
Before going process with disassembly and installation, please carefully both
peruse the chart and confirm the materials.
Page 9
5.3 MISCELLANEOUS
7
5.3.1 Protection of the LD(Laser diode)
Short the parts of LD circuit pattern by soldering.
5.3.2 Cautions on assembly and adjustment
Make sure that the workbenches,jigs,tips,tips of soldering irons and measuring instruments are
grounded,and that personnel wear wrist straps for ground.
Open the LD short lands quickly with a soldering iron after a circuit is connected.
Keep the power source of the pick-up protected from internal and external sources of electrical
noise.
Refrain from operation and storage in atmospheres containing corrosive gases (such as H2S,SO2,
NO2 and Cl2)or toxic gases or in locations containing substances(especially from the organic silicon,cyan,
formalin and phenol groups)which emit toxic gases.It is particularly important to ensure that none of the
above substances are present inside the unit.Otherwise,the motor may no longer run.
Page 10
6.1. Video Output (Luminance Signal) Confirmation
6.Electrical Confirmation
8
DO this confirmation after replacing a P.C.B.
Measurement point
Video output terminal
Measuring equipment,tools
200mV/dir,10sec/dir
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohms.
2.Confirm that luminance signal(Y+S)level is 1000mVp-p±30mV
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
ModeDisc
Color bar 75%
Confirmation value
1000mVp-p±30mV
DVDT-S15
or
DVDT-S01
Page 11
Do the confirmation after replacing P.C.B.
Screwdriver,Oscilloscope
6.2 Video Output(Chrominance Signal) Confirmation
9
Measurement point
Video output terminal
Measuring equipment,toolsConfirmation value
200mV/dir,10sec/dir
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohme.
2.Confirm that the chrominance signal(C)level is 621 mVp-p±30mV
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
ModeDisc
Color bar 75%
621mVp-p±30mV
DVDT-S15
or
DVDT-S01
Page 12
7.MPEG BOARD CHECK WAVEFORM
7.1 27MHz WAVEFORM
7.2 IC5L0380R PIN.2 WAVEFORM DIAGRAM
10
Page 13
KEY FEATURES
11
8. HY29LV800
HY29LV800
8 Mbit (1M x 8/512K x 16) Low Voltage Flash Memory
and Erases Any Combination of Sectors
or the Entire Chip
nn
nAutomatic Program Algorithm Writes and
nn
Verifies Data at Specified Addresses
nn
nCompliant With Common Flash Memory
nn
Interface (CFI) Specification
– Flash device parameters stored directly
on the device
– Allows software driver to identify and use
a variety of different current and future
Flash products
nn
nMinimum 100,000 Write Cycles per Sector
nn
nn
nCompatible With JEDEC standards
nn
– Pinout and software compatible with
single-power supply Flash devices
– Superior inadvertent write protection
nn
nData# Polling and Toggle Bits
nn
– Provide software confirmation of
completion of program and erase
operations
nn
nReady/Busy# Pin
nn
– Provides hardware confirmation of
completion of program and erase
operations
nn
nErase Suspend/Erase Resume
nn
– Suspends an erase operation to allow
reading data from, or programming data
to, a sector that is not being erased
– Erase Resume can then be invoked to
complete suspended erasure
nn
nHardware Reset Pin (RESET#) Resets the
nn
Device to Reading Array Data
nn
nSpace Efficient Packaging
nn
– 44-pin PSOP, 48-pin TSOP and 48-ball
FBGA packages
LOGIC DIAGRAM
19
A[18:0]
CE#
OE#
WE#
RESET#
BYTE#
DQ[7:0]
DQ[14:8]
DQ15/A-1
RY/BY#
8
7
Product Brief
Revision 1, March 2000
Page 14
GENERAL DESCRIPTION
12
HY29LV800
The HY29LV800 is an 8 Mbit, 3 volt-only, CMOS
Flash memory organized as 1,048,576 (1M) bytes
or 524,288 (512K) words that is available in 44pin PSOP, 48-pin TSOP and reverse TSOP and
48-ball FBGA packages. Word-wide data (x16)
appears on DQ[15:0] and byte-wide (x8) data appears on DQ[7:0].
The HY29LV800 can be programmed and erased
in-system with a single 3 volt V
supply. Inter-
CC
nally generated and regulated voltages are provided for program and erase operations, so that
the device does not require a higher voltage V
PP
power supply to perform those functions. The device can also be programmed in standard EPROM
programmers. Access times as low as 65 ns over
the full operating voltage range of 2.7 - 3.6 volts
are offered for timing compatibility with the zero
wait state requirements of high speed microprocessors. To eliminate bus contention, the
HY29LV800 has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC singlepower-supply Flash command set standard. Commands are written to the command register using
standard microprocessor write timings. They are
then routed to an internal state-machine that controls the erase and programming circuits. Device
programming is performed a byte/word at a time
by executing the four-cycle Program Command
write sequence. This initiates an internal algorithm
that automatically times the program pulse widths
and verifies proper cell margin. Faster programming times can be achieved by placing the
HY29LV800 in the Unlock Bypass mode, which
requires only two write cycles to program data instead of four.
The HY29LV800’s sector erase architecture allows
any number of array sectors to be erased and reprogrammed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command sequence. This
initiates an internal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the erase operation.
As during programming cycles, the device automatically times the erase pulse widths and verifies proper cell margin. Hardware Sector Protection optionally disables both program and erase
operations in any combination of the sectors of
the memory array, while Temporary Sector Unprotect allows in-system erasure and code
changes in previously protected sectors. Erase
Suspend enables the user to put erase on hold for
any period of time to read data from, or program
data to, any sector that is not selected for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (toggle) status bits.
Hardware data protection measures include a low
V
detector that automatically inhibits write op-
CC
erations during power transitions.
After a program or erase cycle has been com-
pleted, or after assertion of the RESET# pin (which
terminates any operation in progress), the device
is ready to read data or to accept another command. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Two power-saving features are embodied in the
HY29LV800. When addresses have been stable
for a specified amount of time, the device enters
the automatic sleep mode. The host can also place
the device into the standby mode. Power consumption is greatly reduced in both these modes.
Common Flash Memory Interface (CFI)
To make Flash memories interchangeable and to
encourage adoption of new Flash technologies,
major Flash memory suppliers developed a flexible method of identifying Flash memory sizes and
configurations in which all necessary Flash device
parameters are stored directly on the device.
Parameters stored include memory size, byte/word
configuration, sector configuration, necessary voltages and timing information. This allows one set
of software drivers to identify and use a variety of
different, current and future Flash products. The
standard which details the software interface necessary to access the device to identify it and to
determine its characteristics is the Common Flash
Memory Interface (CFI) Specification. The
HY29LV800 is fully compliant with this specification.
This document describes a product currently under design by
Hyundai. The information in this document is subject to change
PB r1.0/Mar. 00
without notice. Hyundai shall not be responsible for any errors
that may appear in this document and makes no commitment
to update or keep current the information contained in this document. Hyundai advises its customers to obtain the latest version of the device specification to verify, before placing orders,
that the information being relied upon by the customer is current.
Page 17
IC42S16101
15
512K x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Drive Strength for low capacitive bus loading
• Clock frequency: 166, 143, 125 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Package 400mil 50-pin TSOP-2
DESCRIPTION
ICSI
's 16Mb Synchronous DRAM IC42S16101 is organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
20 to 24A0-A10Input PinA0 to A10 are address inputs. A0-A10 are used as row address inputs during active
27 to 32command input and A0-A7 as column address inputs during read or write command
input. A10 is also used to determine the precharge mode during other commands. If
A10 is LOW during precharge command, the bank selected by A11 is precharged,
but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically after the burst access.
These signals become part of the OP CODE during mode register set command
input.
19A11Input PinA11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when
high, bank 1 is selected. This signal becomes part of the OP CODE during mode
register set command input.
16CASInput PinCAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.
34CKEInput PinThe CKE input determines whether the CLK input is enabled within the device.
When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when
LOW, invalid. When CKE is LOW, the device will be in either the power-down mode,
the clock suspend mode, or the self refresh mode.
35CLKInput PinCLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
18CSInput PinThe CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
2, 3, 5, 6, 8, 9, 11I/O0 toI/O PinI/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units
12, 39, 40, 42, 43,I/O15using the LDQM and UDQM pins.
45, 46, 48, 49
14, 36LDQM,Input PinLDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
UDQMmode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the
input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH,
input data is masked and cannot be written to the device.
17RASInput PinRAS, in conjunction with CAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.
15WEInput PinWE, in conjunction with RAS and CAS, forms the device command. See the
"Command Truth Table" item for details on device commands.
7, 13, 38, 44VCCQPower Supply PinVCCQ is the output buffer power supply.
1, 25VCCPower Supply PinVCC is the device internal power supply.
4, 10, 41, 47GNDQPower Supply PinGNDQ is the output buffer ground.
26, 50GNDPower Supply PinGND is the device internal ground.
The CKE is an asynchronous i
nput.
Integrated Circuit Solution Inc.
DR025-0B 04/15/2002
Page 19
IC42S16101
17
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
COMMAND
DECODER
&
CLOCK
GENERATOR
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
LATCH
11
MODE
REGISTER
11
SELF
REFRESH
CONTROLLER
MULTIPLEXER
11
8
11
ROW
ADDRESS
BUFFER
COLUMN
ADDRESS LATCH
ROW
ADDRESS
BUFFER
11
COLUMN
BURST COUNTER
11
MEMORY CELL
2048
ARRAY
BANK 0
SENSE AMP I/O GATE
256
COLUMN DECODER
8
ADDRESS BUFFER
2048
256
SENSE AMP I/O GATE
MEMORY CELL
ARRAY
BANK 1
ROW DECODERROW DECODER
DATA IN
BUFFER
16
DATA OUT
BUFFER
1616
DQM
16
I/O 0-15
Vcc/VccQ
GND/GNDQ
S16BLK.eps
Integrated Circuit Solution Inc.
DR025-0B 04/15/2002
Page 20
8.2 MT1389
18
MT1389
Specifications are subject to change without notice
Progressive-Scan DVD Player SOC
MediaTek MT1389 is a DVD player system-on-chip (SOC) which incorporates advanced features like high
quality TV encoder and state-of-art de-interlace processing. The MT1389 enables consumer electronics
manufacturers to build high quality, cost-effective DVD players, portable DVD players or any other home
entertainment audio/video devices.
rd
Based on MediaTek’s world-leading DVD player SOC architecture, the MT1389 is the 3
player SOC. It integrates the MediaTek 2
decoder.
The progressive scan of the MT1389 utilized a proprietary advanced motion-adaptive de-interlace algorithm to
achieve the best movie/video playback. It can easily detect 3:2/2:2 pull down source and restore the correct
original pictures. It also supports a patent-pending edge-preserving algorithm to remove the saw-tooth effect.
nd
generation front-end analog RF amplifier and the Servo/MPEG AV
generation of the DVD
Key Features
RF/Servo/MPEG Integration
High Performance Audio Processor
Motion-Adaptive, Edge-Preserving De-interlace
108MHz/12-bit, 6 CH TV Encoder
DVD
PUH
Module
CVBS, Y/C,
Component
SDPIF
MT1389L
Applications
FLASH
Front-panel
Remote
DRAM
Audio DAC
Standard DVD Players
Portable DVD Players
DVD Player System Diagram Using MT1389
Page 21
19
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT1389
General Feature List
1024-bytes on-chip RAM
Super Integration DVD player single chip
High performance analog RF amplifier
Servo controller and data channel processing
MPEG-1/MPEG-2/JPEG video
Dolby AC-3/DTS/DVD-Audio
Unified memory architecture
Versatile video scaling & quality
enhancement
OSD & Sub-picture
2-D graphic engine
Built-in clock generator
Built-in high quality TV encoder
Built-in progressive video processor
Audio effect post-processor
Audio input port
Up to 4M bytes FLASH-programming
interface
Supports 5/3.3-Volt. FLASH interface
Supports power-down mode
Supports additional serial port
DVD-ROM/CD-ROM Decoding Logic
High-speed ECC logic capable of correcting
one error per each P-codeword or
Q-codeword
Automatic sector Mode and Form detection
Automatic sector Header verification
Decoder Error Notification Interrupt that
signals various decoder errors
Provide error correction acceleration
High Performance Analog RF Amplifier
Programmable fc
Dual automatic laser power control
Defect and blank detection
RF level signal generator
Speed Performance on Servo/Channel Decoding
DVD-ROM up to 4XS
CD-ROM up to 24XS
Channel Data Processor
Digital data slicer for small jitter capability
Built-in high performance data PLL for
channel data demodulation
EFM/EFM+ data demodulation
Enhanced channel data frame sync protection
& DVD-ROM sector sync protection
Servo Control and Spindle Motor Control
Programmable frequency error gain and
phase error gain of spindle PLL to control
spindle motor on CLV and CAV mode
Built-in ADCs and DACs for digital servo
control
Provide 2 general PWM
Tray control can be PWM output or digital
Supports 16Mb/32Mb/64Mb/128Mb SDRAM
Supports 16-bit SDRAM data bus
Provide the self-refresh mode SDRAM
Block-based sector addressing
Support 3.3 Volt. DRAM Interface
Video Decode
Decodes MPEG1 video and MPEG2 main level,
main profile video (720/480 and 720x576)
Smooth digest view function with I, P and B
picture decoding
Baseline, extended-sequential and
progressive JPEG image decoding
Support CD-G titles
Video/OSD/SPU/HLI Processor
Arbitrary ratio vertical/horizontal scaling of
video, from 0.25X to 256X
65535/256/16/4/2-color bitmap format OSD,
256/16 color RLC format OSD
Automatic scrolling of OSD image
Slide show transition as DVD-Audio
Specification
2-D Graphic Engine
Support decode Text and Bitmap
Support line, rectangle and gradient fill
Support bitblt
Chroma key copy operation
Clip mask
Page 22
20
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT1389
Audio Effect Processing
Dolby Digital (AC-3)/EX decoding
DTS/DTS-ES decoding
MLP decoding for DVD-Audio
MPEG-1 layer 1/layer 2 audio decoding
MPEG-2 layer1/layer2 2-channel audio
High Definition Compatible Digital (HDCD)
Windows Media Audio (WMA)
Advanced Audio Coding (AAC)
Dolby ProLogic II
Concurrent multi-channel and downmix out
IEC 60958/61937 output
- PCM / bit stream / mute mode
- Custom IEC latency up to 2 frames
Pink noise and white noise generator
Karaoke functions
- Microphone echo
- Microphone tone control
- Vocal mute/vocal assistant
- Key shift up to +/- 8 keys
- Chorus/Flanger/Harmony/Reverb
Channel equalizer
3D surround processing include virtual
surround and speaker separation
TV Encoder
Six 108MHz/12bit DACs
Support NTSC, PAL-BDGHINM, PAL-60
Support 525p, 625p progressive TV format
Automatically turn off unconnected channels
Support PC monitor (VGA)
Support Macrovision 7.1 L1, Macrovision
525P and 625P
CGMS-A/WSS
Closed Caption
Progressive Output
Automatic detect film or video source
3:2 pull down source detection
Advanced Motion adaptive de-interlace
Edge Preserving
Minimum external memory requirement
Audio Input
Line-in/SPDIF-in for versatile audio