x Driving IC: ‘PHILIPS’ PCF 2119RU/2/F2 COG form LCD controller/driver.
x Data interface: I2C-bus.
x RTV coating.
x White LED05 backlight.
2. Mechanical Specifications
The mechanical detail is shown in Fig. 1 and summarized in Table 1 below.
Table 1
Parameter Specifications Unit
Outline dimensions 74.5(W) x 29.8(H) x 4.5(D) (Excluded pins, backlight
terminals and epoxy)
Viewing area 61.0(W) x 15.8(H) mm
Active area 56.20(W) x 11.50(H) mm
Display format 16 characters (5 x 8 dots) x 2 lines Character size 2.95(W) x 5.553(H) mm
Character spacing 0.60(W) x 0.394(H) mm
Character pitch 3.55(W) x 5.947(H) mm
Dot size 0.578(W) x 0.681(H) mm
Dot spacing 0.015(W) x 0.015(H) mm
Dot pitch 0.593(W) x 0.696(H) mm
Weight Approx. 13.0 grams
mm
VL-FS-COG-BTHQ21605-01 REV. A
(BTHQ 21605V-FSTF-I2C-COG)
OCT/2003
PAG E 5 OF 12
Figure 1 and Figure 2: Specification Drawing
VL-FS-COG-BTHQ21605-01 REV. A
(BTHQ 21605V-FSTF-I2C-COG)
OCT/2003
PAG E 6 OF 12
Figure 3: Backlight Drawing
SDA
SCL
POR
VDD
VLCD
'PHILI PS'
PCF2119RU/ 2/F2
(COG)
LCD CONTROLLER/
DRIVE R
VL-FS-COG-BTHQ21605-01 REV. A
(BTHQ 21605V-FSTF-I2C-COG)
OCT/2003
PAG E 7 OF 12
COG- BTHQ21605V LCD DISPLAY
16
2 LI NES X 16 CHAR ACTERS
(5 X8 DOTS)
VSS
80
Figure 4: Block Diagram
Figure 5: Reference Circuit
OCT/2003
A
H
V
r
H
3. Interface signals
Table 2
Pin No. Symbol Description
1VLCDLCD driver voltage
2VSSGround (0V)
3VDDPower supply for logic.
4SDAI
2
C serial data input/output
5PORExternal power –on reset input. Active High.
6SCLI
2
C serial clock input
4. Absolute Maximum Ratings
4.1 Electrical Maximum Ratings (Ta = 25 ºC)
VL-FS-COG-BTHQ21605-01 REV. A
(BTHQ 21605V-FSTF-I2C-COG)
PAGE 8 OF 12
Table 3
ParameterConditionSymbolMin.Max.Unit
Supply voltage range (Logic)-VDD - VSS-0.5+4.0V
Input voltage rangeOSC,SCL,SDAVi-0.5VDD +0.5V
Input voltage range (LCD) V
LCD
-0.5+6.5V
Note:
The modules may be destroyed if they are used beyond the absolute maximum ratings.
All voltage values are referenced to VSS = 0V.
4.2 Environmental Condition
Table 4
Storage
Temperature
(Tstg)
Remark
Item
Operating
Temperature
(Topr)
Min.Max.Min.Max.
mbient Temperature
umidity
-10qC+50qC-20qC+65qC
95% max. RH for Ta d 40qC
Dry
no condensation
< 95% RH for Ta > 40qC
ibration (IEC 68-2-6)
cells must be mounted
on a suitable connecto
Shock (IEC 68-2-27)
alf-sine pulse shape
Frequency: 10 a 55 Hz
Amplitude: 0.75 mm
Duration: 20 cycles in each direction.
Pulse duration : 11 ms
Peak acceleration: 981 m/s2= 100g
3 directions
3 directions
Number of shocks : 3 shocks in 3
mutually perpendicular axes.
5. Electrical Specifications
5.1 Typical Electrical Characteristics
At Ta = 25 qC, VDD = 3Vr5%, VSS=0V.
Parameter Symbol ConditionsMin.Typ. Max.Unit
Operating voltage
VDD-VSS2.853.03.15V
(Logic)
Operating voltage for
VLCD-VSSNote 1 5.05.35.6V
LCD (built-in)
Input signal voltage low
Vil 0-0.3 VDDV
(SDA, SCL)
Input signal voltage high
Vih 0.7 VDD-5.5V
(SDA, SCL)
DD
Supply voltage of White
VLED05Forward current
LED05 backlight
Table 5
Character mode,
VDD =3.0V
Checker board
mode,
VDD =3.0V
=15 mA
Number of LED
dies
=1x1
=1.
VL-FS-COG-BTHQ21605-01 REV. A
(BTHQ 21605V-FSTF-I2C-COG)
OCT/2003
PAGE 9 OF 12
-0.170.26mA Operating supply currentI
-0.180.27mA
3.84.04.2V
Note (1) : There is tolerance in optimum LCD driving voltage during production and it will be within the
specified range.
5.2 Timing Specifications
VL-FS-COG-BTHQ21605-01 REV. A
(BTHQ 21605V-FSTF-I2C-COG)
OCT/2003
PAGE 10 OF 12
Ta = -10 qC to +50 qC, VDD =1.8 ~ 5.5V, VSS=0V; V
= 2.2V to 6.5V.
LCD
Refer to Fig. 6, I2C Bus Timing Diagram of ‘PHILIPS’ PCF2119.
Table 6
ParametersSymbolMin. Typ. Max.Unit
LCD frame frequency (internal clock)
f
FR
4581147Hz
(note 1)
Oscillator frequency(not available at any pin) f
External clock frequency f
Oscillator start-up time after power-down t
OSC
OSC(ext)
OSCST
140250450kHz
tbf-450kHz
-200300
Timing characteristics: I2C-bus interface;
(note 2)
SCL clock frequency f
SCL clock LOW period t
SCL clock HIGH period t
Data set-up time t
Data hold time t
SCL and SDA rise time t
SCL and SDA fall time t
Capacitive bus line load C
Set-up time for a repeated START condition t
START condition hold time t
Set-up time for STOP condition t
Tolerable spike width on bus t
SCL
LOW
HIGH
SU;DAT
HD;DAT
r
f
B
SU;STA
HD;STA
SU;STO
SW
--400kHz
1.3--
0.6--
100--ns
0- -ns
--300ns
--300ns
400pF
0.6--
0.6--
0.6--
--50ns
Ps
Ps
Ps
Ps
Ps
Ps
Notes :
1 VDD=5.0V.
2. All timing values are valid within the operating supply voltage and ambient
temperature range and are referenced to VIL and VIH with an input voltage swing to VSS
to VDD.
VL-FS-COG-BTHQ21605-01 REV. A
(BTHQ 21605V-FSTF-I2C-COG)
OCT/2003
PAGE 11 OF 12
Figure 6: I2C Bus Timing Diagram of ‘PHILIPS’ PCF2119.
6.Character Set ‘R’ in CGROM
VL-FS-COG-BTHQ21605-01 REV. A
(BTHQ 21605V-FSTF-I2C-COG)
OCT/2003
PAGE 12 OF 12
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