Specification for
BTHQ 128064AVE-FETF-06-LEDWHITE-COG
Version November 2003
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 2 OF 15
DOCUMENT REVISION HISTORY 1:
DOCUMENT
REVISION
DATE DESCRIPTION CHANGED
BY
CHECKED
BY
FROM TO
A 2003.11.28 First Release. SUNNY LEE PRITT LEE
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 3 OF 15
CONTENTS
Page No.
1. GENERAL DESCRIPTION 4
2. MECHANICAL SPECIFICATIONS 4
3. INTERFACE SIGNALS 7
4. ABSOLUTE MAXIMUM RATINGS 9
4.1
4.2 ENVIRONMENTAL CONDITION 9
5. ELECTRICAL SPECIFICATIONS 10
5.1 TYPICAL ELECTRICAL CHARACTERISTICS 10
5.2 TIMING SPECIFICATIONS 11
5.3 INSTRUCTION SET 14
6. REFERENCE APPLICATION CIRCUIT (8080) EXAMPLE 15
ELECTRICAL MAXIMUM RATINGS (Ta=25°C)
9
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 4 OF 15
Specification
of
LCD Module Type
Model No.: COG-BTHQ12864-03
1. General Description
• 128 x 64 dots FSTN Positive Black & White Transflective Dot Matrix LCD Module.
• Viewing Angle: 6 o’clock direction.
• Driving duty: 1/65 duty, 1/7 bias.
• ‘Epson’ SED1565D0B (COG) Dot Matrix LCD Driver.
• 8080 Series MPU interface (default).
• 6800 Series MPU interface (Optional).
• FPC.
• White LED05 backlight.
2. Mechanical Specifications
The mechanical detail is shown in Fig. 1 and summarized in Table 1 below.
Table 1
Parameter Specifications Unit
Outline dimensions 89.7(W) x 49.8(H) x 6.0(D)(Exclude FPC & gate)
89.7(W) x 149.8(H) x 6.0(D)(Include FPC. Exclude gate)
89.7(W) x 150.0(H) x 6.0(D)(Include FPC and gate)
View area 66.8 MIN.(W) x 35.5 MIN. (H) mm
Active area 63.985(W) x 31.985(H) mm
Display format 128 (W) x 64(H) dots
Dot size 0.485(W) x 0.485(H) mm
Dot spacing 0.015(W) x 0.015(H) mm
Dot pitch 0.500(W) x 0.500(H) mm
Weight: TBD grams
mm
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 5 OF 15
Figure 1: Module Specification
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 6 OF 15
COG-BTHQ12864-03
VDD
GND
/CS 1
/RE S
A0
/WR
/RD
D0 ~
D7
VOUT
CAP3-
CAP1+
CAP1 -
CAP2-
CAP2+
V1
V2
V3
32
8
128 X 64 DOTS
128
DOT MATRIX
LCD DRIVER
'EPSON'
SED1565D0B
(COG)
32
V4
V5
VR
C86
IRS
+
-
WHITE LED05 BACKLIGHT
Figure 2: Block Diagram
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 7 OF 15
3. Interface signals
Table 2 (a)
Pin
Symbol Description
No.
1 NC No connection.
2 /CS1 This is the chip select signal. When /CS1 = “L”, then the chip select become active, and
data/command I/O is enabled.
3 /RES When /RES is set to “L,” the settings are initialized. The reset operation is performed by
the /RES signal level.
4 A0 This is connected to the least significant bit of the normal MPU address bus, and it
determines whether the data bits are data or a command.
A0 = “H”: Indicates that D0 to D7 are display data.
A0 = “L”: Indicates that D0 to D7 are control data.
5 /WR When connected to an 8080 MPU, this is active LOW. This terminal connects to the
8080 MPU /WR signal. The signals on the data bus are latched at the rising edge of the
/WR signal.
6 /RD When connected to an 8080 MPU, this is active LOW.
This pin is connected to the /RD signal of the 8080 MPU, and the SED1565 series data
bus is in an output status when this signal is “L”.
7 D0
8 D1
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit 8 standard
MPU data bus.
9 D2
10 D3
11 D4
12 D5
13 D6
14 D7
15 VDD Power supply. Shared with the MPU power supply terminal VCC.
16 GND Connection with ground.
17 VOUT DC/DC voltage converter. Connect a capacitor between this terminal and
GND .
18 CAP3- DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+
terminal.
19 CAP1+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1-
terminal.
20 CAP1- DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+
terminal.
21 CAP2- DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+
terminal.
22 CAP2+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2-
terminal.
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 8 OF 15
Table 2 (b)
Pin
Symbol Description
No.
23~27V1,V2,
V3,V4,
V5
This is a multi-level power supply for the liquid crystal drive. The voltage applied is
determined by the liquid crystal cell, and is changed through the use of a resistive
voltage divided or through changing the impedance using an op. amp. Voltage levels
are determined based on VDD, and must maintain the relative magnitudes shown
below.
VDD (= V0) ЊV1ЊV2ЊV3 ЊV4ЊV5
Master operation: When the power supply turns ON, the internal power supply
circuits produce the V1 to V4 voltages shown below. The voltage settings are selected
using the LCD bias set command.
For 1/7 bias: V1=(1/7)xV5, V2=(2/7)xV5, V3=(5/7)xV5, V4=(6/7)xV5.
28 VR Output voltage regulator terminal. Provides the voltage between VDD and V5
through a resistive voltage divider.
These are only enabled when the V5 voltage regulator internal resistors are not used
(IRS = “L”).
These cannot be used when the V5 voltage regulator internal resistors are used (IRS =
“H”).
30 IRS This terminal selects the resistors for the V5 voltage level adjustment.
IRS = “H”: Use the internal resistors
IRS = “L”: Do not use the internal resistors. The V5 voltage level is regulated by an
external resistive voltage divider attached to the VR terminal.
This pin is enabled only when the master operation mode is selected.
It is fixed to either “H” or “L” when the slave operation mode is selected.
+ Anode of backlight
- Cathode of backlight.
VL-FS-COG-BTHQ12864-03 REV. A
A
H
V
H
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 9 OF 15
4. Absolute Maximum Ratings
4.1 Electrical Maximum Ratings (Ta = 25 ºC)
Table 3
Parameter Symbol Min. Max. Unit
Power Supply voltage (Logic)VDD-GND
-0.3+7.0V
=VDD-VSS
Power supply voltage
(VDD standard)
Power Supply voltage(V5,VOUT)
-7.0 +0.3 V
GND(=VSS2)
With Triple set-up -6.0 +0.3 V
With Quad step-up
-4.5 +0.3 V
V5,VOUT -18.0 +0.3 V
(VDD standard)
Power Supply voltage(V1~V4)
V1,V2,V3,V4 V5 +0.3 V
(VDD standard)
Input voltageVin-0.3VDD+0.3V
Note: 1.)The modules may be destroyed if they are used beyond the absolute maximum ratings.
2.) Insure that the voltage levels of V1, V2, V3, and V4 are always such that
VDD ЊV1 ЊV2 ЊV3 ЊV4 ЊV5.
3.) The VSS2,V1 to V5 and VOUT are relative to VDD=0V reference.
4.2 Environmental Condition
Table 4
Item
Operating
Temperature
(Topr)
Storage
Temperature
(Tstg)
Min. Max. Min. Max.
mbient Temperature
umidity
-20°C +70°C -30°C +80°C
95% max. RH for Ta ≤ 40°C
Dry
no condensation
< 95% RH for Ta > 40°C
ibration (IEC 68-2-6)
cells must be mounted
on a suitable connector
Shock (IEC 68-2-27)
alf-sine pulse shape
Frequency: 10 ∼ 55 Hz
Amplitude: 0.75 mm
Duration: 20 cycles in each direction.
Pulse duration: 11 ms
Peak acceleration: 981 m/s2= 100g
3 directions
3 directions
Number of shocks: 3 shocks in 3
mutually perpendicular axes.
Remark
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 10 OF 15
5. Electrical Specifications
5.1 Typical Electrical Characteristics
At Ta = 25 °C, VDD = 5V±5%, GND =0V.
Table 5
Parameter Symbol Conditions Min. Typ. Max. Unit
Supply voltage
VDD-GND 4.75 5.0 5.25 V
(Logic)
Supply voltage
(LCD)
Low-level input
VLCD
=VDD-V5
V
GND - 0.2xVDD V
ILC
VDD = +5.0V,
Note (1)
8.6 8.9 9.2 V
signal voltage
High-level input
V
0.8xVDD - VDD V
IHC
signal voltage
(Logic & LCD)
IDD
VDD = 5V,
Character mode
VDD = 5V,
- 0.5 0.7 mA Supply Current
- 1.1 1.3 mA
Checker board
mode
Supply voltage of
white LED05
VLED05 Forward current
4.8 5.0 5.2 V
=45mA
backlight
Number of LED
dies
=1x3=3
Note (1): There is tolerance in optimum LCD driving voltage during production and it will be within
the specified range.
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 11 OF 15
5.2 Timing Specifications
Reset Timing
At Ta = -20 °°°°C to +70 °°°°C, VDD = +5.0V±±±±5%, GND = 0V.
Table 6
Note: All timing is specified with 20% and 80% of VDD as the standard.
/RES
Figure 3:Reset Timing
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 12 OF 15
System Bus Read/Write Characteristics (8080 Series MPU)
At Ta = -20 °°°°C to +70 °°°°C, VDD = +5.0V±±±±5%, GND = 0V.
Table 7
A0
/CS1
Figure 4: MPU bus read / write timing diagram (80 family MPU)
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 13 OF 15
System Bus Read/Write Characteristics (6800 Series MPU)
At Ta = -20 °°°°C to +70 °°°°C, VDD = +5.0V±±±±5%, VSS = 0V.
Table 8
/CS1
Figure 5: MPU bus read / write timing diagram (68 family MPU)
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 14 OF 15
5.3 Instruction Set
Table 8
VL-FS-COG-BTHQ12864-03 REV. A
(BTHQ 128064AVE-FETF-06-LEDWHITE-COG)
NOV/2003
PAGE 15 OF 15
6. Reference Application Circuit (8080) Example
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