avia HX711 DATASHEET

24-Bit Analog-to-Digital Converter (ADC) for Weigh Scales

DESCRIPTION

Based on Avia Semiconductor’s patented
technology, HX711 is a precision 24-bit analog­to-digital converter (ADC) designed for weigh
scales and industrial control applications to
interface directly with a bridge sensor.

The input multiplexer selects either Channel A
or B differential input to the low-noise
programmable gain amplifier (PGA). Channel A
can be programmed with a gain of 128 or 64,
corresponding to a full-scale differential input
voltage of ±20mV or ±40mV respectively, when
a 5V supply is connected to AVDD analog power
supply pin. Channel B has a fixed gain of 32. On­chip power supply regulator eliminates the need
for an external supply regulator to provide analog
power for the ADC and the sensor. Clock input is
flexible. It can be from an external clock source, a
crystal, or the on-chip oscillator that does not
require any external component. On-chip power­on-reset circuitry simplifies digital interface
initialization.

There is no programming needed for the
internal registers. All controls to the HX711 are
through the pins.

HX711

FEATURES

• Two selectable differential input channels

• On-chip active low noise PGA with selectable gain
of 32, 64 and 128

• On-chip power supply regulator for load-cell and
ADC analog power supply

• On-chip oscillator requiring no external
component with optional external crystal

• On-chip power-on-reset

• Simple digital control and serial interface:

pin-driven controls, no programming needed

• Selectable 10SPS or 80SPS output data rate

• Simultaneous 50 and 60Hz supply rejection

• Current consumption including on-chip analog
power supply regulator:

normal operation < 1.5mA, power down < 1uA

• Operation supply voltage range: 2.6 ~ 5.5V

• Operation temperature range: -40 ~ +85℃

• 16 pin SOP-16 package

APPLICATIONS

• Weigh Scales

• Industrial Process Control

V

Load cell

0.1uF

10uF

AVDD

INA+
INA-

INB+

INB-

VBG

AVDD

Input
MUX

Bandgap Reference

R2R

1

VFB

Analog Supply Regulator

Gain = 32, 64, 128

AGND

PGA

S8550

BASE VSUP DVDD

24-bit Σ∆

ADC

Internal

Oscillator

XI XO

Fig. 1 Typical weigh scale application block diagram

TEL: [phone] (P. R. China)
EMAIL: [email protected]

V

SUP

Digital

Interface

HX711

2.7~5.5V

DOUT
PD_SCK

RATE

AVIA SEMICONDUCTOR

To/From

MCU

Pin Description

HX711

Regulator Power

Regulator Control Output

Analog Power AVDD

Regulator Control Input

Anal og Ground

Reference Bypass

Ch. A Negative Input

Ch. A Positive Input

VSUP
BASE

VFB

AGND

VBG

INNA

INPA

16

1

15

2

14

3

13

4

12

5

11

6

10

7
8

DVDD
RATE
XI
XO
DOUT
PD_SCK
INPB

9

INNB

Digital Power
Output Data Rate Control Input
Crystal I/O and External Clock Input
Crystal I/O
Serial Data Output
Power Down and Serial Clock Input
Ch. B Positive Input
Ch. B Negative Input

SOP-16L Package

Pin # Name Function Description

1 VSUP Power Regulator supply: 2.7 ~ 5.5V
2 BASE Analog Output

Regulator control output（NC when not used）
3 AVDD Power Analog supply: 2.6 ~ 5.5V
4 VFB Analog Input

Regulator control input（connect to AGND when not used）
5 AGND Ground Analog Ground
6 VBG Analog Output Reference bypass output
7 INA- Analog Input Channel A negative input
8 INA+ Analog Input Channel A positive input
9 INB- Analog Input Chan nel B negative input

10 INB+ Analog Input Channel B positive input
11 PD_SCK Digital Input Power down control (high active) and serial clock input
12 DOUT Digital Output Serial data output
13 XO Digital I/O

Crystal I/O (NC when not used）

14 XI Digital Input Cryst al I/O or external clock input, 0: use on-chip oscillator
15 RATE Digital Input Output data rate control, 0: 10Hz; 1: 80Hz
16 DVDD Power Digital supply: 2.6 ~ 5.5V

AVIA SEMICONDUCTOR

Table 1 Pin Description

2

HX711

KEY ELECTRICAL CHARACTERISTICS

Parameter

Full scale differential
input range V(inp)-V(inn)

Common mode input AGND+1.2

Output data rate

Output data coding 2’s complement 800000

Output settling time

Input offset drift

Input noise

Temperature drift

Input common mode
rejection

Internal Oscillator, RATE = 0
Internal Oscillator, RATE =
DVDD
Crystal or external clock,
RATE = 0
Crystal or external clock,
RATE = DVDD

RATE = 0

(1)

RATE = DVDD
Gain = 128
Gain = 64

Gain = 128，RATE = 0
Gain = 128
Input offset（Gain = 128）
Gain（Gain = 128）

Gain = 128

Notes

，RATE = DVDD

，

RATE = 0

MIN

TYP

±0.5(AVDD/GAIN)

10

80

f

/1,105,920

clk

f

/138,240

clk

400

50

0.2

0.4
50
90
±6
±5

100

MAX UNIT

AVDD-1.3 V

7FFFFF HEX

V

Hz

ms

mV

nV(rms)

nV/℃

ppm/℃

dB

Power supply rejection
Reference bypass

）

（

V

BG

Crystal or external clock
frequency

Power supply voltage

Analog supply current
(including regulator)

Digital supply current

（1）

Settling time refers to the time from power up, reset, input channel change and gain change

Gain = 128

1 11.0592 20 MHz
DVDD 2.6
AVDD，VSUP

Normal
Power down
Normal

Power down

to valid stable output data.

AVIA SEMICONDUCTOR

，RATE = 0

2.6

Table 2 Key Electrical Characteristics

100

1.25

1400

0.3

100

0.2

5.5 V

5.5

dB

V

µA

µA

3

Analog Inputs

HX711

Channel A differential input is designed to
interface directly with a bridge sensor’s
differential output. It can be programmed with a
gain of 128 or 64. The large gains are needed to
accommodate the small output signal from the
sensor. When 5V supply is used at the AVDD pin,
these gains correspond to a full-scale differential
input voltage of ±20mV or ±40mV respectively.

Channel B differential input has a fixed gain of

32. The full-scale input voltage range is ±80mV,
when 5V supply is used at the AVDD pin.

Power Supply Options

Digital power supply (DVDD) should be the
same power supply as the MCU power supply.

When using internal analog supply regulator,
the dropout voltage of the regulator depends on
the external transistor used. The output voltage is
equal to V

AVDD=VBG

*(R1+R2)/ R1 (Fig. 1). This
voltage should be designed with a minimum of
100mV below VSUP voltage.

If the on-chip analog supply regulator is not
used, the VSUP pin should be connected to either
AVDD or DVDD, depending on which voltage is
higher. Pin VFB should be connected to Ground
and pin BASE becomes NC. The external 0.1uF
bypass capacitor shown on Fig. 1 at the VBG
output pin is then not needed.

Clock Source Options

By connecting pin XI to Ground, the on-chip
oscillator is activated. The nominal output data
rate when using the internal oscillator is 10
(RATE=0) or 80SPS (RATE=1).

If accurate output data rate is needed, crystal or
external reference clock can be used. A crystal
can be directly connected across XI and XO pins.
An external clock can be connected to XI pin,
through a 20pF ac coupled capacitor. This
external clock is not required to be a square wave.
It can come directly from the crystal output pin of
the MCU chip, with amplitude as low as 150 mV.

Output Data Rate and Format

When using the on-chip oscillator, output data
rate is typically 10 (RATE=0) or 80SPS
(RATE=1).

When using external clock or crystal, output
data rate is directly proportional to the clock or
crystal frequency. Using 11.0592MHz clock or
crystal results in an accurate 10 (RTE=0) or
80SPS (RATE=1) output data rate.

The output 24 bits of data is in 2’s complement
format. When input differential signal goes out of
the 24 bit range, the output data will be saturated
at 800000h (MIN) or 7FFFFFh (MAX), until the
input signal comes back to the input range.

Serial Interface

Pin PD_SCK and DOUT are used for data
retrieval, input selection, gain selection and power
down controls.

When output data is not ready for retrieval,
digital output pin DOUT is high. Serial clock
input PD_SCK should be low. When DOUT goes
to low, it indicates data is ready for retrieval. By
applying 25~27 positive clock pulses at the
PD_SCK pin, data is shifted out from the DOUT
output pin. Each PD_SCK pulse shifts out one bit,
starting with the MSB bit first, until all 24 bits are
shifted out. The 25
pull DOUT pin back to high (Fig.2).

Input and gain selection is controlled by the
number of the input PD_SCK pulses (Table 3).
PD_SCK clock pulses should not be less than 25
or more than 27 within one conversion period, to
avoid causing serial communication error.

PD_SCK Pulses

25 A 128

26 B 32

27 A 64

Table 3 Input Channel and Gain Selection

th

pulse at PD_SCK input will

Input

channel

Gain

When using a crystal or an external clock, the

internal oscillator is automatically powered down.

AVIA SEMICONDUCTOR

4

HX711

Current Output Data

DOUT

PD_SCK 12

PD_SCK

PD_SCK

MSB

T

T

1

2

12 24 25

12 24 25

One conversion period

T

3

34

T

4

34

34

LSB

24 25

26

26 27

Next Output Data

Next Conversion

Next Conversion

Next Conversion

：CH.A, Gain:128

：CH.B, Gain:32

：CH.B, Gain:64

Fig.2 Data output, input and gain selecti o n timing and contro l

Symbol Note MIN TYP MAX Unit

T1 DOUT falling edge to PD_SCK rising edge 0.1 　µs
T2 PD_SCK rising edge to DOUT data ready 0.1

µ

s

T3 PD_SCK high time 0.2 1 50 　µs
T4 PD_SCK low time 0.2 1

µ

s

Reset and Power-Down

When chip is powered up, on-chip power on

rest circuitry will reset the chip.

Pin PD_SCK input is used to power down the
HX711. When PD_SCK Input is low, chip is in
normal working mode.

Power down:

PD_SCK

60µs

Fig.3 Power down control

When PD_SCK pin changes from low to high
and stays at high for longer than 60
enters power down mode (Fig.3). When internal
regulator is used for HX711 and the external
transducer, both HX711 and the transducer will be

Power down

Normal

µs

, HX711

powered down. When PD_SCK returns to low,
chip will reset and enter normal operation mode.

After a reset or power-down event, input

selection is default to Channel A with a gain of

128.

Application Example

Fig.1 is a typical weigh scale application using
HX711. It uses on-chip oscillator (XI=0), 10Hz
output data rate (RATE=0). A Single power
supply （2.7～5.5V） comes directly from MCU
power supply. Channel B can be used for battery
level detection. The related circuitry is not shown
on Fig. 1.

AVIA SEMICONDUCTOR

5

HX711

Reference PCB Board (Single Layer)

Fig.4 Reference PCB board schematic

AVIA SEMICONDUCTOR

Fig.5 Reference PCB board layout

6

HX711

Reference Driver (Assembly)

/*------------------------------------------------------------------­Call from ASM: LCALL ReaAD
Call from C: extern unsigned long ReadAD(void);
.
.
unsigned long data;
data=ReadAD();
.
.

----------------------------------------------------------------------*/
PUBLIC ReadAD
HX711ROM segment code
rseg HX711ROM

sbit ADDO = P1.5;
sbit ADSK = P0.0;
/*-------------------------------------------------­ OUT: R4, R5, R6, R7 R7=>LSB

---------------------------------------------------*/
ReadAD:
CLR ADSK //AD Enable（PD_SCK set low）
SETB ADDO //Enable 51CPU I/0
JB ADDO,$ //AD conversion completed?
MOV R4,#24
ShiftOut:
SETB ADSK //PD_SCK set high（positive pulse）
NOP
CLR ADSK //PD_SCK set low
MOV C,ADDO //read on bit
XCH A,R7 //move data
RLC A
XCH A,R7
XCH A,R6
RLC A
XCH A,R6
XCH A,R5
RLC A
XCH A,R5
DJNZ R4,ShiftOut //moved 24BIT?
SETB ADSK
NOP
CLR ADSK
RET

END

AVIA SEMICONDUCTOR

7

HX711

Reference Driver（C）

//-------------------------------------------------------------------

sbit ADDO = P1^5;
sbit ADSK = P0^0;
unsigned long ReadCount(void){
unsigned long Count;
unsigned char i;
ADDO=1;
ADSK=0;
Count=0;
while(ADDO);
for (i=0;i<24;i++){
ADSK=1;
Count=Count<<1;
ADSK=0;
if(ADDO) Count++;
}
ADSK=1;
Count=Count^0x800000;
ADSK=0;
return(Count);
}

AVIA SEMICONDUCTOR

8

Package Dimensions

6.20

6.00

5.80

HX711

10.10

9.90

9.70

4.10

3.90

3.70

MAX

Typ

MIN

Unit: mm

SOP-16L Package

1.27 0.48

0.39

1.60

1.20

AVIA SEMICONDUCTOR

9