Avago Technologies PEX 8605 User Manual

PEX8605

1 Introduction

This document is intended for systems design engineers incorporating the PEX8605 PCI Express switch into a system hardware design. It provides a handy list of basic design checks covering schematic and printed-circuit board (PCB) layout designs. Including these checks as part of your design review can help insure that important details are not overlooked when your design is committed to hardware, thereby improving your chances for a successful bring-up. In preparation for your design review, we also recommend that you check our website, www.plxtech.com, and download the most current technical specifications, errata, and related documentation. This document supersedes and replaces previously dated versions.

2 Schematic Design Checks

This section includes checks on basic elements of the circuit design, including schematic symbol, power supply, configuration straps, clocks, reset, configuration serial EEPROM, I2C, JTAG, GPIO, and other signals. All power and signal pins on the device are covered.

2.1 Schematic Symbol

For designers using ORCAD schematic capture tools, an ORCAD symbol library is available on the PLX website at www.plxtech.com. This library symbol is pre-checked by PLX engineers. For designers not using the PLX-supplied schematic symbol, we highly recommend double-checking your symbol’s signal pin names and numbers for accuracy before using the symbol in your schematic design.

2.2 Power Supply

2.2.1 Regulated DC Supply Voltages

The PEX8605 requires the following regulated DC voltages:

 Core Logic Supply: 1.0 Volts (0.95V – 1.10V) – Powers core logic, SerDes Digital, and PLL  IO Supply: 2.5 or 3.3 Volts (2.3V – 3.6V) - Powers external I/O, SerDes Analog

2.2.2 Power Supply Sequencing Requirements

The Core Logic and IO supplies can be sequenced in any order. No special hardware is required to control the order in which the power supply rails power up and down. It is recommended that both supplies be powered up or down together.

2.3 Power, Ground Pin Connections

Signal Name

Dual-Row QFN Pkg. Pin #

TQFP Package Pin #

Signal Type

Checked

Recommendations

IO Power Pins (2.5 or 3.3 V)

In the simplest applications, all pins in this group can be powered from a common 2.5 V or 3.3 V DC voltage source. All pins in this group must be at the same voltage. See the PEX8605 RDK schematic for a reference circuit, including recommended bypass cap network.PEX8605

PEX_VDDA_P0 PEX_VDDA_P1 PEX_VDDA_P2 PEX_VDDA_P3

B8 B13 B44 B50

14

26 101 114

APWR

YES NO

UNKNOWN

Power for SerDes Analog Circuits (4 Pins)

Power for these pins should be filtered from the main IO supply, VDD_IO. See the PEX8605 RDK schematic for a reference circuit.

Note: If stand-by power (D3cold) is implemented, power for these pins should be filtered from the auxiliary power supply, VAUX_IO.

VDD_IO

A30, A43, B3,

B31, B41

3, 4, 56, 70,

84, 92

IOPWR

YES NO

UNKNOWN

Power for Digital IO Circuits (5 Pins)

Main supply for digital IO circuits. Important Note: Data Sheet version 1.2 corrects

pins A26 and B19 as VAUX_IO. Designs powering VDD_IO and VAUX_IO supplies separately may be impacted by this change.

VAUX_IO

A18, A26, A64,

B19

33, 42, 49, 127

IOPWR

YES NO

UNKNOWN

Auxiliary Power Supply (4 Pins)

If stand-by power is implemented, this power supply should be derived from Vaux (3.3V). Otherwise, connect these pins to the VDD_IO supply.

Core Logic, SerDes, and PLL Power Pins

In the simplest applications, all 1.0 V supply pins can be powered from a common 1.0 V DC voltage source. See the PEX8605 RDK schematic for a reference circuit.

PEX_VDDD0_P0 PEX_VDDD0_P1 PEX_VDDD0_P2 PEX_VDDD0_P3 PEX_VDDD1_P0 PEX_VDDD1_P1 PEX_VDDD1_P2 PEX_VDDD1_P3

B7 B12 B45 B51

A7 A13 B46 B52

12

24 103 116

9

21 106 119

DPWR

YES NO

UNKNOWN

1.0 V Power for SerDes Digital Circuits (8

Pins)

Power for these pins should be filtered from the main 1.0 V supply, VDD_CORE. See the PEX 8603 RDK schematic for a reference circuit.

Note: If stand-by power (D3cold) is implemented, power for these pins should be filtered from the auxiliary power 1.0V supply, VAUX_CORE.

PEX8605

Signal Name

Dual-Row QFN Pkg. Pin #

TQFP Package Pin #

Signal Type

Checked

Recommendations

PLL_AVDD

A31

58

PLLPWR

YES NO

UNKNOWN

1.0 V Power for PLL Analog Circuits

This pin supplies power to the internal PLL. As such it is sensitive to noise, and should be filtered from the main 1.0V supply (VDD_CORE) to reduce noise. See the RDK schematic for an

example filter circuit.

VDD_CORE

A29, A37, A46,

A50, B26, B43

54, 57, 72, 89,

98, 99

CPWR

YES NO

UNKNOWN

1.0 V Power for Core Digital Logic (6 Pins)

Main 1.0 V supply for digital core logic.

VAUX_CORE

A10, A57, B49

15, 16, 112,

113

CPWR

YES NO

UNKNOWN

1.0 V Auxiliary Core Logic Power Supply

(QFN: 3 Pins, TQFP: 4 pins)

If stand-by power is implemented, this power supply should be regulated from Vaux (3.3V). Otherwise, connect these pins to the VDD_CORE supply.

Ground Pins (20 Pins and Center Pad)

Connect all Ground pins below directly to Ground (plane).

PLL_AGND

B27

59

GND

YES NO

UNKNOWN

Connect to Ground

PEX_VSSA_P0 PEX_VSSA_P1 PEX_VSSA_P2 PEX_VSSA_P3

A9 A15 A51 A58

13

25 102 115

GND

YES NO

UNKNOWN

Connect to Ground (4 Pins)

PEX_VSSD0_P0 PEX_VSSD0_P1 PEX_VSSD0_P2 PEX_VSSD0_P3 PEX_VSSD1_P0 PEX_VSSD1_P1 PEX_VSSD1_P2 PEX_VSSD1_P3

B5 A12 A54 B53

B4

B9 B48 B54

8

20 107 120

5

17 110 123

GND

YES NO

UNKNOWN

Connect to Ground (8 Pins)

VSS

A25, A32, A56, A63, B17, B18,

B20

37, 40, 44, 47,

61, 111, 124

GND

YES NO

UNKNOWN

Ground (7 Pins)

Connect to Ground

GROUND (VSS)

CENTER_PAD

GND

YES NO

UNKNOWN

Connect to Ground

See package drawing for pad dimensions.

2.4 Clocks

REFCLK Source

Signal Type

Checked

Requirements

External REFCLK Clock Transmitter

External-CML

YES NO

UNKNOWN

Frequency Tolerance: ± 300 ppm, max. 33 Ω series (in-line) and 49 Ω shunt (to GND) required on each differential

signal, near the clock source.

Signal Name

Dual-Row QFN Pkg. Pin #

TQFP Package Pin #

Signal Type

Checked

Recommendations

PEX_REFCLKn , PEX_REFCLKp

B24

A27

52 51

CML Input

YES

NO

UNKNOWN

100 MHz PCI Express Reference Clock input pair.

Signal Name

Dual-Row QFN Pkg. Pin #

TQFP Package Pin #

Signal Type

Checked

Recommendations

PEX_PERST#

B15

32

I

YES

NO

UNKNOWN

PCI Express Reset

Used to initiate a fundamental reset. This reset is propagated to all downstream ports. Adapter card designs connect this pin directly to the PCI Express slot PERST# pin. PEX_PERST# should remain asserted for 100 ms after power supplies and clocks are stable.

Signal Name

Dual-Row QFN Pkg. Pin #

TQFP Package Pin #

Signal Type

Checked

Recommendations

STRAP_DEBUG_SEL#

C4

30

I

PU

YES

NO

UNKNOWN

Factory Test Only

This signal can be left unconnected in normal applications. If this ball is connected to a board circuit trace, it must be externally pulled up to VDD_IO.

STRAP_FAST_BRINGUP#

A40

78

I

PU

YES NO

UNKNOWN

Factory Test Only

This signal can be left unconnected in normal applications. If this ball is connected to a board circuit trace, it must be externally pulled up to VDD_IO.

2.4.1 Clock Source and Line Termination

2.4.2 Clock Input Pins

PEX8605

2.5 Reset

2.6 Configuration Straps

These pins should be pulled High (to VDD_IO) or Low (to Ground), through 4.7K-10K ohms, as indicated.

Avago Technologies PEX 8605 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual