Avago Technologies LSI8751D User Manual

TECHNICAL

MANUAL

LSI53C875/875E
PCI to Ultra SCSI
I/O Processor

Version 4.2

April 2003

®

DB14-000165-01

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000165-01, Sixth Edition (April 2003)
This document describes the LSI Logic LSI53C875/875E PCI to Ultra SCSI I/O
Processor and will remain the official reference source for all revisions/releases
of this product until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Copyright © 1998–2001/2003 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design, TolerANT, SDMS, and SCRIPTS are registered
trademarks or trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.

ii

Audience

Organization

Preface

This book is the primary reference and technical manual for the LSI Logic
LSI53C875/875E PCI to Ultra SCSI I/O Processor.It contains a complete
functional description for the LSI53C875/875E and includes complete
physical and electrical specifications for the LSI53C875/875E.

This technical manual is intended for system designers and programmers
who are using this device to design a SCSI port for PCI-based personal
computers, workstations, or embedded applications.

This document has the following chapters and appendixes:

• Chapter 1, General Description, includes general information about

the LSI53C875 and other members of the LSI53C8XX family of PCI
to SCSI I/O Processors.

• Chapter 2, Functional Description, describes the main functional

areas of the chip in more detail, including the interfaces to the SCSI
bus.

• Chapter 3, PCI Functional Description, describes the chip’s

connection to the PCI bus, including the PCI commands and
configuration registers supported.

• Chapter 4, Signal Descriptions, contains the pin diagrams and

definitions of each signal.

• Chapter 5, SCSI Operating Registers, describes each bit in the

operating registers, organized by address.

Preface iii

• Chapter 6, Instruction Set of the I/O Processor, defines all of the

• Chapter 7, Instruction Set of the I/O Processor, contains the

• Appendix A, Register Summary, is a register summary.

• Appendix B, External Memory Interface Diagram Examples,

Related Publications

For background information, please contact:

ANSI

11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2); X3.253 (SCSI-3
Parallel Interface)

SCSI SCRIPTS instructions that are supported by the LSI53C875.

electrical characteristics and AC timings for the chip.

contains several example interface drawings to connect the
LSI53C875 to an external ROM.

ENDL Publications

14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI

Tutor

Prentice Hall

113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding

the Small Computer System Interface

iv Preface

LSI Logic World Wide Web Home Page

www.lsilogic.com
SCSI SCRIPTS™ Processors Programming Guide, Version 2.2,

Order Number S14044.A

PCI Special Interest Group

2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]

Conventions Used in This Manual

The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision Record

Revision Date Remarks

1.0 6/95 Revision 1.0

2.0 3/96 Revision 2.0. Fast-20 changed to Ultra SCSI throughout.

3.0 9/96 Revision 3.0. Minor copy changes throughout.

4.0 2/98 Revision 4.0. Minor copy changes throughout

4.1 3/01 Product names changed from SYM to LSI.

4.2 4/03 Revision 4.2. Correct V

Preface v

-S in Table 4.3

DD

vi Preface

Contents

Chapter 1 General Description

1.1 Package and Feature Options 1-4

1.2 Benefits of Ultra SCSI 1-4

1.3 TolerANT®Technology 1-5

1.4 LSI53C875 Benefits Summary 1-6

1.4.1 SCSI Performance 1-6

1.4.2 PCI Performance 1-7

1.4.3 Integration 1-7

1.4.4 Ease of Use 1-7

1.4.5 Flexibility 1-8

1.4.6 Reliability 1-9

1.4.7 Testability 1-9

Chapter 2 Functional Description

2.1 SCSI Functional Description 2-1

2.1.1 SCSI Core 2-1

2.1.2 DMA Core 2-2

2.1.3 SCRIPTS Processor 2-2

2.1.4 Internal SCRIPTS RAM 2-3

2.1.5 SDMS Software: The Total SCSI Solution 2-3

2.2 Designing an Ultra SCSI System 2-4

2.2.1 Using the SCSI Clock Doubler 2-4

2.3 Prefetching SCRIPTS Instructions 2-5

2.3.1 Opcode Fetch Burst Capability 2-6

2.4 External Memory Interface 2-6

2.5 PCI Cache Mode 2-8

2.5.1 Load/Store Instructions 2-8

2.5.2 3.3 V/5 V PCI Interface 2-9

2.5.3 Additional Access to General Purpose Pins 2-9

Contents vii

2.5.4 JTAG Boundary Scan Testing 2-10

2.5.5 Big and Little Endian Support 2-10

2.5.6 Loopback Mode 2-12

2.5.7 Parity Options 2-12

2.5.8 DMA FIFO 2-15

2.5.9 SCSI Bus Interface 2-19

2.5.10 Select/Reselect During Selection/Reselection 2-25

2.5.11 Synchronous Operation 2-25

2.5.12 Ultra SCSI Synchronous Data Transfers 2-27

2.5.13 Interrupt Handling 2-28

2.5.14 Chained Block Moves 2-34

2.6 Power Management 2-38

2.6.1 Power State D0 2-38

2.6.2 Power State D3 2-39

Chapter 3 PCI Functional Description

3.1 PCI Addressing 3-1

3.1.1 PCI Bus Commands and Functions Supported 3-2

3.2 PCI Cache Mode 3-4

3.2.1 Support for PCI Cache Line Size Register 3-4

3.2.2 Selection of Cache Line Size 3-5

3.2.3 Alignment 3-5

3.2.4 Memory Move Misalignment 3-6

3.2.5 Memory Write and Invalidate Command 3-6

3.2.6 Memory Read Line Command 3-8

3.2.7 Memory Read Multiple Command 3-9

3.3 Configuration Registers 3-11

Chapter 4 Signal Descriptions

4.1 MAD Bus Programming 4-22

Chapter 5 SCSI Operating Registers

Chapter 6 Instruction Set of the I/O Processor

6.1 SCSI SCRIPTS 6-1

6.1.1 Sample Operation 6-3

viii Contents

6.2 Block Move Instructions 6-5

6.2.1 First Dword 6-5

6.2.2 Second Dword 6-12

6.3 I/O Instruction 6-12

6.3.1 First Dword 6-12

6.3.2 Second Dword 6-21

6.4 Read/Write Instructions 6-21

6.4.1 First Dword 6-21

6.4.2 Second Dword 6-22

6.4.3 Read-Modify-Write Cycles 6-22

6.4.4 Move To/From SFBR Cycles 6-24

6.5 Transfer Control Instructions 6-26

6.5.1 First Dword 6-26

6.5.2 Second Dword 6-33

6.6 Memory Move Instructions 6-33

6.6.1 Read/Write System Memory from SCRIPTS 6-34

6.6.2 Second Dword 6-35

6.6.3 Third Dword 6-35

6.7 Load and Store Instructions 6-37

6.7.1 First Dword 6-38

6.7.2 Second Dword 6-39

Chapter 7 Instruction Set of the I/O Processor

7.1 DC Characteristics 7-1

7.2 TolerANT Technology Electrical Characteristics 7-7

7.3 AC Characteristics 7-10

7.4 PCI and External Memory Interface Timing Diagrams 7-13

7.4.1 Target Timing 7-15

7.4.2 Initiator Timing 7-24

7.4.3 External Memory Timing 7-32

7.5 PCI and External Memory Interface Timing 7-50

7.6 SCSI Timing Diagrams 7-51

7.7 Package Drawings 7-58

Appendix A Register Summary

Appendix B External Memory Interface Diagram Examples

Contents ix

Figures

Index

Customer Feedback

1.1 LSI53C875 External Memory Interface 1-2

1.2 LSI53C875 Chip Block Diagram 1-3

2.1 DMA FIFO Sections 2-15

2.2 LSI53C875 Host Interface Data Paths 2-16

2.3 Differential Wiring Diagram 2-22

2.4 Regulated Termination 2-24

2.5 Determining the Synchronous Transfer Rate 2-26

2.6 Block Move and Chained Block Move Instructions 2-35

4.1 LSI53C875 Pin Diagram 4-2

4.2 LSI53C875J Pin Diagram 4-3

4.3 LSI53C875N Pin Diagram 4-4

4.4 LSI53C875JB Pin Diagram (Top View) 4-5

4.5 LSI53C875 Functional Signal Grouping 4-9

6.1 SCRIPTS Overview 6-4

6.2 Block Move Instruction Register 6-7

6.3 I/O Instruction Register 6-15

6.4 Read/Write Instruction Register 6-23

6.5 Transfer Control Instructions 6-28

6.6 Memory Move Instruction 6-36

6.7 Load and Store Instruction Format 6-40

7.1 Rise and Fall Time Test Conditions 7-8

7.2 SCSI Input Filtering 7-8

7.3 Hysteresis of SCSI Receiver 7-9

7.4 Input Current as a Function of Input Voltage 7-9

7.5 Output Current as Function of Output Voltage 7-10

7.6 Clock Waveforms 7-11

7.7 Reset Input 7-12

7.8 Interrupt Output 7-13

7.9 PCI Configuration Register Read 7-15

7.10 PCI Configuration Register Write 7-16

7.11 Operating Register/SCRIPTS RAM Read 7-17

x Contents

7.12 Operating Register/SCRIPTS RAM Write 7-18

7.13 External Memory Read 7-20

7.14 External Memory Write 7-22

7.15 Opcode Fetch, Nonburst 7-24

7.16 Burst Opcode Fetch 7-25

7.17 Back-to-Back Read 7-26

7.18 Back-to-Back Write 7-27

7.19 Burst Read 7-28

7.20 Burst Write 7-30

7.21 Read Cycle, Normal/Fast Memory ( 64 Kbytes),
Single Byte Access 7-32

7.22 Write Cycle, Normal/Fast Memory ( 64 Kbytes),
Single Byte Access 7-34

7.23 Read Cycle, Normal/Fast Memory ( 64 Kbyte),
Multiple Byte Access 7-36

7.24 Write Cycle, Normal/Fast Memory ( 64 Kbyte),
Multiple Byte Access 7-38

7.25 Read Cycle, Slow Memory ( 64 Kbyte) 7-40

7.26 Write Cycle, Slow Memory ( 64 Kbyte) 7-42

7.27 Read Cycle, Normal/Fast Memory ( 64 Kbyte) 7-44

7.28 Write Cycle, Normal/Fast Memory ( 64 Kbyte) 7-45

7.29 Read Cycle, Slow Memory (£ 64 Kbyte) 7-46

7.30 Write Cycle, Slow Memory (£ 64 Kbyte) 7-48

7.31 Initiator Asynchronous Send 7-51

7.32 Initiator Asynchronous Receive 7-52

7.33 Target Asynchronous Send 7-52

7.34 Target Asynchronous Receive 7-53

7.35 Initiator and Target Synchronous Transfer 7-53

7.36 169-Pin PBGA (GV) Mechanical Drawing 7-58

7.37 160-pin PQFP (P3) Mechanical Drawing 7-59

B.1 64 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 256 Kbyte Interface with 150 ns Memory B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4

Contents xi

Tables

2.1 External Memory Support 2-7

2.2 Bits Used for Parity Control and Generation 2-13

2.3 SCSI Parity Control 2-14

2.4 SCSI Parity Errors and Interrupts 2-15

2.5 Differential Mode 2-20

3.1 PCI Bus Commands and Encoding Types 3-3

3.2 PCI Configuration Register Map 3-12

4.1 LSI53C875, LSI53C875J, LSI53C875E, and LSI53C875JE
Power and Ground Signals 4-7

4.2 LSI53C875N Power and Ground Signals 4-7

4.3 LSI53C875JB and LSI53C875JBE Power and
Ground Signals 4-8

4.4 System Signals 4-10

4.5 Address and Data Signals 4-11

4.6 Interface Control Signals 4-12

4.7 Arbitration Signals 4-13

4.8 Error Reporting Signals 4-14

4.9 SCSI SIgnals 4-15

4.10 Additional Interface Signals 4-18

4.11 External Memory Interface Signals 4-21

4.12 JTAG Signals (LSI53C875J/LSI53C875N/LSI53C875JB
Only) 4-22

4.13 Subsystem Data Configuration Table for the LSI53C875E
(PCI Rev ID 0x26) 4-23

4.14 Subsystem Data Configuration Table for the LSI53C875
(PCI Rev ID 0x04), Revision G Only 4-23

4.15 External Memory Support 4-24

5.1 LSI53C875 Register Map 5-2

5.2 Examples of Synchronous Transfer Periods for SCSI-1
Transfer Rates 5-16

5.3 Example Transfer Periods for Fast SCSI-2 and Ultra SCSI
Transfer Rates 5-17

5.4 Maximum Synchronous Offset 5-18

5.5 SCSI Synchronous Data FIFO Word Count 5-28

6.1 SCRIPTS Instructions 6-2

6.2 Read/Write Instructions 6-24

xii Contents

7.1 Absolute Maximum Stress Ratings 7-2

7.2 Operating Conditions 7-2

7.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/ 7-3

7.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/,
SSEL/, SRST/ 7-3

7.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/,
TESTIN, DIFFSENS, BIG_LIT/ 7-3

7.6 Capacitance 7-4

7.7 Output Signals—MAC/_TESTOUT, REQ/ 7-4

7.8 Output Signals—IRQ/, SDIR[15:0], SDIRP0, SDIRP1,
BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/[1:0], MCE/,
MOE/, MWE/ 7-4

7.9 Output Signal—SERR/ 7-4

7.10 Bidirectional Signals—AD[31:0], C_BE[3:0], FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR 7-5

7.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/,
GPIO2_MAS2/, GPIO3, GPIO4 7-5

7.12 Bidirectional Signals—MAD[7:0] 7-6

7.13 Input Signals—TDI, TMS, TCK (LSI53C875J,
LSI53C875JB, LSI53C875N Only) 7-6

7.14 Output Signal—TDO (LSI53C875, LSI53C875JB,
LSI53C875N Only) 7-6

7.15 TolerANT Technology Electrical Characteristics 7-7

7.16 Clock Timing 7-11

7.17 Reset Input 7-12

7.18 Interrupt Output 7-13

7.19 LSI53C875 PCI and External Memory Interface Timing 7-50

7.20 Initiator Asynchronous Send 7-51

7.21 Initiator Asynchronous Receive 7-52

7.22 Target Asynchronous Send 7-52

7.23 Target Asynchronous Receive 7-53

7.24 SCSI-1 Transfers (SE, 5.0 Mbytes/s) 7-54

7.25 SCSI-1 Transfers (Differential, 4.17 Mbytes/s) 7-54

7.26 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers)
or 20.0 Mbytes/s (16-Bit Transfers), 40 MHz Clock 7-55

7.27 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers)
or 20.0 Mbytes/s (16-Bit Transfers), 50 MHz Clock 7-55

7.28 Ultra SCSI SE Transfers 20.0 Mbytes/s (8-Bit Transfers)
or 40.0 Mbytes/s (16-Bit Transfers), 80 MHz Clock 7-56

Contents xiii

7.29 Ultra SCSI Differential Transfers 20.0 Mbytes/s
(8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Transfers),
80 MHz Clock 7-57

A.1 Configuration Registers A-1
A.2 LSI53C875 Register Map A-2

xiv Contents

Chapter 1
General Description

Chapter 1 is divided into the following sections:

• Section 1.1, “Package and Feature Options”

• Section 1.2, “Benefits of Ultra SCSI”

• Section 1.3, “TolerANT

• Section 1.4, “LSI53C875 Benefits Summary”

This manual combines information on the LSI53C875 and LSI53C875E,
which are PCI to Ultra SCSI I/O Processors. The LSI53C875E is a minor
modification of the existing LSI53C875 product. It has all the functionality
of the LSI53C875 with the addition of features to enable it to comply with
the Microsoft PC 97 Hardware Design Guide. Specifically, the
LSI53C875E has a Power Management Support enhancement. Because
there are only slight differences between them, the LSI53C875 and
LSI53C875E are referred to as LSI53C875 throughout this technical
manual. Only the new enhancements are referred to as LSI53C875E.

®

Technology”

This technical manual assumes the user is familiar with the current and
proposed standards for SCSI and PCI. For additional background
information on these topics, please refer to the list of reference materials
provided in the Preface of this document.

The LSI53C875 brings high-performance I/O solutions to host adapter,
workstation, and general computer designs, making it easy to add SCSI
to any PCI system. The LSI53C875 has a local memory bus for local
storage of the device’s BIOS ROM in Flash memory or standard
EPROMs. Most versions of the LSI53C875 support big and little endian
byte addressing to accommodate a variety of data configurations. The
LSI53C875 supports programming of local Flash memory for updates to
BIOS or SCRIPTS™ programs.

LSI53C875/875E PCI to Ultra SCSI I/O Processor 1-1

The LSI53C875 is a pin-for-pin replacement for the LSI53C825 PCI to
SCSI I/O processor, with added support for the SCSI-3 Ultra standard as
well as other new features. Some software enhancements are needed to
take advantage of the features and Ultra SCSI transfer rates supported
by the LSI53C875. The LSI53C875 performs Ultra SCSI transfers or fast
8- or 16- bit SCSI transfers in Single-Ended (SE) or differential mode,
and improves performance by optimizing PCI bus utilization. A system
diagram showing the connections of the LSI53C875 with an external
ROM or Flash memory is pictured in Figure 1.1.

Figure 1.1 LSI53C875 External Memory Interface

PCI Bus

SCSI Bus

GPIO4

MWE/

MOE/
MCE/

MAD[7:0]

MAS0/

LSI53C875

MAS1/

GPIO2_MAS2/

BIG_LIT

V

PP

V

PP

Translator

(Optional)

HCT374

HCT374

HCT374

(Optional)

V

PP

ROM or Flash

Memory

D[7:0]

A[7:0]

A[15:8]

A[19:16]

1-2 General Description

A block diagram of the LSI53C875 is pictured in Figure 1.2.

Figure 1.2 LSI53C875 Chip Block Diagram

PCI

PCI Master and Slave Control Block

External
Memory

Memory

Control

Local

Bus

Memory

Data

FIFO

536 Bytes

SCSI

SCRIPTS

Processor

SCSI FIFO and SCSI Control Block

Operating
Registers

TolerANT Drivers and Receivers

SCSI Bus

Configuration

Registers

SCRIPTS

RAM

The LSI53C875 integrates a high-performance SCSI core, a PCI bus
master DMA core, and the LSI Logic SCSI SCRIPTS processor to meet
the flexibility requirements of SCSI-3 and Ultra SCSI standards. It is
designed to implement multithreaded I/O algorithms with a minimum of
processor intervention, solving the protocol overhead problems of
previous intelligent and nonintelligent adapter designs.

The LSI53C875 is fully supported by the LSI Logic Storage Device
Management System (SDMS™), a software package that supports the
Advanced SCSI Protocol Interface (ASPI) and the ANSI Common
Access Method (CAM). SDMS software provides BIOS and driver
support for hard disk, tape, removable media products, and CD-ROM
under the major PC operating systems.

1-3

1.1 Package and Feature Options

The LSI53C875 is available in three versions with different packaging
and feature options. The LSI53C875 is packaged in a 160-pin Plastic
Quad Flat Pack (PQFP). The LSI53C875J is identical to the LSI53C875
with additional pins that support JTAG boundary scan testing. The JTAG
boundary scan signals replace the TESTIN, MAC/_TESTOUT, BIG_LIT/,
and SDIRP1 pins.

The LSI53C875N includes all of the signals in the LSI53C875, with the
addition of the JTAG pins and four additional signals for extended parity
checking and generation. It is packaged in a 208-pin PQFP.

The LSI53C875JB is identical to the LSI53C875J, but is packaged in a
169-pin Ball Grid Array (BGA). The LSI53C875E, LSI53C875JE, and
LSI53C875JBE have been upgraded to include the power management
features.

1.2 Benefits of Ultra SCSI

Ultra SCSI is an extension of the SCSI-3 standard that expands the
bandwidth of the SCSI bus and allows faster synchronous SCSI transfer
rates. When enabled, Ultra SCSI performs 20 megatransfers during an
I/O operation, resulting in approximately twice the synchronous transfer
rates of fast SCSI-2. The LSI53C875 can perform 8-bit, Ultra SCSI
synchronous transfers as fast as 20 Mbytes/s. This advantage is most
noticeable in heavily loaded systems, or large block size requirements,
such as video on-demand and image processing.

An advantage of Ultra SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The LSI53C875 is compatible with all existing LSI53C825 and
LSI53C825A software; the only changes required are to enable the chip
to perform synchronous negotiations for Ultra SCSI rates. The
LSI53C875 can use the same board socket as an LSI53C825, with the
addition of an 80 MHz SCLK or enabling the internal SCSI clock doubler
to provide the correct frequency when transferring synchronous SCSI
data at 50 nanosecond transfer rates. Some changes to existing cabling
or system designs may be needed to maintain signal integrity at Ultra
SCSI synchronous transfer rates. These design issues are discussed in

Chapter 2, “Functional Description.”

1-4 General Description

1.3 TolerANT®Technology

The LSI53C875 features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation actively drives the SCSI Request,
Acknowledge, Data, and Parity signals HIGH rather than allowing them
to be passively pulled up by terminators. Active negation is enabled by
setting bit 7 in the SCSI Test Three (STEST3) register.

TolerANT receiver technology improves data integrity in unreliable
cabling environments, where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations. TolerANT technology input signal filtering is a built-in
feature of the LSI53C875 and all LSI Logic fast SCSI devices. On the
LSI53C875, the user may select a filtering period of 30 or 60 ns, with
bit 1 in the SCSI Test Two (STEST2) register.

The benefits of TolerANT technology include increased immunity to noise
when the signal is going HIGH, better performance due to balanced duty
cycles, and improved fast SCSI transfer rates. In addition, TolerANT
SCSI devices do not cause glitches on the SCSI bus at power-up or
power-down, so other devices on the bus are also protected from data
corruption. TolerANT technology is compatible with both the Alternative
One and Alternative Two termination schemes proposed by the
American National Standards Institute.

TolerANT®Technology 1-5

1.4 LSI53C875 Benefits Summary

The section provides an overview of the LSI53C875 features and
benefits. It contains information on SCSI Performance, PCI Performance,

Integration, Ease of Use, Flexibility, Reliability, and Testability.

1.4.1 SCSI Performance

To improve SCSI performance, the LSI53C875:

• Includes 4 Kbyte internal RAM for SCRIPTS instruction storage.

• Performs wide, Ultra SCSI synchronous transfers as fast as

40 Mbytes/s.

• Increases SCSI synchronous offset from 8 to 16 levels.

• Supports variable block size and scatter/gather data transfers.

• Performs sustained memory-to-memory DMA transfers faster than

47 Mbytes/s (@ 33 MHz).

• Minimizes SCSI I/O start latency.

• Performs complex bus sequences without interrupts, including

restore data pointers.

• Reduces interrupt service routine overhead through a unique

interrupt status reporting method.

• Performs fast and wide SCSI bus transfers in SE and differential

mode.
– 10 Mbytes/s asynchronous (20 Mbytes/s with Ultra SCSI).

– 20 Mbytes/s synchronous (40 Mbytes/s with Ultra SCSI).

• Supports Load and Store SCRIPTS instructions to increase the

performance of data transfers to and from chip registers.

• Supports target disconnect and later reconnect with no interrupt to

the system processor.

• Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast

I/O context switching.

• Supports expanded Register Move instructions to support additional

arithmetic capability.

• Complies with PCI Bus Power Management Specification

(LSI53C875E) Revision 1.0.

1-6 General Description

1.4.2 PCI Performance

To improve PCI performance, the LSI53C875:

• Complies with PCI 2.1 specification.

• Bursts 2, 4, 8, 16, 32, 64, or 128 Dwords across PCI bus.

• Supports 32-bit word data bursts with variable burst lengths.

• Prefetches up to 8 Dwords of SCRIPTS instructions.

• Bursts SCRIPTS opcode fetches across the PCI bus.

• Performs zero wait-state bus master data bursts faster than

110 Mbytes/s (@ 33 MHz).

• Supports PCI Cache Line Size register.

• Supports PCI Write and Invalidate, Read Line, and Read Multiple

commands.

1.4.3 Integration

The following features ease integration of the LSI53C875 into a system:

• 3.3 V/5 V PCI interface.

• Full 32-bit PCI DMA bus master.

• Memory Move instructions allow use as a third-party PCI bus DMA

• High-performance SCSI core.

• Integrated SCRIPTS processor.

1.4.4 Ease of Use

The following features of the LSI53C875 make the device user friendly:

• Up to 1 Mbyte of add-in memory support for BIOS and SCRIPTS

• Direct PCI to SCSI connection.

• Reduced SCSI development effort.

• Easily adapted to the Advanced SCSI Protocol Interface (ASPI) or

LSI53C875 Benefits Summary 1-7

controller.

storage.

the ANSI Common Access Method (CAM), with SDMS software.

1.4.5 Flexibility

• Compiler-compatible with existing LSI53C7XX and LSI53C8XX

family SCRIPTS.

• Direct connection to PCI, and SCSI SE and differential buses.

• Development tools and sample SCSI SCRIPTS available.

• Maskable and pollable interrupts.

• Wide SCSI, A or P cable, and up to 16 devices are supported.

• Three programmable SCSI timers: Select/Reselect, Handshake-to-

Handshake, and General Purpose. The time-out period is
programmable from 100 µs to greater than 25.6 seconds.

• SDMS software for complete PC-based operating system support.

• Support for relative jumps.

• SCSI Selected As ID bits for responding with multiple IDs.

The following features increase the flexibility of the LSI53C875:

• High level programming interface (SCSI SCRIPTS).

• Programs local memory and bus Flash memory.

• Big/little endian support.

• Selectable 88 or 536 byte DMA FIFO for backward compatibility.

• Tailored SCSI sequences execute from main system RAM or internal

SCRIPTS RAM.

• Flexible programming interface to tune I/O performance or to adapt

to unique SCSI devices.

• Support for changes in the logical I/O interface definition.

• Low level access to all registers and all SCSI bus signals.

• Fetch, Master, and Memory Access control pins.

• Separate SCSI and system clocks.

• SCSI clock doubler bits enable Ultra SCSI transfer rates with a

40 MHz SCSI clock.

• Selectable IRQ pin disable bit.

• 32 additional scratch pad registers.

• Ability to route system clock to SCSI clock.

1-8 General Description

1.4.6 Reliability

The following features enhance the reliability of the LSI53C875:

• 2 kV ESD protection on SCSI signals.

• Typical 300 mV SCSI bus hysteresis.

• Protection against bus reflections due to impedance mismatches.

• Controlled bus assertion times (reduces RFI, improves reliability, and

eases FCC certification).

• Latch-up protection greater than 150 mA.

• Voltage feed-through protection (minimum leakage current through

SCSI pads).

• A high proportion (> 25%) of pins are power and ground.

• Power and ground isolation of I/O pads and internal chip logic.

• TolerANT technology which provides:

– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved fast SCSI transfer rates.

– Input signal filtering on SCSI receivers improves data integrity,

even in noisy cabling environments.

• JTAG Boundary scan support (LSI53C875J, LSI53C875JB,

LSI53C875N only).

1.4.7 Testability

• Extended PCI parity checking and generation (LSI53C875N only).

• Extended SCSI parity checking.

The following features enhance the testability of the LSI53C875:

• Access to all SCSI signals through programmed I/O.

• SCSI loopback diagnostics.

• SCSI bus signal continuity checking.

• Support for single step mode operation.

• Test mode (AND tree) to check pin continuity to the board (most

package options).

• JTAG Boundary scan support (LSI53C875J, LSI53C875JB,

LSI53C875N only).

LSI53C875 Benefits Summary 1-9

1-10 General Description

Chapter 2
Functional Description

Chapter 2 is divided into the following sections:

• Section 2.1, “SCSI Functional Description”

• Section 2.2, “Designing an Ultra SCSI System”

• Section 2.3, “Prefetching SCRIPTS Instructions”

• Section 2.4, “External Memory Interface”

• Section 2.5, “PCI Cache Mode”

• Section 2.6, “Power Management”

2.1 SCSI Functional Description

The LSI53C875 is composed of three functional blocks: the SCSI Core,
the DMA Core, and the SCRIPTS Processor. The LSI53C875 is fully
supported by SDMS software, a complete software package that
supports the LSI Logic product line of SCSI processors and controllers.
The PCI Bus Power Management support (LSI53C875E) is discussed

Section 2.6, “Power Management.”

2.1.1 SCSI Core

The SCSI core supports the 8-bit or 16-bit data bus. It supports Ultra
SCSI synchronous transfer rates up to 40 Mbytes/s, SCSI synchronous
transfer rates up to 20 Mbytes/s, and asynchronous transfer rates up to
10 Mbytes/s on a 16-bit wide SCSI bus. The SCSI core can be
programmed with SCSI SCRIPTS, making it easy to “fine tune” the
system for specific mass storage devices or SCSI-3 requirements.

LSI53C875/875E PCI to Ultra SCSI I/O Processor 2-1

2.1.2 DMA Core

The SCSI core offers low level register access or a high level control
interface. Like first generation SCSI devices, the LSI53C875 SCSI core
can be accessed as a register oriented device. The ability to sample
and/or assert any signal on the SCSI bus can be used in error recovery
and diagnostic procedures. In support of loopback diagnostics, the SCSI
core may perform a self-selection and operate as both an initiator and a
target.

The LSI53C875 SCSI core is controlled by the integrated SCRIPTS
processor through a high level logical interface. Commands controlling
the SCSI core are fetched out of the main host memory or local memory.
These commands instruct the SCSI core to Select, Reselect, Disconnect,
Wait for a Disconnect, Transfer Information, Change Bus Phases and, in
general, implement all aspects of the SCSI protocol. The SCRIPTS
processor is a special high speed processor optimized for SCSI protocol.

The DMA core is a bus master DMA device that attaches directly to the
industry standard PCI Bus. The DMA core is tightly coupled to the SCSI
core through the SCRIPTS processor, which supports uninterrupted
scatter/gather memory operations.

The LSI53C875 supports 32-bit memory and automatically supports
misaligned DMA transfers. A 536-byte FIFO allows the LSI53C875 to
support 2, 4, 8, 16, 32, 64, or 128 longword bursts across the PCI bus
interface.

2.1.3 SCRIPTS Processor

The SCSI SCRIPTS processor allows both DMA and SCSI commands
to be fetched from host memory or internal SCRIPTS RAM. Algorithms
written in SCSI SCRIPTS control the actions of the SCSI and DMA cores
and are executed from 32-bit system RAM. The SCRIPTS processor
executes complex SCSI bus sequences independently of the host CPU.

The SCRIPTS processor can begin a SCSI I/O operation in
approximately 500 ns. This compares with 2–8 ms required for traditional
intelligent host adapters. Algorithms may be designed to tune SCSI bus
performance, to adjust to new bus device types (such as scanners,
communication gateways, etc.), or to incorporate changes in the SCSI-2

2-2 Functional Description

or SCSI-3 logical bus definitions without sacrificing I/O performance.
SCSI SCRIPTS are hardware independent, so they can be used
interchangeably on any host or CPU system bus.

2.1.4 Internal SCRIPTS RAM

The LSI53C875 has 4 Kbyte (1024 x 32 bits) of internal, general purpose
RAM. The RAM is designed for SCRIPTS program storage, but is not
limited to this type of information. When the chip fetches SCRIPTS
instructions or Table Indirect information from the internal RAM, these
fetches remain internal to the chip and do not use the PCI bus. Other
types of access to the RAM by the LSI53C875 use the PCI bus, as if
they were external accesses. The MAD5 pin enables the 4 Kbyte internal
RAM. To disable the internal RAM, connect a 4.7 kΩ resistor between
the MAD5 pin and V

The RAM can be relocated by the PCI system BIOS anywhere in 32-bit
address space. The RAM Base Address register in PCI configuration
space contains the base address of the internal RAM. This register is
similar to the ROM Base Address register in PCI configuration space. To
simplify loading of SCRIPTS instructions, the base address of the RAM
will appear in the Scratch Register B (SCRATCHB) register when bit 3 of
the Chip Test Two (CTEST2) register is set. The RAM is byte accessible
from the PCI bus and is visible to any bus mastering device on the bus.
External accesses to the RAM (by the CPU) follow the same timing
sequence as a standard slave register access, except that the target
wait-states required drop from 5 to 3.

SS

.

A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C875, see Chapter 6, “Instruction Set

of the I/O Processor.”

2.1.5 SDMS Software: The Total SCSI Solution

For users who do not need to develop custom drivers, LSI Logic provides
a total SCSI solution in PC environments with the SDMS. SDMS
software provides BIOS driver support for hard disk, tape, and removable
media peripherals for the major PC-based operating systems.

SCSI Functional Description 2-3

SDMS software includes a SCSI BIOS to manage all SCSI functions
related to the device. It also provides a series of SCSI device drivers that
support most major operating systems. SDMS software supports a
multithreaded I/O application programming interface (API) for user
developed SCSI applications. SDMS software supports both the ASPI
and CAM SCSI software specifications.

2.2 Designing an Ultra SCSI System

Migrating an existing SE SCSI design from SCSI-2 to Ultra SCSI requires
minor software modifications as well as consideration for some hardware
design guidelines. Since Ultra SCSI is based on existing SCSI standards,
it can use existing software programs as long as the software is able to
negotiate for Ultra SCSI synchronous transfer rates.

In the area of hardware, the primary area of concern in SE systems is to
maintain signal integrity at high data transfer rates. To assure reliable
operation at Ultra SCSI transfer speeds, follow the system design
parameters recommended in the SCSI-3 Ultra Parallel Interface
standard. Chapter 7, “Instruction Set of the I/O Processor,” contains Ultra
SCSI timing information. In addition to the guidelines in the draft
standard, make the following software and hardware adjustments to
accommodate Ultra SCSI transfers:

• Set the Ultra Enable bit to enable Ultra SCSI transfers.

• Set the TolerANT Enable bit, bit 7 in the SCSI Test Three (STEST3)

register whenever the Ultra Enable bit is set.

• Do not extend the SREQ/SACK filtering period with SCSI Test Two

(STEST2), bit 1.

2.2.1 Using the SCSI Clock Doubler

The LSI53C875 can double the frequency of a 40–50 MHz SCSI clock,
allowing the system to perform Ultra SCSI transfers in systems that do
not have 80 MHz clock input. This option is user selectable with bit
settings in the SCSI Test One (STEST1), SCSI Test Three (STEST3),
and SCSI Control Three (SCNTL3) registers. At power-on or reset, the
doubler is disabled and powered down. Follow these steps to use the
clock doubler:

2-4 Functional Description

Step 1. Set the SCLK Doubler Enable bit (SCSI Test One (STEST1),

bit 3).
Step 2. Wait 20 µs.
Step 3. Halt the SCSI clock by setting the Halt SCSI Clock bit (SCSI

Test Three (STEST3), bit 5).

Step 4. Set the clock conversion factor using the SCF and CCF fields

in the SCSI Control Three (SCNTL3) register.
Step 5. Set the SCLK Doubler Select bit (SCSI Test One (STEST1),

bit 2).
Step 6. Clear the Halt SCSI Clock bit.

2.3 Prefetching SCRIPTS Instructions

When enabled by setting the Prefetch Enable bit in the DMA Control

(DCNTL) register, the prefetch logic in the LSI53C875 fetches 8 Dwords

of instructions. The prefetch logic automatically determines the maximum
burst size that it can perform, based on the burst length as determined
by the values in the DMA Mode (DMODE) register. If the unit cannot
perform bursts of at least four Dwords, it disables itself. While the
LSI53C875 is prefetching SCRIPTS instructions, the PCI Cache Line
Size register value does not have any effect and the Read Line, Read
Multiple, and Write and Invalidate commands are not used.

The LSI53C875 may flush the contents of the prefetch unit under certain
conditions, listed below, to ensure that the chip always operates from the
most current version of the software. When one of these conditions
apply, the contents of the prefetch unit are automatically flushed.

• On every Memory Move instruction. The Memory Move instruction is

often used to place modified code directly into memory. To make
sure that the chip executes all recent modifications, the prefetch unit
flushes its contents and loads the modified code every time an
instruction is issued. To avoid inadvertently flushing the prefetch unit
contents, use the No Flush option for all Memory Move operations
that do not modify code within the next 8 Dwords. For more
information on this instruction, refer to Chapter 6, “Instruction Set of

the I/O Processor.”

Prefetching SCRIPTS Instructions 2-5

• On every Store instruction. The Store instruction may also be used

to place modified code directly into memory. To avoid inadvertently
flushing the prefetch unit contents use the No Flush option for all
Store operations that do not modify code within the next 8 Dwords.

• On every write to the DMA SCRIPTS Pointer (DSP).

• On all Transfer Control instructions when the transfer conditions are

met. This is necessary because the next instruction to execute is not
the sequential next instruction in the prefetch unit.

• When the Prefetch Flush bit (DMA Control (DCNTL), bit 6) is set. The

unit flushes whenever this bit is set. The bit is self-clearing.

2.3.1 Opcode Fetch Burst Capability

Setting the Burst Opcode Fetch Enable bit in the DMA Mode (DMODE)
register (0x38) causes the LSI53C875 to burst in the first two longwords
of all instruction fetches. If the instruction is a Memory-to-Memory Move,
the third longword is accessed in a separate ownership. If the instruction
is an indirect type, the additional longword is accessed in a subsequent
bus ownership. If the instruction is a Table Indirect Block Move, the chip
uses two accesses to obtain the four longwords required, in two bursts
of two longwords each.

Note: This feature is only useful if prefetching is disabled.

2.4 External Memory Interface

The LSI53C875 supports up to one megabyte of external memory in
binary increments from 16 Kbytes, to allow the use of expansion ROM
for add-in PCI cards. The device also supports Flash ROM updates
through the add-in interface and the GPIO4 pin (used to control VPP, the
power supply for programming external memory). This interface is
designed for low speed operations such as downloading instruction code
from ROM. It is not intended for dynamic activities such as executing
instructions.

System requirements include the LSI53C875, two or three external 8-bit
address holding registers (HCT273 or HCT374), and the appropriate
memory device. The 4.7 kΩ pull-down resistors on the MAD bus require
HC or HCT external components to be used. If in-system Flash ROM

2-6 Functional Description