LSI53C876/876E
PCI to Dual Channel
SCSI Multifunction
Controller
Version 2.1
March 2001
®
S14066
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000167-00, First Edition (March 2001)
This document describes the LSI Logic LSI53C876/876E PCI to Dual Channel
SCSI Multifunction Controller and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
The LSI Logic logo design, TolerANT, SDMS, SYMplicity, and SCRIPTS are
registered trademarks or trademarks of LSI Logic Corporation. All other brand
and product names may be trademarks of their respective companies.
ii
Audience
Preface
This book is the primary reference and technical manual for the LSI Logic
LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller. It
contains a complete functional description for the product and includes
complete physical and electrical specifications.
This technical manual assumes the user is familiar with the current and
proposed standards for SCSI and PCI. For additional background
information on these topics, please refer to the list of reference materials
provided in the Related Publications list.
This manual assumes some prior knowledge of current and proposed
SCSI and PCI standards.
Organization
This document has the following chapters and appendixes:
•Chapter 1, General Description, includes general information about
the LSI53C876/876E.
•Chapter 2, Functional Description, describes the main functional
areas of the chip in more detail, including the interfaces to the SCSI
bus and external memory.
•Chapter 3, Signal Descriptions, contains pin diagrams and signal
descriptions.
•Chapter 4, Registers, describes each bit in the operating registers,
and is organized by register address.
•Chapter 5, SCSI SCRIPTS Instruction Set, defines the SCSI
SCRIPTS instructions supported by the LSI53C876/876E.
Prefaceiii
•Chapter 6, Electrical Characteristics, contains the electrical
•Appendix A, Register Summary, is a register summary.
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Ask for document number X3.131-1994 (SCSI-2) or X3.253
(SCSI-3 Parallel Interface)
characteristics and AC timing diagrams.
contains serveral example interface drawings for connecting the
LSI53C876 to external ROMs.
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ivPreface
SCSI Bench Reference, SCSI Encyclopedia,
SCSI: Understanding
PCI Special Interest Group
2575 N. E. Katherine
Hillsboro, OR 97214
(800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344
SCSI SCRIPTS™ Processors Programming Guide,
S14044.A
Conventions Used in This Manual
The word
deassert
assert
means to drive a signal true or active. The word
means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
6.49SCSI-2 Fast-20 SE Transfers (20.0 Mbytes/s
(8-Bit Transfers) or 40.0 Mbytes/s (16-Bit Transfers),
80 MHz Clock) with Clock Doubled Internally6-59
A.1Configuration RegistersA-1
A.2SCSI RegistersA-2
xivContents
Chapter 1
General Description
This chapter includes the following sections:
•Section 1.1, “Wide Ultra SCSI Benefits”
•Section 1.2, “TolerANT
•Section 1.3, “LSI53C876 Benefits”
This manual combines information for the LSI53C876 and LSI53C876E,
which are a PCI to dual SCSI controllers. The LSI53C876E is a minor
modification of the existing LSI53C876 product. It has all of the
functionality of the LSI53C876 with the addition of features to enable it
to comply with the Microsoft PC 97 Hardware Design Guide. Specifically,
the LSI53C876E has a Power Management Support enhancement.
Because there are only slight differences between them, the LSI53C876
and LSI53C876E are referred to as LSI53C876 throughout this technical
manual. Only the new enhancements are referred to as LSI53C876E.
®
Technology”
The LSI53C876 PCI to Dual Channel SCSI Multifunction Controller is a
PCI 2.1 compliant device. It implements two LSI53C875 PCI to Ultra
SCSI controllers on a single chip. The LSI53C876 presents only one load
to the PCI bus, and it uses one REQ/ - GNT/ signal pair in arbitration for
PCI bus mastership.
Two packaging options are available. The 208-pin Plastic Quad Flat Pack
(PQFP) provides a differential Single-Ended (SE) SCSI interface on SCSI
Function A and an SE interface on SCSI Function B. The 256-bump Ball
Grid Array (BGA) provides a differential SE interface on both SCSI
Function A and SCSI Function B.
The LSI53C876 has a local memory bus for storage of the device’s BIOS
ROM in Flash memory or standard EPROMs. The LSI53C876 supports
programming of local Flash memory for updates to BIOS or SCRIPTS™
programs.
LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller1-1
The LSI53C876 reduces the requirement for system BIOS support and
PCI bus bandwidth. It also supports the Wide Ultra SCSI standard. The
LSI53C876 performs Wide Ultra SCSI transfers or Fast SCSI transfers,
and it improves performance by optimizing PCI bus utilization. Figure 1.1
illustrates a typical LSI53C876 system and Figure 1.2 illustrates a typical
LSI53C876 board application.
Figure 1.1Typical LSI53C876 System Application
PCI Bus
Interface
Controller
Processor Bus
Central
Processing
Unit
(CPU)
Typical PCI Computer
System Architecture
LSI53C876 PCI
to Wide Ultra SCSI
Function A
and
LSI53C876 PCI
to Wide Ultra SCSI
Function B
One PCI Bus Load
PCI Graphic Accelerator
PCI Sound Card
Memory
Controller
Memory
SCSI Bus
SCSI Bus
Fixed Disk, Optical Disk,
Printer, Tape, and Other
Peripherals
Fixed Disk, Optical Disk,
Printer, Tape, and Other
Peripherals
1-2General Description
Figure 1.2Typical LSI53C876 Board Application
Function A
68 Pin
Wide SCSI
Connector
Function B
68 Pin
Wide SCSI
Connector
SCSI Data,
Parity, and
Control Signals
LSI53C876
PCI
SCSI Data,
Parity, and
Control Signals
PCI Address, Data, Parity and Control Signals
Dual Channel SCSI
PCI Interface
to
Multifunction
Controller
Memory
Address/Data
A_GPIO/[1:0]
B_GPIO/[1:0]
Bus
Memory Control
Block
Flash EEPROM
Serial EEPROM
Function A
Serial EEPROM
Function B
The LSI53C876 integrates a high-performance SCSI core, a PCI bus
master DMA core, and the LSI Logic SCSI SCRIPTS processor to meet
the flexibility requirements of SCSI, Fast SCSI, and Wide Ultra SCSI
standards. It is designed to implement multithreaded I/O algorithms with
a minimum of processor intervention, solving the protocol overhead
problems of previous intelligent and nonintelligent controller designs.
The LSI53C876 is fully supported by the LSI Logic Storage Device
Management System (SDMS™), a software package that supports the
Advanced SCSI Protocol Interface (ASPI). SDMS software provides
BIOS and driver support for hard disk, tape, removable media products,
and CD-ROM under the major PC operating systems.
In addition, LSI Logic provides a SYMplicity™ I2O Hardware Device
Module for the LSI53C876 to support the device in I2O-ready systems.
The SYMplicity I2O architecture is compliant with the I2O specification.
I2O is a split driver architecture that increases system efficiency by
transferring I/O intensive processing tasks from the host CPU to
intelligent peripheral platforms.
1-3
1.1Wide Ultra SCSI Benefits
Wide Ultra SCSI is an extension of the SCSI-3 family of standards that
expands the bandwidth of the SCSI bus and allows faster synchronous
SCSI transfer rates. When enabled, Wide Ultra SCSI performs
40 megatransfers per second during an I/O operation, resulting in
approximately twice the synchronous transfer rates of Fast SCSI. The
LSI53C876 can perform Ultra SCSI synchronous transfers at
20 Mbytes/s. It can also perform Wide Ultra SCSI transfers at
40 Mbytes/s. This advantage is most noticeable in heavily loaded
systems or large block size requirements, such as video on-demand and
image processing.
An advantage of Wide Ultra SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The LSI53C876 is compatible with all existing LSI53C875 software.
1.2TolerANT®Technology
The LSI53C876 features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation actively drives the SCSI Request,
Acknowledge, Data, and Parity signals HIGH rather than allowing them
to be passively pulled up by terminators. Active negation is enabled by
setting bit 7 in the SCSI Test Three (STEST3) register.
TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations. TolerANT input signal filtering is a built in feature of the
LSI53C876 and all LSI Logic Fast SCSI and Ultra SCSI devices.
The benefits of TolerANT technology include increased immunity to noise
on the deasserting signal edge, better performance due to balanced duty
cycles, and improved Fast SCSI transfer rates. In addition, TolerANT
SCSI devices do not cause glitches on the SCSI bus at power-up or
1-4General Description
power-down, so other devices on the bus are also protected from data
corruption. TolerANT technology is compatible with both the Alternative
One and Alternative Two termination schemes proposed by the American
National Standards Institute (ANSI).
1.3LSI53C876 Benefits
This section provides an overview of the LSI53C876 features and
benefits. It contains information on PCI Performance, SCSI Performance,
Testability, Integration, and Reliability.
1.3.1 PCI Performance
To improve SCSI performance, the LSI53C876:
•Complies with PCI 2.1 specification
•Presents a single electrical load to the PCI bus (True PCI
multifunction device).
•Supports 32-bit word data bursts with variable burst lengths of 2, 4,
8, 16, 32, 64 or 128 Dwords across the PCI bus.
•Prefetches up to 8 Dwords of SCSI SCRIPTS.
•Bursts SCSI SCRIPTS opcode fetches across the PCI bus.
•Performs zero wait-state bus master data bursts up to 132 Mbytes/s
(@ 33 MHz).
•Supports PCI Cache Line Size register.
•Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
•Complies with PCI Bus Power Management Specification
(LSI53C876E) Revision 1.0.
1.3.2 SCSI Performance
To improve SCSI performance, the LSI53C876:
•Includes 4 Kbytes internal RAM on each channel for SCRIPTS
instruction storage.
•Wide Ultra SCSI SE Interface.
LSI53C876 Benefits1-5
•Performs Wide Ultra SCSI synchronous transfers as fast as
40 Mbytes/s.
•Supports 536-byte DMA FIFO for more effective PCI and SCSI bus
utilization.
•Supports 16 levels of SCSI synchronous offset.
•Supports variable block size and scatter/gather data transfers
•Minimizes SCSI I/O start latency.
•Performs complex bus sequences without interrupts, including
restore data pointers.
•Reduces interrupt service routine overhead through a unique
interrupt status reporting method.
•Supports Load and Store SCRIPTS instructions to increase the
performance of data transfers to and from chip registers.
•Supports target disconnect and later reconnect with no interrupt to
the system processor.
•Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching.
•Supports expanded Register Move instructions.
•Compatible with LSI53C875 software (drivers and SCRIPTS).
•Enables Ultra SCSI with 40 MHz SCSI clock input with integrated
clock doubler.
1.3.3 Testability
The LSI53C876 contains these testability features:
•All SCSI signals accessible through programmed I/O.
•SCSI loopback diagnostics.
•SCSI bus signal continuity checking.
•Support for single step mode operation.
•Test mode (AND-tree) to check pin continuity to the board.
1-6General Description
1.3.4 Integration
1.3.5 Reliability
The LSI53C876 contains these integration features:
•Dual channel SCSI multifunction controller.
•3.3 V/5 V PCI interface.
•Full 32-bit PCI DMA bus master.
•Memory-to-Memory Move instructions allow use as a third-party PCI
bus DMA controller.
•High-performance SCSI core.
•Integrated SCRIPTS processor.
The LSI53C876 contains these reliability features:
•2 kV ESD protection on SCSI signals.
•Typical 300 mV SCSI bus hysteresis.
•Protection against bus reflections due to impedance mismatches.
•Controlled bus assertion times (reduces EMI, improves reliability, and
eases FCC certification).
•Latch-up protection greater than 150 mA.
•Voltage feed-through protection (minimum leakage current through
SCSI pads).
•Power and ground isolation of I/O pads and internal chip logic.
•TolerANT technology, which provides:
–Active negation of SCSI Data, Parity, Request, and Acknowledge
signals for improved fast SCSI transfer rates.
–Input signal filtering on SCSI receivers improves data integrity,
even in noisy cabling environments.
LSI53C876 Benefits1-7
1-8General Description
Chapter 2
Functional Description
Chapter 2 is divided into the following sections:
•Section 2.1, “PCI Functional Description”
•Section 2.2, “SCSI Functional Description”
•Section 2.3, “Parallel ROM Interface”
•Section 2.4, “Serial EEPROM Interface”
•Section 2.5, “Power Management”
The LSI53C876 is a multifunction device composed of the following
modules:
Figure 2.1 illustrates the relationship between these modules.
LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller2-1
Figure 2.1LSI53C876 Block Diagram
PCI Bus
PCI Master and Slave Control Block, PCI Configuration Registers (2 sets), and SCSI Function Arbitration
Wide Ultra SCSI Controller
4 Kbyte
SCRIPTS RAM
536 Byte
DMA FIFO
SCSI FIFO and SCSI Control Block
8 Dword SCRIPTS
Prefetch Buffer
Registers
Processor
SCSI SCRIPTS
TolerANT
Drivers and Receivers
SCSI Function A
Wide Ultra
SCSI Bus
Operating
Local
Memory
ROM/Flash
Memory
Bus
ROM/Flash Memory Control
Bus
2-Wire Serial
EEPROM Bus
SCRIPTS RAM
and Autoconfiguration
Serial EEPROM Controller
Wide Ultra SCSI Controller
4 Kbyte
Registers
Operating
SCSI FIFO and SCSI Control Block
2-Wire Serial
EEPROM Bus
8 Dword SCRIPTS
Prefetch Buffer
Processor
SCSI SCRIPTS
TolerANT
Drivers and Receivers
SCSI Function B
Wide Ultra
SCSI Bus
536 Byte
DMA FIFO
2-2Functional Description
2.1PCI Functional Description
The LSI53C876 implements two PCI-to-Wide Ultra SCSI controllers in a
single package. This configuration presents only one load to the PCI bus
and uses one REQ/ - GNT/ pair to arbitrate for PCI bus mastership.
However, separate interrupt signals are generated for SCSI Function A
and SCSI Function B.
2.1.1 PCI Addressing
There are three physical PCI-defined address spaces:
•Configuration Space
•I/O Space
•Memory Space
2.1.1.1 Configuration Space
Two independent sets of configuration space registers are defined, one
set for each SCSI function. The Configuration registers are accessible
only by system BIOS during PCI configuration cycles. The configuration
space is a contiguous 256 x 8-bit set of addresses. Decoding C_BE/[3:0]
determines if a PCI cycle is intended to access configuration register
space. The IDSEL bus signal is a “chip select” that allows access to the
configuration register space only. A configuration read/write cycle without
IDSEL is ignored. The eight lower order address bits AD[7:0], are used
to select a specific 8-bit register. Since the LSI53C876 is a PCI
multifunction device, AD[10:8] decodes either SCSI Function A
Configuration register (AD [10:8] = 000 binary) or SCSI Function B
Configuration register (AD [10:8] = 001 binary). The host processor uses
this configuration space to initialize the LSI53C876.
At initialization time, each PCI device is assigned a base address for
memory accesses and I/O accesses. In the case of the LSI53C876, the
upper 24 bits of the address are selected. On every access, the
LSI53C876 compares its assigned base addresses with the value on the
Address/Data bus during the PCI address phase. If the upper 24 bits
match, the access is for the LSI53C876 and the low-order eight bits
define the register being accessed. A decode of C_BE/[3:0] determines
which registers and what type of access is to be performed.
PCI Functional Description2-3
I/O Space – The PCI specification defines I/O space as a contiguous
32-bit I/O address that is shared by all system resources, including the
LSI53C876. The Base Address Register Zero (I/O) register determines
which 256-byte I/O area this device occupies.
Memory Space – The PCI specification defines memory space as a
contiguous 32-bit memory address that is shared by all system
resources, including the LSI53C876. The Base Address Register One
(Memory) register determines which 256-byte memory area this device
occupies. Each SCSI function uses a 4 K SCRIPT RAM memory space.
The Base Address Register Two (Memory) register determines the
4 Kbyte memory area occupied by SCRIPTS RAM.
2.1.2 PCI Bus Commands and Functions Supported
Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE/[3:0] lines
during the address phase. PCI bus commands and encoding types
appear in Table 2.1.
Table 2.1PCI Bus Commands and Encoding Types
C_BE[3:0] Command TypeSupported as Master Supported as Slave
The LSI53C876 does not respond to this command as a slave and it
never generates this command as a master.
2.1.2.2 Special Cycle Command
The LSI53C876 does not respond to this command as a slave and it
never generates this command as a master.
2.1.2.3 I/O Read Command
The I/O Read command reads data from an agent mapped in I/O
address space. All 32 address bits are decoded.
2.1.2.4 I/O Write Command
The I/O Write command writes data to an agent mapped in I/O address
space. All 32 address bits are decoded.
2.1.2.5 Reserved Command
The LSI53C876 does not respond to this command as a slave and it
never generates this command as a master.
PCI Functional Description2-5
2.1.2.6 Memory Read Command
The Memory Read command reads data from an agent mapped in the
Memory Address Space. The target is free to do an anticipatory read for
this command only if it can guarantee that such a read has no side
effects.
2.1.2.7 Memory Write Command
The Memory Write command writes data to an agent mapped in the
Memory Address Space. When the target returns “ready”, it assumes
responsibility for the coherency (which includes ordering) of the subject
data.
2.1.2.8 Configuration Read Command
The Configuration Read command reads the configuration space of each
agent. An agent is selected during a configuration access when its
IDSEL signal is asserted and AD[1:0] are 0b00. During the address
phase of a configuration cycle, AD[7:2] address one of the 64 Dword
registers (where byte enables address of the bytes within each Dword)
in the configuration space of each device and AD[31:11] are logical don’t
cares to the selected agent. AD[10:8] indicate which device of a
multifunction agent is being addressed.
2.1.2.9 Configuration Write Command
The Configuration Write command transfers data to the configuration
space of each agent. An agent is selected when its IDSEL signal is
asserted and AD[1:0] are 0b00. During the address phase of a
configuration cycle, the AD[7:2] lines address the 64 Dword registers
(where byte enables address of the bytes within each Dword) in the
configuration space of each device,and AD[31:11] are logical don’t cares
to the selected agent. AD[10:8] indicate which device of a multifunction
agent is addressed.
2.1.2.10 Memory Read Multiple Command
This command is identical to the Memory Read command except that it
additionally indicates that the master may intend to fetch more than one
cache line before disconnecting. The LSI53C876 supports PCI Read
Multiple functionality and issues Read Multiple commands on the PCI
2-6Functional Description
bus when the Read Multiple Mode is enabled. This mode is enabled by
setting bit 2 (ERMP) of the DMA Mode (DMODE) register. If cache mode
is enabled, a Read Multiple command is issued on all read cycles, except
opcode fetches, when the following conditions are met:
•The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL)
register) and the ERMP bit (Enable Read Multiple, bit 2, DMA Mode
(DMODE) register) are set.
•The Cache Line Size register for each function contains a legal burst
size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or
equal to the DMA Mode (DMODE) burst size.
•The number of bytes to transfer at the time a cache boundary is
reached is at least twice the full cache line size.
•The chip is aligned to a cache line boundary.
When these conditions are met, the chip issues a Read Multiple
command instead of a Memory Read during all PCI read cycles.
Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data in a single bus ownership. The number of cache lines
to read is a multiple of the cache line size specified in Revision 2.1 of
the PCI specification. The logic selects the largest multiple of the cache
line size based on the amount of data to transfer, with the maximum
allowableburstsizedetermined from the DMA Mode (DMODE) burst size
bits, and the Chip Test Five (CTEST5), bit 2.
2.1.2.11 Dual Address Cycles (DACs) Command
The LSI53C876 does not respond to this command as a slave, and it
never generates this command as a master.
2.1.2.12 Memory Read Line Command
This command is identical to the Memory Read command, except that it
additionally indicates that the master intends to fetch a complete cache
line. This command is intended for use with bulk sequential data transfers
where the memory system and the requesting master might gain some
performance advantage by reading up to a cache line boundary rather
than a single memory cycle. The Read Line function in the previous
LSI53C8XX chips is modified in the LSI53C876 to reflect the PCI Cache
Line Size register specifications. The functionality of the Enable Read
PCI Functional Description2-7
Line bit (DMA Mode (DMODE) register, bit 3) is modified to more
resemble the Write and Invalidate mode in terms of conditions that must
be met before a Read Line command is issued. However, the Read Line
option operates exactly like the previous LSI53C8XX chips when cache
mode is disabled by a CLSE bit reset or when certain conditions exist in
the chip (explained below).
If cache mode is disabled, Read Line commands are issued on every
read data transfer, except opcode fetches, as in previous LSI53C8XX
chips.
If cache mode is enabled, a Read Line command is issued on all read
cycles, except opcode fetches, when the following conditions are met:
•The CLSE (Cache Line Size Enable, bit 7, DMA Control (DCNTL)
register) and ERL (Enable Read Line, bit 3, DMA Mode (DMODE)
register) bits are set.
•The Cache Line Size register for each function must contain a legal
burst size value (2, 4, 8, 16, 32, 64, or 128) and that value is less
than or equal to the DMA Mode (DMODE) burst size.
•The number of bytes to be transferred at the time a cache boundary
is reached is equal to or greater than the DMA Mode (DMODE) burst
size.
•The chip is aligned to a cache line boundary.
When these conditions are met, the chip issues a Read Line command
instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.
Read Multiple with Read Line Enabled – When both the Read
Multiple and Read Line modes are enabled, the Read Line command is
not issued if the above conditions are met. Instead, a Read Multiple
command is issued, even though the conditions for Read Line are met.
If the Read Multiple mode is enabled and the Read Line mode is
disabled, Read Multiple commands are issued if the Read Multiple
conditions are met.
2-8Functional Description
2.1.2.13 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; that is to say, the master intends to
write all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI Cache Line Size register at address 0x0C in the PCI
configuration space. The LSI53C876 enables Memory Write and
Invalidate cycles when bit 0 (WRIE) in the Chip Test Three (CTEST3)
register and bit 4 (WIE) in the PCI Command register are set. When the
following conditions are met, Memory Write and Invalidate commands
are issued:
•The CLSE bit (Cache Line Size Enable, DMA Control (DCNTL)
register, bit 7), WRIE bit (Write and Invalid Enable, Chip Test Three
(CTEST3) register, bit 0), and PCI configuration Command register,
bit 4 are set.
•The Cache Line Size register for each function contains a legal burst
size value (2, 4, 8, 16, 32, 64, or 128) and that value is less than or
equal to the DMA Mode (DMODE) burst size.
•The chip has enough bytes in the DMA FIFO to complete at least
one full cache line burst.
•The chip is aligned to a cache line boundary.
When these conditions are met, the LSI53C876 issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.
Multiple Cache Line Transfers – The Write and Invalidate command
can write multiple cache lines of data in a single bus ownership. The chip
issues a burst transfer as soon as it reaches a cache line boundary. The
size of the transfer is not automatically the cache line size, but rather a
multiple of the cache line size as specified in Revision 2.1 of the PCI
specification. The logic selects the largest multiple of the cache line size
based on the amount of data to transfer, with the maximum allowable
burst size determined from the DMA Mode (DMODE) burst size bits, and
Chip Test Five (CTEST5), bit 2. If multiple cache line size transfers are
not desired, set the DMA Mode (DMODE) burst size to exactly the cache
line size and the chip only issues single cache line transfers.
PCI Functional Description2-9
After each data transfer, the chip re-evaluates the burst size based on
the amount of remaining data to transfer and again selects the highest
possible multiple of the cache line size, no larger than the DMA Mode
(DMODE) burst size. The most likely scenario of this scheme is that the
chip selects the DMA Mode (DMODE) burst size after alignment, and
issues bursts of this size. The burst size is, in effect, throttled down
toward the end of a long Memory Move or Block Move transfer until only
the cache line size burst size is left. The chip finishes the transfer with
this burst size.
Latency – In accordance with the PCI specification, the chip's latency
timer is ignored when issuing a Write and Invalidate command such that
when a latency time-out occurs, the LSI53C876 continues to transfer up
to a cache line boundary. At that point, the chip relinquishes the bus, and
finishes the transfer at a later time using another bus ownership. If the
chip is transferring multiple cache lines it continues to transfer until the
next cache boundary is reached.
PCI Target Retry – During a Write and Invalidate transfer, if the target
device issues a retry (STOP with no TRDY, indicating that no data was
transferred), the chip relinquishes the bus and immediately tries to finish
the transfer on another bus ownership. The chip issues another Write
and Invalidate command on the next ownership, in accordance with the
PCI specification.
PCI Target Disconnect – During a Write and Invalidate transfer, if the
target device issues a disconnect the LSI53C876 relinquishes the bus
and immediately tries to finish the transfer on another bus ownership.
The chip does not issue another Write and Invalidate command on the
next ownership unless the address is aligned.
2.1.3 Internal Arbiter
The PCI to SCSI controller uses a single REQ/ - GNT/ signal pair to
arbitrate for access to the PCI bus. The LSI53C876 uses a round robin
arbitration scheme to allow both SCSI functions to arbitrate for PCI bus
access.
An internal arbiter circuit allows the different bus mastering functions
resident in the chip to arbitrate among themselves for the privilege of
arbitrating for PCI bus access. There are two independent bus mastering
functions inside the LSI53C876, one for each of the SCSI functions.
2-10Functional Description
2.1.4 PCI Cache Mode
The LSI53C876 supports the PCI specification for an 8-bit Cache Line
Size register located in the PCI configuration space. The Cache Line
Size register provides the ability to sense and react to nonaligned
addresses corresponding to cache line boundaries. In conjunction with
the Cache Line Size register, the PCI commands Read Line, Read
Multiple, and Write and Invalidate are each software enabled or disabled
to allow the user full flexibility in using these commands.
2.1.4.1 Selection of Cache Line Size
The cache logic for each bus mastering function selects a cache line size
based on the values for the burst size in the DMA Mode (DMODE)
register, and the PCI Cache Line Size register, whichever is appropriate.
Note:Each bus mastering function does not automatically use the
value in its PCI Cache Line Size register as the cache line
size value. The chip scales the value of the Cache Line
Size register down to the nearest binary burst size allowed
by the chip (2, 4, 8, 16, 32, 64, or 128). The SCSI function
compares this value to the DMODE burst size, then selects
the smaller as the value for the cache line size.
2.1.4.2 Alignment
The LSI53C876 uses the calculated line size value to monitor the current
address for alignment to the cache line size. When it is not aligned, the
chip attempts to align to the cache boundary by using a “smart aligning”
scheme. This means that it attempts to use the largest burst size
possible that is less than the cache line size, to reach the cache
boundary quickly with no overflow. This process is a stepping mechanism
that steps up to the highest possible burst size based on the current
address.
The stepping process begins at a 4 Dword boundary. The LSI53C876
first tries to align toa4Dwordboundary (0x0000, 0x0010, 0x0020, etc.)
by using single Dword transfers (no bursting). Once this boundary is
reached the chip evaluates the current alignment to various burst sizes
allowed, and selects the largest possible as the next burst size, while not
exceeding the cache line size. The chip then issues this burst and
re-evaluates the alignment to various burst sizes, again selecting the
PCI Functional Description2-11
largest possible while not exceeding the cache line size, as the next burst
size. This stepping process continues until the chip reaches the cache
line size boundary or runs out of data. Once a cache line boundary is
reached, the chip uses the cache line size as the burst size from then
on, except in the case of multiples (explained below). The alignment
process is finished at this point.
Example: Cache Line Size = 16, Current Address = 0x01 – The chip
is not aligned to a 4 Dword cache boundary (the stepping threshold), so
it issues four single Dword transfers (the first is a 3-byte transfer). At
address 0x10, the chip is aligned to a 4-Dword boundary, but not aligned
to any higher burst size boundaries that are less than the cache line size.
So, the part issues a burst of 4. At this point, the address is 0x20, and
the chip evaluates that it is aligned not only toa4Dwordboundary, but
also to an 8 Dword boundary. It selects the highest, 8, and bursts
8 Dwords. At this point, the address is 0x40, which is a cache line size
boundary. Alignment stops, and the burst size from then on is switched
to 16.
2.1.4.3 Memory Move Misalignment
The LSI53C876 does not operate in a cache alignment mode when a
Memory Move instruction type is issued and the read and write
addresses are different distances from the nearest cache line boundary.
For example,if the read address is 0x21F and the write address is 0x42F,
and the cache line size is 8, the addresses are byte aligned, but they are
not the same distance from the nearest cache boundary. The read
address is 1 byte from the cache boundary 0x220 and the write address
is 17 bytes from the cache boundary 0x440. In this situation, the chip
does not align to cache boundaries.
2-12Functional Description
2.2SCSI Functional Description
2.2.1 Two SCSI Controllers
The LSI53C876 provides two SCSI controllers on a single chip. Each
SCSI controller provides a SCSI function that supports an 8-bit or 16-bit
bus. Each supports Ultra SCSI synchronous transfer rates up to
40 Mbytes/s, Ultra SCSI synchronous transfer rates up to 20 Mbytes/s,
and asynchronous transfer rates up to 14 Mbytes/s on a wide SCSI bus.
The SCSI functions are programmed with SCSI SCRIPTS, making it
easy to “fine tune” the system for specific mass storage devices or
SCSI-2 requirements.
The LSI53C876 offers low-level register access or a high-level control
interface. Like first generation SCSI devices, the LSI53C876 is accessed
as a register-oriented device. Error recovery and diagnostic procedures
use the ability to sample and/or assert any signal on the SCSI bus. In
support of SCSI loopback diagnostics, each SCSI core may perform a
self-selection and operate as both an initiator and a target.
The LSI53C876 is controlled by the integrated SCRIPTS processor
through a high-level logical interface. Commands controlling the SCSI
core are fetched out of the main host memory or local memory. These
commands instruct the SCSI core to Select, Reselect, Disconnect, Wait
for a Disconnect, Transfer Information, Change Bus Phases and, in
general, implement all aspects of the SCSI protocol. The SCRIPTS
processor is a special high-speed processor optimized for SCSI protocol.
2.2.2 SCRIPTS Processor
The SCSI SCRIPTS processor allows both DMA and SCSI commands
to be fetched from host memory or internal SCRIPTS RAM. Algorithms
written in SCSI SCRIPTS control the actions of the SCSI and DMA
cores. The SCRIPTS processor executes complex SCSI bus sequences
independently of the host CPU.
Algorithms may be designed to tune SCSI bus performance, to adjust to
new bus device types (such as scanners, communication gateways,etc.),
or to incorporate changes in the SCSI-2 or SCSI-3 logical bus definitions
SCSI Functional Description2-13
without sacrificing I/O performance. SCSI SCRIPTS are hardware
independent, so they can be used interchangeably on any host or CPU
system bus.
2.2.2.1 Internal SCRIPTS RAM
The LSI53C876 has 4 Kbytes (1024 x 32 bits) of internal, general
purpose RAM. The RAM is designed for SCRIPTS program storage, but
is not limited to this type of information. When the chip fetches SCRIPTS
instructions or Table Indirect information from the internal RAM, these
fetches remain internal to the chip and do not use the PCI bus. Other
types of access to the RAM by the chip use the PCI bus, as if they were
external accesses. The MAD5 pin disables the 4 K internal RAM. To
disable the internal RAM, connect a 4.7 kΩ resistor between the MAD5
pin and VSS(ground). The SCRIPTS RAM powers up enabled by default.
The RAM can be relocated by the PCI system BIOS anywhere in 32-bit
address space. The Base Address Register Two (Memory) register in
PCI configuration space contains the base address of the internal RAM.
This register is similar to the ROM Base Address register in PCI
configuration space. To simplify loading of the SCRIPTS instructions, the
base address of the RAM appears in the Scratch Register B
(SCRATCHB) register when bit 3 of the Chip Test Two (CTEST2) register
is set. The RAM is byte accessible from the PCI bus and is visible to any
bus mastering device on the bus. External accesses to the RAM (by the
CPU) follow the same timing sequence as a standard slave register
access, except that the required target wait-states drop from 5 to 3.
A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C876, see Chapter 5, “SCSI
SCRIPTS Instruction Set.”
2.2.2.2 Prefetching SCRIPTS Instructions
When enabled by setting the Prefetch Enable bit (bit 5) in the DMA
Control (DCNTL) register, the prefetch logic in the LSI53C876 fetches
8 Dwords of instructions. The prefetch logic automatically determines the
maximum burst size that it can perform based on the burst length as
determined by the values in the DMA Mode (DMODE) register. If the unit
cannot perform bursts of at least four Dwords, it disables itself. While the
2-14Functional Description
chip is prefetching SCRIPTS instructions, the PCI Cache Line Size
register value does not have any effect and the Read Line, Read
Multiple, and Write and Invalidate commands are not used.
Note:This feature is only useful if fetching SCRIPTS instructions
from main memory. Due to the short access time of
SCRIPTS RAM, prefetching is not necessary when fetching
instructions from this memory.
The LSI53C876 may flush the contents of the prefetch unit under certain
conditions, listed below, to ensure that the chip always operates from the
most current version of the SCRIPTS instruction. When one of these
conditions apply, the contents of the prefetch unit are automatically
flushed.
•On every Memory Move instruction. The Memory Move instruction
often places modified code directly into memory. To make sure that
the chip executes all recent modifications, the prefetch unit flushes
its contents and loads the modified code every time a instruction is
issued. To avoid inadvertently flushing the prefetch unit contents, use
the No Flush option for all Memory Move operations that do not
modify code within the next 8 Dwords. For more information on this
instruction, refer to Chapter 5, “SCSI SCRIPTS Instruction Set.”
•On every Store instruction. The Store instruction may also be used
to place modified code directly into memory. To avoid inadvertently
flushing the prefetch unit contents use the No Flush option for all
Store operations that do not modify code within the next 8 Dwords.
•On every write to the DMA SCRIPTS Pointer (DSP) register.
•On all Transfer Control instructions when the transfer conditions are
met. This is necessary because the next instruction to execute is not
the sequential next instruction in the prefetch unit.
•When the Prefetch Flush bit (DMA Control (DCNTL) register, bit 6)
is set. The unit flushes whenever this bit is set. The bit is
self-clearing.
2.2.2.3 OpCode Fetch Burst Capability
Setting the Burst OpCode Fetch Enable bit (bit 1) in the DMA Mode
(DMODE) register (0x38) causes the LSI53C876 to burst in the first two
Dwords of all instruction fetches. If the instruction is a Memory-to-
SCSI Functional Description2-15
Memory Move, the third Dword is accessed in a separate ownership. If
the instruction is an indirect type, the additional Dword is accessed in a
subsequent bus ownership. If the instruction is a Table Indirect Block
Move, the chip uses two accesses to obtain the four Dwords required, in
two bursts of two Dwords each.
Note:This feature is only useful if prefetching is disabled and
SCRIPTS instructions are fetched from main memory. Due
to the short access time of SCRIPTS RAM, burst opcode
fetching is not necessary when fetching instructions from
this memory.
2.2.2.4 Load/Store Instructions
The LSI53C876 supports the Load and Store instruction type, which
simplifies the movement of data between memory and the internal chip
registers. It also enables the chip to transfer bytes to addresses relative
to the Data Structure Address (DSA) register. For more information on
the Load and Store instructions, refer to Chapter 5, “SCSI SCRIPTS
Instruction Set.”
2.2.3 JTAG Boundary Scan Testing
The LSI53C876 includes support for JTAG boundary scan testing in
accordance with the IEEE 1149.1 specification with one exception, which
is explained in this section. This device accepts all required boundary
scan instructions including the optional CLAMP, HIGH-Z, and IDCODE
instructions.
The LSI53C876 uses an 8-bit instruction register to support all boundary
scan instructions. The data registers included in the device are the
Boundary Data register, the IDCODE register, and the Bypass register.
This device can handle a 10 MHz TCK frequency for TDO and TDI.
Due to design constraints, the RST/ pin (system reset) always 3-states
the SCSI pins when it is asserted. Boundary scan logic does not control
this action, and this is not compliant with the specification. There are two
solutions that resolve this issue:
2-16Functional Description
1. Use the RST/ pin as a boundary scan compliance pin. When the pin
deasserts, the device is boundary scan compliant and when it
asserts, the device is noncompliant. To maintain compliance the
RST/ pin must be driven high.
2. When RST/ asserts during boundary scan testing the expected
output on the SCSI pins must be the HIGH-Z condition, and not what
is contained in the boundary scan data registers for the SCSI pin
output cells.
2.2.4 SCSI Loopback Mode
The LSI53C876 loopback mode allows testing of both initiator and target
functions and, in effect, lets the chip communicate with itself. When the
Loopback Enable bit is set in the SCSI Test Two (STEST2) register, bit 4,
the LSI53C876 allows control of all SCSI signals, whether the chip is
operating in the initiator or target mode. For more information on this
mode of operation, refer to the
Guide
.
2.2.5 Parity Options
The LSI53C876 implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures. Table 2.2 defines the bits that
are involved in parity control and observation. Table 2.3 describes the
parity control function of the Enable Parity Checking and Assert SCSI
Even Parity bits in the SCSI Control One (SCNTL1) register, bit 2.
Table 2.4 describes the options available when a parity error occurs.
Figure 2.2 shows where parity checking is done in the LSI53C876.
SCSI SCRIPTS Processors Programming
SCSI Functional Description2-17
Table 2.2Bits Used for Parity Control and Generation
BIt NameLocationDescription
Assert SATN/ on Parity
Errors
Enable Parity CheckingSCSI Control
Assert Even SCSI Parity SCSI Control
Disable Halton SATN/or
a Parity Error (Target
Mode Only)
Enable Parity Error
Interrupt
Parity ErrorSCSI Interrupt
Status of SCSI Parity
Signal
SCSI SDP1 SignalSCSI Status Two
SCSI Control
Zero (SCNTL0),
Bit 1
Zero (SCNTL0),
Bit 3
One (SCNTL1),
Bit 2
SCSI Control
One (SCNTL1),
Bit 5
SCSI Interrupt
Enable Zero
(SIEN0), Bit 0
Status Zero
(SIST0), Bit 0
SCSIStatusZero
(SSTAT0), Bit 0
(SSTAT2), Bit 0
Causes the LSI53C876 to automatically assert SATN/
when it detects a parity error while operating as an
initiator.
Enables the LSI53C876 to check for parity errors. The
LSI53C876 checks for odd parity.
Determines the SCSI parity sense generated by the
LSI53C876 to the SCSI bus.
Causes the LSI53C876 not to halt operations when a
parity error is detected in target mode.
Determines whether the LSI53C876 generates an
interrupt when it detects a SCSI parity error.
This status bit is set whenever the LSI53C876 detects
a parity error on the SCSI bus.
This status bit represents the active HIGH current state
of the SCSI SDP0 parity signal.
This bit represents the active HIGH current state of the
SCSI SDP1 parity signal.
Latched SCSI ParitySCSI Status Two
Master Parity Error
Enable
Master Data Parity Error DMA Status
Master Data Parity Error
Interrupt Enable
(SSTAT2), Bit 3
and SCSI Status
One (SSTAT1),
Bit 3
Chip Test Four
(CTEST4), Bit 3
(DSTAT), Bit 6
DMA Interrupt
Enable (DIEN),
Bit 6
2-18Functional Description
These bits reflect the SCSI odd parity signal
corresponding to the data latched into the SCSI Input
Data Latch (SIDL) register.
Enables parity checking during master data phases.
Set when the LSI53C876, as a PCI master, detects a
target device signaling a parity error during a data
phase.
By clearing this bit, a Master Data Parity Error does not
cause assertion of INTA/ (or INTB/), but the status bit
is set in the DMA Status (DSTAT) register.
Table 2.3SCSI Parity Control
EPCAESPDescription
00Does not check for parity errors. Parity is generated when sending
01Does not check for parity errors. Parity is generated when sending
10Checks for odd parity on SCSI data received. Parity is generated
11Checks for odd parity on SCSI data received. Parity is generated
1. Key:
EPC = Enable Parity Checking (bit 3, SCSI Control Zero (SCNTL0)).
ASEP = Assert SCSI Even Parity (bit 2, SCSI Control One (SCNTL1)).
SCSI data. Asserts odd parity when sending SCSI data.
SCSI data. Asserts even parity when sending SCSI data.
when sending SCSI data. Asserts odd parity when sending SCSI
data.
when sending SCSI data. Asserts even parity when sending SCSI
data.
Table 2.4SCSI Parity Errors and Interrupts
DPHPARDescription
00Halts when a parity error occurs in the target or initiator mode and
01Halts when a parity error occurs in the target mode and generates
does not generate an interrupt.
an interrupt in target or initiator mode.
10Does not halt in target mode when a parity error occurs until the
11Does not halt in target mode when a parity error occurs until the
Key:
DHP = Disable Halt on SATN/ or Parity Error (bit 5, SCSI Control One (SCNTL1).
PAR = Parity Error (bit 0, SCSI Interrupt Enable Zero (SIEN0).
end of the transfer. An interrupt is not generated.
end of the transfer. An interrupt is generated.
SCSI Functional Description2-19
Figure 2.2Parity Checking/Generation
Asynchronous
SCSI Send
PCI Interface**
X
DMA FIFO*
(32 Bits x 134)
SODL Register*
S
SCSI Interface**
X - Check parity
G - Generate 32-bit even PCI parity
S - Generate 8-bit odd SCSI parity
Asynchronous
SCSI Receive
PCI Interface**
DMA FIFO*
(32 Bits x 134)
SIDL Register*
SCSI Interface**
2.2.6 DMA FIFO
The DMA FIFO is 4 bytes wide by 134 transfers deep. The DMA FIFO is
illustrated in Figure 2.3. The default DMA FIFO size is 88 bytes to assure
compatibility with older products in the LSI53C8XX family.
The DMA FIFO size may be set to 536 bytes by setting the DMA FIFO
Size bit, bit 5, in the Chip Test Five (CTEST5) register.
Synchronous
SCSI Send
PCI Interface**
G
(32 Bits x 134)
SODL Register*
X
SODR Register*
SCSI Interface**
X
DMA FIFO*
S
Synchronous
SCSI Receive
PCI Interface**
G
DMA FIFO*
(32 Bits x 134)
X
SCSI FIFO*
(8 or 16 Bits x 16)
X
SCSI Interface**
* = No parity protection
** = Parity protected
Figure 2.3DMA FIFO Sections
134
134
Transfers
Transfers
Deep
Deep
2-20Functional Description
.
.
.
8 Bits
8 Bits
Byte Lane 3
Byte Lane 3
8 Bits
8 Bits
Byte Lane 2
Byte Lane 2
32 Bytes Wide
32 Bytes Wide
8 Bits
8 Bits
Byte Lane 1
Byte Lane 1
8 Bits
8 Bits
Byte Lane 0
Byte Lane 0
.
.
.
.
.
.
2.2.6.1 Data Paths
The LSI53C876 automatically supports misaligned DMA transfers. A
536-byte FIFO allows the LSI53C876 to support 2, 4, 8, 16, 32, 64, or
128 Dword bursts across the PCI bus interface.
The data path through the LSI53C876 depends on whether data is being
moved into or out of the chip, and whether SCSI data is being transferred
asynchronously or synchronously.
Figure 2.4 shows how data is moved to/from the SCSI bus in each of the
different modes.
The following steps determine if any bytes remain in the data path when
the chip halts an operation:
Asynchronous SCSI Send –
Step 1. If the DMA FIFO size is set to 88 bytes, look at the DMA FIFO
(DFIFO) and DMA Byte Counter (DBC) registers and calculate
if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DMA Byte
Counter (DBC) register from the 7-bit value of the DMA FIFO
(DFIFO) register. AND the result with 0x7F for a byte count
between 0 and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the Chip
Test Five (CTEST5) register), subtract the 10 least significant
bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO (DFIFO) register. AND the result with 0x3FF
for a byte count between 0 and 536.
Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status
Two (SSTAT2) registers to determine if any bytes are left in the
SCSI Output Data Latch (SODL) register. If bit 5 is set in the
SSTAT0 or SSTAT2 register, then the least significant byte or
the most significant byte in the SCSI Output Data Latch (SODL)
register is full, respectively. Checking this bit also reveals bytes
left in the SCSI Output Data Latch (SODL) register from a
Chained Move operation with an odd byte count.
SCSI Functional Description2-21
Synchronous SCSI Send –
Step 1. If the DMA FIFO size is set to 88 bytes, look at the DMA FIFO
(DFIFO) and DMA Byte Counter (DBC) registers and calculate
if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DMA Byte
Counter (DBC) register from the 7-bit value of the DMA FIFO
(DFIFO) register. AND the result with 0x7F for a byte count
between 0 and 88.
If the DMA FIFO size is set to 536 bytes (bit 5 of the Chip Test
Five (CTEST5) register it set), subtract the 10 least significant
bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO (DFIFO) register. AND the result with 0x3FF
for a byte count between 0 and 536.
Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status
Two (SSTAT2) registers to determine if any bytes are left in the
SCSI Output Data Latch (SODL) register. If bit 5 is set in the
SSTAT0 or SSTAT2 register, then the least significant byte or
the most significant byte in the SCSI Output Data Latch (SODL)
register is full, respectively. Checking this bit also reveals bytes
left in the SCSI Output Data Latch (SODL) register from a
Chained Move operation with an odd byte count.
Step 3. Read bit 6 in the SCSI Status Zero (SSTAT0) and SCSI Status
Two (SSTAT2) registers to determine if any bytes are left in the
SODR register. If bit 6 is set in the SCSI Status Zero (SSTAT0)
or SCSI Status Two (SSTAT2) register, then the least significant
byte or the most significant byte in the SODR register is full,
respectively.
Asynchronous SCSI Receive –
Step 1. If the DMA FIFO size is set to 88 bytes, look at the DMA FIFO
(DFIFO) and DMA Byte Counter (DBC) registers and calculate
if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DMA Byte
Counter (DBC) register from the 7-bit value of the DMA FIFO
(DFIFO) register. AND the result with 0x7F for a byte count
between 0 and 88.
2-22Functional Description
If the DMA FIFO size is set to 536 bytes (bit 5 of the Chip Test
Five (CTEST5) register is set), subtract the 10 least significant
bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO (DFIFO) register. AND the result with 0x3FF
for a byte count between 0 and 536.
Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) and SCSI Status
Two (SSTAT2) register to determine if any bytes are left in the
SCSI Input Data Latch (SIDL) register. If bit 7 is set in the
SSTAT0 or SSTAT2, then the least significant byte or the most
significant byte is full, respectively.
Step 3. If any wide transfers have been performed using the Chained
Move instruction, read the Wide SCSI Receive bit (SCSI
Control Two (SCNTL2), bit 0) to determine whether a byte is left
in the SCSI Wide Residue (SWIDE) register.
Synchronous SCSI Receive –
Step 1. If the DMA FIFO size is set to 88 bytes, subtract the seven least
significant bits of the DMA Byte Counter (DBC) register from
the 7-bit value of the DMA FIFO (DFIFO) register. AND the
result with ox7F for a byte count between 0 and 88.
If the DMA FIFO size is set to 536 bytes (bit 5 of the Chip Test
Five (CTEST5) register is set), subtract the 10 least significant
bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO (DFIFO) register. AND the result with 0x3FF
for a byte count between 0 and 536.
Step 2. Read the SCSI Status One (SSTAT1) register and examine bits
[7:4], the binary representation of the number of valid bytes in
the SCSI FIFO, to determine if any bytes are left in the SCSI
FIFO.
Step 3. If any wide transfers have been performed using the Chained
Move instruction, read the Wide SCSI Receive bit (SCSI
Control Two (SCNTL2), bit 0) to determine whether a byte is left
in the SCSI Wide Residue (SWIDE) register.
SCSI Functional Description2-23
Figure 2.4 shows how data is moved to/from the SCSI bus in each of the
different modes.
Figure 2.4LSI53C876 Host Interface SCSI Data Paths
Asynchronous
SCSI Send
PCI Interface
DMA FIFO
(32 Bits x 134)
SODL Register
SCSI Interface
Asynchronous
SCSI Receive
PCI Interface
DMA FIFO
(32 Bits x 134)
SIDL Register
SCSI Interface
2.2.7 SCSI Bus Interface
All SCSI signals are active LOW. The LSI53C876 contains the SE output
drivers and can be connected directly to the SCSI bus. Each output is
isolated from the power supply to ensure that a powered-down
LSI53C876 has no effect on an active SCSI bus (CMOS “voltage
feed-through” phenomena). TolerANT technology provides signal filtering
at the inputs of SREQ/ and SACK/ to increase immunity to signal
reflections.
SWIDE Register
Synchronous
SCSI Send
PCI Interface
DMA FIFO
(32 Bits x 134)
SODL Register
SODR Register
SCSI Interface
Synchronous
SCSI Receive
PCI Interface
DMA FIFO
(32 Bits x 134)
SWIDE Register
SCSI FIFO
(8 or 16 Bits x 16)
SCSI Interface
2.2.7.1 Differential Mode
In differential mode, the SDIR[15:0], SDIRP[1:0], IGS, TGS, RSTDIR,
BSYDIR, and SELDIR signals control the direction of external differential
pair transceivers. The LSI53C876 is placed in differential mode by setting
the DIF bit, bit 5 of the SCSI Test Two (STEST2) register (0x4E). Setting
this bit 3-states the BSY/, SEL/, and RST/ pads so they can be used as
pure input pins. When TolerANT active negation is enabled, the
recommended resistor value on the REQ/, ACK/, MSG/, C_D/, I_O/,
2-24Functional Description
ATN/, SD[15:0], and SDP[1:0]/ signals is 1.5 kΩ. In addition to the
standard SCSI lines, the following signals defined in Table 2.5 are used
during differential operation by the LSI53C876:
Table 2.5Differential Mode
SignalFunction
BSYDIR, SELDIR,
RSTDIR
SDIR[15:0],
SDIRP[1:0]
IGSActive HIGH signal used to control direction of the differential driver for initiator
TGSActive HIGH signal used to control direction of the differential drivers for target
DIFFSENSInput to the LSI53C876 used to detect the presence of an SE device on a
Active HIGH signals used to enable the differential drivers as outputs for SCSI
signals BSY/, SEL/, and RST/, respectively.
Active HIGH signals used to control direction of the differential drivers for SCSI
data and parity lines, respectively.
group signals ATN/ and ACK/.
group signals MSG/, C/D/, I/O/, and REQ/.
differential system. If a logical zero is detected on this pin, then it is assumed
that an SE device is on the bus and all SCSI outputs will be 3-stated to avoid
damage to the transceiver.
See Figure 2.5 for an example differential wiring diagram, in which the
LSI53C876 is connected to the TI SN75976A differential transceiver. The
recommended value of the pull-up resistor on the REQ/, ACK/, MSG/,
C/D/, I/O/, ATN/, SD[15:0]/, SDP0/, and SDP1/ lines is 680 Ω when the
Active Negation portion of LSI Logic TolerANT technology is not enabled.
When TolerANT technology is enabled, the recommended resistor value
on the REQ/, ACK/, SD[7:0]/, and SDP0/ signals is 1.5 kΩ. The electrical
characteristics of these pins change when TolerANT is enabled,
permitting a higher resistor value.
To interface the LSI53C876 to the SN75976A, connect the DIR pins, as
well as IGS and TGS, of the LSI53C876 directly to the transceiver
enables (nDE/RE/). These signals control the direction of the channels
on the SN75976A.
The SCSI bidirectional control and data pins (SD[15:0]/, SDP0/, SDP1/,
REQ/, ACK/, MSG/, I_O/, C_D/, and ATN/) of the LSI53C876 connect to
the bidirectional data pins (nA) of the SN75976A with a pull-up resistor.
The three remaining pins, SEL/, BSY/, and RST/ are connected to the
SN75976A with a pull-down resistor. The pull-down resistors are required
SCSI Functional Description2-25
when the pins (nA) of the SN75976A are configured as inputs. When the
data pins are inputs, the resistors provide a bias voltage to both the
LSI53C876 pins (SEL/, BSY/, and RST/) and the SN75976A data pins.
Because the SEL/, BSY/, and RST/ pins on the LSI53C876 are inputs
only, this configuration allows for the SEL/, BSY/, and RST/ SCSI signals
to be asserted on the SCSI bus. The differential pairs on the SCSI bus
are reversed when connected to the SN75976A, due to the active low
nature of the SCSI bus.
The pull-up value should be no lower than the transceiver IOLcan
tolerate, but not so high as to cause RC timing problems.
Note:Use the TI SN75976A differential transceivers to achieve
Ultra SCSI transfer rates.
8-Bit/16-Bit SCSI and the Differential Interface – In an 8-bit SCSI
bus, the SD[15:8] pins on the LSI53C876 should be pulled up with a
1.5 kΩ. resistor or terminated like the rest of the SCSI bus lines. This is
very important, as errors may occur during reselection if these lines are
left floating.
The terminator networks provide the biasing needed to pull signals to an
inactive voltage level, and to match the impedance seen at the end of
the cable with the characteristic impedance of the cable. Terminators
must be installed at the extreme ends of the SCSI chain, and only at the
ends. No system should ever have more or less than two terminators
installed and active. SCSI host adapters should provide a means of
accommodating terminators. There should be a means of disabling
termination.
SE cables can use a 220 Ω pull-up to the terminator power supply
(Term Power) line and a 330 Ω pull-down to ground. Because of the
high-performance nature of the LSI53C876, regulated (or active)
termination is recommended. Figure 2.6 shows a Unitrode active
terminator. For additional information, refer to the SCSI-2 Specification.
TolerANT technology active negation can be used with either termination
network.
2-28Functional Description
Note:If the LSI53C876 is to be used in a design with only an
8-bit SCSI bus, all 16 data lines must still be terminated or
pulled high. Active termination is required for Wide Ultra
SCSI synchronous transfers.
The LSI53C876 can transfer synchronous SCSI data in both initiator and
target modes. The SCSI Transfer (SXFER) register controls both the
synchronous offset and the transfer period. It may be loaded by the CPU
before SCRIPTS execution begins, from within SCRIPTS using a Table
Indirect I/O instruction, or with a Read-Modify-Write instruction.
The LSI53C876 can receive data from the SCSI bus at a synchronous
transfer period as short as 50 ns, regardless of the transfer period used
to send data. The chip can receive data at one-fourth of the divided
SCLK frequency. Depending on the SCLK frequency, the negotiated
transfer period, and the synchronous clock divider, the chip can send
synchronous data at intervals as short as 50 ns for Ultra SCSI, 100 ns
for Fast SCSI, and 200 ns for SCSI-1.
2.2.8.1 Determining the Data Transfer Rate
Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C876. Following is a brief description of the bits.
Figure 2.7 illustrates the clock division factors used in each register, and
the role of the register bits in determining the transfer rate.
2.2.8.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0])
The SCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the synchronous SCSI control logic.
The output from this divider controls the rate at which data can be
received; this rate must not exceed 80 MHz. The receive rate is
one-fourth of the divider output.
2.2.8.3 SCSI Control Three (SCNTL3) Register, Bits [2:0] (CCF[2:0]
The CCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the asynchronous SCSI controller
logic. This divider must be set according to the input clock frequency in
the table.
2.2.8.4 SCSI Transfer (SXFER) Register, Bits [7:5] (TP[2:0])
The TP[2:0] bits determine the SCSI synchronous transfer period when
sending synchronous SCSI data in either initiator or target mode.
2-30Functional Description
2.2.8.5 Wide Ultra SCSI Synchronous Transfers
Wide Ultra SCSI is an extension of current Fast SCSI synchronous
transfer specifications. It allows synchronous transfer periods to be
negotiated down as low as 50 ns, which is half the 100 ns period allowed
under Fast SCSI. This allows a maximum transfer rate of 40 Mbytes/s on
a 16-bit SCSI bus. The LSI53C876 requires that the 40 MHz clock is
doubled by the internal clock doubler (see the SCSI Test One (STEST1)
register description) to perform Wide Ultra SCSI transfers. In addition,
the following bit values affect the chip’s ability to support Wide Ultra SCSI
synchronous transfer rates:
•Clock Conversion Factor bits, SCSI Control Three (SCNTL3) register
bits [2:0] and Synchronous Clock Conversion Factor bits, SCNTL3
register bits [6:4]. These fields now support a value of 101 (binary),
allowing the SCLK frequency to be divided down by 4. This allows
systems with a 40 MHz clock to operate at Fast SCSI-2 transfer rates
as well as Wide Ultra SCSI rates, if needed.
•Wide Ultra SCSI Mode Enable bit, SCSI Control Three (SCNTL3)
register, bit 7. Setting this bit enables Wide Ultra SCSI synchronous
transfers in systems that have a 40 MHz clock using the internal
clock doubler.
•TolerANT Enable bit, SCSI Test Three (STEST3) register, bit 7.
Setting this bit enables active negation.
SCSI Functional Description2-31
Figure 2.7Determining the Synchronous Transfer Rate
Migrating an existing SCSI design from Fast SCSI to Wide Ultra SCSI
requires minor software modifications as well as consideration for some
hardware design guidelines. Since Wide Ultra SCSI is based on existing
SCSI standards, it can use existing software programs as long as the
software is able to negotiate for Wide Ultra SCSI synchronous transfer
rates.
In the area of hardware, the primary area of concern in SE systems is
to maintain signal integrity at high data transfer rates. To assure reliable
operation at Wide Ultra SCSI transfer speeds, follow the system design
parameters recommended in the Wide Ultra SCSI Parallel Interface draft
standard. Chapter 6, “Electrical Characteristics,” contains Wide Ultra
2-32Functional Description
SCSI timing information. In addition to the guidelines in the draft
standard, make the following software and hardware adjustments to
accommodate Wide Ultra SCSI transfers:
•Set the Wide Ultra SCSI Enable bit to enable Wide Ultra SCSI
transfers.
•Set the TolerANT Enable bit, bit 7 in the SCSI Test Three (STEST3)
register, whenever the Wide Ultra SCSI Enable bit is set.
•Do not extend the SREQ/SACK filtering period with SCSI Test Two
(STEST2), bit 1.
•Use a 40 MHz SCSI clock with an internal clock doubler.
2.2.10 Interrupt Handling
The SCRIPTS processors in the LSI53C876 performs most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C876.
2.2.10.1 Polling and Hardware Interrupts
The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit set that
indicates an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C876 asserts the Interrupt Request (INTA/ or INTB/) line that
interrupts the microprocessor, causing the microprocessor to execute an
interrupt service routine. A hybrid approach would use hardware
interrupts for long waits, and use polling for short waits.
2.2.10.2 Registers
The registers in the LSI53C876 that are used for detecting or defining
interrupts are the Interrupt Status (ISTAT), SCSI Interrupt Status Zero
(SIST0), SCSI Interrupt Status One (SIST1), DMA Status (DSTAT), SCSI
Interrupt Enable Zero (SIEN0), SCSI Interrupt Enable One (SIEN1), DMA
Control (DCNTL), and DMA Interrupt Enable (DIEN).
SCSI Functional Description2-33
ISTAT – The Interrupt Status (ISTAT) is the only register that can be
accessed as a slave during SCRIPTS operation. Therefore, it is the
register that is polled when polled interrupts are used. It is also the first
register that should be read after the INTA/ (or INTB/) pin is asserted in
association with a hardware interrupt. The INTF (Interrupt-on-the-Fly) bit
should be the first interrupt serviced. It must be written to one to be
cleared. This interrupt must be cleared before servicing any other
interrupts.
If the SIP bit in the Interrupt Status (ISTAT) register is set, then a
SCSI-type interrupt has occurred and the SCSI Interrupt Status Zero
(SIST0) and SCSI Interrupt Status One (SIST1) registers should be read.
If the DIP bit in the Interrupt Status (ISTAT) register is set, then a
DMA-type interrupt has occurred and the DMA Status (DSTAT) register
should be read.
SCSI-type and DMA-type interrupts may occur simultaneously, so in
some cases both SIP and DIP may be set.
SIST0 and SIST1 – The SCSI Interrupt Status Zero (SIST0) and SCSI
Interrupt Status One (SIST1) registers contain the SCSI-type interrupt
bits. Reading these registers determines which condition or conditions
caused the SCSI-type interrupt, and clears that SCSI interrupt condition.
If the LSI53C876 is receiving data from the SCSI bus and a fatal interrupt
condition occurs, the chip attempts to send the contents of the DMA
FIFO to memory before generating the interrupt.
If the LSI53C876 is sending data to the SCSI bus and a fatal SCSI
interrupt condition occurs, data could be left in the DMA FIFO. Because
of this the DMA FIFO Empty (DFE) bit in DMA Status (DSTAT) should be
checked.
If this bit is cleared, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI
FIFO) bits before continuing. The CLF bit is bit 2 in Chip Test Three
(CTEST3). The CSF bit is bit 1 in SCSI Test Three (STEST3).
DSTAT – The DMA Status (DSTAT) register contains the DMA-type
interrupt bits. Reading this register determines which condition or
conditions caused the DMA-type interrupt, and clears that DMA interrupt
condition. Bit 7 in DMA Status (DSTAT), DFE, is purely a status bit; it will
not generate an interrupt under any circumstances and is not cleared
2-34Functional Description
when read. DMA interrupts flush neither the DMA nor SCSI FIFOs before
generating the interrupt, so the DFE bit in the DMA Status (DSTAT)
register should be checked after any DMA interrupt.
If the DFE bit is cleared, then the FIFOs must be cleared by setting the
CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits, or flushed by
setting the FLF (Flush DMA FIFO) bit.
SIEN0 and SIEN1 – The SCSI Interrupt Enable Zero (SIEN0) and SCSI
Interrupt Enable One (SIEN1) registers are the interrupt enable registers
for the SCSI interrupts in SCSI Interrupt Status Zero (SIST0) and SCSI
Interrupt Status One (SIST1).
DIEN – The DMA Interrupt Enable (DIEN) register is the interrupt enable
register for DMA interrupts in DMA Status (DSTAT).
DCNTL – When bit 1 in this register is set, the INTA/ (or INTB/) pin is
not asserted when an interrupt condition occurs. The interrupt is not lost
or ignored, but merely masked at the pin. Clearing this bit when an
interrupt is pending immediately causes the INTA/ (or INTB/) pin to
assert. As with any register other than Interrupt Status (ISTAT), this
register cannot be accessed except by a SCRIPTS instruction during
SCRIPTS execution.
2.2.10.3 Fatal vs. Nonfatal Interrupts
A fatal interrupt, as the name implies, always causes the SCRIPTS to
stop running. All nonfatal interrupts become fatal when they are enabled
by setting the appropriate interrupt enable bit. Interrupt masking is
discussed Section 2.2.10.4, “Masking.” All DMA interrupts (indicated by
the DIP bit in Interrupt Status (ISTAT) and one or more bits in DMA
Status (DSTAT) being set) are fatal.
Some SCSI interrupts (indicated by the SIP bit in the Interrupt Status
(ISTAT) and one or more bits in SCSI Interrupt Status Zero (SIST0) or
SCSI Interrupt Status One (SIST1) being set) are nonfatal.
When the LSI53C876 is operating in the Initiator mode, only the Function
Complete (CMP), Selected (SEL), Reselected (RSL), General Purpose
Timer Expired (GEN), and Handshake-to-Handshake Timer Expired
(HTH) interrupts are nonfatal.
SCSI Functional Description2-35
2.2.10.4 Masking
When operating in Target mode CMP, SEL, RSL, Target mode: SATN/
active (M/A), GEN, and HTH are nonfatal. Refer to the description for the
Disable Halt on a Parity Error or SATN/ active (Target Mode Only) (DHP)
bit in the SCSI Control One (SCNTL1) register to configure the chip’s
behavior when the SATN/ interrupt is enabled during Target mode
operation. The Interrupt-on-the-Fly interrupt is also nonfatal, since
SCRIPTS can continue when it occurs.
The reason for nonfatal interrupts is to prevent SCRIPTS from stopping
when an interrupt occurs that does not require service from the CPU.
This prevents an interrupt when arbitration is complete (CMP set), when
the LSI53C876 is selected or reselected (SEL or RSL set), when the
initiator asserts ATN (target mode: SATN/ active), or when the General
Purpose or Handshake-to-Handshaketimers expire. These interrupts are
not needed for events that occur during high-level SCRIPTS operation.
Masking an interrupt means disabling or ignoring that interrupt. Interrupts
can be masked by clearing bits in the SCSI Interrupt Enable Zero
(SIEN0) and SCSI Interrupt Enable One (SIEN1) (for SCSI interrupts)
registers or DIEN (for DMA interrupts) register. How the chip responds
to masked interrupts depends on: whether polling or hardware interrupts
are being used; whether the interrupt is fatal or nonfatal; and whether the
chip is operating in the Initiator or Target mode.
If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS
do not stop, the appropriate bit in the SCSI Interrupt Status Zero (SIST0)
or SCSI Interrupt Status One (SIST1) is still set, the SIP bit in the ISTAT
is not set, and the INTA/ (or INTB/) pin is not asserted. See Section
2.2.10.3, “Fatal vs. Nonfatal Interrupts,” for a list of the nonfatal interrupts.
If a fatal interrupt is masked and that condition occurs, then the SCRIPTS
still stop, the appropriate bit in the DMA Status (DSTAT), SCSI Interrupt
Status Zero (SIST0),orSCSI Interrupt Status One (SIST1) register is
set, and the SIP or DIP bits in the ISTAT is set, but the INTA/ (or INTB/)
pin is not asserted.
2-36Functional Description
When the chip is initialized, enable all fatal interrupts if you are using
hardware interrupts. If a fatal interrupt is disabled and that interrupt
condition occurs, the SCRIPTS halts and the system never knows it
unless it times out and checks the ISTAT after a certain period of
inactivity.
If you are polling the Interrupt Status (ISTAT) instead of using hardware
interrupts, then masking a fatal interrupt makes no difference since the
SIP and DIP bits in the ISTAT inform the system of interrupts, not the
INTA/ (or INTB/) pin.
Masking an interrupt after INTA/ (or INTB/) is asserted does not cause
deassertion of INTA/ (or INTB/).
2.2.10.5 Stacked Interrupts
The LSI53C876 stacks interrupts if they occur one after the other. If the
SIP or DIP bits in the Interrupt Status (ISTAT) register are set (first level),
then there is already at least one pending interrupt, and any future
interrupts are stacked in extra registers behind the SCSI Interrupt Status
Zero (SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) registers (second level). When two interrupts have occurred and
the two levels of the stack are full, any further interrupts set additional
bits in the extra registers behind SIST0, SIST1, and DSTAT. When the
first level of interrupts are cleared, all the interrupts that came in
afterward move into the SIST0, SIST1, and DSTAT. After the first interrupt
is cleared by reading the appropriate register, the INTA/ (or INTB/) pin is
deasserted for a minimum of three CLKs; the stacked interrupts move
into the SIST0, SIST1, or DSTAT; and the INTA/ (or INTB/) pin is
asserted once again.
Since a masked nonfatal interrupt does not set the SIP or DIP bits,
interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in SIST0, but does not assert the INTA/ (or INTB/) pin. Since
no interrupt is generated, future interrupts move right into the SCSI
Interrupt Status Zero (SIST0) or SCSI Interrupt Status One (SIST1)
instead of being stacked behind another interrupt. When another
condition occurs that generates an interrupt, the bit corresponding to the
earlier masked nonfatal interrupt is still set.
SCSI Functional Description2-37
A related situation to interrupt stacking is when two interrupts occur
simultaneously. Since stacking does not occur until the SIP or DIP bits
are set, there is a small timing window in which multiple interrupts can
occur but are not stacked. These could be multiple SCSI interrupts (SIP
set), multiple DMA interrupts (DIP set), or multiple SCSI and multiple
DMA interrupts (both SIP and DIP set).
As previously mentioned, DMA interrupts do not attempt to flush the
FIFOs before generating the interrupt. It is important to set either the
Clear DMA FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA
interrupt occurs and the DMA FIFO Empty (DFE) bit is not set. This is
because any future SCSI interrupts are not posted until the DMA FIFO
is cleared of data. These “locked out” SCSI interrupts are posted as soon
as the DMA FIFO is empty.
2.2.10.6 Halting in an Orderly Fashion
When an interrupt occurs, the LSI53C876 attempts to halt in an orderly
fashion.
•If the interrupt occurs in the middle of an instruction fetch, the fetch
is completed, except in the case of a Bus Fault. Execution does not
begin, but the DMA SCRIPTS Pointer (DSP) points to the next
instruction since it is updated when the current instruction is fetched.
•If the DMA direction is a write to memory and a SCSI interrupt
occurs, the LSI53C876 attempts to flush the DMA FIFO to memory
before halting. Under any other circumstances only the current cycle
is completed before halting, so the DFE bit in DMA Status (DSTAT)
register should be checked to see if any data remains in the DMA
FIFO.
•SCSI SREQ/SACK handshakes that have begun are completed
before halting.
•The LSI53C876 attempts to clean up any outstanding synchronous
offset before halting.
•In the case of Transfer Control Instructions, once instruction
execution begins it continues to completion before halting.
•If the instruction is a JUMP/CALL WHEN/IF <phase>, the DMA
SCRIPTS Pointer (DSP) is updated to the transfer address before
halting.
•All other instructions may halt before completion.
2-38Functional Description
2.2.10.7 Sample Interrupt Service Routine
The following is a sample of an interrupt service routine for the
LSI53C876. It can be repeated if polling is used, or should be called
when the INTA/ (or INTB/) pin is asserted during hardware interrupts.
1. Read Interrupt Status (ISTAT).
2. If the INTF bit is set, it must be written to a one to clear this status.
3. If only the SIP bit is set, read SCSI Interrupt Status Zero (SIST0) and
SCSI Interrupt Status One (SIST1) to clear the SCSI interrupt
condition and get the SCSI interrupt status. The bits in the SIST0
and SIST1 tell which SCSI interrupts occurred and determine what
action is required to service the interrupts.
4. If only the DIP bit is set, read the DMA Status (DSTAT) to clear the
interrupt condition and get the DMA interrupt status. The bits in the
DSTAT tells which DMA interrupts occurred and determine what
action is required to service the interrupts.
5. If both the SIP and DIP bits are set, read SCSI Interrupt Status Zero
(SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) to clear the SCSI and DMA interrupt condition and get the
interrupt status. If using 8-bit reads of the SIST0, SIST1, and DSTAT
registers to clear interrupts, insert a 12 CLK delay between the
consecutive reads to ensure that the interrupts clear properly. Both
the SCSI and DMA interrupt conditions should be handled before
leaving the interrupt service routine. It is recommended that the DMA
interrupt is serviced before the SCSI interrupt, because a serious
DMA interrupt condition could influence how the SCSI interrupt is
acted upon.
6. When using polled interrupts, go back to Step 1 before leaving the
interrupt service routine, in case any stacked interrupts moved in
when the first interrupt was cleared. When using hardware interrupts,
the INTA/ (or INTB/) pin is asserted again if there are any stacked
interrupts. This should cause the system to re-enter the interrupt
service routine.
SCSI Functional Description2-39
2.2.11 Chained Block Moves
Since the LSI53C876 has the capability to transfer 16-bit wide SCSI
data, a unique situation occurs when dealing with odd bytes. The
chained move (CHMOV) SCRIPTS instruction along with the Wide SCSI
Send (WSS) and Wide SCSI Receive (WSR) bits in the SCSI Control
Two (SCNTL2) register are used to facilitate these situations. The
Chained Block Move instruction is illustrated in Figure 2.8.
Figure 2.8Block Move and Chained Block Move Instructions
Host MemorySCSI Bus
0x03 0x02 0x01 0x00
0x07 0x06 0x05 0x04
0x0B 0x0A 0x09 0x08
0x0F 0x0E 0x0D 0x0C
0x13 0x12 0x11 0x10
32 Bits16 Bits
00
04
08
0C
10
0x04 0x03
0x06 0x05
0x09 0x07
0x0B 0x0A
0x0D 0x0C
CHMOV 5, 3 when Data_Out
Moves five bytes from address 0x03 in the host memory to the SCSI bus.
Bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in
the low-order byte of the SCSI Output Data Latch (SODL) register and
is combined with the first byte of the following MOVE instruction.
Move 5, 9 when Data_Out
Moves five bytes from address 0x09 in the host memory to the SCSI bus.
2-40Functional Description
2.2.11.1 Wide SCSI Send Bit
The WSS bit is set whenever the SCSI controller is sending data
(Data-Out for initiator or Data-In for target), and the controller detects a
partial transfer at the end of a chained Block Move SCRIPTS instruction
(this flag is not set if a normal Block Move instruction is used). Under this
condition, the SCSI controller does not send the low-order byte of the last
partial memory transfer across the SCSI bus. Instead, the low-order byte
is temporarily stored in the lower byte of the SCSI Output Data Latch
(SODL) register and the WSS flag is set. The hardware uses the WSS
flag to determine what behavior must occur at the start of the next data
send transfer. When the WSS flag is set at the start of the next transfer,
the first byte (the high-order byte) of the next data send transfer is
“married” with the stored low-order byte in the SCSI Output Data Latch
(SODL) register; and the two bytes are sent out across the bus,
regardless of the type of Block Move instruction (normal or chained). The
flag is automatically cleared when the “married” word is sent. The flag is
alternately cleared through SCRIPTS or by the microprocessor. Also, the
microprocessor or SCRIPTS can use this bit for error detection and
recovery purposes.
2.2.11.2 Wide SCSI Receive Bit
The WSR bit is set whenever the SCSI controller is receiving data
(Data-In for initiator or Data-Out for target) and the controller detects a
partial transfer at the end of a block move or chained block move
SCRIPTS instruction. When WSR is set, the high order byte of the last
SCSI bus transfer is not transferred to memory. Instead, the byte is
temporarily stored in the SCSI Wide Residue (SWIDE) register. The
hardware uses the WSR bit to determine what behavior must occur at
the start of the next data receive transfer. The bit is automatically cleared
at the start of the next data receive transfer. The bit can alternatively be
cleared by the microprocessor or through SCRIPTS. Also, the
microprocessor or SCRIPTS can use this bit for error detection and
recovery purposes.
2.2.11.3 SWIDE Register
This register stores data for partial byte data transfers. For receive data,
the SCSI Wide Residue (SWIDE) register holds the high-order byte of a
partial SCSI transfer that has not yet been transferred to memory. This
SCSI Functional Description2-41
stored data may be a residue byte (and therefore ignored) or it may be
valid data that is transferredto memory at the beginning of the next Block
Move instruction.
2.2.11.4 SODL Register
For send data, the low-order byte of the SCSI Output Data Latch (SODL)
register holds the low-order byte of a partial memory transfer which has
not yet been transferred across the SCSI bus. This stored data is usually
“married” with the first byte of the next data send transfer, and both bytes
are sent across the SCSI bus at the start of the next data send block
move command.
2.2.11.5 Chained Block Move SCRIPTS Instruction
A chained Block Move SCRIPTS instruction is primarily used to transfer
consecutive data send or data receive blocks. Using the chained Block
Move instruction facilitates partial receive transfers and allows correct
partial send behavior without additional opcode overhead. Behavior of
the chained Block Move instruction varies slightly for sending and
receiving data.
For receive data (Data-In for initiator or Data-Out for target), a chained
Block Move instruction indicates that if a partial transfer occurred at the
end of the instruction, the WSR flag is set. The high-order byte of the
last SCSI transfer is stored in the SCSI Wide Residue (SWIDE) register
rather than transferred to memory. The contents of the SCSI Wide
Residue (SWIDE) register should be the first byte transferred to memory
at the start of the chained Block Move data stream. Since the byte count
always represents data transfers to/from memory (as opposed to the
SCSI bus), the byte transferred out of the SCSI Wide Residue (SWIDE)
register is one of the bytes in the byte count. If the WSR bit is cleared
when a receive data chained Block Move instruction is executed, the data
transfer occurs similar to that of the regular Block Move instruction.
Whether the WSR bit is set or cleared, when a normal block move
instruction is executed, the contents of the SCSI Wide Residue (SWIDE)
register are ignored and the transfer takes place normally. For “N”
consecutive wide data receive Block Move instructions, the 2nd through
the Nth Block Move instructions should be chained block moves.
2-42Functional Description
For send data (Data-Out for initiator or Data-In for target), a chained
Block Move instruction indicates that if a partial transfer terminates the
chained block move instruction, the last low-order byte (the partial
memory transfer) should be stored in the lower byte of the SCSI Output
Data Latch (SODL) register and not sent across the SCSI bus. Without
the chained Block Move instruction, the last low-order byte would be sent
across the SCSI bus. The starting byte count represents data bytes
transferred from memory but not to the SCSI bus when a partial transfer
exists. For example, if the instruction is an Initiator chained Block Move
Data Out of five bytes (and WSS is not previously set), five bytes are
transferred out of memory to the SCSI controller, four bytes are
transferred from the SCSI controller across the SCSI bus, and one byte
is temporarily stored in the lower byte of the SCSI Output Data Latch
(SODL) register waiting to be married with the first byte of the next Block
Move instruction. Regardless of whether a chained Block Move or normal
Block Move instruction is used, if the WSS bit is set at the start of a data
send command, the first byte of the data send command is assumed to
be the high-order byte and is “married” with the low-order byte stored in
the stored in the lower byte of the SCSI Output Data Latch (SODL)
register before the two bytes are sent across the SCSI bus. For “N”
consecutive wide data send Block Move commands, the first through the
(Nth – 1) Block Move instructions should be Chained Block Moves.
2.3 Parallel ROM Interface
The LSI53C876 supports up to one megabyte of external memory in
binary increments from 16 Kbytes, to allow the use of expansion ROM
for add-in PCI cards. Both functions of the device share the ROM
interface. This interface is designed for low speed operations such as
downloading instruction code from ROM; it is not intended for dynamic
activities such as executing instructions.
System requirements include the LSI53C876, two or three external 8-bit
address holding registers (HCT273 or HCT374), and the appropriate
memory device. The 4.7 kΩ pull-down resistors on the MAD bus require
HC or HCT external components to be used. If in-system Flash ROM
updates are required, a 7406 (high voltage open collector inverter), a
MTD4P05, and several passive components are also needed. The
memory size and speed is determined by pull-down resistors on the
8-bit bidirectional memory bus at power-up. The LSI53C876 senses this
Parallel ROM Interface2-43
bus shortly after the release of the Reset signal and configures the ROM
Base Address register and the memory cycle state machines for the
appropriate conditions.
The external memory interface works with a variety of ROM sizes and
speeds. An example set of interface drawings is in Appendix B, “External
Memory Interface Diagram Examples.”
The LSI53C876 supports a variety of sizes and speeds of expansion
ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of
pins MAD[3:1] allows the user to define how much external memory is
available to the LSI53C876. Table 2.6 shows the memory space
associated with the possible values of MAD[3:1]. The MAD[3:1] pins are
fully defined in Chapter 3, “Signal Descriptions.”
To use one of the configurations mentioned above in a host adapter
board design, put 4.7 kΩ pull-down resistors on the MAD pins
corresponding to the available memory space. For example, to connect
to a 32 Kbytes external ROM, use pull-downs on MAD[3] and MAD[2]. If
the external memory interface is not used, then no external resistors are
necessary since there are internal pull-ups on the MAD bus. The internal
pull-up resistors are disabled when external pull-down resistors are
detected, to reduce current drain.
2-44Functional Description
The LSI53C876 allows the system to determine the size of the available
external memory using the Expansion ROM Base Address register in
PCI configuration space. For more information on how this works, refer
to the PCI specification or the Expansion ROM Base Address register
description in Chapter 4, “Registers.”
MAD[0] is the slow ROM pin. When pulled down, it enables two extra
clock cycles of data access time to allow use of slower memory devices.
The external memory interface also supports updates to Flash memory.
2.4 Serial EEPROM Interface
The LSI53C876 implements an interface that allows attachment of a
serial EEPROM device to the GPIO0 and GPIO1 pins for each SCSI
function. There are severalmodes of operation. These relate to the serial
EEPROM and the Subsystem ID register and Subsystem Vendor ID
register for each SCSI function. These modes are programmable through
the MAD6 and MAD7 pins which are sampled at power-up or hard reset.
2.4.1 Mode A Operation
No pull-down on MAD6, no pull-down on MAD7. In this mode, GPIO0 is
the serial data signal (SDA) and GPIO1 is the serial clock signal (SCL).
Certain data in the serial EEPROM is automatically loaded into chip
registers at power-up or hard reset.
The format of the serial EEPROM data is defined in Table 2.7. If the
EEPROM is not present, or the checksum fails, the Subsystem ID and
Subsystem Vendor ID registers read back all zeros. At power-up or hard
reset, only five bytes are loaded into the chip from locations 0x00 through
0x04.
The Subsystem ID and Subsystem Vendor ID registers are read only, in
accordance with the PCI specification, with a default value of all zeros.
Serial EEPROM Interface2-45
Table 2.7Mode A Serial EEPROM Data Format
ByteNameDescription
0x00SVID(0)Subsystem Vendor ID, LSB. This byte is loaded into the least significant
0x01SVID(1)Subsystem VendorID, MSB. This byte is loaded into the most significant
0x02SID(0)Subsystem ID, LSB. This byte is loaded into the least significant byte of
0x03SID(1)Subsystem ID, MSB. This byte is loaded into the most significant byte
0x04CKSUMChecksum. This 8-bit checksum is formed by adding, bytewise, each
0x05–0xFFRSVReserved.
0x100–EOMUDUser Data.
byte of the Subsystem Vendor ID register in the appropriate PCI
configuration space at chip power-up or hard reset.
byte of the Subsystem Vendor ID register in the appropriate PCI
configuration space at chip power-up or hard reset.
the Subsystem ID register in the appropriate PCI configuration space at
chip power-up or hard reset.
of the Subsystem ID register in the appropriate PCI configuration space
at chip power-up or hard reset.
byte contained in locations 0x00–0x03 to the seed value 0x55, and then
taking the 2’s complement of the result.
2.4.2 Mode B Operation
A 4.7 K pull-down on MAD6, no pull-down on MAD7. In this mode,
GPIO0 and GPIO1 are each defined as either the SDA or the SCL, since
both pins are controlled through software.
No data is automatically loaded into chip registers at power-up or hard
reset. The Subsystem ID register and Subsystem Vendor ID register are
read/write, in violation of the PCI specification, with a default value of all
zero’s.
2.4.3 Mode C Operation
A 4.7 K pull-down on MAD6, and a 4.7 K pull-down on MAD7. In this
mode, GPIO1 is the SDA and GPIO0 is the SCL. Certain data in the
serial EEPROM is automatically loaded into chip registers at
power-up or hard reset.
2-46Functional Description
The format of the serial EEPROM data is defined in Table 2.8. If the
EEPROM is not present, or the checksum fails, the Subsystem ID and
Subsystem Vendor ID registers read back all zeros. At power-up or hard
reset, only five bytes are loaded into the chip from locations 0xFB
through 0xFF.
The Subsystem ID and Subsystem Vendor ID registers are read only, in
accordance with the PCI specification, with a default value of all zeros.
Before implementing Mode C, contact LSI Logic for additional
information.
Table 2.8Mode C Serial EEPROM Data Format
ByteNameDescription
0x00–0xFAUD0User Data.
0xFBSVID(0)Subsystem Vendor ID, LSB. This byte is loaded into the least significant
0xFCSVID(1)Subsystem VendorID, MSB. This byte is loaded into the most significant
0xFDSID(0)Subsystem ID, LSB. This byte is loaded into the least significant byte of
0xFESID(1)Subsystem ID, MSB. This byte is loaded into the most significant byte
0xFFCKSUMChecksum. This 8-bit checksum is formed by adding, bytewise, each
0x100–EOMUDUser Data.
byte of the Subsystem Vendor ID register in the appropriate PCI
configuration space at chip power-up or hard reset.
byte of the Subsystem Vendor ID register in the appropriate PCI
configuration space at chip power-up or hard reset.
the Subsystem ID register in the appropriate PCI configuration space at
chip power-up or hard reset.
of the Subsystem ID register in the appropriate PCI configuration space
at chip power-up or hard reset.
byte contained in locations 0x00–0x03 to the seed value 0x55, and then
taking the 2’s complement of the result.
Serial EEPROM Interface2-47
2.4.4 Mode D Operation
No pull-down on MAD6, and a 4.7 K pull-down on MAD7. The
Subsystem ID and the Subsystem Vendor ID are automatically set to
0x1000. This allows the OEM to have a non-zero value in the registers
without requiring a serial EEPROM on the board.
2.5 Power Management
The LSI53C876E complies with the PCI Bus Power Management
Interface Specification, Revision 1.0. The PCI Function PowerStates D0,
D1, D2, and D3 are defined in that specification.
D0 is the maximum powered state, and D3 is the minimum powered
state. Power state D3 is further categorized as D3hot or D3cold.
The LSI53C876E power states shown in Table 2.9 are independently
controlled through two power state bits that are located in the PCI
Configuration Space register 0x44.
Table 2.9Power States
Configuration Register
0x44 Bits [1:0]Power State Function
00D0Maximum Power
01D1Disables SCSI clock
10D2Coma Mode
11D3Minimum Power
Although the PCI Bus Power Management Interface Specification does
not allow power state transitions D2 to D1, D3 to D2, or D3 to D1, the
LSI53C876E hardware places no restriction on transitions between
power states.
As the device transitions from one power level to a lower one, the
attributes that occur from the higher power state level are carried over
into the lower power state level. For example, D1 disables the SCSI CLK.
Therefore, D2 will include this attribute as well as the attributes defined
2-48Functional Description
in the Power State D2 section. The PCI Function Power States D0, D1,
D2, and D3 are described below. Power state actions are separate for
each function.
2.5.1 Power State D0
Power state D0 is the maximum power state and is the power-up default
state for each function.
2.5.2 Power State D1
Power state D1 is a lower power state than D0. In this state, the
LSI53C876 core is placed in the snooze mode and the SCSI CLK is
disabled. In the snooze mode, a SCSI reset does not generate an /IRQ
signal. However, by setting the Wakeup Interrupt Enable bit (bit 3 in the
SCSI Interrupt Enable One (SIEN1) register), then a SCSI reset
generates an /IRQ signal, but SCSI CLK is still disabled.
2.5.3 Power State D2
Power state D2 is a lower power state than D1. In this state, the
LSI53C876 core is placed in the coma mode. The following PCI
Configuration Space command register enable bits are suppressed:
•I/O Space Enable
•Memory Space Enable
•Bus Mastering Enable
•SERR
•PERR
Thus, the memory and I/O spaces cannot be accessed, and the
LSI53C876 cannot be a PCI bus master. Furthermore, SCSI and DMA
interrupts are disabled when in power state D2. If changed from power
state D2 to power state D1 or D0, the previous values of the PCI
Command register are restored. Also, any pending interrupts before the
function entered power state D2 are asserted.
Power Management2-49
2.5.4 Power State D3
Power state D3 is the minimum power state, which includes subsettings
called D3hot and D3cold. D3hot allows the device to transition to D0
using software. The LSI53C876E is considered to be in power state
D3cold when power is removed from the device. D3cold can transition to
D0 by applying VCCand resetting the device.
Power state D3 is a lower power level than power state D2. In this state,
the LSI53C876 core is placed in the coma mode. Furthermore, the
function’s soft reset is continually asserted while in power state D3,
which clears all pending interrupts and 3-states the SCSI bus. In
addition, the device’s PCI Command register is cleared. If both
LSI53C876E functions are placed in power state D3, the Phase Lock
Loop (PLL) is disabled, which results in further power savings.
2-50Functional Description
Chapter 3
Signal Descriptions
This chapter presents the LSI53C876 pin configuration and signal
definitions using tables and illustrations. Figure 3.1 and Figure 3.2 are
the pin diagrams for all versions of the LSI53C876 and Figure 3.3 is the
functional signal grouping. The pin definitions are presented in Table 3.1
through Table 3.16. This chapter is divided into the following sections:
•Section 3.1, “PCI Interface Signals”
•Section 3.2, “SCSI Bus Interface Signals”
•Section 3.3, “ROM/Flash Interface Signals”
•Section 3.4, “Test Interface Signals”
•Section 3.5, “Power and Ground Signals”
•Section 3.6, “MAD Bus Programming”
LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller3-1
SCSI Function B
Differential
Control
(256 BGA only)
SCSI Function A
SCSI Bus
Interface
SCSI Function B
SCSI Bus
Interface
3-4Signal Descriptions
TESTIN/
TCK
TMS
TDI
TDO
Test
Interface
The LSI53C876 signals are divided into three primary interfaces:
•PCI Interface
•SCSI Interface
•ROM/Flash Memory Interface
A slash (/) at the end of the signal name indicates that the active state
occurs when the signal is at a LOW voltage. When the slash is absent,
the signal is active at a HIGH voltage.
There are five signal type definitions:
IInput, a standard input only signal.
OOutput, a standard output driver (typically a Totem Pole Output).
I/OInput and output (bidirectional).
T/S3-state, a bidirectional, 3-state input/output signal.
S/T/SSustained 3-state, an active LOW 3-state signal owned and driven by
one and only one agent at a time.
3-5
3.1 PCI Interface Signals
The PCI interface signals are organized into the following functional
groups: System Signals, Address and Data Signals, Interface Control
Table 3.1 describes the signals for the System Signals group.
Table 3.1System Signals
Name Pin No. Type Strength Description
CLK197, D7IN/AClock provides timing for all transactions on the PCI bus and is
RST/196, A5IN/AReset forces the PCI sequencer of each device to a known state.
an input to every PCI device. All other PCI signals are sampled
on the rising edge of CLK, and other timing parameters are
defined with respect to this edge. Clock can optionally serve as
the SCSI core clock, but this may effect fast SCSI transfer rates.
All T/S and S/T/S signals are forced to a high impedance state,
and all internal logic is reset. The RST/ input is synchronized
internally to the rising edge of CLK. The CLK input must be
active while RST/ is active to properly reset the device.
3-6Signal Descriptions
3.1.2 Address and Data Signals
Table 3.2 describes the signals for the Address and Data Signals group.
Physical Dword Address and Data are
multiplexed on the same PCI pins. During the first
clock of a transaction, AD[31:0] contain a physical
byte address. During subsequent clocks, AD[31:0]
contain data. A bus transaction consists of an
address phase followed by one or more data
phases. PCI supports both read and write bursts.
AD[7:0] define the least significant byte, and
AD[31:24] define the most significant byte.
Bus Command and Byte Enables are multiplexed
on the same PCI pins. During the address phase
of a transaction, C_BE/[3:0] define the bus
command. During the data phase, C_BE/[3:0] are
used as byte enables. The byte enables determine
which byte lanes carry meaningful data. C_BE/[0]
applies to byte 0, and C_BE/[3] to byte 3.
Parity is the even parity bit that protects the
AD[31:0] and C_BE/[3:0] lines. During address
phase, both the address and command bits are
covered. During data phase, both data and byte
enables are covered.
PCI Interface Signals3-7
3.1.3 Interface Control Signals
Table 3.3 describes the signals for the Interface Control Signals group.
Table 3.3Interface Control Signals
NamePin No.TypeStrength Description
FRAME/21, J1S/T/S16 mA
PCI
TRDY/25, L1S/T/S16 mA
PCI
IRDY/23, K3S/T/S16 mA
PCI
STOP/28, L4S/T/S16 mA
PCI
Cycle Frame is driven by the current master to indicate
the beginning and duration of an access. FRAME/ is
asserted to indicate that a bus transaction is beginning.
While FRAME/ is deasserted, either the transaction is in
the final data phase or the bus is idle.
Target Ready indicates the target agent’s (selected
device’s) ability to complete the current data phase of the
transaction. TRDY/ is used with IRDY/. A data phase is
completed on any clock when used with IRDY/. A data
phase is completed on any clock when both TRDY/ and
IRDY/ are sampled asserted. During a read, TRDY/
indicates that valid data is present on AD[31:0]. During a
write, it indicates that the target is prepared to accept
data. Wait cycles are inserted until both IRDY/ and TRDY/
are asserted together.
Initiator Ready indicates the initiating agent’s (bus
master’s) ability to complete the current data phase of the
transaction. IRDY/ is used with TRDY/. A data phase is
completed on any clock when both IRDY/ and TRDY/ are
sampled asserted. During a write, IRDY/ indicates that
valid data is present on AD[31:0]. During a read, it
indicates that the master is prepared to accept data. Wait
cycles are inserted until both IRDY/ and TRDY/ are
asserted together.
Stop indicates that the selected target is requesting the
master to stop the current transaction.
DEVSEL/ 26, L2S/T/S16 mA
PCI
IDSEL7, E2IN/AInitialization Device Select is used as a chip select in
Device Select indicates that the driving device has
decoded its address as the target of the current access.
As an input, it indicates to a master whether any device
on the bus has been selected.
place of the upper 24 address lines during configuration
read and write transactions.
3-8Signal Descriptions
3.1.4 Arbitration Signals
Table 3.4 describes the signals for the Arbitration Signals group.
Table 3.4Arbitration Signals
Name Pin No. TypeStrengthDescription
REQ/200, A4O16 mA PCIRequest indicates to the system arbiter that this agent
GNT/199, B5IN/AGrant indicates to the agent that access to the PCI bus has
desires use of the PCI bus. Both SCSI functions share the
GNT/ signal.
been granted. Both SCSI functions share the GNT/ signal.
3.1.5 Error Reporting Signals
Table 3.5 describes the signals for the Error Reporting Signals group.
Table 3.5Error Reporting Signals
NamePin No.TypeStrengthDescription
PERR/ 30, M2S/T/S16 mA PCIParity Error may be pulsed active by an agent that
SERR/ 32, M4O16 mA PCISystem Error is an open drain output is used to report
detects a data parity error. PERR/ can be used by any
agent to signal data corruption. However, on detection
of a PERR/ pulse, the central resource may generate a
nonmaskable interrupt to the host CPU, which often
implies the system is unable to continue operation once
error processing is complete.
address parity errors.
PCI Interface Signals3-9
3.1.6 PCI Interrupt Signals
Table 3.6 describes the signals PCI Interrupt Signals group.
Table 3.6PCI Interrupt Signals
NamePin No.TypeStrengthDescription
INTA/195, B6O16 mA PCIInterrupt Function A. This signal, when asserted LOW,
INTB/194, C7O16 mA PCIInterrupt Function B. This signal, when asserted LOW,
indicates an interrupting condition in SCSI Function A
and that service is required from the host CPU. The
output drive of this pin is open drain with an internal
weak pull-up. If the SCSI Function B interrupt is
rerouted at power-up using the INTA/ enable sense
resistor (pull-down on MAD4), then this signal indicates
an interrupt in either SCSI Function A or SCSI
Function B.
indicates an interrupting condition in SCSI Function B
and that service is required from the host CPU. The
output drive of this pin is open drain with an internal
weak pull-up. This interrupt can be rerouted at
power-up using the INTA/ enable sense resistor
(pull-down on MAD4). This causes the LSI53C876 to
program the SCSI Function B PCI register Interrupt Pin
(3D) to 0x01.
3-10Signal Descriptions
3.1.7 GPIO Interface Signals
Table 3.7 describes the signals for the SCSI GPIO Function A Signals
group.
Table 3.7SCSI GPIO Function A Signals
NamePin No.TypeStrengthDescription
A_GPIO0_
FETCH/
A_GPIO1_
MASTER/
A_GPIO270, V8I/O16 mASCSI Function A General Purpose I/O pin 2. This
A_GPIO371, W8I/O16 mASCSI Function A General Purpose I/O pin 3.
A_GPIO473, Y8I/O16 mASCSI Function A General Purpose I/O pin 4.
68, W7I/O16 mASCSI Function A General Purpose I/O pin 0.
Optionally, when driven LOW, indicates that the next
bus request is for an opcode fetch. This pin is
programmable at power-up through the MAD[7:6] pins
to serve as either the data or clock signal for the serial
EEPROM interface.
69, Y7I/O16 mASCSI Function A General Purpose I/O pin 1.
Optionally, when driven LOW, indicates that the
LSI53C876 is bus master. This pin is programmable
at power-up through the MAD[7:6] pins to serve as
either the data or clock signal for the serial EEPROM
interface.
pin is a general purpose I/O pin that powers up as an
input.
A_GPIO3 powers up as an input. Currently our drivers
use A_GPIO3 as a means to detect Diffsense.
A_GPIO4 powers up as an output. It can be used as
the enable line for VPP, the 12 V power supply to the
external Flash memory interface.
PCI Interface Signals3-11
Table 3.8 describes the signals for the SCSI GPIO Function B Signals
group.
Table 3.8SCSI GPIO Function B Signals
NamePin No.TypeStrengthDescription
B_GPIO0_
FETCH/
B_GPIO1_
MASTER/
B_GPIO287, W12I/O16 mASCSI Function B General Purpose I/O pin 2.
B_GPIO388, V12I/O16 mASCSI Function B General Purpose I/O pin 3.
B_GPIO489, U12I/O16 mASCSI Function B General Purpose I/O pin 4.
84, U11I/O16 mASCSI Function B General Purpose I/O pin 0.
Optionally, when driven LOW, indicates that the next
bus request is for an opcode fetch. This pin is
programmable at power-up through the MAD[7:6] pins
to serve as either the data or clock signal for the serial
EEPROM interface.
86, Y12I/O16 mASCSI Function B General Purpose I/O pin 1.
Optionally, when driven LOW, indicates that the
LSI53C876 is bus master. This pin is programmable
at power-up through the MAD[7:6] pins to serve as
either the data or clock signal for the serial EEPROM
interface.
B_GPIO2 powers up as an input.
B_GPIO3 powers up as an input. Currently our drivers
use B_GPIO3 as a means to detect Diffsense.
B_GPIO4 powers up as an output. It can be used as
the enable line for VPP, the 12 V power supply to the
external Flash memory interface.
3-12Signal Descriptions
3.2 SCSI Bus Interface Signals
The SCSI Bus Interface signals section contains tables describing the
signals for the following signal groups: SCSI Bus Interface Signal and
SCSI Bus Interface.
3.2.1 SCSI Bus Interface Signal
Table 3.9 describes the SCSI Bus Interface signal.
Table 3.9SCSI Bus Interface Signal
NamePin No.Type Strength Description
SCLK65, W6IN/ASCSI Clock is used to derive all
SCSI-related timings. The speed of this clock
is determined by the application requirements.
In some applications, SCLK may be sourced
internally from the PCI bus clock (CLK). If
SCLK is internally sourced, tie the SCLK pin
LOW. For Ultra SCSI operations, the clock
supplied to SCLK must be at 40 MHz. The
frequency is doubled to create the 80 MHz
clock required by both SCSI functions.
SCSI Bus Interface Signals3-13
3.2.2 SCSI Bus Interface
Table 3.10 describes the signals for the SCSI Function A Signals group.
SCSI Function A Data includes the following
data lines and parity signals: A_SD/[15:0]
(16-bit SCSI data bus), and A_SDP/[1:0]
(SCSI data parity bits).
SCSI Function A Control includes the
following signals:
A_SC_D/SCSI phase line, command/data
A_SI_O/SCSI phase line, input/output
A_SMSG/SCSI phase line, message
A_SREQ/Data handshake line from target
device
A_SACK/Data handshake signal from
initiator device
A_SBSY/SCSI bus arbitration signal,
busy
A_SATN/SCSI Attention, the initiator is
requesting a message out
phase
A_SRST/SCSI bus reset
A_SSEL/SCSI bus arbitration signal,
select device
3-14Signal Descriptions
Table 3.11 describes the signals for the SCSI Function B Signals group.
SCSI Function B Data includes the following
data lines and parity signals: B_SD/[15:0]
(16-bit SCSI data bus), and B_SDP/[1:0]
(SCSI data parity bits).
SCSI Function B Control includes the
following signals:
B_SC_D/SCSI phase line, command/data
B_SI_O/SCSI phase line, input/output
B_SMSG/SCSI phase line, message
B_SREQ/Data handshake line from target
device
B_SACK/Data handshake signal from
initiator device
B_SBSY/SCSI bus arbitration signal,
busy
B_SATN/SCSI Attention, the initiator is
requesting a message out
phase
B_SRST/SCSI bus reset
B_SSEL/SCSI bus arbitration signal,
select device
SCSI Bus Interface Signals3-15
Table 3.12 describes the signals for the SCSI Function A Differential
Control Signals group.
Table 3.12SCSI Function A Differential Control Signals
A_SDIRP0/1173, B14O4 mADriver direction control for SCSI Function A
A_BSYDIR132, H20O4 mADriver enable control for SCSI Function A
A_SELDIR128, J20O4 mADriver enable control for SCSI Function A
A_RSTDIR130, J18O4 mADriver enable control for SCSI Function A
A_DIFFSENS 125, K19IN/ASCSI Function A Differential Sense. This
O4 mADriver direction control for SCSI Function A
data lines.
parity line.
SBSY/ signal.
SSEL/ signal.
SRST/ signal.
pin detects the presence of an SE device
on a differential system. When external
differential transceivers are used and a
zero is detected on this pin, all SCSI
Function A chip outputs are 3-stated to
avoid damage to the transceivers. Tie this
pin HIGH during SE operation. The normal
value of this pin is 1.
A_IGS127, K17O4 mASCSI Function A direction control for
A_TGS126, K18O4 mASCSI Function A direction control for target
initiator driver group.
driver group.
3-16Signal Descriptions
Table 3.13 describes the signals for the SCSI Function B Differential
Control Signals group.
Table 3.13SCSI Function B Differential Control Signals
B_SDIRP0/1N19O4 mADriver direction control for SCSI Function B
B_BSYDIRY14O4 mADriver enable control for SCSI Function B
B_SELDIRW13O4 mADriver enable control for SCSI Function B
B_RSTDIRV13O4 mADriver enable control for SCSI Function B
B_DIFFSENSY16IN/ASCSI Function B Differential Sense. This
B_IGSA8O4 mASCSI Function B direction control for
O4 mADriver direction control for SCSI Function B
data lines.
parity line.
SBSY/ signal.
SSEL/ signal.
SRST/ signal.
pin detects the presence of an SE device
on a differential system. When external
differential transceivers are used and a
zero is detected on this pin, all SCSI
Function B chip outputs are 3-stated to
avoid damage to the transceivers. Tie this
pin HIGH during SE operation. The normal
value of this pin is 1.
initiator driver group.
B_TGSD9O4 mASCSI Function B direction control for target
driver group.
SCSI Bus Interface Signals3-17
3.3 ROM/Flash Interface Signals
Table 3.14 describes the signals for the ROM/Flash Interface Signals
group.
Table 3.14ROM/Flash Interface Signals
NamePin No.TypeStrength Description
MAS0/190, C8O4 mAMemory Address Strobe 0. This pin is used
MAS1/189, B8O4 mAMemory Address Strobe 1. This pin is used
to latch in the least significant address byte of
an external EPROM or Flash memory. Since
the LSI53C876E moves addresses eight bits at
a time, this pin connects to the clock of an
external bank of flip-flops which are used to
assemble up to a 20-bit address for the
external memory. If an external memory
requires more than 16 bits of addressing as
specified by the pull-down resistors at
power-up and bit 0 in the Expansion ROM
Base Address register, see the External
Memory Interface diagram for proper usage.
to latch in the address byte corresponding to
address bits [15:8] of an external EPROM or
Flash memory. Since the LSI53C876E moves
addresses eight bits at a time, this pin connects
to the clock of an external bank of flip-flops
which assemble up to a 20-bit address for the
external memory. If an external memory
requires more than 16 bits of addressing as
specified by the pull-down resistors at
power-up and bit 0 in the Expansion ROM
Base Address register, see the External
Memory Interface diagram for proper usage.
in conjunction with the memory address strobe
pins and external address latches to assemble
up to a 20-bit address for an external EPROM
or Flash memory.This bus will put out the least
significant byte first and finishes with the most
significant bits. It is also used to write data to a
Flash memory or read data into the chip from
external EPROM/Flash memory. All MAD pins
have internal pull-up resistors.
3-18Signal Descriptions
Table 3.14ROM/Flash Interface Signals (Cont.)
NamePin No.TypeStrength Description
MWE/191, A7O4 mAMemory Write Enable. This pin is used as a
MOE/_TESTOUT 192, B7O4 mAMemory Output Enable. This pin is used as
MCE/193, A6O4 mAMemory Chip Enable. This pin is used as a
write enable signal to an external Flash
memory.
an output enable signal to an external EPROM
or Flash memory during read operations. It is
also used to test the connectivity of the
LSI53C876E signals in the “AND-tree” test
mode. This pin is only driven as the Test Out
function when the TESTIN/ pin is driven LOW.
chip enable signal to an external EPROM or
Flash memory device.
3.4 Test Interface Signals
Table 3.15 describes the signals for the Test Interface Signals group.
Table 3.15Test Interface Signals
NamePin No.TypeStrength Description
TESTIN/66, Y6IN/ATest In. When this pin is driven LOW, the
LSI53C876E connects all inputs and outputs to an
“AND-tree”. The SCSI control signals and data
lines are not connected to the tree. The output of
the “AND-tree” is connected to the Test Out pin
(MOE/_TESTOUT). When the TESTIN/ pin is
driven LOW internal pull-ups are enabled on all
input, output, and bidirectional pins; all output and
bidirectional pins signals are 3-stated; and the
MOE/_TESTOUT pin is enabled. Connectivity is
tested by driving one of the LSI53C876E pins
LOW. The MOE/_TESTOUT should respond by
also driving LOW.
TCK60, V5IN/ATest Clock. This pin provides the clock for the
TMS62, Y5IN/ATest Mode Select. The signal received at TMS is
Test Interface Signals3-19
JTAG test logic. It has a static pull-up.
decoded by the TAPcontroller to control JTAG test
operations. It has a static pull-up.
Table 3.15Test Interface Signals (Cont.)
TDI61, W5IN/ATest Data In. Serial test instructions are received
by the JTAG test logic at this pin. It has a static
pull-up.
TDO63, V6ON/ATest Data Out. This pin is the serial output for test
instructions and data from the JTAG test logic.
3.5 Power and Ground Signals
Table 3.16 describes the signals for the Power and Ground Signals
75, 186PN/APower for other I/O.
72, 85, 133, 178, 188GN/AGround for other I/O.
3-20Signal Descriptions
PN/APower for SCSI bus drivers/receivers.
GN/AGround for SCSI bus drivers/receivers.
PN/APower for core logic.
GN/AGround for core logic.
3.5.1 Isolated Power Supplies
The I/O driver pad rows and digital core have isolated power supplies as
delineated by the "I/O" and "CORE" extensions on their respective V
and VDDnames.
These power and ground pins should be connected directly to the
primary power and ground planes of the circuit board. Bypass capacitors
of 0.01 µF should be applied between adjacent VSSand VDDpairs
wherever possible. Do not connect bypass capacitors between VSSand
VDDpairs that cross power and ground bus boundaries.
3.6 MAD Bus Programming
The MAD[7:0] pins, in addition to serving as the address/data bus for the
local memory interface, also are used to program power-up options for
the chip. A particular option is programmed by connecting a 4.7 kΩ
resistor between the appropriate MAD(x) pin and VSS. The pull-down
resistors require that HC or HCT external components are used for the
memory interface.
•MAD[7] – Serial EEPROM programmable option. Please refer to
Section 2.4, “Serial EEPROM Interface,” in Chapter 2, “Functional
Description,” for details.
SS
•MAD[6] – Serial EEPROM programmable option. Please refer to
Section 2.4, “Serial EEPROM Interface,” in Chapter 2, “Functional
Description,” for details.
•MAD[5] – SCRIPTS RAM disable.
•MAD[4] – INTA/ routing enable. Placing a pull-down resistor on this
pin causes SCSI Function B interrupt requests to appear on the
INTA/ pin, along with SCSI Function A interrupt requests, instead of
on INTB/. Placing a pull-down resistor on this pin also causes the
SCSI Function B interrupt pin register (0x3D) in PCI configuration
space to be programmed to 0x01 instead of 0x02.
•MAD[3:1] – Used to set the size of the external expansion ROM
device attached. Encoding for these pins are listed in the following
table (“0” indicates a pull-down resistor is attached, “1” indicates no
pull-down resistor attached).
•MAD[0] – The slow ROM pin. When pulled down, it enables two
extra cycles of data access time to allow use of slower memory
devices.
Note:All MAD pins have internal pull-up resistors.
3-22Signal Descriptions
Chapter 4
Registers
This chapter describes all LSI53C876 registers and is divided into the
following sections:
•Section 4.1, “PCI Configuration Registers”
•Section 4.2, “SCSI Registers”
4.1 PCI Configuration Registers
The PCI Configuration registers are accessed by performing a
configuration read/write to the device with its IDSEL pin asserted and the
appropriate value in AD[10:8] during the address phase of the
transaction. SCSI Function A is identified by a binary value of 000b, and
SCSI Function B by a value of 001b. Each SCSI channel contains the
same register set with identical default values, except the Interrupt Pin
register.
Table 4.1 shows the PCI configuration registers implemented by the
LSI53C876.
All PCI-compliant devices, such as the LSI53C876, must support the
Vendor ID, Device ID, Command, and Status registers. Support of other
PCI-compliant registers is optional. In the LSI53C876, registers that are
not supported are not writable and return all zeros when read. Only those
registers and bits that are currently supported by the LSI53C876 are
described in this chapter.
LSI53C876/876E PCI to Dual Channel SCSI Multifunction Controller4-1
Table 4.1PCI to SCSI Configuration Register Map
3116 150
Device IDVendor ID0x00
StatusCommand0x04
Class CodeRevision ID0x08
Not SupportedHeader TypeLatency TimerCache Line Size0x0C
Base Address Register Zero (I/O) SCSI Operating Registers0x10
Base Address Register One (Memory) bits [31:0] SCSI Operating Registers0x14
Base Address Register Two (Memory)0x18
Not Supported0x1C
Not Supported0x20
Not Supported0x24
Reserved0x28
Subsystem IDSubsystem Vendor ID0x2C
Expansion ROM Base Address0x30
ReservedCapabilities Pointer0x34
Reserved0x38
Max_LatMin_GntInterrupt Pin
Power Management CapabilitiesNext Item PointerCapability ID0x40
DataPMCSR BSEPower Management Control/Status0x44
1. Each SCSI function contains the same register set with identical default values. One exception is
the Interrupt Pin register.
Note: Shaded areas are reserved or represent the LSI53C876E capabilities.
1
Interrupt Line0x3C
4-2Registers
Register: 0x00
Vendor ID
Read Only
150
VID
1111000000000000
VIDVendor ID[15:0]
This field identifies the manufacturer of the device. The
Vendor ID is 0x1000.
Register: 0x02
Device ID
Read Only
150
DID
0000000000000000
DIDDevice ID[15:0]
This field identifies the particular device. The LSI53C876
Device ID is 0x000F.
Register: 0x04
Command
Read/Write
159876543210
RSER EPER R WIE REBMEMS EIS
00000000000000 00
The Command register provides coarse control over a device’s ability to
generate and respond to PCI cycles. When a zero is written to this
register, the LSI53C876 is logically disconnected from the PCI bus for all
accesses except configuration accesses.
PCI Configuration Registers4-3
RReserved[15:9]
SESERR/ Enable8
This bit enables the SERR/ driver. SERR/ is disabled
when this bit is cleared. The default value of this bit is
zero. This bit and bit 6 must be set to report address
parity errors. In the LSI53C876E, this bit is suppressed in
Power State D2.
RReserved7
EPEREnable Parity Error Response6
This bit allows a SCSI function of the LSI53C876E to
detect parity errors on the PCI bus and report these
errors to the system. Only data parity checking is enabled
and disabled with this bit. The LSI53C876 always
generates parity for the PCI bus. In the LSI53C876E, this
bit is suppressed in Power State D2.
RReserved5
WIEWrite and Invalidate Enable4
This bit allows a SCSI function of the LSI53C876 to
generate write and invalidate commands on the PCI bus.
The WRIE bit in the Chip Test Three (CTEST3) register
must also be set for the SCSI function to generate Write
and Invalidate commands.
RReserved3
EBMEnable Bus Mastering2
EMSEnable Memory Space1
4-4Registers
This bit controls the ability of a SCSI function to act as a
master on the PCI bus. A value of zero disables this
device from generating PCI bus master accesses. A
value of one allows the SCSI function to behave as a bus
master. The SCSI function must be a bus master in order
to fetch SCRIPTS instructions and transfer data. In the
LSI53C876E, this bit is suppressed in Power State D2.
This bit controls the ability of a SCSI function to respond
to Memory space accesses. A value of zero disables the
device response. A value of one allows a SCSI function
of the LSI53C876 to respond to Memory Space accesses
at the address range specified by the Base Address Reg-
ister One (Memory) and Base Address Register Two
(Memory) registers in the SCSI function’s PCI
configuration space. In the LSI53C876E, this bit is
suppressed in Power State D2.
EISEnable I/O Space0
This bit controls a SCSI function’s response to I/O space
accesses. A value of zero disables the device response.
A value of one allows the LSI53C876 to respond to I/O
Space accesses at the address range specified by the
Base Address Register Zero (I/O) register in the SCSI
function’s PCI configuration space. In the LSI53C876E,
this bit is suppressed in Power State D2.
Register: 0x06
Status
Read/Write
1514131211109875430
DPE SSE RMA RTA RDT[1:0] DPRRNC R
0000000000010000
Reads to this register behave normally. Writes are slightly different in that
bits can be cleared, but not set. A bit is cleared whenever the register is
written, and the data in the corresponding bit location is a one. For
instance, to clear bit 15 and not affect any other bits, write the value
0x8000 to the register.
DPEDetected Parity Error (from Slave)15
This bit is set by the a SCSI function of the LSI53C876
whenever it detects a data parity error, even if data parity
error handling is disabled.
SSESignaled System Error14
This bit is set whenever the device asserts the SERR/
signal.
RMAReceived Master Abort (from Master)13
A master device should set this bit whenever its
transaction (except for Special Cycle) is terminated with
Master Abort.
RTAReceived Target Abort (from Master)12
A master device should set this bit whenever its
transaction is terminated by target abort.
PCI Configuration Registers4-5
RReserved11
DT[1:0]DEVSEL/ Timing[10:9]
These bits encode the timing of DEVSEL/. These are
encoded as:
0b00fast
0b01medium
0b10slow
0b11reserved
These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. In the SCSI functions of the LSI53C876, 0b01 is
supported.
DPRData Parity Reported8
This bit is set when the following conditions are met:
• The bus agent asserted PERR/ itself or observed
PERR/ asserted.
• The agent setting this bit acted as the bus master for
the operation in which the error occurred.
• The Parity Error Response bit in the Command
register is set.
RReserved[7:5]
NCNew Capabilities4
RReserved[3:0]
4-6Registers
This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is read only.
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