Avago Technologies LSI53C825AE User Manual

TECHNICAL

MANUAL

LSI53C825A/825AE
PCI to SCSI
I/O Processor

Version 3.1

January 2001

®

S14058

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000159-00, Fourth Edition (January 2001)
This document describes the LSI Logic LSI53C825A/AE PCI to SCSI I/O
Processor and will remain the official reference source for all revisions/releases
of this product until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design, TolerANT, SDMS, and SCRIPTS are registered
trademarks or trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.

ii

Audience

Organization

Preface

This book is the primary reference and technical manual for the LSI Logic
LSI53C825A/825AE PCI to SCSI I/O Processor. It contains a complete
functional description for the LSI53C825A/825AE and includes complete
physical and electrical specifications for the LSI53C825A/825AE.

This technical manual is intended for system designers and programmers
who are using this device to design a SCSI port for PCI-based personal
computers, workstations, or embedded applications.

This document has the following chapters and appendixes:

• Chapter 1, Introduction, includes general information about the

LSI53C825A and other members of the LSI53C8XX family of PCI to
SCSI I/O Processors.

• Chapter 2, Functional Description, describes the main functional

areas of the chip in more detail, including the interfaces to the SCSI
bus.

• Chapter 3, Signal Descriptions, describes the chip’s connection to

the PCI bus, including the PCI commands and configuration registers
supported.

• Chapter 4, Registers, contains the pin diagrams and definitions of

each signal.

• Chapter 5, SCSI SCRIPTS Instruction Set, describes each bit in the

operating registers, organized by address.

Preface iii

• Chapter 6, Specifications, defines all of the SCSI SCRIPTS

• Appendix A, Register Summary, contains a register summary.

• Appendix B, External Memory Interface Diagram Examples,

Related Publications

For background information, please contact:

ANSI

11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2); X3.253 (

Parallel Interface

instructions that are supported by the LSI53C825A.

contains several example interface drawings to connect the
LSI53C825A to an external ROM.

SCSI-3

)

ENDL Publications

14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names:

Tutor

Prentice Hall

113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8,

the Small Computer System Interface

LSI Logic World Wide Web Home Page

www.lsilogic.com

iv Preface

SCSI Bench Reference, SCSI Encyclopedia, SCSI

SCSI: Understanding

SCSI SCRIPTS™ Processors Programming Guide

Order Number S15044.A

PCI Special Interest Group

2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]

Conventions Used in This Manual

, Version 2.2,

The word

deassert

assert

means to drive a signal true or active. The word

means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision Record

Revision Date Remarks

1.0 6/95 Revision 1.0

2.0 3/96 Revision 2.0

3.0 12/97 Revision 3.0

3.1 1/01 Product names changed from SYM to LSI.

Preface v

vi Preface

Contents

Chapter 1 Introduction

1.1 General Description 1-1

1.2 Package and Feature Options 1-2

1.2.1 PCI Pad Power-up Sequence 1-3

1.3 TolerANT®Technology 1-3

1.4 LSI53C825A Benefits Summary 1-4

1.4.1 SCSI Performance 1-4

1.4.2 PCI Performance 1-5

1.4.3 Integration 1-6

1.4.4 Ease of Use 1-6

1.4.5 Flexibility 1-7

1.4.6 Reliability 1-7

1.4.7 Testability 1-8

Chapter 2 Functional Description

2.1 PCI Addressing 2-1

2.1.1 Configuration Space 2-1

2.1.2 PCI Bus Commands and Functions Supported 2-2

2.1.3 PCI Cache Mode 2-4

2.2 SCSI Functional Description 2-10

2.2.1 SCSI Core 2-10

2.2.2 DMA Core 2-11

2.2.3 SCRIPTS Processor 2-11

2.2.4 Internal SCRIPTS RAM 2-11

2.2.5 SDMS: The Total SCSI Solution 2-12

2.2.6 Prefetching SCRIPTS Instructions 2-13

2.2.7 Opcode Fetch Burst Capability 2-14

2.3 External Memory Interface 2-14

2.4 PCI Cache Mode 2-17

Contents vii

2.4.1 Load and Store Instructions 2-17

2.4.2 3.3 V/5 V PCI Interface 2-17

2.4.3 Additional Access to General Purpose Pins 2-17

2.4.4 JTAG Boundary Scan Testing 2-18

2.4.5 Big and Little Endian Support 2-19

2.4.6 Loopback Mode 2-20

2.4.7 Parity Options 2-21

2.4.8 DMA FIFO 2-23

2.4.9 SCSI Bus Interface 2-27

2.4.10 Select/Reselect During Selection/Reselection 2-33

2.4.11 Synchronous Operation 2-33

2.4.12 Achieving Optimal SCSI Send Rates 2-34

2.4.13 Interrupt Handling 2-35

2.4.14 Chained Block Moves 2-42

2.5 Power Management 2-46

2.5.1 Power State D0 2-46

2.5.2 Power State D3 2-46

Chapter 3 Signal Descriptions

3.1 PCI Bus Interface Signals 3-6

3.1.1 System Signals 3-6

3.1.2 Address and Data Signals 3-7

3.1.3 Interface Control Signals 3-8

3.1.4 Arbitration Signals 3-9

3.1.5 Error Reporting Signals 3-9

3.1.6 SCSI Bus Interface Signals 3-10

3.1.7 Additional Interface Signals 3-11

3.1.8 External Memory Interface Signals 3-14

3.1.9 JTAG Signals 3-15

3.2 MAD Bus Programming 3-15

Chapter 4 Registers

4.1 Configuration Registers 4-1

4.2 Operating Registers 4-18

viii Contents

Chapter 5 SCSI SCRIPTS Instruction Set

5.1 Low Level Register Interface Mode 5-1

5.2 High Level SCSI SCRIPTS Mode 5-2

5.2.1 Sample Operation 5-3

5.3 Block Move Instructions 5-6

5.3.1 First Dword 5-6

5.3.2 Second Dword 5-13

5.4 I/O Instruction 5-14

5.4.1 First Dword 5-14

5.4.2 Second Dword 5-23

5.5 Read/Write Instructions 5-24

5.5.1 First Dword 5-24

5.5.2 Second Dword 5-26

5.5.3 Read-Modify-Write Cycles 5-26

5.5.4 Move To/From SFBR Cycles 5-27

5.6 Transfer Control Instructions 5-29

5.6.1 First Dword 5-29

5.6.2 Second Dword 5-36

5.7 Memory Move Instructions 5-36

5.7.1 First Dword 5-37

5.7.2 Read/Write System Memory from SCRIPTS 5-38

5.7.3 Second Dword 5-38

5.7.4 Third Dword 5-38

5.8 Load and Store Instructions 5-40

5.8.1 First Dword 5-41

5.8.2 Second Dword 5-42

Chapter 6 Specifications

6.1 DC Characteristics 6-1

6.2 TolerANT Technology Electrical Characteristics 6-7

6.3 AC Characteristics 6-11

6.4 PCI and External Memory Interface Timing Diagrams 6-13

6.4.1 Target Timing 6-15

6.4.2 Initiator Timing 6-24

6.4.3 External Memory Timing 6-32

Contents ix

6.5 PCI and External Memory Interface Timing 6-44

6.6 SCSI Timing Diagrams 6-45

6.7 Package Drawings 6-52

Appendix A Register Summary

Appendix B External Memory Interface Diagram Examples

Index

Customer Feedback

Figures

1.1 LSI53C825A External Memory Interface 1-9

1.2 LSI53C825A Chip Block Diagram 1-10

2.1 DMA FIFO Sections 2-23

2.2 LSI53C825A Host Interface Data Paths 2-27

2.3 LSI53C825A Differential Wiring Diagram 2-31

2.4 Regulated Termination 2-32

2.5 Determining the Synchronous Transfer Rate 2-35

2.6 Block Move and Chained Block Move Instructions 2-45

3.1 LSI53C825A Pin Diagram 3-2

3.2 LSI53C825AJ Pin Diagram 3-3

3.3 LSI53C825A Functional Signal Grouping 3-5

5.1 SCRIPTS Overview 5-5

5.2 Block Move Instruction Register 5-8

5.3 I/O Instruction Register 5-17

5.4 Read/Write Instruction Register 5-25

5.5 Transfer Control Instruction 5-31

5.6 Memory Move Instruction 5-39

5.7 Load and Store Instruction Format 5-43

6.1 Rise and Fall Time Test Conditions 6-9

6.2 SCSI Input Filtering 6-9

6.3 Hysteresis of SCSI Receivers 6-9

6.4 Input Current as a Function of Input Voltage 6-10

6.5 Output Current as a Function of Output Voltage 6-10

x Contents

6.6 External Clock 6-11

6.7 Reset Input 6-12

6.8 Interrupt Output 6-13

6.9 PCI Configuration Register Read 6-15

6.10 PCI Configuration Register Write 6-16

6.11 Operating Register/SCRIPTS RAM Read 6-17

6.12 Operating Register/SCRIPTS RAM Write 6-18

6.13 External Memory Read 6-20

6.14 External Memory Write 6-22

6.15 Nonburst Opcode Fetch 6-24

6.16 Burst Opcode Fetch 6-25

6.17 Back-to-Back Read 6-26

6.18 Back-to-Back Write 6-27

6.19 Burst Read 6-28

6.20 Burst Write 6-30

6.21 Read Cycle, Normal/Fast Memory (≥ 64 Kbytes),
Single Byte Access 6-32

6.22 Write Cycle, Normal/Fast Memory (≥ 64 Kbytes),
Single Byte Access 6-33

6.23 Read Cycle, Normal/Fast Memory (≥ 64 Kbytes),
Multiple Byte Access 6-34

6.24 Write Cycle, Normal/Fast Memory (≥ 64 Kbytes),
Multiple Byte Access 6-36

6.25 Read Cycle, Slow Memory (≥ 64 Kbytes) 6-38

6.26 Write Cycle, Slow Memory (≥ 64 Kbytes) 6-39

6.27 Read Cycle, Normal/Fast Memory (≥ 64 Kbytes) 6-40

6.28 Write Cycle, Normal/Fast Memory (≥ 64 Kbytes) 6-41

6.29 Read Cycle, Slow Memory (≤ 64 Kbytes) 6-42

6.30 Write Cycle, Slow Memory (≤ 64 Kbytes) 6-43

6.31 Initiator Asynchronous Send 6-45

6.32 Initiator Asynchronous Receive 6-46

6.33 Target Asynchronous Send 6-47

6.34 Target Asynchronous Receive 6-48

6.35 Initiator and Target Synchronous Transfers 6-48

6.36 LSI53C825A 160 Pin PQFP (PF) Mechanical Drawing 6-52

B.1 64 Kbyte Interface with 200 ns Memory B-1

Contents xi

Tables

B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 256 Kbyte Interface with 150 ns Memory B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4

2.1 PCI Bus Commands and Encoding Types 2-3

2.2 External Memory Support 2-16

2.3 Bits Used for Parity Control and Generation 2-21

2.4 SCSI Parity Control 2-22

2.5 SCSI Parity Errors and Interrupts 2-23

2.6 Differential Mode 2-28

3.1 LSI53C825A, LSI53C825AJ, LSI53C825AE, and
LSI53C825AJE Power and Ground Pins 3-4

3.2 System Signals 3-6

3.3 Address and Data Signals 3-7

3.4 Interface Control Signals 3-8

3.5 Arbitration Signals 3-9

3.6 Error Reporting Signals 3-9

3.7 SCSI Bus Interface Signals 3-10

3.8 Additional Interface Signals 3-11

3.9 External Memory Interface Signals 3-14

3.10 JTAG Signals (LSI53C825AJ, LSI53C825AJE Only) 3-15

3.11 Subsystem Data Configuration Table for the
LSI53C825AE (PCI Rev ID 0x26) 3-16

3.12 Subsystem Data Configuration Table for the
LSI53C825A (PCI Rev ID 0x14) Revision G Only 3-16

3.13 External Memory Support 3-17

4.1 PCI Configuration Register Map 4-2

4.2 LSI53C825A Register Map 4-19

4.3 Synchronous Clock Conversion Factor 4-29

4.4 Examples of Synchronous Transfer Periods and
Rates for SCSI-1 4-33

4.5 Example Transfer Periods and Rates for Fast SCSI-2 4-33

4.6 Maximum Synchronous Offset 4-34

4.7 Timeout Periods 4-82

4.8 Timeout Periods, 50 MHz Clock 4-83

5.1 SCRIPTS Instructions 5-3

5.2 Read/Write Instructions 5-27

xii Contents

6.1 Absolute Maximum Stress Ratings 6-2

6.2 Operating Conditions 6-2

6.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/ 6-3

6.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/,
SSEL/, SRST/ 6-3

6.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/,
TESTIN, DIFFSENS, BIG_LIT/ 6-3

6.6 Capacitance 6-4

6.7 Output Signals—MAC/_TESTOUT, REQ/ 6-4

6.8 Output Signals—IRQ/, SDIR[15:0], SDIRP0, SDIRP1,
BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/[1:0],
MCE/, MOE/, MWE/ 6-4

6.9 Output Signal—SERR/ 6-4

6.10 Bidirectional Signals—AD[31:0], C_BE[3:0], FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR/ 6-5

6.11 Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/, GPIO2_MAS2/, GPIO3, GPIO4 6-5

6.12 Bidirectional Signals—MAD[7:0] 6-6

6.13 Input Signals—TDI, TMS, TCK (LSI53C825AJ only) 6-6

6.14 Output Signal—TDO (LSI53C825AJ only) 6-6

6.15 TolerANT Technology Electrical Characteristics 6-8

6.16 External Clock 6-11

6.17 Reset Input 6-12

6.18 Interrupt Output 6-13

6.19 LSI53C825A PCI and External Memory Interface
Timing 6-44

6.20 Initiator Asynchronous Send 6-45

6.21 Initiator Asynchronous Receive 6-46

6.22 Target Asynchronous Send 6-47

6.23 Target Asynchronous Receive 6-48

6.24 SCSI-1 Transfers (SE 5.0 Mbytes) 6-49

6.25 SCSI-1 Transfers (Differential, 4.17 Mbytes/s) 6-49

6.26 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers)
or 20.0 Mbytes/s (16-Bit Transfers), 40 MHz Clock) 6-50

6.27 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers)
or 20.0 Mbytes/s (16-Bit Transfers) 50 MHz Clock 6-50

A.1 Configuration Registers A-1
A.2 LSI53C825A Register Map A-2

Contents xiii

xiv Contents

Chapter 1
Introduction

This chapter includes general information about the LSI53C825A and
other members of the LSI53C8XX family of PCI to SCSI I/O Processors
and contains the following sections:

• Section 1.1, “General Description”

• Section 1.2, “Package and Feature Options”

• Section 1.3, “TolerANT

• Section 1.4, “LSI53C825A Benefits Summary”

1.1 General Description

This manual combines information on the LSI53C825A and
LSI53C825AE, which are PCI to SCSI I/O Processors. The
LSI53C825AE is a minor modification of the existing LSI53C825A
product. It has all the functionality of the LSI53C825A with the addition
of features to enable it to comply with the Microsoft PC 97 Hardware
Design Guide. Specifically, the LSI53C825AE has a Power Management
Support enhancement. Because there are only slight differences
between them, the LSI53C825A and LSI53C825AE are referred to as
LSI53C825A throughout this technical manual. Only the new
enhancements are referred to as LSI53C825AE.

®

Technology”

This technical manual assumes the user is familiar with the current and
proposed standards for SCSI and PCI. For additional background
information on these topics, please refer to the list of reference materials
provided in the Preface of this document.

The LSI53C825A PCI to SCSI I/O Processor brings high-performance
I/O solutions to host adapter, workstation, and general computer designs,
making it easy to add SCSI to any PCI system. It provides a local

LSI53C825A/825AE PCI to SCSI I/O Processor 1-1

memory bus for local storage of the device’s BIOS ROM in flash memory
or standard EPROMs. The LSI53C825A supports big and little endian
byte addressing to accommodate a variety of data configurations. The
LSI53C825A supports programming of local FLASH memory for updates
to BIOS or SCRIPTS™ programs.

The LSI53C825A is a pin-for-pin replacement for the LSI53C825 PCI to
SCSI I/O processor, although some software enhancements are needed
to take advantage of the features in the LSI53C825A. The LSI53C825A
performs fast 8-bit or 16-bit SCSI transfers in Single-Ended (SE) or
differential mode, and improves performance by optimizing PCI bus
utilization.

The LSI53C825A integrates a high-performance SCSI core, a PCI bus
master DMA core, and the LSI Logic SCSI SCRIPTS processor to meet
the flexibility requirements of SCSI-3 and future SCSI standards. It is
designed to implement multithreaded I/O algorithms with a minimum of
processor intervention, solving the protocol overhead problems of
previous intelligent and nonintelligent adapter designs.

The LSI53C825A is fully supported by the LSI Logic Storage Device
Management System (SDMS™), a software package that supports the
Advanced SCSI Protocol Interface(ASPI)andtheANSICommonAccess
Method (CAM). SDMS provides BIOS and driver support for hard disk,
tape, removable media products, and CD-ROM under the major PC
operating systems.

1.2 Package and Feature Options

The LSI53C825A is packaged in a 160-pin plastic quad flat pack. The
device is also available, as the LSI53C825AJ, with additional pins that
support JTAG boundary scan testing. The JTAG boundary scan signals
replace the TESTIN, MAC/_TESTOUT, BIG_LIT/, and SDIRP1 pins. The
devices that have been upgraded to include the power management
features are the LSI53C825AE and LSI53C825AJE.

1-2 Introduction

1.2.1 PCI Pad Power-up Sequence

This power-up sequence should be followed when separate power
supplies are being applied to the VDD-IO and VDD-CORE pins in a chip
testing environment. Following this recommended power-up sequence
helps prevent potential damage to these devices.

1.2.1.1 Description of the Issue

The Universal PCI pad input receiver in this cell library has all devices in
a common N well attached to the 5 V core VDD supply. The P channel
is powered from the VDD PCI supply.

In the event that the I/O VDD PCI supply goes high prior to the core VDD
supply, the parasitic diode between the P channel source and the N well
of the device can become forward biased. This creates an excessive
current flow between the two nodes, and it causes damage to the device.

1.2.1.2 Solution for the Issue

In most system applications and production environments, the two VDD
pins power-up simultaneously. The user should know of this potential
hazard if using separate power supplies in a testing environment.

Either power-up the Core and I/O VDD PCI simultaneously, or if this is
not possible, power-up the Core VDD before powering up the I/O VDD
PCI supply.

Note that a power-down situation can have the same effect. The I/O must
always power-down prior to the Core.

1.3 TolerANT®Technology

The LSI53C825A features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation drives the SCSI Request, Acknowledge, Data,
and Parity signals HIGH rather than passively pulled up by terminators.
Active negation is enabled by setting bit 7 in the SCSI Test Three

(STEST3) register.

TolerANT®Technology 1-3

TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations. TolerANT input signal filtering is a built-in feature of the
LSI53C825A and all LSI Logic fast SCSI devices. On the LSI53C825A,
the user may select a filtering period of 30 or 60 ns, with bit 1 in the SCSI

Test Two (STEST2) register.

The benefits of TolerANT technology include increased immunity to noise
when the signal is going HIGH, better performance due to balanced duty
cycles, and improvedfast SCSI transfer rates. In addition, TolerANT SCSI
devices do not cause glitches on the SCSI bus at power-up or
power-down, so other devices on the bus are also protected from data
corruption. TolerANT technology is compatible with both the Alternative
One and Alternative Two termination schemes proposed by the American
National Standards Institute.

1.4 LSI53C825A Benefits Summary

This section provides an overview of the LSI53C825A features and
benefits. It contains information on SCSI Performance, PCI Performance,

Integration, Ease of Use, Flexibility, Reliability, and Testability.

1.4.1 SCSI Performance

To improve SCSI performance, the LSI53C825A:

• Includes 4 Kbyte internal RAM for SCRIPTS instruction storage

• SCSI synchronous offset increased from 8 to 16 levels

• Supports variable block size and scatter/gather data transfers

• Performs sustained memory-to-memory DMA transfers faster than

47 Mbytes/s (@ 33 MHz)

• Minimizes SCSI I/O start latency

• Performs complex bus sequences without interrupts, including

restore data pointers

1-4 Introduction

• Reduces ISR overhead through a unique interrupt status reporting

method

• Performs fast and wide SCSI bus transfers in SE and differential

mode
– 10 Mbytes/s asynchronous

• 20 Mbytes/s synchronous Load/Store SCRIPTS instruction increases

performance of data transfers to and from chip registers

• Supports target disconnect and later reconnect with no interrupt to

the system processor

• Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast

I/O context switching

• Expanded Register Move instruction supports additional arithmetic

capability

• Complies with PCI Bus Power Management Specification

(LSI53C825AE), Revision 1.0

1.4.2 PCI Performance

To improve PCI performance, the LSI53C825A:

• Complies with PCI 2.1 specification

• Bursts 2, 4, 8, 16, 32, 64, or 128 Dwords across PCI bus

• Supports 32-bit word data bursts with variable burst lengths

• Prefetches up to 8 Dwords of SCRIPTS instructions

• Bursts SCRIPTS opcode fetches across the PCI bus

• Performs zero wait-state bus master data bursts faster than

110 Mbytes/s (@ 33 MHz)

• Supports PCI Cache Line Size register

• Supports PCI Write and Invalidate, Read Line, and Read Multiple

commands

LSI53C825A Benefits Summary 1-5

1.4.3 Integration

The LSI53C825A contains these integration features:

• 3.3 V/5 V PCI interface

• Full 32-bit PCI DMA bus master

• Can be used as a third-party PCI bus DMA controller by using

• High-performance SCSI core

• Integrated SCRIPTS processor

1.4.4 Ease of Use

The LSI53C825A provides ease of use by having:

• Up to one megabyte of add-in memory support for BIOS and

• Direct PCI to SCSI connection

• Reduced SCSI development effort

• Easily adapted to the ASPI or the ANSI CAM, with SDMS software

• Compiler compatible withexisting LSI53C7XX and LSI53C8XX family

Memory-to-Memory Move instructions

SCRIPTS storage

SCRIPTS

• Direct connection to PCI, SCSI SE, and differential buses

• Development tools and sample SCSI SCRIPTS available

• Maskable and pollable interrupts

• Wide SCSI, A or P cable, and up to 16 devices supported

• Three programmable SCSI timers: Select/Reselect, Handshake-to-

Handshake, and General Purpose. The time-out period is
programmable from 100 µs to greater than 25.6 seconds

• SDMS software for complete PC-based operating system support

• Support for relative jumps

• SCSI Selected As ID bits (SSAID) for responding with multiple IDs

1-6 Introduction

1.4.5 Flexibility

The LSI53C825A contains these flexibility features:

• High level programming interface (SCSI SCRIPTS)

• Programs local memory bus Flash memory

• Big/little endian support

• Selectable 88-byte or 536-byte DMA FIFO for backward compatibility

• Tailored SCSI sequences execute from main system RAM or internal

SCRIPTS RAM

• Flexible programming interface to tune I/O performance or to adapt

to unique SCSI devices

• Support for changes in the logical I/O interface definition

• Low level access to all registers and all SCSI bus signals

• Fetch, Master, and Memory Access control pins

• Separate SCSI and system clocks

• Selectable IRQ pins disable bit

• 32 additional scratch pad registers

• Ability to route system clock to SCSI clock

1.4.6 Reliability

The LSI53C825A contains these reliability features:

• 2 kV ESD protection on SCSI signals

• Typical 300 mV SCSI bus hysteresis

• Protection against bus reflections due to impedance mismatches

• Controlled bus assertion times (reduces RFI, improves reliability, and

eases FCC certification)

• Latch-up protection greater than 150 mA

• Voltage feed-through protection (minimum leakage current through

SCSI pads)

• 25% of pins are power and ground

• Power and ground isolation of I/O pads and internal chip logic

LSI53C825A Benefits Summary 1-7

1.4.7 Testability

• TolerANT technology provides:

– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved Fast SCSI transfer rates

– Input signal filtering on SCSI receivers improves data integrity,

even in noisy cabling environments

• JTAG Boundary scan support (LSI53C825AJ only)

The LSI53C825A contains these testability features:

• All SCSI signals accessible through programmed I/O

• SCSI loopback diagnostics

• SCSI bus signal continuity checking

• Support for single-step mode operation

• Test mode (AND tree) to check pin continuity to the board (most

package options)

• JTAG Boundary scan support (LSI53C825AJ only)

A system diagram showing the connections of the LSI53C825A with an
external ROM or Flash memory is pictured in Figure 1.1. A block diagram
of the LSI53C825A is pictured in Figure 1.2.

1-8 Introduction

Figure 1.1 LSI53C825A External Memory Interface

PCI Bus

SCSI Bus

GPIO4

MWE/

MOE/
MCE/

MAD[7:0]

MAS0/

LSI53C825A

MAS1/

GPIO2_MAS2/

BIG_LIT

V

PP

V

PP

Translator

(Optional)

HCT374

HCT374

HCT374

(Optional)

V

PP

ROM or Flash

Memory

D[7:0]

A[7:0]

A[15:8]

A[19:16]

LSI53C825A Benefits Summary 1-9

Figure 1.2 LSI53C825A Chip Block Diagram

PCI

PCI Master and Slave Control Block

External
Memory

Memory

Control

Local

Bus

Memory

Data

FIFO

536 Bytes

SCSI

SCRIPTS

Processor

SCSI FIFO and SCSI Control Block

Operating
Registers

TolerANT Drivers and Receivers

SCSI Bus

Configuration

Registers

SCRIPTS

RAM

1-10 Introduction

Chapter 2
Functional Description

Chapter 2 is divided into the following sections:

• Section 2.1, “PCI Addressing”

• Section 2.2, “SCSI Functional Description”

• Section 2.3, “External Memory Interface”

• Section 2.4, “PCI Cache Mode”

• Section 2.5, “Power Management”

2.1 PCI Addressing

There are three physical PCI-defined address spaces:

• PCI Configuration Space

• I/O Space

• Memory Space

2.1.1 Configuration Space

Configuration space is a contiguous 256 x 8-bit set of addresses
dedicated to each “slot” or “stub” on the bus. Decoding C_BE/[3:0]
determines if a PCI cycle is intended to access configuration register
space. The IDSEL bus signal is a “chip select” that allows access to the
configuration register space only. A configuration read/write cycle without
IDSEL is ignored. The eight lower order addresses are used to select a
specific 8-bit register. AD[10:8] are decoded as well, but they must be
zero or the LSI53C825A does not respond. According to the PCI
specification, AD[10:8] are to be used for multifunction devices. The host
processor uses the PCI configuration space to initialize the LSI53C825A.

LSI53C825A/825AE PCI to SCSI I/O Processor 2-1

The lower 128 bytes of the LSI53C825A configuration space hold system
parameters while the upper 128 bytes map into the LSI53C825A
operating registers. For all PCI cycles except configuration cycles, the
LSI53C825A registers are located on the 256-byte block boundary
defined by the base address assigned through the configured register.
The LSI53C825A operating registers are available in both the upper and
lower 128-byte portions of the 256-byte space selected.

At initialization time, each PCI device is assigned a base address (in the
case of the LSI53C825A, the upper 24 bits of the address are selected)
for memory accesses and I/O accesses. On every access, the
LSI53C825A compares its assigned base addresses with the value on
the Address/Data bus during the PCI address phase. If the upper 24 bits
match, the access is for the LSI53C825A and the low-order eight bits
define the register to be accessed. A decode of C_BE/ [3:0] determines
which registers and what type of access is to be performed.

I/O Space – PCI defines memory space as a contiguous 32-bit memory
address that is shared by all system resources, including the
LSI53C825A. Base Address One (Memory) determines which 256-byte
memory area this device will occupy.

Memory Space – PCI defines I/O space as a contiguous 32-bit I/O
address that is shared by all system resources, including the
LSI53C825A. Base Address Zero (I/O) determines which 256-byte I/O
area this device will occupy.

2.1.2 PCI Bus Commands and Functions Supported

Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE/[3:0] lines
during the address phase. PCI bus command encoding and types appear
in Table 2.1.

2-2 Functional Description

Table 2.1 PCI Bus Commands and Encoding Types

C_BE[3:0] Command Type Supported as Master Supported as Slave

0000 Special Interrupt Acknowledge No No
0001 Special Cycle No No
0010 I/O Read Cycle Yes Yes
0011 I/O Write Cycle Yes Yes
0100 Reserved N/A N/A
0101 Reserved N/A N/A
0110 Memory Read Yes Yes
0111 Memory Write Yes Yes
1000 Reserved N/A N/A
1001 Reserved N/A N/A
1010 Configuration Read No Yes
1011 Configuration Write No Yes
1100 Memory Read Multiple Yes

1

No (defaults to 0110)
1101 Dual Address Cycle No No
1110 Memory Read Line Yes
1111 Memory Write and Invalidate Yes

1. This operation is selectable by bit 2 in the DMA Mode (DMODE) operating register.

2. This operation is selectable by bit 3 in the DMA Mode (DMODE) operating register.

3. This operation is selectable by bit 0 in the Chip Test Three (CTEST3) operating register.

2

3

No (defaults to 0110)

No (defaults to 0111)

2.1.2.1 I/O Read Command

The I/O Read command reads data from an agent mapped in I/O
address space. All 32 address bits are decoded.

2.1.2.2 I/O Write Command

The I/O Write command writes data to an agent when mapped in I/O
address space. All 32 address bits are decoded.

PCI Addressing 2-3

2.1.2.3 Memory Read Command

The Memory Read command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.

2.1.2.4 Memory Write Command

The Memory Write command writes data to an agent when mapped in
memory address space. All 32 address bits are decoded.

2.1.2.5 Memory Read Multiple Command

The Memory Read Multiple command reads data from an agent mapped
in memory address space. All 32 address bits are decoded.

2.1.2.6 Memory Read Line Command

The Memory Read Line command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.

2.1.2.7 Memory Write and Invalidate Command

The Memory Write and Invalidate command writes data to an agent
when mapped in memory address space. All 32 address bits are
decoded.

2.1.3 PCI Cache Mode

The LSI53C825A supports the PCI specification for an 8-bit Cache Line

Size register located in PCI configuration space. The Cache Line Size

register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. In conjunction with the Cache

Line Size register, the PCI commands Read Line, Read Multiple, and

Write and Invalidate are each software enabled or disabled to allow the
user full flexibility in using these commands.

2.1.3.1 Support for PCI Cache Line Size Register

The LSI53C825A supports the PCI specification for an 8-bit Cache Line

Size register in PCI configuration space. It can sense and react to

nonaligned addresses corresponding to cache line boundaries.

2-4 Functional Description

2.1.3.2 Selection of Cache Line Size

The cache logic selects a cache line size based on the values for the
burst size in the DMA Mode (DMODE) register, bit 2 in the Chip Test Five

(CTEST5) register, and the PCI Cache Line Size register.

Note: The LSI53C825A does not automatically use the value in

the PCI Cache Line Size register as the cache line size
value. The chip scales the value of the Cache Line Size
register down to the nearest binary burst size allowed by
the chip (2, 4, 8, 16, 32, 64, or 128), compares this value
to the burst size defined by the values of the DMA Mode

(DMODE) register and bit 2 of the Chip TestFive (CTEST5)

register, then selects the smallest as the value for the
cache line size. The LSI53C825A uses this value for all
burst data transfers.

2.1.3.3 Alignment

The LSI53C825A uses the calculated line size value to monitor the
current address for alignment to the cache line size. When it is not
aligned, the chip attempts to align to the cache boundary by using a
“smart aligning” scheme. This means that it attempts to use the largest
burst size possible that is less than the cache line size, to reach the
cache boundary quickly with no overflow. This process is a stepping
mechanism that steps up to the highest possible burst size based on the
current address.

The stepping process begins at a 4 Dword boundary. The LSI53C825A
will first try to align to a 4 Dword boundary (0x00, 0x010, 0x020, etc.) by
using single Dword transfers (no bursting). Once this boundary is
reached the chip evaluates the current alignment to various burst sizes
allowed, and selects the largest possible as the next burst size, while not
exceeding the cache line size. The chip then issues this burst, and
reevaluates the alignment to various burst sizes, again selecting the
largest possible while not exceeding the cache line size, as the next burst
size. This stepping process continues until the chip reaches the cache
line size boundary or runs out of data. Once a cache line boundary is
reached, the chip uses the cache line size as the burst size from then
on, except in the case of multiples (explained below). The alignment
process is finished at this point.

PCI Addressing 2-5

Example: Cache Line Size - 16, Current Address = 0x01 – The chip
is not aligned to a 4 Dword cache boundary (the stepping threshold), so
it issues four single Dword transfers (the first is a 3-byte transfer). At
address 0x10, the chip is aligned to a 4 Dword boundary, but not aligned
to any higher burst size boundaries that are less than the cache line size.
So, the part issues a burst of 4. At this point, the address is 0x20, and
the chip evaluates that it is aligned not only toa4Dwordboundary, but
also to an 8 Dword boundary. It selects the highest, 8, and burst
8 Dwords. At this point, the address is 0x40, which is a cache line size
boundary. Alignment stops, and the burst size from then on is switched
to 16.

2.1.3.4 Memory Move Misalignment

The LSI53C825A does not operate in a cache alignment mode when a
Memory Move instruction type is issued and the read and write
addresses are different distances from the nearest cache line boundary.
For example, if the read address is 0x21F and the write address is 0x42F,
and the cache line size is 8, the addresses are byte aligned, but they are
not the same distance from the nearest cache boundary. The read
address is 1 byte from the cache boundary 0x220 and the write address
is 17 bytes from the cache boundary 0x440. In this situation, the chip
does not align to cache boundaries and operates as a LSI53C825.

2.1.3.5 Memory Write and Invalidate Command

The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; that is to say, the master intends to
write all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI Cache Line Size register at address 0x0C in PCI configuration
space. The LSI53C825A enables Memory Write and Invalidate cycles
when bit 0 in the Chip Test Three (CTEST3) register (WRIE) and bit 4 in
the PCI Command register are set. When the following conditions are
met, Memory Write and Invalidate commands are issued:

• The CLSE bit, WRIE bit, and PCI configuration Command register,

bit 4 are set.

2-6 Functional Description