Avago Technologies LSI53C825AE User Manual

TECHNICAL

MANUAL

LSI53C825A/825AE
PCI to SCSI
I/O Processor

Version 3.1

January 2001

®

S14058

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000159-00, Fourth Edition (January 2001)
This document describes the LSI Logic LSI53C825A/AE PCI to SCSI I/O
Processor and will remain the official reference source for all revisions/releases
of this product until rescinded by an update.

To receive product literature, visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Copyright © 1998–2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

The LSI Logic logo design, TolerANT, SDMS, and SCRIPTS are registered
trademarks or trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.

ii

Audience

Organization

Preface

This book is the primary reference and technical manual for the LSI Logic
LSI53C825A/825AE PCI to SCSI I/O Processor. It contains a complete
functional description for the LSI53C825A/825AE and includes complete
physical and electrical specifications for the LSI53C825A/825AE.

This technical manual is intended for system designers and programmers
who are using this device to design a SCSI port for PCI-based personal
computers, workstations, or embedded applications.

This document has the following chapters and appendixes:

• Chapter 1, Introduction, includes general information about the

LSI53C825A and other members of the LSI53C8XX family of PCI to
SCSI I/O Processors.

• Chapter 2, Functional Description, describes the main functional

areas of the chip in more detail, including the interfaces to the SCSI
bus.

• Chapter 3, Signal Descriptions, describes the chip’s connection to

the PCI bus, including the PCI commands and configuration registers
supported.

• Chapter 4, Registers, contains the pin diagrams and definitions of

each signal.

• Chapter 5, SCSI SCRIPTS Instruction Set, describes each bit in the

operating registers, organized by address.

Preface iii

• Chapter 6, Specifications, defines all of the SCSI SCRIPTS

• Appendix A, Register Summary, contains a register summary.

• Appendix B, External Memory Interface Diagram Examples,

Related Publications

For background information, please contact:

ANSI

11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2); X3.253 (

Parallel Interface

instructions that are supported by the LSI53C825A.

contains several example interface drawings to connect the
LSI53C825A to an external ROM.

SCSI-3

)

ENDL Publications

14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names:

Tutor

Prentice Hall

113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8,

the Small Computer System Interface

LSI Logic World Wide Web Home Page

www.lsilogic.com

iv Preface

SCSI Bench Reference, SCSI Encyclopedia, SCSI

SCSI: Understanding

SCSI SCRIPTS™ Processors Programming Guide

Order Number S15044.A

PCI Special Interest Group

2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]

Conventions Used in This Manual

, Version 2.2,

The word

deassert

assert

means to drive a signal true or active. The word

means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision Record

Revision Date Remarks

1.0 6/95 Revision 1.0

2.0 3/96 Revision 2.0

3.0 12/97 Revision 3.0

3.1 1/01 Product names changed from SYM to LSI.

Preface v

vi Preface

Contents

Chapter 1 Introduction

1.1 General Description 1-1

1.2 Package and Feature Options 1-2

1.2.1 PCI Pad Power-up Sequence 1-3

1.3 TolerANT®Technology 1-3

1.4 LSI53C825A Benefits Summary 1-4

1.4.1 SCSI Performance 1-4

1.4.2 PCI Performance 1-5

1.4.3 Integration 1-6

1.4.4 Ease of Use 1-6

1.4.5 Flexibility 1-7

1.4.6 Reliability 1-7

1.4.7 Testability 1-8

Chapter 2 Functional Description

2.1 PCI Addressing 2-1

2.1.1 Configuration Space 2-1

2.1.2 PCI Bus Commands and Functions Supported 2-2

2.1.3 PCI Cache Mode 2-4

2.2 SCSI Functional Description 2-10

2.2.1 SCSI Core 2-10

2.2.2 DMA Core 2-11

2.2.3 SCRIPTS Processor 2-11

2.2.4 Internal SCRIPTS RAM 2-11

2.2.5 SDMS: The Total SCSI Solution 2-12

2.2.6 Prefetching SCRIPTS Instructions 2-13

2.2.7 Opcode Fetch Burst Capability 2-14

2.3 External Memory Interface 2-14

2.4 PCI Cache Mode 2-17

Contents vii

2.4.1 Load and Store Instructions 2-17

2.4.2 3.3 V/5 V PCI Interface 2-17

2.4.3 Additional Access to General Purpose Pins 2-17

2.4.4 JTAG Boundary Scan Testing 2-18

2.4.5 Big and Little Endian Support 2-19

2.4.6 Loopback Mode 2-20

2.4.7 Parity Options 2-21

2.4.8 DMA FIFO 2-23

2.4.9 SCSI Bus Interface 2-27

2.4.10 Select/Reselect During Selection/Reselection 2-33

2.4.11 Synchronous Operation 2-33

2.4.12 Achieving Optimal SCSI Send Rates 2-34

2.4.13 Interrupt Handling 2-35

2.4.14 Chained Block Moves 2-42

2.5 Power Management 2-46

2.5.1 Power State D0 2-46

2.5.2 Power State D3 2-46

Chapter 3 Signal Descriptions

3.1 PCI Bus Interface Signals 3-6

3.1.1 System Signals 3-6

3.1.2 Address and Data Signals 3-7

3.1.3 Interface Control Signals 3-8

3.1.4 Arbitration Signals 3-9

3.1.5 Error Reporting Signals 3-9

3.1.6 SCSI Bus Interface Signals 3-10

3.1.7 Additional Interface Signals 3-11

3.1.8 External Memory Interface Signals 3-14

3.1.9 JTAG Signals 3-15

3.2 MAD Bus Programming 3-15

Chapter 4 Registers

4.1 Configuration Registers 4-1

4.2 Operating Registers 4-18

viii Contents

Chapter 5 SCSI SCRIPTS Instruction Set

5.1 Low Level Register Interface Mode 5-1

5.2 High Level SCSI SCRIPTS Mode 5-2

5.2.1 Sample Operation 5-3

5.3 Block Move Instructions 5-6

5.3.1 First Dword 5-6

5.3.2 Second Dword 5-13

5.4 I/O Instruction 5-14

5.4.1 First Dword 5-14

5.4.2 Second Dword 5-23

5.5 Read/Write Instructions 5-24

5.5.1 First Dword 5-24

5.5.2 Second Dword 5-26

5.5.3 Read-Modify-Write Cycles 5-26

5.5.4 Move To/From SFBR Cycles 5-27

5.6 Transfer Control Instructions 5-29

5.6.1 First Dword 5-29

5.6.2 Second Dword 5-36

5.7 Memory Move Instructions 5-36

5.7.1 First Dword 5-37

5.7.2 Read/Write System Memory from SCRIPTS 5-38

5.7.3 Second Dword 5-38

5.7.4 Third Dword 5-38

5.8 Load and Store Instructions 5-40

5.8.1 First Dword 5-41

5.8.2 Second Dword 5-42

Chapter 6 Specifications

6.1 DC Characteristics 6-1

6.2 TolerANT Technology Electrical Characteristics 6-7

6.3 AC Characteristics 6-11

6.4 PCI and External Memory Interface Timing Diagrams 6-13

6.4.1 Target Timing 6-15

6.4.2 Initiator Timing 6-24

6.4.3 External Memory Timing 6-32

Contents ix

6.5 PCI and External Memory Interface Timing 6-44

6.6 SCSI Timing Diagrams 6-45

6.7 Package Drawings 6-52

Appendix A Register Summary

Appendix B External Memory Interface Diagram Examples

Index

Customer Feedback

Figures

1.1 LSI53C825A External Memory Interface 1-9

1.2 LSI53C825A Chip Block Diagram 1-10

2.1 DMA FIFO Sections 2-23

2.2 LSI53C825A Host Interface Data Paths 2-27

2.3 LSI53C825A Differential Wiring Diagram 2-31

2.4 Regulated Termination 2-32

2.5 Determining the Synchronous Transfer Rate 2-35

2.6 Block Move and Chained Block Move Instructions 2-45

3.1 LSI53C825A Pin Diagram 3-2

3.2 LSI53C825AJ Pin Diagram 3-3

3.3 LSI53C825A Functional Signal Grouping 3-5

5.1 SCRIPTS Overview 5-5

5.2 Block Move Instruction Register 5-8

5.3 I/O Instruction Register 5-17

5.4 Read/Write Instruction Register 5-25

5.5 Transfer Control Instruction 5-31

5.6 Memory Move Instruction 5-39

5.7 Load and Store Instruction Format 5-43

6.1 Rise and Fall Time Test Conditions 6-9

6.2 SCSI Input Filtering 6-9

6.3 Hysteresis of SCSI Receivers 6-9

6.4 Input Current as a Function of Input Voltage 6-10

6.5 Output Current as a Function of Output Voltage 6-10

x Contents

6.6 External Clock 6-11

6.7 Reset Input 6-12

6.8 Interrupt Output 6-13

6.9 PCI Configuration Register Read 6-15

6.10 PCI Configuration Register Write 6-16

6.11 Operating Register/SCRIPTS RAM Read 6-17

6.12 Operating Register/SCRIPTS RAM Write 6-18

6.13 External Memory Read 6-20

6.14 External Memory Write 6-22

6.15 Nonburst Opcode Fetch 6-24

6.16 Burst Opcode Fetch 6-25

6.17 Back-to-Back Read 6-26

6.18 Back-to-Back Write 6-27

6.19 Burst Read 6-28

6.20 Burst Write 6-30

6.21 Read Cycle, Normal/Fast Memory (≥ 64 Kbytes),
Single Byte Access 6-32

6.22 Write Cycle, Normal/Fast Memory (≥ 64 Kbytes),
Single Byte Access 6-33

6.23 Read Cycle, Normal/Fast Memory (≥ 64 Kbytes),
Multiple Byte Access 6-34

6.24 Write Cycle, Normal/Fast Memory (≥ 64 Kbytes),
Multiple Byte Access 6-36

6.25 Read Cycle, Slow Memory (≥ 64 Kbytes) 6-38

6.26 Write Cycle, Slow Memory (≥ 64 Kbytes) 6-39

6.27 Read Cycle, Normal/Fast Memory (≥ 64 Kbytes) 6-40

6.28 Write Cycle, Normal/Fast Memory (≥ 64 Kbytes) 6-41

6.29 Read Cycle, Slow Memory (≤ 64 Kbytes) 6-42

6.30 Write Cycle, Slow Memory (≤ 64 Kbytes) 6-43

6.31 Initiator Asynchronous Send 6-45

6.32 Initiator Asynchronous Receive 6-46

6.33 Target Asynchronous Send 6-47

6.34 Target Asynchronous Receive 6-48

6.35 Initiator and Target Synchronous Transfers 6-48

6.36 LSI53C825A 160 Pin PQFP (PF) Mechanical Drawing 6-52

B.1 64 Kbyte Interface with 200 ns Memory B-1

Contents xi

Tables

B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 256 Kbyte Interface with 150 ns Memory B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4

2.1 PCI Bus Commands and Encoding Types 2-3

2.2 External Memory Support 2-16

2.3 Bits Used for Parity Control and Generation 2-21

2.4 SCSI Parity Control 2-22

2.5 SCSI Parity Errors and Interrupts 2-23

2.6 Differential Mode 2-28

3.1 LSI53C825A, LSI53C825AJ, LSI53C825AE, and
LSI53C825AJE Power and Ground Pins 3-4

3.2 System Signals 3-6

3.3 Address and Data Signals 3-7

3.4 Interface Control Signals 3-8

3.5 Arbitration Signals 3-9

3.6 Error Reporting Signals 3-9

3.7 SCSI Bus Interface Signals 3-10

3.8 Additional Interface Signals 3-11

3.9 External Memory Interface Signals 3-14

3.10 JTAG Signals (LSI53C825AJ, LSI53C825AJE Only) 3-15

3.11 Subsystem Data Configuration Table for the
LSI53C825AE (PCI Rev ID 0x26) 3-16

3.12 Subsystem Data Configuration Table for the
LSI53C825A (PCI Rev ID 0x14) Revision G Only 3-16

3.13 External Memory Support 3-17

4.1 PCI Configuration Register Map 4-2

4.2 LSI53C825A Register Map 4-19

4.3 Synchronous Clock Conversion Factor 4-29

4.4 Examples of Synchronous Transfer Periods and
Rates for SCSI-1 4-33

4.5 Example Transfer Periods and Rates for Fast SCSI-2 4-33

4.6 Maximum Synchronous Offset 4-34

4.7 Timeout Periods 4-82

4.8 Timeout Periods, 50 MHz Clock 4-83

5.1 SCRIPTS Instructions 5-3

5.2 Read/Write Instructions 5-27

xii Contents

6.1 Absolute Maximum Stress Ratings 6-2

6.2 Operating Conditions 6-2

6.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/ 6-3

6.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/,
SSEL/, SRST/ 6-3

6.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/,
TESTIN, DIFFSENS, BIG_LIT/ 6-3

6.6 Capacitance 6-4

6.7 Output Signals—MAC/_TESTOUT, REQ/ 6-4

6.8 Output Signals—IRQ/, SDIR[15:0], SDIRP0, SDIRP1,
BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/[1:0],
MCE/, MOE/, MWE/ 6-4

6.9 Output Signal—SERR/ 6-4

6.10 Bidirectional Signals—AD[31:0], C_BE[3:0], FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR/ 6-5

6.11 Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/, GPIO2_MAS2/, GPIO3, GPIO4 6-5

6.12 Bidirectional Signals—MAD[7:0] 6-6

6.13 Input Signals—TDI, TMS, TCK (LSI53C825AJ only) 6-6

6.14 Output Signal—TDO (LSI53C825AJ only) 6-6

6.15 TolerANT Technology Electrical Characteristics 6-8

6.16 External Clock 6-11

6.17 Reset Input 6-12

6.18 Interrupt Output 6-13

6.19 LSI53C825A PCI and External Memory Interface
Timing 6-44

6.20 Initiator Asynchronous Send 6-45

6.21 Initiator Asynchronous Receive 6-46

6.22 Target Asynchronous Send 6-47

6.23 Target Asynchronous Receive 6-48

6.24 SCSI-1 Transfers (SE 5.0 Mbytes) 6-49

6.25 SCSI-1 Transfers (Differential, 4.17 Mbytes/s) 6-49

6.26 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers)
or 20.0 Mbytes/s (16-Bit Transfers), 40 MHz Clock) 6-50

6.27 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers)
or 20.0 Mbytes/s (16-Bit Transfers) 50 MHz Clock 6-50

A.1 Configuration Registers A-1
A.2 LSI53C825A Register Map A-2

Contents xiii

xiv Contents

Chapter 1
Introduction

This chapter includes general information about the LSI53C825A and
other members of the LSI53C8XX family of PCI to SCSI I/O Processors
and contains the following sections:

• Section 1.1, “General Description”

• Section 1.2, “Package and Feature Options”

• Section 1.3, “TolerANT

• Section 1.4, “LSI53C825A Benefits Summary”

1.1 General Description

This manual combines information on the LSI53C825A and
LSI53C825AE, which are PCI to SCSI I/O Processors. The
LSI53C825AE is a minor modification of the existing LSI53C825A
product. It has all the functionality of the LSI53C825A with the addition
of features to enable it to comply with the Microsoft PC 97 Hardware
Design Guide. Specifically, the LSI53C825AE has a Power Management
Support enhancement. Because there are only slight differences
between them, the LSI53C825A and LSI53C825AE are referred to as
LSI53C825A throughout this technical manual. Only the new
enhancements are referred to as LSI53C825AE.

®

Technology”

This technical manual assumes the user is familiar with the current and
proposed standards for SCSI and PCI. For additional background
information on these topics, please refer to the list of reference materials
provided in the Preface of this document.

The LSI53C825A PCI to SCSI I/O Processor brings high-performance
I/O solutions to host adapter, workstation, and general computer designs,
making it easy to add SCSI to any PCI system. It provides a local

LSI53C825A/825AE PCI to SCSI I/O Processor 1-1

memory bus for local storage of the device’s BIOS ROM in flash memory
or standard EPROMs. The LSI53C825A supports big and little endian
byte addressing to accommodate a variety of data configurations. The
LSI53C825A supports programming of local FLASH memory for updates
to BIOS or SCRIPTS™ programs.

The LSI53C825A is a pin-for-pin replacement for the LSI53C825 PCI to
SCSI I/O processor, although some software enhancements are needed
to take advantage of the features in the LSI53C825A. The LSI53C825A
performs fast 8-bit or 16-bit SCSI transfers in Single-Ended (SE) or
differential mode, and improves performance by optimizing PCI bus
utilization.

The LSI53C825A integrates a high-performance SCSI core, a PCI bus
master DMA core, and the LSI Logic SCSI SCRIPTS processor to meet
the flexibility requirements of SCSI-3 and future SCSI standards. It is
designed to implement multithreaded I/O algorithms with a minimum of
processor intervention, solving the protocol overhead problems of
previous intelligent and nonintelligent adapter designs.

The LSI53C825A is fully supported by the LSI Logic Storage Device
Management System (SDMS™), a software package that supports the
Advanced SCSI Protocol Interface(ASPI)andtheANSICommonAccess
Method (CAM). SDMS provides BIOS and driver support for hard disk,
tape, removable media products, and CD-ROM under the major PC
operating systems.

1.2 Package and Feature Options

The LSI53C825A is packaged in a 160-pin plastic quad flat pack. The
device is also available, as the LSI53C825AJ, with additional pins that
support JTAG boundary scan testing. The JTAG boundary scan signals
replace the TESTIN, MAC/_TESTOUT, BIG_LIT/, and SDIRP1 pins. The
devices that have been upgraded to include the power management
features are the LSI53C825AE and LSI53C825AJE.

1-2 Introduction

1.2.1 PCI Pad Power-up Sequence

This power-up sequence should be followed when separate power
supplies are being applied to the VDD-IO and VDD-CORE pins in a chip
testing environment. Following this recommended power-up sequence
helps prevent potential damage to these devices.

1.2.1.1 Description of the Issue

The Universal PCI pad input receiver in this cell library has all devices in
a common N well attached to the 5 V core VDD supply. The P channel
is powered from the VDD PCI supply.

In the event that the I/O VDD PCI supply goes high prior to the core VDD
supply, the parasitic diode between the P channel source and the N well
of the device can become forward biased. This creates an excessive
current flow between the two nodes, and it causes damage to the device.

1.2.1.2 Solution for the Issue

In most system applications and production environments, the two VDD
pins power-up simultaneously. The user should know of this potential
hazard if using separate power supplies in a testing environment.

Either power-up the Core and I/O VDD PCI simultaneously, or if this is
not possible, power-up the Core VDD before powering up the I/O VDD
PCI supply.

Note that a power-down situation can have the same effect. The I/O must
always power-down prior to the Core.

1.3 TolerANT®Technology

The LSI53C825A features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation drives the SCSI Request, Acknowledge, Data,
and Parity signals HIGH rather than passively pulled up by terminators.
Active negation is enabled by setting bit 7 in the SCSI Test Three

(STEST3) register.

TolerANT®Technology 1-3

TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations. TolerANT input signal filtering is a built-in feature of the
LSI53C825A and all LSI Logic fast SCSI devices. On the LSI53C825A,
the user may select a filtering period of 30 or 60 ns, with bit 1 in the SCSI

Test Two (STEST2) register.

The benefits of TolerANT technology include increased immunity to noise
when the signal is going HIGH, better performance due to balanced duty
cycles, and improvedfast SCSI transfer rates. In addition, TolerANT SCSI
devices do not cause glitches on the SCSI bus at power-up or
power-down, so other devices on the bus are also protected from data
corruption. TolerANT technology is compatible with both the Alternative
One and Alternative Two termination schemes proposed by the American
National Standards Institute.

1.4 LSI53C825A Benefits Summary

This section provides an overview of the LSI53C825A features and
benefits. It contains information on SCSI Performance, PCI Performance,

Integration, Ease of Use, Flexibility, Reliability, and Testability.

1.4.1 SCSI Performance

To improve SCSI performance, the LSI53C825A:

• Includes 4 Kbyte internal RAM for SCRIPTS instruction storage

• SCSI synchronous offset increased from 8 to 16 levels

• Supports variable block size and scatter/gather data transfers

• Performs sustained memory-to-memory DMA transfers faster than

47 Mbytes/s (@ 33 MHz)

• Minimizes SCSI I/O start latency

• Performs complex bus sequences without interrupts, including

restore data pointers

1-4 Introduction

• Reduces ISR overhead through a unique interrupt status reporting

method

• Performs fast and wide SCSI bus transfers in SE and differential

mode
– 10 Mbytes/s asynchronous

• 20 Mbytes/s synchronous Load/Store SCRIPTS instruction increases

performance of data transfers to and from chip registers

• Supports target disconnect and later reconnect with no interrupt to

the system processor

• Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast

I/O context switching

• Expanded Register Move instruction supports additional arithmetic

capability

• Complies with PCI Bus Power Management Specification

(LSI53C825AE), Revision 1.0

1.4.2 PCI Performance

To improve PCI performance, the LSI53C825A:

• Complies with PCI 2.1 specification

• Bursts 2, 4, 8, 16, 32, 64, or 128 Dwords across PCI bus

• Supports 32-bit word data bursts with variable burst lengths

• Prefetches up to 8 Dwords of SCRIPTS instructions

• Bursts SCRIPTS opcode fetches across the PCI bus

• Performs zero wait-state bus master data bursts faster than

110 Mbytes/s (@ 33 MHz)

• Supports PCI Cache Line Size register

• Supports PCI Write and Invalidate, Read Line, and Read Multiple

commands

LSI53C825A Benefits Summary 1-5

1.4.3 Integration

The LSI53C825A contains these integration features:

• 3.3 V/5 V PCI interface

• Full 32-bit PCI DMA bus master

• Can be used as a third-party PCI bus DMA controller by using

• High-performance SCSI core

• Integrated SCRIPTS processor

1.4.4 Ease of Use

The LSI53C825A provides ease of use by having:

• Up to one megabyte of add-in memory support for BIOS and

• Direct PCI to SCSI connection

• Reduced SCSI development effort

• Easily adapted to the ASPI or the ANSI CAM, with SDMS software

• Compiler compatible withexisting LSI53C7XX and LSI53C8XX family

Memory-to-Memory Move instructions

SCRIPTS storage

SCRIPTS

• Direct connection to PCI, SCSI SE, and differential buses

• Development tools and sample SCSI SCRIPTS available

• Maskable and pollable interrupts

• Wide SCSI, A or P cable, and up to 16 devices supported

• Three programmable SCSI timers: Select/Reselect, Handshake-to-

Handshake, and General Purpose. The time-out period is
programmable from 100 µs to greater than 25.6 seconds

• SDMS software for complete PC-based operating system support

• Support for relative jumps

• SCSI Selected As ID bits (SSAID) for responding with multiple IDs

1-6 Introduction

1.4.5 Flexibility

The LSI53C825A contains these flexibility features:

• High level programming interface (SCSI SCRIPTS)

• Programs local memory bus Flash memory

• Big/little endian support

• Selectable 88-byte or 536-byte DMA FIFO for backward compatibility

• Tailored SCSI sequences execute from main system RAM or internal

SCRIPTS RAM

• Flexible programming interface to tune I/O performance or to adapt

to unique SCSI devices

• Support for changes in the logical I/O interface definition

• Low level access to all registers and all SCSI bus signals

• Fetch, Master, and Memory Access control pins

• Separate SCSI and system clocks

• Selectable IRQ pins disable bit

• 32 additional scratch pad registers

• Ability to route system clock to SCSI clock

1.4.6 Reliability

The LSI53C825A contains these reliability features:

• 2 kV ESD protection on SCSI signals

• Typical 300 mV SCSI bus hysteresis

• Protection against bus reflections due to impedance mismatches

• Controlled bus assertion times (reduces RFI, improves reliability, and

eases FCC certification)

• Latch-up protection greater than 150 mA

• Voltage feed-through protection (minimum leakage current through

SCSI pads)

• 25% of pins are power and ground

• Power and ground isolation of I/O pads and internal chip logic

LSI53C825A Benefits Summary 1-7

1.4.7 Testability

• TolerANT technology provides:

– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved Fast SCSI transfer rates

– Input signal filtering on SCSI receivers improves data integrity,

even in noisy cabling environments

• JTAG Boundary scan support (LSI53C825AJ only)

The LSI53C825A contains these testability features:

• All SCSI signals accessible through programmed I/O

• SCSI loopback diagnostics

• SCSI bus signal continuity checking

• Support for single-step mode operation

• Test mode (AND tree) to check pin continuity to the board (most

package options)

• JTAG Boundary scan support (LSI53C825AJ only)

A system diagram showing the connections of the LSI53C825A with an
external ROM or Flash memory is pictured in Figure 1.1. A block diagram
of the LSI53C825A is pictured in Figure 1.2.

1-8 Introduction

Figure 1.1 LSI53C825A External Memory Interface

PCI Bus

SCSI Bus

GPIO4

MWE/

MOE/
MCE/

MAD[7:0]

MAS0/

LSI53C825A

MAS1/

GPIO2_MAS2/

BIG_LIT

V

PP

V

PP

Translator

(Optional)

HCT374

HCT374

HCT374

(Optional)

V

PP

ROM or Flash

Memory

D[7:0]

A[7:0]

A[15:8]

A[19:16]

LSI53C825A Benefits Summary 1-9

Figure 1.2 LSI53C825A Chip Block Diagram

PCI

PCI Master and Slave Control Block

External
Memory

Memory

Control

Local

Bus

Memory

Data

FIFO

536 Bytes

SCSI

SCRIPTS

Processor

SCSI FIFO and SCSI Control Block

Operating
Registers

TolerANT Drivers and Receivers

SCSI Bus

Configuration

Registers

SCRIPTS

RAM

1-10 Introduction

Chapter 2
Functional Description

Chapter 2 is divided into the following sections:

• Section 2.1, “PCI Addressing”

• Section 2.2, “SCSI Functional Description”

• Section 2.3, “External Memory Interface”

• Section 2.4, “PCI Cache Mode”

• Section 2.5, “Power Management”

2.1 PCI Addressing

There are three physical PCI-defined address spaces:

• PCI Configuration Space

• I/O Space

• Memory Space

2.1.1 Configuration Space

Configuration space is a contiguous 256 x 8-bit set of addresses
dedicated to each “slot” or “stub” on the bus. Decoding C_BE/[3:0]
determines if a PCI cycle is intended to access configuration register
space. The IDSEL bus signal is a “chip select” that allows access to the
configuration register space only. A configuration read/write cycle without
IDSEL is ignored. The eight lower order addresses are used to select a
specific 8-bit register. AD[10:8] are decoded as well, but they must be
zero or the LSI53C825A does not respond. According to the PCI
specification, AD[10:8] are to be used for multifunction devices. The host
processor uses the PCI configuration space to initialize the LSI53C825A.

LSI53C825A/825AE PCI to SCSI I/O Processor 2-1

The lower 128 bytes of the LSI53C825A configuration space hold system
parameters while the upper 128 bytes map into the LSI53C825A
operating registers. For all PCI cycles except configuration cycles, the
LSI53C825A registers are located on the 256-byte block boundary
defined by the base address assigned through the configured register.
The LSI53C825A operating registers are available in both the upper and
lower 128-byte portions of the 256-byte space selected.

At initialization time, each PCI device is assigned a base address (in the
case of the LSI53C825A, the upper 24 bits of the address are selected)
for memory accesses and I/O accesses. On every access, the
LSI53C825A compares its assigned base addresses with the value on
the Address/Data bus during the PCI address phase. If the upper 24 bits
match, the access is for the LSI53C825A and the low-order eight bits
define the register to be accessed. A decode of C_BE/ [3:0] determines
which registers and what type of access is to be performed.

I/O Space – PCI defines memory space as a contiguous 32-bit memory
address that is shared by all system resources, including the
LSI53C825A. Base Address One (Memory) determines which 256-byte
memory area this device will occupy.

Memory Space – PCI defines I/O space as a contiguous 32-bit I/O
address that is shared by all system resources, including the
LSI53C825A. Base Address Zero (I/O) determines which 256-byte I/O
area this device will occupy.

2.1.2 PCI Bus Commands and Functions Supported

Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE/[3:0] lines
during the address phase. PCI bus command encoding and types appear
in Table 2.1.

2-2 Functional Description

Table 2.1 PCI Bus Commands and Encoding Types

C_BE[3:0] Command Type Supported as Master Supported as Slave

0000 Special Interrupt Acknowledge No No
0001 Special Cycle No No
0010 I/O Read Cycle Yes Yes
0011 I/O Write Cycle Yes Yes
0100 Reserved N/A N/A
0101 Reserved N/A N/A
0110 Memory Read Yes Yes
0111 Memory Write Yes Yes
1000 Reserved N/A N/A
1001 Reserved N/A N/A
1010 Configuration Read No Yes
1011 Configuration Write No Yes
1100 Memory Read Multiple Yes

1

No (defaults to 0110)
1101 Dual Address Cycle No No
1110 Memory Read Line Yes
1111 Memory Write and Invalidate Yes

1. This operation is selectable by bit 2 in the DMA Mode (DMODE) operating register.

2. This operation is selectable by bit 3 in the DMA Mode (DMODE) operating register.

3. This operation is selectable by bit 0 in the Chip Test Three (CTEST3) operating register.

2

3

No (defaults to 0110)

No (defaults to 0111)

2.1.2.1 I/O Read Command

The I/O Read command reads data from an agent mapped in I/O
address space. All 32 address bits are decoded.

2.1.2.2 I/O Write Command

The I/O Write command writes data to an agent when mapped in I/O
address space. All 32 address bits are decoded.

PCI Addressing 2-3

2.1.2.3 Memory Read Command

The Memory Read command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.

2.1.2.4 Memory Write Command

The Memory Write command writes data to an agent when mapped in
memory address space. All 32 address bits are decoded.

2.1.2.5 Memory Read Multiple Command

The Memory Read Multiple command reads data from an agent mapped
in memory address space. All 32 address bits are decoded.

2.1.2.6 Memory Read Line Command

The Memory Read Line command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.

2.1.2.7 Memory Write and Invalidate Command

The Memory Write and Invalidate command writes data to an agent
when mapped in memory address space. All 32 address bits are
decoded.

2.1.3 PCI Cache Mode

The LSI53C825A supports the PCI specification for an 8-bit Cache Line

Size register located in PCI configuration space. The Cache Line Size

register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. In conjunction with the Cache

Line Size register, the PCI commands Read Line, Read Multiple, and

Write and Invalidate are each software enabled or disabled to allow the
user full flexibility in using these commands.

2.1.3.1 Support for PCI Cache Line Size Register

The LSI53C825A supports the PCI specification for an 8-bit Cache Line

Size register in PCI configuration space. It can sense and react to

nonaligned addresses corresponding to cache line boundaries.

2-4 Functional Description

2.1.3.2 Selection of Cache Line Size

The cache logic selects a cache line size based on the values for the
burst size in the DMA Mode (DMODE) register, bit 2 in the Chip Test Five

(CTEST5) register, and the PCI Cache Line Size register.

Note: The LSI53C825A does not automatically use the value in

the PCI Cache Line Size register as the cache line size
value. The chip scales the value of the Cache Line Size
register down to the nearest binary burst size allowed by
the chip (2, 4, 8, 16, 32, 64, or 128), compares this value
to the burst size defined by the values of the DMA Mode

(DMODE) register and bit 2 of the Chip TestFive (CTEST5)

register, then selects the smallest as the value for the
cache line size. The LSI53C825A uses this value for all
burst data transfers.

2.1.3.3 Alignment

The LSI53C825A uses the calculated line size value to monitor the
current address for alignment to the cache line size. When it is not
aligned, the chip attempts to align to the cache boundary by using a
“smart aligning” scheme. This means that it attempts to use the largest
burst size possible that is less than the cache line size, to reach the
cache boundary quickly with no overflow. This process is a stepping
mechanism that steps up to the highest possible burst size based on the
current address.

The stepping process begins at a 4 Dword boundary. The LSI53C825A
will first try to align to a 4 Dword boundary (0x00, 0x010, 0x020, etc.) by
using single Dword transfers (no bursting). Once this boundary is
reached the chip evaluates the current alignment to various burst sizes
allowed, and selects the largest possible as the next burst size, while not
exceeding the cache line size. The chip then issues this burst, and
reevaluates the alignment to various burst sizes, again selecting the
largest possible while not exceeding the cache line size, as the next burst
size. This stepping process continues until the chip reaches the cache
line size boundary or runs out of data. Once a cache line boundary is
reached, the chip uses the cache line size as the burst size from then
on, except in the case of multiples (explained below). The alignment
process is finished at this point.

PCI Addressing 2-5

Example: Cache Line Size - 16, Current Address = 0x01 – The chip
is not aligned to a 4 Dword cache boundary (the stepping threshold), so
it issues four single Dword transfers (the first is a 3-byte transfer). At
address 0x10, the chip is aligned to a 4 Dword boundary, but not aligned
to any higher burst size boundaries that are less than the cache line size.
So, the part issues a burst of 4. At this point, the address is 0x20, and
the chip evaluates that it is aligned not only toa4Dwordboundary, but
also to an 8 Dword boundary. It selects the highest, 8, and burst
8 Dwords. At this point, the address is 0x40, which is a cache line size
boundary. Alignment stops, and the burst size from then on is switched
to 16.

2.1.3.4 Memory Move Misalignment

The LSI53C825A does not operate in a cache alignment mode when a
Memory Move instruction type is issued and the read and write
addresses are different distances from the nearest cache line boundary.
For example, if the read address is 0x21F and the write address is 0x42F,
and the cache line size is 8, the addresses are byte aligned, but they are
not the same distance from the nearest cache boundary. The read
address is 1 byte from the cache boundary 0x220 and the write address
is 17 bytes from the cache boundary 0x440. In this situation, the chip
does not align to cache boundaries and operates as a LSI53C825.

2.1.3.5 Memory Write and Invalidate Command

The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; that is to say, the master intends to
write all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI Cache Line Size register at address 0x0C in PCI configuration
space. The LSI53C825A enables Memory Write and Invalidate cycles
when bit 0 in the Chip Test Three (CTEST3) register (WRIE) and bit 4 in
the PCI Command register are set. When the following conditions are
met, Memory Write and Invalidate commands are issued:

• The CLSE bit, WRIE bit, and PCI configuration Command register,

bit 4 are set.

2-6 Functional Description

• The Cache Line Size register contains a legal burst size in Dwords

(2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to
the DMA Mode (DMODE) burst size.

• The chip has enough bytes in the DMA FIFO (DFIFO) to complete

at least one full cache line burst.

• The chip is aligned to a cache line boundary.

When these conditions are met, the LSI53C825A issues a Write and
Invalidate command instead of a Memory Write command during all PCI
write cycles.

Multiple Cache Line Transfers – The Write and Invalidate command
can write multiple cache lines of data in a single bus ownership. The chip
issues a burst transfer as soon as it reaches a cache line boundary. The
size of the transfer is not automatically the cache line size, but rather a
multiple of the cache line size specified in the Revision 2.1 of the PCI
specification. The logic selects the largest multiple of the cache line size
based on the amount of data to transfer, with the maximum allowable
burst size being that determined from the DMA Mode (DMODE) burst
size bits and Chip Test Five (CTEST5), bit 2. If multiple cache line size
transfers are not desired, the DMA Mode (DMODE) burst size to exactly
the cache line size and the chip only issues single cache line transfers.

After each data transfer, the chip reevaluates the burst size based on the
amount of remaining data to transfer and again selects the highest
possible multiple of the cache line size, no larger than the DMODE burst
size. The most likely scenario of this scheme is that the chip selects the
DMODE burst size after alignment, and issue bursts of this size. The
burst size is, in effect, throttled down toward the end of a long Memory
Move or Block Move transfer until only the cache line size burst size is
left. The chip finishes the transfer with this burst size.

Latency – In accordance with the PCI specification, the latency timer is
ignored when issuing a Write and Invalidate command such that when a
latency time-out occurs, the LSI53C825A continues to transfer up until a
cache line boundary. At that point, the chip relinquishes the bus, and
finishes the transfer at a later time using another bus ownership. If the
chip is transferring multiple cache lines it continues to transfer until the
next cache boundary is reached.

PCI Addressing 2-7

PCI Target Retry – During a Write and Invalidate transfer, if the target
device issues a retry (STOP with no TRDY, indicating that no data was
transferred), the chip relinquishes the bus and immediately tries to finish
the transfer on another bus ownership. The chip issues another Write
and Invalidate command on the next ownership, in accordance with the
PCI specification.

PCI Target Disconnect – During a Write and Invalidate transfer, if the
target device issues a disconnect the LSI53C825A relinquishes the bus
and immediately tries to finish the transfer on another bus ownership.
The chip does not issue another Write and Invalidate command on the
next ownership unless the address is aligned.

2.1.3.6 Memory Read Line Command

This command is identical to the Memory Read command, except that it
additionally indicates that the master intends to fetch a complete cache
line. This command is intended for use with bulk sequential data transfers
where the memory system and the requesting master might gain some
performance advantage by reading up to a cache line boundary rather
than a single memory cycle. The Read Line Mode function that exists in
the previous LSI53C8XX chips has been modified in the LSI53C825A to
reflect the PCI Cache Line Size register specifications. The functionality
of the Enable Read Line bit (bit 3 in DMA Mode (DMODE)) has been
modified to more resemble the Write and Invalidate mode in terms of
conditions that must be met before a Read Line command is issued.
However, the Read Line option operates exactly like the previous
LSI53C8XX chips when cache mode is disabled by a CLSE bit reset or
when certain conditions exist in the chip (explained below).

The Read Line mode is enabled by setting bit 3 in the DMA Mode

(DMODE) register. If cache mode is disabled, Read Line commands are

issued on every read data transfer, except opcode fetches, as in previous
LSI53C8XX chips.

If cache mode is enabled, a Read Line command is issued on all read
cycles, except opcode fetches, when the following conditions are met:

• The CLSE and Enable Read Line bits are set.

• The Cache Line Size register contains a legal burst size value in

Dwords (2, 4, 8, 16, 32, 64, or 128) that value is less than or equal
to the DMODE burst size.

2-8 Functional Description

• The number of bytes to be transferred at the time a cache boundary

is reached is equal to or greater than the DMODE burst size.

• The chip is aligned to a cache line boundary.

When these conditions are met, the chip issues a Read Line command
instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.

2.1.3.7 Memory Read Multiple Command

This command is identical to the Memory Read command except that it
additionally indicates that the master may intend to fetch more than one
cache line before disconnecting. The LSI53C825A supports PCI Read
Multiple functionality and issues Read Multiple commands on the PCI
bus when the Read Multiple Mode is enabled. This mode is enabled by
setting bit 2 of the DMA Mode (DMODE) register (ERMP). If cache mode
is enabled, a Read Multiple command is issued on all read cycles, except
opcode fetches, when the following conditions are met:

• The CLSE and ERMP bits are set.

• The Cache Line Size register contains a legal burst size value in

Dwords (2, 4, 8, 16, 32, 64, or 128) and that value is less than or
equal to the DMODE burst size.

• The number of bytes to be transferred at the time a cache line

boundary has been reached must be at least twice the full cache line
size.

• The chip is aligned to a cache line boundary.

When these conditions are met, the chip issues a Read Multiple
command instead of a Memory Read during all PCI read cycles.

Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data in a single bus ownership. The number of cache lines
to be read is a multiple of the cache line size as allowed for in the
Revision 2.1 of the PCI specification. The logic selects the largest
multiple of the cache line size based on the amount of data to transfer,
with the maximum allowable burst size determined from the DMODE
burst size bits and Chip Test Five (CTEST5), bit 2.

PCI Addressing 2-9

2.1.3.8 Read Multiple with Read Line Enabled

When both the Read Multiple and Read Line modes are enabled, the
Read Line command is not issued if the above conditions are met.
Instead, a Read Multiple command is issued, even though the conditions
for Read Line are met.

If the Read Multiple mode is enabled and the Read Line mode is
disabled, Read Multiple commands are issued if the Read Multiple
conditions are met.

2.1.3.9 Unsupported PCI Commands

The LSI53C825A does not respond to reserved commands, special
cycle, dual address cycle, or interrupt acknowledge commands as a
slave. It never generates these commands as a master.

2.2 SCSI Functional Description

The LSI53C825A is composed of three functional blocks: the SCSI Core,
the DMA Core, and the SCRIPTS Processor. The LSI53C825A is fully
supported by the SDMS, a complete software package that supports the
LSI Logic product line of SCSI processors and controllers. The PCI Bus

Power Management support (LSI53C825AE) is discussed at the end of

this chapter.

2.2.1 SCSI Core

The SCSI core supports the 8-bit or 16-bit data bus. It supports SCSI
synchronous transfer rates up to 20 Mbytes/s, and asynchronous transfer
rates up to 10 Mbytes/s on a 16-bit wide SCSI bus. The SCSI core can
be programmed with SCSI SCRIPTS, making it easy to “fine tune” the
system for specific mass storage devices or SCSI-3 requirements.

The SCSI core offers low level register access or a high level control
interface. Like first generation SCSI devices, the LSI53C825A SCSI core
can be accessed as a register oriented device. The ability to sample
and/or assert any signal on the SCSI bus can be used in error recovery
and diagnostic procedures. In support of loopback diagnostics, the SCSI
core may perform a self-selection and operate as both an initiator and a
target.

2-10 Functional Description

The LSI53C825A SCSI core is controlled by the integrated SCRIPTS
processor through a high level logical interface. Commands controlling
the SCSI core are fetched out of the main host memory or local memory.
These commands instruct the SCSI core to Select, Reselect, Disconnect,
Wait for a Disconnect, Transfer Information, Change Bus Phases and, in
general, implement all aspects of the SCSI protocol. The SCRIPTS
processor is a special high speed processor optimized for SCSI protocol.

2.2.2 DMA Core

The DMA core is a bus master DMA device that attaches directly to the
industry standard PCI Bus. The DMA core is tightly coupled to the SCSI
core through the SCRIPTS processor, which supports uninterrupted
scatter/gather memory operations.

The LSI53C825A supports 32-bit memory and automatically supports
misaligned DMA transfers. A 536-byte FIFO allows the LSI53C825A to
support 2, 4, 8, 16, 32, 64, or 128 longword bursts across the PCI bus
interface.

2.2.3 SCRIPTS Processor

The SCSI SCRIPTS processor allows both DMA and SCSI commands
to be fetched from host memory or internal SCRIPTS RAM. Algorithms
written in SCSI SCRIPTS control the actions of the SCSI and DMA cores
and are executed from 32-bit system RAM. The SCRIPTS processor
executes complex SCSI bus sequences independently of the host CPU.

The SCRIPTS processor can begin a SCSI I/O operation in
approximately 500 ns. This compares with 2–8 ms required for traditional
intelligent host adapters. Algorithms may be designed to tune SCSI bus
performance, to adjust to new bus device types (such as scanners,
communication gateways, etc.), or to incorporate changes in the SCSI-2
or SCSI-3 logical bus definitions without sacrificing I/O performance.
SCSI SCRIPTS are hardware independent, so they can be used
interchangeably on any host or CPU system bus.

2.2.4 Internal SCRIPTS RAM

The LSI53C825A has 4 Kbytes (1024 x 32 bits) of internal, general
purpose RAM. The RAM is designed for SCRIPTS program storage, but
is not limited to this type of information. When the chip fetches SCRIPTS

SCSI Functional Description 2-11

instructions or Table Indirect information from the internal RAM, these
fetches remain internal to the chip and do not use the PCI bus. Other
types of access to the RAM by the LSI53C825A use the PCI bus, as if
they were external accesses. The MAD5 pin enables the 4 K internal
RAM. To disable the internal RAM, connect a 4.7 kΩ resistor between
the MAD5 pin and VSS.

The RAM can be relocated by the PCI system BIOS anywhere in 32-bit
address space. The RAM Base Address register in PCI configuration
space contains the base address of the internal RAM. This register is
similar to the ROM Base Address register in PCI configuration space. To
simplify loading of SCRIPTS instructions, the base address of the RAM
will appear in the Scratch Register B (SCRATCHB) register when bit 3 of
the Chip Test Two (CTEST2) register is set. The RAM is byte accessible
from the PCI bus and is visible to any bus mastering device on the bus.
External accesses to the RAM (i.e., by the CPU) follow the same timing
sequence as a standard slave register access, except that the target wait
states required drop from 5 to 3.

A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C825A, see Chapter 5, “SCSI

SCRIPTS Instruction Set.”

2.2.5 SDMS: The Total SCSI Solution

For users who do not need to develop custom drivers, LSI Logic provides
a total SCSI solution in PC environments with the SDMS. SDMS software
provides BIOS driver support for hard disk, tape, and removable media
peripherals for the major PC-based operating systems.

SDMS software includes a SCSI BIOS to manage all SCSI functions
related to the device. It also provides a series of SCSI device drivers that
support most major operating systems. SDMS software supports a
multithreaded I/O application programming interface (API) for user
developed SCSI applications. SDMS software supports both the ASPI
and CAM SCSI software specifications.

2-12 Functional Description

2.2.6 Prefetching SCRIPTS Instructions

When enabled (by setting the Prefetch Enable bit in the DMA Control

(DCNTL) register), the prefetch logic in the LSI53C825A fetches

8 Dwords of instructions. The prefetch logic automatically determines the
maximum burst size that it can perform, based on the burst length as
determined by the values in the DMA Mode (DMODE) register. If the unit
cannot perform bursts of at least 4 Dwords, it disables itself. While the
LSI53C825A is prefetching SCRIPTS instructions, the PCI Cache Line

Size register value does not have any effect and the Read Line, Read

Multiple, and Write and Invalidate commands are not used.
The LSI53C825A may flush the contents of the prefetch unit under

certain conditions, listed below, to ensure that the chip always operates
from the most current version of the software. When one of these
conditions apply, the contents of the prefetch unit are flushed
automatically.

• On every Memory Move instruction. The Memory Move instruction is

often used to place modified code directly into memory. To make
sure that the chip executes all recent modifications, the prefetch unit
flushes its contents and loads the modified code every time an
instruction is issued. To avoid inadvertently flushing the prefetch unit
contents, use the No Flush option for all Memory Move operations
that do not modify code within the next 8 Dwords. For more
information on this instruction, refer to Section 5.7, “Memory Move

Instructions,” in Chapter 5, “SCSI SCRIPTS Instruction Set.”

• On every Store instruction. The Store instruction may also be used

to place modified code directly into memory. To avoid inadvertently
flushing the prefetch unit contents, use the No Flush option for all
Store operations that do not modify code within the next 8 Dwords.

• On every write to the DSP.

• On all Transfer Control instructions when the transfer conditions are

met. This is necessary because the next instruction to be executed
is not the sequential next instruction in the prefetch unit.

• When the Prefetch Flush bit (DMA Control (DCNTL), bit 6) is set. The

unit flushes whenever this bit is set. The bit is self-clearing.

SCSI Functional Description 2-13

2.2.7 Opcode Fetch Burst Capability

Setting the Burst Opcode Fetch Enable bit in the DMA Mode (DMODE)
register (0x38) causes the LSI53C825A to burst in the first two longwords
of all instruction fetches. If the instruction is a memory-to-memory move,
the third longword is accessed in a separate ownership. If the instruction
is an indirect type, the additional longword is accessed in a subsequent
bus ownership. If the instruction is a table indirect Block Move, the chip
uses two accesses to obtain the four longwords required, in two bursts
of two longwords each.

Note: This feature is only useful if prefetching is disabled.

2.3 External Memory Interface

The LSI53C825A supports up to one megabyte of external memory in
binary increments from 16 Kbytes, to allow the use of expansion ROM
for add-in PCI cards. The device also supports Flash ROM updates
through the add-in interface and the GPIO4 pin (used to control VPP, the
power supply for programming external memory). This interface is
designed for low speed operations such as downloading instruction code
from ROM; it is not intended for dynamic activities such as executing
instructions.

System requirements include the LSI53C825A, two or three external
8-bit address holding registers (HCT273 or HCT374), and the
appropriate memory device. The 4.7 kΩ pull-down resistors on the MAD
bus require HC or HCT external components to be used. If in-system
Flash ROM updates are required, a 7406 (high voltage open collector
inverter), an MTD4P05, and several passive components are also
needed. The memory size and speed is determined by pull-down
resistors on the 8-bit bidirectional memory bus at power-up. The
LSI53C825A senses this bus shortly after the release of the Reset signal
and configures the ROM Base Address register and the memory cycle
state machines for the appropriate conditions.

The external memory interface works with a variety of ROM sizes and
speeds. An example set of interface drawings is in Appendix B, “External

Memory Interface Diagram Examples.”

2-14 Functional Description

The LSI53C825A supports a variety of sizes and speeds of expansion
ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of
pins MAD[3:1] allows the user to define how much external memory is
available to the LSI53C825A. Table 2.2 shows the memory space
associated with the possible values of MAD[3:1]. The MAD[3:1] pins are
fully defined in Chapter 4, “Registers.”

External Memory Interface 2-15

Table 2.2 External Memory Support

MAD[3:1] Available Memory Space

000 16 Kbytes
001 32 Kbytes
010 64 Kbytes
011 128 Kbytes
100 256 Kbytes
101 512 Kbytes
110 1024 Kbytes
111 No external memory present

To use one of the configurations mentioned above in a host adapter
board design, put 4.7 kΩ pull-down resistors on the MAD pins
corresponding to the available memory space. For example, to connect
to a 32 Kbyte external ROM, use pull-downs on MAD3 and MAD2. If the
external memory interface is not used, then no external resistors are
necessary since there are internal pull-ups on the MAD bus. The internal
pull-up resistors are disabled when external pull-down resistors are
detected, to reduce current drain.

The LSI53C825A allows the system to determine the size of the available
external memory using the Expansion ROM Base Address register in
PCI configuration space. For more information on how this works, refer
to the PCI specification or the Expansion ROM Base Address register
description in Chapter 3, “Signal Descriptions.”

MAD0 is the slow ROM pin. When pulled down, it enables two extra clock
cycles of data access time to allow use of slower memory devices. The
external memory interface also supports updates to flash memory. The
12 V power supply for flash memory, VPP, is enabled and disabled with
the GPIO4 pin and the GPIO4 control bit. For more information on the
GPIO4 pin, refer to Chapter 4, “Registers.”

2-16 Functional Description

2.4 PCI Cache Mode

The LSI53C825A supports the PCI specification for an 8-bit Cache Line

Size register located in PCI configuration space. The Cache Line Size

register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. In conjunction with the Cache

Line Size register, the PCI commands Read Line, Read Multiple, and

Write and Invalidate are each software enabled or disabled to allow the
user full flexibility in using these commands. For more information on PCI
cache mode operations, refer to Chapter 3, “Signal Descriptions.”

2.4.1 Load and Store Instructions

The LSI53C825A supports the Load and Store instruction type, which
simplifies the movement of data between memory and the internal chip
registers. It also enables the LSI53C825A to transfer bytes to addresses
relative to the Data Structure Address (DSA) register. For more
information on the Load and Store instructions, refer to Chapter 5, “SCSI

SCRIPTS Instruction Set.”

2.4.2 3.3 V/5 V PCI Interface

The LSI53C825A can attach directly to a 3.3 V or a 5 V PCI interface,
due to separate VDDpins for the PCI bus drivers. This allows the devices
to be used on the universal board recommended by the PCI Special
Interest Group.

2.4.3 Additional Access to General Purpose Pins

The LSI53C825A can access the GPIO0 and GPIO1 general purpose
pins through register bits in the PCI configuration space, instead of using
the General Purpose Pin Control (GPCNTL) register in the operating
register space to control these pins. In the LSI Logic SDMS software, the
configuration bits control pins as the clock and data lines, respectively.

To access the GPIO[1:0] pins through the configuration space, connect
a 4.7 kΩ resistor between the MAD7 pin and VSS. MAD7 contains an
internal pull-up that is sensed shortly after chip reset. If the pin is sensed
high, GPIO[1:0] access is disabled; if it is low, GPIO[1:0] access is
enabled. Additionally, if GPIO[1:0] access has been enabled through the

PCI Cache Mode 2-17

MAD7 pin and if GPIO0 and/or GPIO1 are sensed low after chip reset,
GPIO[1:0] access is disabled. If GPIO[1:0] access through configuration
space is enabled, the GPIO0 and GPIO1 pins cannot be controlled from
the General Purpose Pin Control (GPCNTL) and General Purpose

(GPREG) registers, but are observable from the General Purpose
(GPREG) register. When GPIO[1:0] access is enabled, the Serial

Interface Control register at configuration addresses 0x34–0x35 controls
the GPIO0 and GPIO1 pins. For more information on GPIO[1:0] access,
refer to the Serial Interface Control register description in Chapter 3,

“Signal Descriptions.” For more information on the GPIO pins, see
Chapter 4, “Registers.” This does not apply to the LSI53C825AE.

Note: The LSI Logic SDMS software controls the GPIO0 and

GPIO1 pins using the General Purpose Pin Control

(GPCNTL) and General Purpose (GPREG) registers.

Therefore, if using SDMS, do not connect a 4.7 kΩ resistor
between MAD7 and VSS.

2.4.4 JTAG Boundary Scan Testing

The LSI53C825AJ includes support for JTAG boundary scan testing in
accordance with the IEEE 1149.1 specification, with one exception that
is discussed in this section. The device can accept all required boundary
scan instructions, as well as the optional CLAMP, HIGH-Z, and IDCODE
instructions.

The LSI53C825AJ uses an 8-bit instruction register to support all
boundary scan instructions. The data registers included in the device are
the Boundary Data register, the IDCODE register, and the Bypass
register. The device can handle a 10 MHz TCK frequency for TDO and
TDI.

Due to design constrains, the RST/ pin (System Reset) always
3-states the SCSI pins when it is asserted. This action cannot be
controlled by the boundary scan logic, and thus is not compliant with the
specification. There are two solutions that resolve this issue:

• Use the RST/ pin as a boundary scan compliance pin. When the pin

is deasserted, the device is boundary scan compliant and when
asserted, the device is noncompliant. To maintain compliance, the
RST/ pin must be driven high.

2-18 Functional Description

• When RST/ is asserted during boundary scan testing, the expected

output on the SCSI pins must be HIGH-Z condition, and not what is
contained in the boundary scan data registers for the SCSI pin
output cells.

Because of package limitations, the LSI53C825AJ replaces the TESTIN,
MAC/_TESTOUT, BIG_LIT, and SDIRP1 signals with the JTAG boundary
scan signals.

2.4.5 Big and Little Endian Support

The LSI53C825A supports both big and little endian byte ordering
through pin selection. The LSI53C825AJ operates in little endian mode
only (the BIG_LIT pin is replaced by one of the JTAG boundary scan
signals). In big endian mode, the first byte of an aligned SCSI to PCI
transfer is routed to lane three and succeeding transfers are routed to
descending lanes. This mode of operation also applies to data transfers
over the add-in ROM interface. The byte of data accessed at location
0x0000 from memory is routed to lane three, and the data at location
0x0003 is routed to byte lane 0. In little endian mode, the first byte of an
aligned SCSI to PCI transfer is routed to lane zero and succeeding
transfers are routed to ascending lanes. This mode of operation also
applies to the add-in ROM interface. The byte of data accessed at
location 0x0000 from memory is routed to lane zero, and the data at
location 0x0003 is routed to byte lane 3.

The Big_Lit pin gives the LSI53C825A the flexibility of operating with
either big or little endian byte orientation. Internally, in either mode, the
actual byte lanes of the DMA FIFO and registers are not modified. The
LSI53C825A supports slave accesses in big or little endian mode.

When a Dword is accessed, no repositioning of the individual bytes is
necessary since Dwords are addressed by the address of the least
significant byte. SCRIPTS always uses Dwords in 32-bit systems, so
compatibility is maintained between systems using different byte
orientations. When less than a Dword is accessed, individual bytes must
be repositioned. Internally, the LSI53C825A adjusts the byte control logic
of the DMA FIFO and register decodes to access the appropriate byte
lanes. The registers always appear on the same byte lane, but the
address of the register are repositioned.

PCI Cache Mode 2-19

Big/little endian mode selection has the most effect on individual byte
access. Internally, the LSI53C825A adjusts the byte control logic of the
DMA FIFO and register decodes to enable the appropriate byte lane. The
registers always appear on the same byte lane, but the address of the
register are repositioned.

Data to be transferred between system memory and the SCSI bus
always starts at address zero and continues through address ‘n’ – there
is no byte ordering in the chip. The first byte in from the SCSI bus goes
to address 0, the second to address 1, etc. Going out onto the SCSI bus,
address zero is the first byte out on the SCSI bus, address 1 is the
second byte, etc. The only difference is that in a little endian system,
address 0 is on byte lane 0, and in big endian mode address zero is on
byte lane 3.

Correct SCRIPTS are generated if the SCRIPTS compiler is run on a
system that has the same byte ordering as the target system. Any
SCRIPTS patching in memory must patch the instruction with the byte
ordering that the SCRIPTS processor expects.

Software drivers for the LSI53C825A should access registers by their
logical name (i.e., SCNTL0) rather than by their address. The logical
name should be equated to the register’s big endian address in big
endian mode (SCNTL0 = 0x03), and its little endian address in little
endian mode (SCNTL0 = 0x00). This way, there is no change to the
software when moving from one mode to the other; only the equate
statement setting the operating modes needs to be changed.

Addressing of registers from within a SCRIPTS instruction is independent
of bus mode. Internally, the LSI53C825A always operates in little endian
mode.

2.4.6 Loopback Mode

The LSI53C825A loopback mode allows testing of both initiator and
target functions and, in effect, lets the chip communicate with itself.
When the Loopback Enable bit is set in the Chip Test One (CTEST1)
register, the LSI53C825A allows control of all SCSI signals, whether the
LSI53C825A is operating in initiator or target mode. For more information
on this mode of operation, refer to the

Programming Guide

2-20 Functional Description

SCSI SCRIPTS Processors

.

2.4.7 Parity Options

The LSI53C825A implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures. Table 2.3 defines the bits that
are involved in parity control and observation. Table 2.4 describes the
parity control function of the Enable Parity Checking and Assert SCSI
Even Parity bits in the SCSI Control Zero (SCNTL0) register. Table 2.5
describes the options available when a parity error occurs.

Table 2.3 Bits Used for Parity Control and Generation

BIt Name Location Description

Assert SATN/ on Parity
Errors

Enable Parity Checking SCSI Control

Assert Even SCSI Parity SCSI Control

Disable Halt on SATN/or
a Parity Error (Target
Mode Only)

Enable Parity Error
Interrupt

Parity Error SCSI Interrupt

SCSI Control
Zero (SCNTL0),

Bit 1

Zero (SCNTL0),

Bit 3

One (SCNTL1),

Bit 2

SCSI Control
One (SCNTL1),

Bit 5

SCSI Interrupt
Enable Zero
(SIEN0), Bit 0

Status Zero
(SIST0), Bit 0

Causes theLSI53C825Ato automatically assert SATN/
when it detects a parity error while operating as an
initiator.

Enables the LSI53C825A to check for parity errors.
The LSI53C825A checks for odd parity.

DeterminestheSCSIparity sensegeneratedbythe
LSI53C825A to the SCSI bus.

Causes the LSI53C825A not to halt operations when a
parity error is detected in target mode.

Determines whether the LSI53C825A will generate an
interrupt when it detects a SCSI parity error.

This status bit is set whenever the LSI53C825A has
detected a parity error on the SCSI bus.

PCI Cache Mode 2-21

Table 2.3 Bits Used for Parity Control and Generation (Cont.)

BIt Name Location Description

Status of SCSI Parity
Signal

SCSI SDP1 Signal SCSI Status Two

Latched SCSI Parity SCSI Status Two

Master Parity Error
Enable

Master Data Parity Error DMA Status

Master Data Parity Error
Interrupt Enable

SCSIStatus Zero
(SSTAT0), Bit 0

(SSTAT2), Bit 0

(SSTAT2), Bit 3

and SCSI Status

One (SSTAT1),

Bit 3

Chip Test Four
(CTEST4), Bit 3

(DSTAT), Bit 6

DMA Interrupt
Enable (DIEN),

Bit 6

This status bit represents the active HIGH current state
of the SCSI SDP0 parity signal.

This bit represents the active HIGH current state of the
SCSI SDP1 parity signal.

These bits reflect the SCSI odd parity signal
corresponding to the data latched into the SCSI Input

Data Latch (SIDL) register.

Enables parity checking during master data phases.

Set when the LSI53C825A as a master detects that a
target device has signaled a parity error during a data
phase.

By clearing this bit, a Master Data Parity Error will not
cause IRQ/ to be asserted, but the status bit will be set
in the DMA Status (DSTAT) register.

Table 2.4 SCSI Parity Control

EPC AESP Description

0 0 Does not check for parity errors. Parity is generated when sending

SCSI data. Asserts odd parity when sending SCSI data.

0 1 Does not check for parity errors. Parity is generated when sending

1 0 Checks for odd parity on SCSI data received. Parity is generated

1 1 Checks for odd parity on SCSI data received. Parity is generated

1. Key:

EPC = Enable Parity Checking (bit 3, SCSI Control Zero (SCNTL0)).
ASEP = Assert SCSI Even Parity (bit 2, SCSI Control One (SCNTL1)).

2. This table only applies when the Enable Parity Checking bit is set.

SCSI data. Asserts even parity when sending SCSI data.

when sending SCSI data. Asserts odd parity when sending SCSI
data.

when sending SCSI data. Asserts even parity when sending SCSI
data.

2-22 Functional Description

Table 2.5 SCSI Parity Errors and Interrupts

DPH PAR Description

0 0 Halts when a parity error occurs in target or initiator mode and will

0 1 Halts when a parity error occurs in target mode and will generate

1 0 Does not halt in target mode when a parity error occurs until the

1 1 Does not halt in target mode when a parity error occurs until the

Key:
DHP = Disable Halt on SATN/ or Parity Error (bit 5, SCSI Control One (SCNTL1).
PAR = Parity Error (bit 0, SCSI Interrupt Enable Zero (SIEN0).

not generate an interrupt.

an interrupt in target or initiator mode.

end of the transfer. An interrupt will not be generated.

end of the transfer. An interrupt will be generated.

2.4.8 DMA FIFO

The DMA FIFO is 4 bytes wide by 134 transfers deep. The DMA FIFO is
illustrated in Figure 2.1. To assure compatibility with older products in the
LSI53C8XX family, the user may set the DMA FIFO size to 88 bytes by
clearing the DMA FIFO Size bit, bit 5 in the Chip Test Five (CTEST5)
register.

Figure 2.1 DMA FIFO Sections

32 Bytes Wide

134

Transfers

Deep

.

.

.

8 Bits

Byte Lane 3

.

.

.

8 Bits

Byte Lane 2

PCI Cache Mode 2-23

8 Bits

Byte Lane 1

8 Bits

Byte Lane 0

2.4.8.1 Data Paths

The data path through the LSI53C825A is dependent on whether data is
being moved into or out of the chip, and whether SCSI data is being
transferred asynchronously or synchronously.

The following steps determine if any bytes remain in the data path when
the chip halts an operation:

Asynchronous SCSI Send –

Step 1. If the DMA FIFO size is set to 88 bytes, look at the DMA FIFO

(DFIFO) and DMA Byte Counter (DBC) registers and calculate

if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DMA Byte

Counter (DBC) register from the 7-bit value of the DMA FIFO
(DFIFO) register. AND the result with 0x7F for a byte count

between zero and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the Chip

Test Five (CTEST5) register), subtract the 10 least significant

bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO register. AND the result with 0x3FF for a byte
count between zero and 536.

Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the
SCSI Output Data Latch (SODL) register. If bit 5 is set in the

SSTAT0 or SSTAT2, then the least significant byte or the most
significant byte in the SCSI Output Data Latch (SODL) register
is full, respectively. Checking this bit also reveals bytes left in
the SCSI Output Data Latch (SODL) register from a Chained
Move operation with an odd byte count.

Synchronous SCSI Send –

Step 1. If the DMA FIFO size is set to 88 bytes, look at the DMA FIFO

(DFIFO) and DMA Byte Counter (DBC) registers and calculate

if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DMA Byte

2-24 Functional Description

Counter (DBC) register from the 7-bit value of the DMA FIFO
(DFIFO) register. AND the result with 0x7F for a byte count

between zero and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the Chip

Test Five (CTEST5) register), subtract the 10 least significant

bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO register. AND the result with 0x3FF for a byte
count between zero and 536.

Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the
SCSI Output Data Latch (SODL) register. If bit 5 is set in the

SSTAT0 or SSTAT2, then the least significant byte or the most
significant byte in the SCSI Output Data Latch (SODL) register
is full, respectively. Checking this bit also reveals bytes left in
the SCSI Output Data Latch (SODL) register from a Chained
Move operation with an odd byte count.

Step 3. Read bit 6 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) registers to determine if any bytes are left in the

SODR register. If bit 6 is set in the SCSI Status Zero (SSTAT0)
or SCSI Status Two (SSTAT2), then the least significant byte or
the most significant byte in the SODR register is full,
respectively.

Asynchronous SCSI Receive –

Step 1. If the DMA FIFO size is set to 88 bytes, look at the DMA FIFO

(DFIFO) and DMA Byte Counter (DBC) registers and calculate

if there are bytes left in the DMA FIFO. To make this calculation,
subtract the seven least significant bits of the DMA Byte

Counter (DBC) register from the 7-bit value of the DMA FIFO
(DFIFO) register. AND the result with 0x7F for a byte count

between zero and 88.
If the DMA FIFO size is set to 536 bytes (using bit 5 of the Chip

Test Five (CTEST5) register), subtract the 10 least significant

bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of

PCI Cache Mode 2-25

bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO register. AND the result with 0x3FF for a byte
count between zero and 536.

Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) and SCSI Status

Two (SSTAT2) register to determine if any bytes are left in the
SCSI Input Data Latch (SIDL) register. If bit 7 is set in the SCSI
Status Zero (SSTAT0) or SCSI Status Two (SSTAT2), then the

least significant byte or the most significant byte is full,
respectively.

Step 3. If any wide transfers have been performed using the Chained

Move instruction, read the Wide SCSI Receive bit (SCSI

Control Two (SCNTL2), bit 0) to determine whether a byte is left

in the SCSI Wide Residue (SWIDE) register.

Synchronous SCSI Receive –

Step 1. If the DMA FIFO size is set to 88 bytes, subtract the seven least

significant bits of the DMA Byte Counter (DBC) register from
the 7-bit value of the DMA FIFO (DFIFO) register. AND the
result with 0x7F for a byte count between zero and 88.

If the DMA FIFO size is set to 536 bytes (using bit 5 of the Chip

Test Five (CTEST5) register), subtract the 10 least significant

bits of the DMA Byte Counter (DBC) register from the 10-bit
value of the DMA FIFO Byte Offset Counter, which consists of
bits [1:0] in the Chip Test Five (CTEST5) register and bits [7:0]
of the DMA FIFO (DFIFO) register. AND the result with 0x3FF
for a byte count between zero and 536.

Step 2. Read bits [7:4] of the SCSI Status One (SSTAT1) register and

bit 4 of the SCSI Status Two (SSTAT2) register, the binary
representation of the number of valid bytes in the SCSI FIFO,
to determine if any bytes are left in the SCSI FIFO.

Step 3. If any wide transfers have been performed using the Chained

Move instruction, read the Wide SCSI Receive bit (SCSI

Control Two (SCNTL2), bit 0) to determine whether a byte is left

in the SCSI Wide Residue (SWIDE) register.

Figure 2.2 shows how data is moved to/from the SCSI bus in

each of the different modes.

2-26 Functional Description

Figure 2.2 LSI53C825A Host Interface Data Paths

Asynchronous

SCSI Send

PCI Interface

DMA FIFO

(32 Bits x 16)

SODL Register

SCSI Interface

Asynchronous

SCSI Receive

PCI Interface

DMA FIFO

(32 Bits x 16)

SIDL Register

SCSI Interface

SWIDE Register

Synchronous

SCSI Send

PCI Interface

DMA FIFO

(32 Bits x 16)

SODL Register

SODR Register SCSI Interface

SCSI Interface

Synchronous

SCSI Receive

PCI Interface

DMA FIFO

(32 Bits x 16)

SCSI FIFO

(8 or 16 Bits x 16)

SWIDE Register

2.4.9 SCSI Bus Interface

The LSI53C825A supports both SE and differential operation.
All SCSI signals are active LOW. The LSI53C825A contains the SE

output drivers and can be connected directly to the SCSI bus. Each
output is isolated from the power supply to ensure that a powered-down
LSI53C825A has no effect on an active SCSI bus (CMOS “voltage
feed-through” phenomena). TolerANT technology provides signal filtering
at the inputs of SREQ/ and SACK/ to increase immunity to signal
reflections.

PCI Cache Mode 2-27

2.4.9.1 Differential Mode

In differential mode, the SDIR[15:0], SDIRP[1:0], IGS, TGS, RSTDIR,
BSYDIR, and SELDIR signals control the direction of external differential
pair transceivers. The LSI53C825A is placed in differential mode by
setting the DIF bit, bit 5 of the SCSI Test Two (STEST2) register (0x4E).
Setting this bit 3-states the BSY/, SEL/, and RST/ pads so they can be
used as pure input pins. In addition to the standard SCSI lines, the
following signals defined in Table 2.6 are used during differential
operation by the LSI53C825A.

Table 2.6 Differential Mode

Signal Function

BSYDIR, SELDIR,
RSTDIR

SDIR[15:0],
SDIRP[1:0]

IGS Active HIGH signal used to control direction of the differential driver for initiator

TGS Active HIGH signal used to control direction of the differential drivers for target

DIFFSENS Input to the LSI53C825A used to detect the presence of a SE device on a

Active HIGH signals used to enable the differential drivers as outputs for SCSI
signals BSY/, SEL/, and RST/, respectively.

Active HIGH signals used to control direction of the differential drivers for SCSI
data and parity lines, respectively.

group signals ATN/ and ACK/.

group signals MSG/, C/D/, I/O/, and REQ/.

differential system. If a logical zero is detected on this pin, then it is assumed
that an SE device is on the bus and all SCSI outputs will be 3-stated to avoid
damage to the transceiver.

See Figure 2.3 for an example differential wiring diagram, in which the
LSI53C825A is connected to the TI 75LBC976 differential transceiver.
The recommended value of the pull-up resistor on the REQ/, ACK/,
MSG/, C/D/, I/O/, ATN/, SD[7:0]/, and SDP0/ lines is 680 Ω when the
Active Negation portion of LSI Logic TolerANTtechnology is not enabled.
When TolerANT technology is enabled, the recommended resistor value
on the REQ/, ACK/, SD[7:0]/, and SDP0/ signals is 1.5 kΩ. The electrical
characteristics of these pins change when TolerANT is enabled,
permitting a higher resistor value.

2-28 Functional Description

To interface the LSI53C825A to the 75LBC976, connect the DIR pins, as
well as IGS and TGS, of the LSI53C825A directly to the transceiver
enables (nDE/RE/). These signals control the direction of the channels
on the 75LBC976.

The SCSI bidirectional control and data pins (SD[7:0]/, SDP0/, REQ/,
ACK/, MSG/, I_O/, C_D/, and ATN/) of the LSI53C825A connect to the
bidirectional data pins (nA) of the 75LBC976 with a pull-up resistor. The
pull-up value should be no lower than the transceiver IOLcan tolerate,
but not so high as to cause RC timing problems. The three remaining
pins, SEL/, BSY/, and RST/ are connected to the 75LBC976 with a
pull-down resistor. The pull-down resistors are required when the pins
(nA) of the 75LBC976 are configured as inputs. When the data pins are
inputs, the resistors provide a bias voltage to both the LSI53C825A pins
(SEL/, BSY/, and RST/) and the 75LBC976 data pins. Because the SEL/,
BSY/, and RST/ pins on the LSI53C825A are inputs only, this
configuration allows for the SEL/, BSY/, and RST/ SCSI signals to be
asserted on the SCSI bus. The differential pairs on the SCSI bus are
reversed when connected to the 75LBC976, due to the active low nature
of the SCSI bus.

8-Bit/16-Bit SCSI and the Differential Interface – In an 8-bit SCSI
bus, the SD[15:8] pins on the LSI53C825A should be pulled up with a

1.5 kΩ resistor or terminated like the rest of the SCSI bus lines. This is
very important, as errors may occur during reselection if these lines are
left floating. In the LSI53C825AJ, the SDIRP1 pin is replaced by the TCK
JTAG signal. If the device is used in a wide differential system, use the
SDIRP0 pin to control the direction of the differential transceiver for both
the SP0 and SP1 signals. The SDIRP0 signal is capable of driving both
direction inputs from a transceiver.

2.4.9.2 Terminator Networks

The terminator networks provide the biasing needed to pull signals to an
inactive voltage level, and to match the impedance seen at the end of
the cable with the characteristic impedance of the cable. Terminators
must be installed at the extreme ends of the SCSI chain, and only at the
ends; no system should ever have more or less than two terminators
installed and active. SCSI host adapters should provide a means of

PCI Cache Mode 2-29

accommodating terminators. The terminators should be socketed, so that
if not needed they may be removed, or there should be a means of
disabling them with software.

SE cables can use a 220 Ω pull-up to the terminator power supply (Term
Power) line and a 330 Ω pull-down to ground. Because of the
high-performance nature of the LSI53C825A, Regulated (or Active)
termination is recommended.

Note: If the LSI53C825A is to be used in a design with only an

8-bit SCSI bus, all 16 data lines still must be terminated or

pulled HIGH.

Figure 2.3 is an example differential wiring diagram.
Figure 2.4 shows a Unitrode active terminator. For additional information,

refer to the SCSI-2 Specification. TolerANT active negation can be used
with either termination network.

2-30 Functional Description

Figure 2.3 LSI53C825A Differential Wiring Diagram

LSI53C8XX

SELDIR
BSYDIR
RSTDIR

REQ/

MSG/

SD[8:15]/

SDP1/

SDIRP0

SDIR7
SDIR6
SDIR5
SDIR4
SDIR3
SDIR2
SDIR1
SDIR0

SDP0/

DIFFSENS

SEL/
BSY/
RST/

ACK/

C/D/

I/O/

ATN/

TGS

IGS

SD7/
SD6/
SD5/
SD4/
SD3/
SD2/
SD1/
SD0/

VDD

1.5 KΩ

VDD

DIFFSENS

1.5 K

VDD

VDD

1.5 KΩ

1.5 KΩ

1.5 KΩ

VDD

1.5 K

1.5 KΩ

SEL­BSY­RST-

SD0
SD1
SD2/
SD3/
SD4
SD5
SD6/
SD7/
SDP0/

DIFFSENS

/
/

/
/

VDD

1.5 KΩ

SELDIR
BSYDIR
RSTDIR

REQ/

ACK/
MSG/

C_D/
I_O/

ATN/

SDIR0
SDIR1
SDIR2
SDIR3
SDIR4
SDIR5
SDIR6
SDIR7
SDIRP0

DIFFSENS

Schottky

Diode

SN75976A

CDE0
CDE1
CDE2
BSR
CRE

1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE

SN75976A

CDE0
CDE1
CDE2
BSR
CRE

1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5A
5DE/RE
6A
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE

DIFFSENS (pin 21)

−SEL
+SEL

−BSY

+BSY

−RST
+RST

−REQ

+REQ

−ACK
+ACK

−MSG

+MSG

−C/D
+C/D

−I/O
+I/O

−ATN
+ATN

−DB0
+DB0

−DB1
+DB1

−DB2
+DB2

−DB3
+DB3

−DB4
+DB4

−DB5
+DB5

−DB6
+DB6

−DB7
+DB7

−DBP

+DBP

(42)
(41)

(34)
(33)
(38)
(37)
(46)
(45)
(36)
(35)
(40)
(39)
(44)
(43)
(48)
(47)
(30)
(29)

(4)
(3)

(6)
(5)
(8)
(7)

(10)

(9)
(12)
(11)
(14)
(13)
(16)
(15)
(18)
(17)
(20)
(19)

1B+
1B−
2B+
2B−
3B+
3B−
4B+
4B−
5B+
5B−
6B+
6B−
7B+
7B−
8B+
8B−
9B+
9B−

1B+
1B−
2B+
2B−
3B+
3B−
4B+
4B−
5B+
5B−
6B+
6B−
7B+
7B−
8B+
8B−
9B+
9B−

SCSI
Bus

PCI Cache Mode 2-31

Figure 2.4 Regulated Termination

2.85 V
C1 C2

C3

2

REG_OUT

19

DISCONNECT

14

REG_OUT

6

DISCONNECT

UC5601QP

UC5603DP

TERML1
TERML2
TERML3
TERML4
TERML5
TERML6
TERML7
TERML8
TERML9

TERML10
TERML11
TERML12
TERML13
TERML14
TERML15
TERML16
TERML17
TERML18

TERML1
TERML2
TERML3
TERML4
TERML5
TERML6
TERML7
TERML8
TERML9

20
21
22
23
24
25
26
27
28

3
4
5
6
7
8
9
10
11

10
9
8
7
3
2
1
16
15

SD0 (J1.40)
SD1 (J1.41)
SD2 (J1.42)
SD3 (J1.43)
SD4 (J1.44)
SD5 (J1.45)
SD6 (J1.46)
SD7 (J1.47)
SDP (J1.48)

ATN (J1.55)
BSY (J1.57)
ACK (J1.58)
RST (J1.59)
MSG (J1.60)
SEL (J1.61)
C/D (J1.62)
REQ (J1.63)
I/O (J1.64)

SD15 (J1.38)
SD14 (J1.37)
SD13 (J1.36)
SD12 (J1.35)
SD11 (J1.68)
SD10 (J1.67)
SD9 (J1.66)
SD8 (J1.65)
SDP1 (J1.39)

Note:

1. C1 - 10 µF SMT

2. C2 - 0.1 µF SMT

3. C3 - 2.2 µF SMT

4. J1 - 68-pin, high density “P” connector

2-32 Functional Description

2.4.10 Select/Reselect During Selection/Reselection

In multithreaded SCSI I/O environments, it is not uncommon to be
selected or reselected while trying to perform selection/reselection. This
situation may occur when a SCSI controller (operating in initiator mode)
tries to select a target and is reselected by another. The Select SCRIPTS
instruction has an alternate address to which the SCRIPTS jumps when
this situation occurs. The analogous situation for target devices is being
selected while trying to perform a reselection.

Once a change in operating mode occurs, the initiator SCRIPTS should
start with a Set Initiator instruction or the target SCRIPTS should start
with a Set Target instruction. The Selection and Reselection Enable bits
(SCID bits 5 and 6, respectively) should both be asserted so that the
LSI53C825A may respond as an initiator or as a target. If only selection
is enabled, the LSI53C825A cannot be reselected as an initiator. There
are also status and interrupt bits in the SCSI Interrupt Status Zero

(SIST0) and SCSI Interrupt Enable Zero (SIEN0) registers, respectively,

indicating that the LSI53C825A has been selected (bit 5) and reselected
(bit 4).

2.4.11 Synchronous Operation

The LSI53C825A can transfer synchronous SCSI data in both initiator
and target modes. The SCSI Transfer (SXFER) register controls both the
synchronous offset and the transfer period. It may be loaded by the CPU
before SCRIPTS execution begins, from within SCRIPTS using a Table
Indirect I/O instruction, or with a Read-Modify-Write instruction.

The LSI53C825A can receive data from the SCSI bus at a synchronous
transfer period as short as 80 or 160 ns (with a 50 MHz clock),
regardless of the transfer period used to send data. The LSI53C825A
can receive data at one-fourth of the divided SCLK frequency. Depending
on the SCLK frequency, the negotiated transfer period, and the
synchronous clock divider, the LSI53C825A can send synchronous data
at intervals as short as 100 ns for fast SCSI and 200 ns for SCSI-1.

2.4.11.1 Determining the Data Transfer Rate

Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C825A. A brief description of the bits is provided
below.

PCI Cache Mode 2-33

2.4.11.2 SCSI Control Three (SCNTL3) Register, Bits [6:4]

The SCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the synchronous SCSI control logic.
The output from this divider controls the rate at which data can be
received; this rate must not exceed 50 MHz. The receive rate of
synchronous SCSI data is one-fourth of the SCF divider output. For
example, if SCLK is 40 MHz and the SCF value is set to divide by one,
then the maximum rate at which data can be received is 10 MHz
(40/(1*4) = 10).

2.4.11.3 SCSI Control Three (SCNTL3) Register, Bits [2:0]

The CCF[2:0] bits select the factor by which the frequency of SCLK is
divided before being presented to the asynchronous SCSI core logic.
This divider must be set according to the input clock frequency in the
table.

2.4.11.4 SCSI Transfer (SXFER) Register, Bits [7:5]

The TP[2:0] divider bits determine the SCSI synchronous transfer period
when sending synchronous SCSI data in either initiator or target mode.
This value further divides the output from the SCF divider.

2.4.12 Achieving Optimal SCSI Send Rates

To achieve optimal synchronous SCSI send timings, the SCF divisor
value should be set HIGH, to divide the clock as much as possible before
presenting the clock to the TP divider bits in the SCSI Transfer (SXFER)
register. The TP[2:0] divider value should be as low as possible. For
example, with a 40 MHz clock to achieve a 5 Mbytes/s send rate, the
SCF bits can be set to divide by 1 and the TP bits to divide by 8; or the
SCF bits can be set to divide by 2 and the TP bits set to divide by 2. Use
the second option to achieve optimal SCSI timings.

Figure 2.5 illustrates the clock division factors used in each register, and

the role of the register bits in determining the transfer rate.

2-34 Functional Description

Figure 2.5 Determining the Synchronous Transfer Rate

SCF2 SCF1 SCF0 SCF

0011
0 1 0 1.5
0112
1003
0003

SCLK

CCF2 CCF1 CCF0 Divisor

0011
0 1 0 1.5
0112
1003
0003

Divisor

SCF

Divider

CCF

Divider

TP2 TP1 TP0 XFERP

0004
0015
0106
0117
1008
1019
11010
11111

This point

must not

exceed
50 MHz

This point

must not

exceed

25 MHz

Example:
SCLK = 40 MHz, SCF = 1, XFERP = 4,
SCSI transfer rate = 10 MHz, CCF = 2

(40 MHz ÷ 1 = synchronous core rate)
(40 MHz ÷ 4 = 10 MHz synchronous rate =
10 Mbytes/s on an 8-bit SCSI bus)

Divide by 4

Synchronous

Divider

Asynchronous

SCSI Logic

Send Clock

(to SCSI Bus)

Divisor

Receive

Clock

2.4.13 Interrupt Handling

The SCRIPTS processor in the LSI53C825A performs most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C825A.

2.4.13.1 Polling and Hardware Interrupts

The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit set that
indicates an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of

PCI Cache Mode 2-35

2.4.13.2 Registers

detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C825A asserts the Interrupt Request (IRQ/) line that interrupts
the microprocessor, causing the microprocessor to execute an interrupt
service routine. A hybrid approach would use hardware interrupts for
long waits, and use polling for short waits.

The registers in the LSI53C825A that are used for detecting or defining
interrupts are the Interrupt Status (ISTAT), SCSI Interrupt Status Zero

(SIST0), SCSI Interrupt Status One (SIST1), DMA Status (DSTAT), SCSI
Interrupt Enable Zero (SIEN0), SCSI Interrupt Enable One (SIEN1), DMA
Control (DCNTL), and DMA Interrupt Enable (DIEN).

ISTAT – The Interrupt Status (ISTAT) is the only register that can be
accessed as a slave during SCRIPTS operation, therefore it is the
register that is polled when polled interrupts are used. It is also the first
register that should be read when the IRQ/ pin has been asserted in
association with a hardware interrupt. The INTF (Interrupt-on-the-Fly) bit
should be the first interrupt serviced. It must be written to one to be
cleared. This interrupt must be cleared before servicing any other
interrupts. If the SIP bit in the ISTAT register is set, then a SCSI-type
interrupt has occurred and the SCSI Interrupt Status Zero (SIST0) and

SCSI Interrupt Status One (SIST1) registers should be read. If the DIP

bit in the Interrupt Status (ISTAT) register is set, then a DMA-type
interrupt has occurred and the DMA Status (DSTAT) register should be
read. SCSI-type and DMA-type interrupts may occur simultaneously, so
in some cases both SIP and DIP may be set.

SIST0 and SIST1 – The SCSI Interrupt Status Zero (SIST0) and SCSI

Interrupt Status One (SIST1) registers contain the SCSI-type interrupt

bits. Reading these registers determines which condition or conditions
caused the SCSI-type interrupt, and clears that SCSI interrupt condition.
If the LSI53C825A is receiving data from the SCSI bus and a fatal
interrupt condition occurs, the chip attempts to send the contents of the
DMA FIFO to memory before generating the interrupt. If the LSI53C825A
is sending data to the SCSI bus and a fatal SCSI interrupt condition
occurs, data could be left in the DMA FIFO. Because of this the DMA
FIFO Empty (DFE) bit in DMA Status (DSTAT) should be checked. If this

2-36 Functional Description

bit is clear, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO)
bits before continuing. The CLF bit is bit 2 in Chip Test Three (CTEST3).
The CSF bit is bit 1 in Chip Test Three (CTEST3).

DSTAT – The DMA Status (DSTAT) register contains the DMA-type
interrupt bits. Reading this register determines which condition or
conditions caused the DMA-type interrupt, and clears that DMA interrupt
condition. Bit 7 in DSTAT, DFE, is purely a status bit. It does not generate
an interrupt under any circumstances and will not be cleared when read.
DMA interrupts flush neither the DMA nor SCSI FIFOs before generating
the interrupt, so the DFE bit in the DMA Status (DSTAT) register should
be checked after any DMA interrupt. If the DFE bit is cleared, then the
FIFOs must be cleared by setting the CLF (Clear DMA FIFO) and CSF
(Clear SCSI FIFO) bits, or flushed by setting the FLF (Flush DMA FIFO)
bit.

SIEN0 and SIEN1 – The SCSI Interrupt Enable Zero (SIEN0) and SCSI

Interrupt Enable One (SIEN1) registers are the interrupt enable registers

for the SCSI interrupts in SCSI Interrupt Status Zero (SIST0) and SCSI

Interrupt Status One (SIST1).

DIEN – The DMA Interrupt Enable (DIEN) register is the interrupt enable
register for DMA interrupts in DMA Status (DSTAT).

DCNTL – When bit 1 in this register is set, the IRQ/ pin is not asserted
when an interrupt condition occurs. The interrupt is not lost or ignored,
but merely masked at the pin. Clearing this bit when an interrupt is
pending immediately causes the IRQ/ pin to assert. As with any register
other than Interrupt Status (ISTAT), this register cannot be accessed
except by a SCRIPTS instruction during SCRIPTS execution.

2.4.13.3 Fatal vs. Nonfatal Interrupts

A fatal interrupt, as the name implies, always causes SCRIPTS to stop
running. All nonfatal interrupts become fatal when they are enabled by
setting the appropriate interrupt enable bit. Interrupt masking will be
discussed in Section 2.4.13.4, “Masking.” All DMA interrupts (indicated
by the DIP bit in Interrupt Status (ISTAT) and one or more bits in DMA

Status (DSTAT) being set) are fatal.

PCI Cache Mode 2-37

Some SCSI interrupts (indicated by the SIP bit in the ISTAT and one or
more bits in SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt Status

One (SIST1) being set) are nonfatal. When the LSI53C825A is operating

in Initiator mode, only the Function Complete (CMP), Selected (SEL),
Reselected (RSL), General Purpose Timer Expired (GEN), and
Handshake-to-Handshake Timer Expired (HTH) interrupts are nonfatal.
When operating in Target mode CMP, SEL, RSL, Target mode: SATN/
active (M/A), GEN, and HTH are nonfatal. Refer to the description for the
Disable Halt on a Parity Error or SATN/ active (Target Mode Only) (DHP)
bit in the SCSI Control One (SCNTL1) register to configure the chip’s
behavior when the SATN/ interrupt is enabled during Target mode
operation. The Interrupt-on-the-Fly interrupt is also nonfatal, since
SCRIPTS can continue when it occurs.

The reason for nonfatal interrupts is to prevent SCRIPTS from stopping
when an interrupt occurs that does not require service from the CPU.
This prevents an interrupt when arbitration is complete (CMP set), when
the LSI53C825A has been selected or reselected (SEL or RSL set),
when the initiator has asserted ATN (target mode: SATN/ active), or when
the General Purpose or Handshake-to-Handshake timers expire. These
interrupts are not needed for events that occur during high-level
SCRIPTS operation.

2.4.13.4 Masking

Masking an interrupt means disabling or ignoring that interrupt. Interrupts
can be masked by clearing bits in the SCSI Interrupt Enable Zero

(SIEN0) and SCSI Interrupt Enable One (SIEN1) (for SCSI interrupts)

registers or DMA Interrupt Enable (DIEN) (for DMA interrupts) register.
How the chip responds to masked interrupts depends on: whether polling
or hardware interrupts are being used; whether the interrupt is fatal or
nonfatal; and whether the chip is operating in Initiator or Target mode.

If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS
do not stop, the appropriate bit in the SIST0 or SIST1 is still set, the SIP
bit in the ISTAT is not set, and the IRQ/ pin is not asserted. See

Section 2.4.13.3, “Fatal vs. Nonfatal Interrupts,” for a list of the nonfatal

interrupts.

2-38 Functional Description

If a fatal interrupt is masked and that condition occurs, then the SCRIPTS
still stop, the appropriate bit in the DMA Status (DSTAT), SCSI Interrupt

Status Zero (SIST0),orSCSI Interrupt Status One (SIST1) register is

set, and the SIP or DIP bit in the Interrupt Status (ISTAT) is set, but the
IRQ/ pin is not asserted.

When the chip is initialized, enable all fatal interrupts if you are using
hardware interrupts. If a fatal interrupt is disabled and that interrupt
condition occurs, the SCRIPTS halts and the system will never know it
unless it times out and checks the ISTAT after a certain period of
inactivity.

If you are polling the ISTAT instead of using hardware interrupts, then
masking a fatal interrupt will make no difference since the SIP and DIP
bits in the ISTAT inform the system of interrupts, not the IRQ/ pin.

Masking an interrupt after IRQ/ is asserted does not cause IRQ/ to be
deasserted.

2.4.13.5 Stacked Interrupts

The LSI53C825A stacks interrupts if they occur one after the other. If the
SIP or DIP bits in the Interrupt Status (ISTAT) register are set (first level),
then there is already at least one pending interrupt, and any future
interrupts are stacked in extra registers behind the SCSI Interrupt Status

Zero (SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) registers (second level). When two interrupts have occurred and

the two levels of the stack are full, any further interrupts set additional
bits in the extra registers behind SCSI Interrupt Status Zero (SIST0),

SCSI Interrupt Status One (SIST1), and DMA Status (DSTAT). When the

first level of interrupts are cleared, all the interrupts that came in
afterward will move into the SCSI Interrupt Status Zero (SIST0), SCSI

Interrupt Status One (SIST1), and DMA Status (DSTAT). After the first

interrupt is cleared by reading the appropriate register, the IRQ/ pin is
deasserted for a minimum of three CLKs. The stacked interrupts move
into the SIST0, SIST1, or DSTAT and the IRQ/ pin is asserted once
again.

Since a masked nonfatal interrupt does not set the SIP or DIP bits,
interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in SIST0, but does not assert the IRQ/ pin. Since no
interrupt is generated, future interrupts move right into the SIST0 or

PCI Cache Mode 2-39

SIST1 instead of being stacked behind another interrupt. When another
condition occurs that generates an interrupt, the bit corresponding to the
earlier masked nonfatal interrupt is still set.

A related situation to interrupt stacking is when two interrupts occur
simultaneously. Since stacking does not occur until the SIP or DIP bits
are set, there is a small timing window in which multiple interrupts can
occur but are not stacked. These could be multiple SCSI interrupts (SIP
set), multiple DMA interrupts (DIP set), or multiple SCSI and multiple
DMA interrupts (both SIP and DIP set).

As previously mentioned, DMA interrupts do not attempt to flush the
FIFOs before generating the interrupt. It is important to set either the
Clear DMA FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA
interrupt occurs and the DMA FIFO Empty (DFE) bit is not set. This is
because any future SCSI interrupts are not posted until the DMA FIFO
is cleared of data. These ‘locked out’ SCSI interrupts are posted as soon
as the DMA FIFO is empty.

2.4.13.6 Halting in an Orderly Fashion

When an interrupt occurs, the LSI53C825A attempts to halt in an orderly
fashion.

• If the interrupt occurs in the middle of an instruction fetch, the fetch

is completed, except in the case of a Bus Fault. Execution does not
begin, but the DSP points to the next instruction since it is updated
when the current instruction is fetched.

• If the DMA direction is a write to memory and a SCSI interrupt

occurs, the LSI53C825A attempts to flush the DMA FIFO (DFIFO) to
memory before halting. Under any other circumstances only the
current cycle is completed before halting, so the DFE bit in DMA

Status (DSTAT) should be checked to see if any data remains in the

DMA FIFO.

• SCSI SREQ/SACK handshakes that have begun are completed

before halting.

• The LSI53C825A attempts to clean up any outstanding synchronous

offset before halting.

• In the case of Transfer Control Instructions, once instruction

execution begins it continues to completion before halting.

2-40 Functional Description

• If the instruction is a JUMP/CALL WHEN/IF <phase>, the DSP is

updated to the transfer address before halting.

• All other instructions may halt before completion.

2.4.13.7 Sample Interrupt Service Routine

The following is a sample of an interrupt service routine for the
LSI53C825A. It can be repeated during polling or should be called when
the IRQ/ pin is asserted during hardware interrupts.

1. Read Interrupt Status (ISTAT).

2. If the INTF bit is set, it must be written to a one to clear this status.

3. If only the SIP bit is set, read SCSI Interrupt Status Zero (SIST0) and

SCSI Interrupt Status One (SIST1) to clear the SCSI interrupt

condition and get the SCSI interrupt status. The bits in the SIST0
and SIST1 tell which SCSI interrupts occurred and determine what
action is required to service the interrupts.

4. If only the DIP bit is set, read the DMA Status (DSTAT) to clear the
interrupt condition and get the DMA interrupt status. The bits in the
DSTAT tells which DMA interrupts occurred and determine what
action is required to service the interrupts.

5. If both the SIP and DIP bits are set, read SCSI Interrupt Status Zero

(SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) to clear the SCSI and DMA interrupt condition and get the

interrupt status. If using 8-bit reads of the SCSI Interrupt Status Zero

(SIST0), SCSI Interrupt Status One (SIST1), and DMA Status
(DSTAT) registers to clear interrupts, insert a 12 CLK delay between

the consecutive reads to ensure that the interrupts clear properly.
Both the SCSI and DMA interrupt conditions should be handled
before leaving the ISR. It is recommended that the DMA interrupt is
serviced before the SCSI interrupt, because a serious DMA interrupt
condition could influence how the SCSI interrupt is acted upon.

6. When using polled interrupts, go back to Step 1 before leaving the
interrupt service routine, in case any stacked interrupts moved in
when the first interrupt was cleared. When using hardware interrupts,
the IRQ/ pin is asserted again if there are any stacked interrupts.
This should cause the system to re-enter the interrupt service
routine.

PCI Cache Mode 2-41

2.4.14 Chained Block Moves

Since the LSI53C825A has the capability to transfer 16-bit wide SCSI
data, a unique situation occurs when dealing with odd bytes. The
chained move (CHMOV) SCRIPTS instruction along with the Wide SCSI
Send (WSS) and Wide SCSI Receive (WSR) bits in the SCSI Control

Two (SCNTL2) register are used to facilitate these situations.

2.4.14.1 Wide SCSI Send Bit

The WSS bit is set whenever the SCSI controller is sending data
(Data-Out for initiator or Data-In for target) and the controller detects a
partial transfer at the end of a chained Block Move SCRIPTS instruction
(this flag is not set if a normal Block Move instruction is used). Under this
condition, the SCSI controller does not send the low-order byte of the last
partial memory transfer across the SCSI bus. Instead, the low-order byte
is temporarily stored in the lower byte of the SCSI Output Data Latch

(SODL) register and the WSS flag is set. The hardware uses the WSS

flag to determine what behavior must occur at the start of the next data
send transfer. When the WSS flag is set at the start of the next transfer,
the first byte (the high-order byte) of the next data send transfer is
“married” with the stored low-order byte in the SCSI Output Data Latch

(SODL) register; and the two bytes are sent out across the bus,

regardless of the type of Block Move instruction (normal or chained). The
flag is automatically cleared when the “married” word is sent. The flag is
alternately cleared through SCRIPTS or by the microprocessor.
Additionally, this bit can be used by the microprocessor or SCRIPTS for
error detection and recovery purposes.

2.4.14.2 Wide SCSI Receive Bit

The WSR bit is set whenever the SCSI controller is receiving data
(Data-In for initiator or Data-Out for target) and the controller detects a
partial transfer at the end of a block move or chained block move
SCRIPTS instruction. When WSR is set, the high-order byte of the last
SCSI bus transfer is not transferred to memory. Instead, the byte is
temporarily stored in the SCSI Wide Residue (SWIDE) register. The
hardware uses the WSR bit to determine what behavior must occur at
the start of the next data receive transfer. The bit is automatically cleared
at the start of the next data receive transfer. The bit can alternatively be

2-42 Functional Description

cleared by the microprocessor or through SCRIPTS. The bit can also be
used by the microprocessor or SCRIPTS for error detection and recovery
purposes.

2.4.14.3 SWIDE Register

This register stores data for partial byte data transfers. For receive data,
the SCSI Wide Residue (SWIDE) register holds the high-order byte of a
partial SCSI transfer which has not yet been transferred to memory. This
stored data may be a residue byte (and therefore ignored) or it may be
valid data that is transferred to memory at the beginning of the next Block
Move instruction.

2.4.14.4 SODL Register

For send data, the low-order byte of the SCSI Output Data Latch (SODL)
register holds the low-order byte of a partial memory transfer which has
not yet been transferred across the SCSI bus. This stored data is usually
“married” with the first byte of the next data send transfer, and both bytes
are sent across the SCSI bus at the start of the next data send block
move command.

2.4.14.5 Chained Block Move SCRIPTS Instruction

A chained Block Move SCRIPTS instruction is primarily used to transfer
consecutive data send or data receive blocks. Using the chained Block
Move instruction facilitates partial receive transfers and allows correct
partial send behavior without additional opcode overhead. Behavior of
the chained Block Move instruction varies slightly for sending and
receiving data.

For receive data (Data-In for initiator or Data-Out for target), a chained
Block Move instruction indicates that if a partial transfer occurred at the
end of the instruction, the WSR flag is set. The high-order byte of the
last SCSI transfer is stored in the SCSI Wide Residue (SWIDE) register
rather than transferred to memory. The contents of the SCSI Wide

Residue (SWIDE) register should be the first byte transferred to memory

at the start of the chained block move data stream. Since the byte count
always represents data transfers to/from memory (as opposed to the
SCSI bus), the byte transferred out of the SCSI Wide Residue (SWIDE)
register is one of the bytes in the byte count. If the WSR bit is cleared
when a receive data chained Block Moveinstruction is executed,the data

PCI Cache Mode 2-43

transfer occurs similar to that of the regular block move instruction.
Whether the WSR bit is set or cleared, when a normal block move
instruction is executed, the contents of the SCSI Wide Residue (SWIDE)
register are ignored and the transfer takes place normally. For “N”
consecutive wide data receive Block Move instructions, the 2nd through
the Nth Block Move instructions should be chained block moves.

For send data (Data-Out for initiator or Data-In for target), a chained
Block Move instruction indicates that if a partial transfer terminates the
chained block move instruction, the last low-order byte (the partial
memory transfer) should be stored in the lower byte of the SCSI Output

Data Latch (SODL) register and not sent across the SCSI bus. Without

the chained block move instruction, the last low-order byte would be sent
across the SCSI bus. The starting byte count represents data bytes
transferred from memory but not to the SCSI bus when a partial transfer
exists. For example, if the instruction is an Initiator chained Block Move
Data Out of five bytes (and WSS is not previously set), five bytes will be
transferred out of memory to the SCSI controller, four bytes are
transferred from the SCSI controller across the SCSI bus, and one byte
is temporarily stored in the lower byte of the SCSI Output Data Latch

(SODL) register waiting to be married with the first byte of the next block

move instruction. Regardless of whether a chained Block Move or normal
Block Move instruction is used, if the WSS bit is set at the start of a data
send command, the first byte of the data send command is assumed to
be the high-order byte and is “married” with the low-order byte stored in
the lower byte of the SCSI Output Data Latch (SODL) register before the
two bytes are sent across the SCSI bus. For “N” consecutive wide data
send Block Move commands, the first through the (Nth – 1) Block Move
instructions should be Chained Block Moves.

2-44 Functional Description

The Chained Block Move instruction is illustrated in Figure 2.6.

Figure 2.6 Block Move and Chained Block Move Instructions

Host Memory SCSI Bus

0x03 0x02 0x01 0x00

0x07 0x06 0x05 0x04

0x0B 0x0A 0x09 0x08

0x0F 0x0E 0x0D 0x0C

0x13 0x12 0x11 0x10

32 Bits 16 Bits

00

04

08

0C

10

0x04 0x03

0x06 0x05

0x09 0x07

0x0B 0x0A

0x0D 0x0C

CHMOV 5, 3 when Data_Out
Moves five bytes from address 0x03 in the host memory to the SCSI bus.

Bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in
the low-order byte of the SCSI Output Data Latch (SODL) register and
is combined with the first byte of the following MOVE instruction.

Move 5, 9 when Data_Out
Moves five bytes from address 0x09 in the host memory to the SCSI bus.

PCI Cache Mode 2-45

2.5 Power Management

This feature complies with the PCI Bus Power Management Interface
Specification, Revision 1.0. The PCI Function Power States are defined
in that specification: D0, D1, D2, and D3. D0 and D3 are required by
specification, and D1 and D2 are optional. D0 is the maximum powered
state, and D3 is the minimum powered state. Power state D3 is further
categorized as D3hot or D3cold. A function that is powered off is said to
be in the D3cold power state.

The power states for the SCSI function are independently controlled
through two power state bits that are located in the PCI Configuration
Space register 0x44. The bits are encoded as:

Power states D1 and D2 are not discussed because they have not been
implemented as a new feature.

The Power states – D0 and D3 – are described below in conjunction with
each SCSI function. Power state actions are separate for each function.

00b D0
01b Reserved
10b Reserved
11b D3

2.5.1 Power State D0

Power state D0 is the maximum power state and is the power-up default
state for each function.

2.5.2 Power State D3

Power state D3 is the minimum power state, which includes subsettings
called D3hot and D3cold. The devices are considered to be in power
state D3cold when power is removed from them. D3cold can transition
to D0 by applying Vcc and resetting the device. D3hot allows the device
to transition to D0 using software. To obtain power reduction in D3hot,
the SCSI clock and the SCSI clock doubler Phase Lock Loop (PLL) are
disabled. Furthermore, the function’s soft reset is continually asserted
while in power state D3, which clears all pending interrupts and 3-states
the SCSI bus. In addition, the function’s PCI Command register is
cleared.

2-46 Functional Description

Chapter 3
Signal Descriptions

This chapter presents the LSI53C825A pin configuration and signal
definitions using tables and illustrations. Figure 3.1 through Figure 3.2
are the pin diagrams for all versions of the LSI53C825A and Figure 3.3
is the functional signal grouping. The pin definitions are presented in

Table 3.1 through Table 3.10. The LSI53C825A is a pin-for-pin

replacement for the LSI53C825. This chapter is divided into the following
sections:

• Section 3.1, “PCI Bus Interface Signals”

• Section 3.2, “MAD Bus Programming”

LSI53C825A/825AE PCI to SCSI I/O Processor 3-1

Figure 3.1 LSI53C825A Pin Diagram

SS-C

DD-C

SS

DD-I

SS

AD24

AD25

AD29

AD28

V

AD27

AD26

V

V

AD30

AD31

GNT/

V

REQ/

BIG_LIT/

CLK

V

RST/

SERR/

MCE/

MWE/

VDDMOE/

MAS1/

MAS0/

VSSSDIR12

SDIR13

SDIR15

SDIR14

SDIRP1

SDIR0

DD

V

SDIR1

SDIR2

VSSSDIR3

SDIR4

SDIR5

SDIR6

C_BE3/

IDSEL

AD23

V
AD22
AD21
AD20

V

DD-I

AD19

V
AD18
AD17
AD16

V

C_BE2/

FRAME/

IRDY/

V

TRDY/

DEVSEL/

V

DD-I

STOP/

V

PERR/

PAR/

C_BE1/

V
AD15
AD14
AD13

V
AD12

V

DD-I

AD11
AD10

AD9

V

AD8

C_BE0/

AD7

160

158

157

159

1

2

3

4

SS

5

6

7

8

9

10

SS

11

12

13

14

SS

15
16
17
18

SS

19
20
21
22
23

SS

24
25
26
27

SS

28
29
30
31

SS

32
33
34
35
36
37

SS

38
39
40

4143454749515355575961636567697173757677787980

4244464850525456586062646668707274

SS

V

AD6

AD5

AD4

152

154

156

153

155

SS

DD-I

V

AD2

AD3

AD1

V

147

148

150

149

151

SCSI I/O Processor

DD-C

IRQ/

V

GPIO0_FETCH/

SS-C

V

GPIO1_MASTER/

AD0

141

143

144

145

146

142

140

160-pin

Quad Flat Pack

(Top View)

SCLK

TESTIN

MAC/_TESTOUT

MAD7

MAD6

MAD5

139

MAD4

135

137

134

136

138

DD

V

MAD2

MAD0

MAD1

MAD3

131

133

130

132

SS

V

GPIO4

GPIO3

DIFFSENS

GPIO2_MAS2/

129

TGS

128

123

125

127

122

124

126

IGS

SELDIR

RSTDIR

SS

V

BSYDIR

DD

V

Note: The decoupling capacitor arrangement shown above is recommended to maximize

the benefits of the internal split ground system. Capacitor values between 0.01 and

0.1µF should provide adequate noise isolation. Because of the number of high
current drivers on the LSI53C825A, a multilayer PC board with power and ground
planes is required.

121

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

SDIR11

SDIR7
SDIRP0
V

DD

SD12/
SD13/
SD14/
V

SS-S

SD15/
SDP1/
SD0/
SD1/
V

SS-S

SD2/
SD3/
SD4/
SD5/
V

SS-S

SD6/
SD7/
SDP0/
SATN/
V

SS-S

SBSY/
SACK/
SRST/
SMSG/
SSEL/
V

SS-S

SC_D/
SREQ/
SI_O/
SD8/
V

SS-S

SD9/
SD10/
SD11/
V

DD

SDIR8
SDIR9
SDIR10

3-2 Signal Descriptions

Figure 3.2 LSI53C825AJ Pin Diagram

SS-C

DD-C

SS

DD-I

SS

AD24

AD25

AD29

AD28

V

AD27

AD26

V

V

AD30

AD31

GNT/

V

REQ/

TDI

CLK

V

RST/

SERR/

MCE/

MWE/

VDDMOE/

MAS1/

MAS0/

VSSSDIR12

SDIR13

SDIR15

SDIR14

TCK

SDIR0

DD

V

SDIR1

SDIR2

VSSSDIR3

SDIR4

SDIR5

SDIR6

C_BE3/

IDSEL

AD23

V
AD22
AD21
AD20

V

DD-I

AD19

V
AD18
AD17
AD16

V

C_BE2/

FRAME/

IRDY/

V

TRDY/

DEVSEL/

V

DD-I

STOP/

V

PERR/

PAR/

C_BE1/

V
AD15
AD14
AD13

V
AD12

V

DD-I

AD11
AD10

AD9

V

AD8

C_BE0/

AD7

160

156

158

157

159

1
2
3
4

SS

5
6
7
8
9
10

SS

11
12
13
14

SS

15
16
17
18

SS

19
20
21
22
23

SS

24
25
26
27

SS

28
29
30
31

SS

32
33
34
35
36
37

SS

38
39
40

4143454749515355575961636567697173757677787980

4244464850525456586062646668707274

SS

DD-I

V

AD6

AD5

AD4

AD3

V

155

AD2

154

150

152

151

153

SS

V

AD0

AD1

DD-C

IRQ/

V

144

145

146

147

148

149

SCSI I/O Processor

Quad Flat Pack

(Top View)

SS-C

TMS

V

SCLK

GPIO0_FETCH/

GPIO1_MASTER/

141

143

142

160-pin

TDO

MAD7

MAD6

140

MAD5

139

MAD4

138

DD

V

137

MAD2

MAD3

136

135

MAD1

133

132

134

SS

V

MAD0

GPIO2_MAS2/

131

GPIO4

GPIO3

129

130

TGS

DIFFSENS

128

127

126

DD

IGS

V

125

124

SELDIR

RSTDIR

123

122

SS

V

BSYDIR

121

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81

SDIR11

SDIR7
SDIRP0
V

DD

SD12/
SD13/
SD14/
V

SS-S

SD15/
SDP1/
SD0/
SD1/
V

SS-S

SD2/
SD3/
SD4/
SD5/
V

SS-S

SD6/
SD7/
SDP0/
SATN/
V

SS-S

SBSY/
SACK/
SRST/
SMSG/
SSEL/
V

SS-S

SC_D/
SREQ/
SI_O/
SD8/
V

SS-S

SD9/
SD10/
SD11/
V

DD

SDIR8
SDIR9
SDIR10

The PCI/SCSI pin definitions are organized into the following functional
groups: System, Address/Data, Interface Control, Arbitration, Error
Reporting, SCSI, and Optional Interface. A slash (/) at the end of the
signal name indicates that the active state occurs when the signal is at
a LOW voltage. When the slash is absent, the signal is active at a HIGH
voltage.

3-3

There are four signal type definitions:

I Input, a standard input-only signal.
O Output, a standard output driver (typically a Totem Pole Output).
T/S 3-state, a bidirectional, 3-state input/output signal.
S/T/S Sustained 3-state, an active LOW 3-state signal owned and driven by

one and only one agent at a time.

Table 3.1 LSI53C825A, LSI53C825AJ, LSI53C825AE, and

LSI53C825AJE Power and Ground Pins

Symbol Pin No. Description

V

SS

V

DD

V

DD-I

V

-S 88, 93, 99, 104, 109,

SS

V

-C 55, 146 Ground to the internal logic core

SS

V

-C 51, 149 Power supplies to the internal logic core

DD

1. These pins can accept a VDD source of 3.3 or 5 Volts. All other VDD pins
must be supplied 5 Volts.

4, 10, 14, 18, 23, 27,
31, 37, 42, 48, 69, 79,
123, 133, 152, 158

8, 33, 45, 63, 74, 84,

118, 128, 138

1

8, 21, 33, 45, 155 V

114

, 155

Ground to the PCI I/O pins

Power supplies to the Standard I/O pins

pad for PCI I/O pins

DD

Ground to the SCSI bus I/O pins

3-4 Signal Descriptions

Figure 3.3 is the functional signal grouping for the LSI53C825A.

Figure 3.3 LSI53C825A Functional Signal Grouping

LSI53C825A

System

Address

and

Data

Interface

Control

Arbitration

Error

Reporting

CLK
RST

AD[31:0]
C_BE/[3:0]
PAR

FRAME/
TRDY/
IRDY/
STOP/
DEVSEL/
IDSEL

REQ/
GNT/

PERR/
SERR/

GPIO0_FETCH/

GPIO1_MASTER/

MAC/_TESTOUT

GPIO2_MAS2/

SCLK

SD[15:0]

SDP[1:0]

SCTRL

SDIR[15:0]

SDIRP[1:0]

SELDIR
RSTDIR
BSYDIR

IGS

TGS

TESTIN/

GPIO[4:3]

DIFFSENS

IRQ/

BIG_LIT/

MAS0/
MAS1/

MAD[7:0]

MWE/

MOE/

MCE/

SCSI

Additional
Interface

Device Local
Memory Bus
and Control

3-5

3.1 PCI Bus Interface Signals

The PCI Bus Interface Signals section contains tables describing the
signals for the following signal groups: System Signals, Address and

Data Signals, Interface Control Signals, Arbitration Signals, Error
Reporting Signals, SCSI Bus Interface Signals, Additional Interface
Signals, External Memory Interface Signals, and JTAG Signals.

3.1.1 System Signals

Table 3.2 describes the signals for the System Signals group:

Table 3.2 System Signals

Name Pin No. Type Description

CLK 145 I Clock provides timing for all transactions on the PCI bus and is an input to

RST/ 144 I Reset forces the PCI sequencer of each device to a known state. All t/s and

every PCI device. All other PCI signals are sampled on the rising edge of
CLK, and other timing parameters are defined with respect to this edge. This
clock can optionally be used as the SCSI core clock; however, the
LSI53C825A is not able to achieve Fast SCSI transfer rates.

s/t/s signals are forced to a high impedance state, and all internal logic is
reset. The RST/ input is synchronized internally to the rising edge of CLK.
The CLK input must be active while RST/ is active to properly reset the
device.

3-6 Signal Descriptions

3.1.2 Address and Data Signals

Table 3.3 describes the signals for the Address and Data Signals group:

Table 3.3 Address and Data Signals

Name Pin No. Type Description

AD[31:0] 150, 151, 153,

154, 156, 157,
159, 160, 3, 5,
6, 7, 9, 11, 12,
13, 28, 29, 30,
32, 34, 35, 36,
38, 40, 41, 43,
44, 46, 47, 49,

50

C_BE[3:0]/ 1, 15, 26, 39 T/S Bus Command and Byte Enables are multiplexed on the same

PAR 25 T/S Parity is the even parity bit that protects the AD[31:0] and

T/S Physical longword Address and Data are multiplexed on the

same PCI pins. During the first clock of a transaction,
AD[31:0] contain a physical address. During subsequent clocks,
AD[31:0] contain data. A bus transaction consists of an address
phase, followed by one or more data phases. PCI supports both
read and write bursts. AD[7:0] define the least significant byte,
and AD[31:24] define the most significant byte.

PCI pins. During the address phase of a transaction,
C_BE[3:0]/ define the bus command. During the data phase,
C_BE[3:0]/ are used as byte enables. The byte enables
determine which byte lanes carry meaningful data. C_BE(0)/
applies to byte 0, and C_BE(3)/ to byte 3.

C_BE[3:0]/ lines. During address phase, both the address and
command bits are covered. During data phase, both data and
byte enables are covered.

PCI Bus Interface Signals 3-7

3.1.3 Interface Control Signals

Table 3.4 describes the signals for the Interface Control Signals group:

Table 3.4 Interface Control Signals

Name Pin No. Type Description

FRAME/ 16 S/T/S Cycle Frame is driven by the current master to indicate the beginning

TRDY/ 19 S/T/S Target Ready indicates the target agent’s (selected device’s) ability to

IRDY/ 17 S/T/S Initiator Ready indicates the initiating agent’s (bus master’s) ability to

STOP/ 22 S/T/S Stop indicates that the selected target is requesting the master to stop

DEVSEL/ 20 S/T/S Device Select indicates that the driving device has decoded its address

IDSEL 2 I Initialization Device Select is used as a chip select in place of the

and duration of an access. FRAME/ is asserted to indicate a bus
transaction is beginning. While FRAME/ is asserted, data transfers
continue. When FRAME/ is deasserted, the transaction is in the final
data phase or the bus is idle.

complete the current data phase of the transaction. TRDY/ is used with
IRDY/. A data phase is completed on any clock when both TRDY/ and
IRDY/ are sampled asserted. During a read, TRDY/ indicates that valid
data is present on AD[31:0]. During a write, it indicates the target is
prepared to accept data. Wait cycles are inserted until both IRDY/ and
TRDY/ are asserted together.

complete the current data phase of the transaction. This signal is used
with TRDY/. A data phase is completed on any clock when both IRDY/
and TRDY/ are sampled asserted. During a write, IRDY/ indicates that
valid data is present on AD[31:0]. During a read, it indicates the master
is prepared to accept data. Wait cycles are inserted until both IRDY/ and
TRDY/ are asserted together.

the current transaction.

as the target of the current access. As an input, it indicates to a master
whether any device on the bus has been selected.

upper 24 address lines during configuration read and write transactions.

3-8 Signal Descriptions

3.1.4 Arbitration Signals

Table 3.5 describes the signals for the Arbitration Signals group:

Table 3.5 Arbitration Signals

Name Pin No. Type Description

REQ/ 148 O Request indicates to the arbiter that this agent desires use of the PCI bus.

GNT/ 147 I Grant indicates to the agent that access to the PCI bus has been granted.

This is a point-to-point signal. Every master has its own REQ/.

This is a point-to-point signal. Every master has its own GNT/.

3.1.5 Error Reporting Signals

Table 3.6 describes the signals for the Error Reporting Signals group:

Table 3.6 Error Reporting Signals

Name Pin No. Type Description

PERR/ 24 S/T/S Parity Error may be pulsed active by an agent that detects a data parity

SERR/ 143 O System Error is an open drain output pin used to report address parity

error. PERR/ can be used by any agent to signal data corruptions.

errors. On detection of a PERR/ pulse, the central resource may generate
a nonmaskable interrupt to the host CPU, which often implies the system
is unable to continue operation once error processing is complete.

PCI Bus Interface Signals 3-9

3.1.6 SCSI Bus Interface Signals

Table 3.7 describes the SCSI Bus Interface Signals group:

Table 3.7 SCSI Bus Interface Signals

Name Pin No. Type Description

SCLK 56 I SCLK is used to derive all SCSI-related timings. The speed

SD[15:0]/,
SDP[1:0]/

SCTRL/ 92, 90, 95,91,

SDIR[15:0] 131,132,134,

113,115, 116,

117, 85, 86,

87, 89, 102,
103,105, 106,
107,108, 110,

111, 112, 101

97, 98, 100,

96, 94

135, 80, 81,

82, 83, 120,
121,122, 124,
125,126, 127,

129

of this clock is determined by the application’s requirements;
in some applications SCLK may be sourced internally from
the PCI bus clock (CLK). If SCLK is internally sourced, then
the SCLK pin should be tied LOW.

I/O SCSI Data includes the following data lines and parity

signals: SD[15:0]/ (16-bit SCSI data bus), and SDP[1:0]/
(SCSI data parity bits).

I/O SCSI Control includes the following signals:

SC_D/ SCSI phase line, command/data
SI_O/ SCSI phase line, input/output
SMSG/ SCSI phase line, message
SREQ/ Data handshake signal from target device
SACK/ Data handshake signal from initiator device
SBSY/ SCSI bus arbitration signal, busy
SATN/ SCSI Attention, the initiator is requesting a

message out phase
SRST/ SCSI bus reset
SSEL/ SCSI bus arbitration signal, select device

O Driver direction control for SCSI data lines.

SDIRP[1:0]
(SDIPR1 not
available on
LSI53C825AJ)

SELDIR 76 O Driver Enable Control for SCSI SEL/ signal.

130, 119 O Driver direction control for SCSI parity signals. In the

LSI53C825AJ, this pin is replaced by the TCK JTAG signal. If
the device is used in a wide differential system, use the
SDIRP0 pin to control the direction of the differential
transceiver for both the SP0 and SP1 signals. The SDIRP0
signal is capable of driving both direction inputs from a
transceiver.

3-10 Signal Descriptions

Table 3.7 SCSI Bus Interface Signals (Cont.)

Name Pin No. Type Description

RSTDIR 77 O Driver Enable Control for SCSI RST/ signal.
BSYDIR 78 O Driver Enable Control for SCSI BSY/ signal.
IGS 75 O Direction Control for initiator driver group.
TGS 73 O Direction Control for target driver group.

3.1.7 Additional Interface Signals

Table 3.8 describes the signals for the Additional Interface Signals group:

Table 3.8 Additional Interface Signals

Name Pin No. Type Description

TESTIN (Not
available on
LSI53C825AJ)

GPIO0_
FETCH/

57, NA I TestIn. When this pin is driven LOW, the LSI53C825A connects

all inputs and outputs to an “AND tree.” The SCSI control
signals and data lines are not connected to the “AND tree.” The
output of the “AND tree” is connected to the Test Out pin. This
allows manufacturers to verify chip connectivity and determine
exactly which pins are not properly attached. When the TESTIN
pin is driven LOW, internal pull-ups are enabled on all input,
output, and bidirectional pins, all outputs and bidirectional
signals are 3-stated, and the MAC/_TESTOUT pin is enabled.
Connectivity can be tested by driving one of the LSI53C825A
pins LOW. The MAC/_TESTOUT pin should respond by also
driving LOW.

53/70/N5 I/O General Purpose I/O pin. Optionally, when driven LOW, this pin

indicates that the next bus request will be for an opcode fetch.
This pin powers up as a general purpose input.
This pin has two specific purposes in the LSI Logic SDMS
software. SDMS software uses it to toggle SCSI device LEDs,
turning on the LED whenever the LSI53C825A is on the SCSI
bus. SDMS software drives this pin LOW to turn on the LED, or
drives it HIGH to turn off the LED. This signal can also be used
as data I/O for serial EEPROM access. In this case it is used
with the GPIO0 pin, which serves as a clock, and the pin can
be controlled from PCI configuration register 0x35 or observed
from the General Purpose (GPREG) register, at address 0x07.

PCI Bus Interface Signals 3-11

Table 3.8 Additional Interface Signals (Cont.)

Name Pin No. Type Description

GPIO1_
MASTER/

54 I/O General purpose I/O pin. Optionally, when driven LOW,

indicates that the LSI53C825A is bus master. This pin powers
up as a general purpose input.
LSI Logic SDMS software supports use of this signal in serial
EEPROM applications, when enabled, in combination with the
GPIO0 pin. When this signal is used as a clock for serial
EEPROM access, the GPIO1 pin serves as data, and the pin is
controlled from PCI configuration register 0x35.

GPIO[4:3] 71, 70 I/O General purpose I/O pins. GPIO4 powers up as an output. It

can be used as the enable line for V
to the external flash memory interface. GPIO3 powers up as an

, the 12 Volt power supply

PP

input.
LSI Logic SDMS software uses GPIO3 to detect a differential
board. If the pin is pulled LOW externally, the board will be
configured by SDMS software as a differential board. If it is
pulled HIGH or left floating, SDMS software will configure it as
a SE board. The LSI Logic PCI to SCSI host adapters use the
GPIO4 pin in the process of flashing a new SDMS software
ROM.

DIFFSENS 72 I The Differential Sense pin detects the presence of a SE device

on a differential system. When external differential transceivers
are used and a zero is detected on this pin, all chip SCSI
outputs will be 3-stated to avoid damage to the transceivers.
This pin should be tied HIGH during SE operation. The normal
value of this pin is 1.

MAC/_
TESTOUT (Not
available on
LSI53C825AJ)

58, NA T/S Memory Access Control. This pin can be programmed to

indicate local or system memory accesses (non-PCI
applications). It is also used to test the connectivity of the
LSI53C825A signals using an “AND tree” scheme. The
MAC/_TESTOUT pin is only driven as the Test Out function
when the TESTIN/ pin is driven LOW.

IRQ/ 52/69/

M5

O Interrupt. This signal, when asserted LOW, indicates that an

interrupting condition has occurred and that service is required
from the host CPU. The output drive of this pin is programmed
as either open drain with an internal weak pull-up or, optionally,
as a totem pole driver. Refer to the description of DMA Control

(DCNTL) register, bit 3, for additional information.

3-12 Signal Descriptions

Table 3.8 Additional Interface Signals (Cont.)

Name Pin No. Type Description

BIG_LIT/ (Not
available on
LSI53C825AJ)

142, NA I Big_Little Endian Select. When this pin is driven LOW, the

LSI53C825A routes the first byte of an aligned SCSI to PCI
transfer to byte lane zero of the PCI bus and subsequent bytes
received are routed to ascending lanes. An aligned PCI to SCSI
transfer routes PCI byte lane zero onto the SCSI bus first, and
transfers ascending byte lanes in order. When this pin is driven
HIGH, the LSI53C825A routes the first byte of an aligned SCSI
to PCI transfer to byte lane three of the PCI bus and subsequent
bytes received are routed to descending lanes. An aligned PCI
to SCSI transfer routes PCI byte lane three onto the SCSI bus
first and transfer descending byte lanes in order. This mode of
operation also applies to the external memory interface. When
this pin is driven in little endian mode and the chip is performing
a read from external memory, the byte of data accessed at
location 0x00000 is routed to PCI byte lane zero and the data
accessed at location 0x00003 is routed to PCI byte lane three.
When the chip is performing a write to flash memory, PCI byte
lane zero is routed to location 0x00000 and ascending byte
lanes are routed to subsequent memory locations. When this
pin is driven in big endian mode and the chip is performing a
read from external memory, the byte of data accessed at
location 0x00000 is routed to PCI byte lane three and the data
accessed at location 0x00003 is routed to byte lane zero. When
the chip is performing a write to flash memory, PCI byte lane
three is routed to location 0x00000 and descending byte lanes
is routed to subsequent memory locations.

PCI Bus Interface Signals 3-13

3.1.8 External Memory Interface Signals

Table 3.9 describes the signals for the External Memory Interface Signals

group:

Table 3.9 External Memory Interface Signals

Name Pin No. Type Description

MAS0/ 137/179/A8 O Memory Address Strobe 0. This pin is used to latch in the least

MAS1/ 136/178/B8 O Memory Address Strobe 1. This pin is used to latch in the address

MAD[7:0] 59, 60, 61,

MWE/ 139/181/C7 O Memory Write Enable. This pin is used as a write enable signal to

MOE/ 140/182/B7 O Memory Output Enable. This pin is used as an output enable signal

MCE/ 141/183/A7 O Memory Chip Enable. This pin is used as a chip enable signal to

GPIO2_
MAS2/

62, 64, 65,

66, 67

68/87/J8 I/O General Purpose I/O pin. Optionally, this pin is used as a Memory

significant address byte of an external EPROM or flash memory.
Since the LSI53C825A moves addresses eight bits at a time, this pin
connects to the clock of an external bank of flip-flops which are used
to assemble up to a 20-bit address for the external memory.

byte corresponding to address bits [15:8] of an external EPROM or
flash memory. Since the LSI53C825A moves addresses eight bits at
a time, this pin connects to the clock of an external bank of flip-flops
which assemble up to a 20-bit address for the external memory.

I/O Memory Address/Data Bus. This bus is used in conjunction with the

memory address strobe pins and external address latches to
assemble up to a 20-bit address for an external EPROM or flash
memory.This bus will put out the most significant byte first and finish
with the least significant bits. It is also used to write data to a flash
memory or read data into the chip from external EPROM/flash
memory. See Section 3.2, “MAD Bus Programming,” for more details.

an external flash memory.

to an external EPROM or flash memory during read operations.

an external EPROM or flash memory device.

Address Strobe 2 if an external memory with more than 16 bits of
addressing is specified by the pull-down resistors at power-up and
bit 0 in the Expansion ROM Base Address register is set.

3-14 Signal Descriptions

3.1.9 JTAG Signals

Table 3.10 describes the signals for the JTAG Signals group:

Table 3.10 JTAG Signals (LSI53C825AJ, LSI53C825AJE Only)

Name Pin No. Type Description

TCK 130/130 – Test Clock pin for JTAG boundary scan.
TMS 57/57 – Test Mode Select pin for JTAG boundary scan.
TDI 142/142 – Test Data In pin for JTAG boundary scan.
TDO 58/58 – Test Data Out pin for JTAG boundary scan.

3.2 MAD Bus Programming

The MAD[7:0] pins, in addition to serving as the address/data bus for the
local memory interface, are also used to program power-up options for
the chip. A particular option is programmed by connecting a 4.7 kΩ
resistor between the appropriate MAD(x) pin and Vss. The pull-down
resistors require that HC or HCT external components are used for a
memory interface.

• MAD[7] – has no functionality. Do not place a pull-down resistor on

this pin.

• MAD[6] – Subsystem Data configuration. Please refer to the

Table 3.11 for the different configurations.

• MAD[5] – SCRIPTS RAM disable. Connecting a 4.7 kΩ resistor

between MAD[5] and Vss disables SCRIPTS RAM.

• MAD[4] – Subsystem Data configuration. Please refer to the

Table 3.11 and Table 3.12 below for the different configurations.

MAD Bus Programming 3-15

Table 3.11 Subsystem Data Configuration Table for the LSI53C825AE

(PCI Rev ID 0x26)

Mode MAD Pins Offset

Vendor ID 0x00 0x1000 0x1000 – 0x1000
Device ID 0x02 0x000F 0x000F – 0x000F
Subsystem Vendor ID 0x2C 0x1000 0x0000 – 0x0000
Subsystem ID 0x2E 0x1000 0x0000 – 0x0000

Table 3.12 Subsystem Data Configuration Table for the LSI53C825A (PCI Rev ID 0x14)

Revision G Only

Mode MAD Pins Offset

Vendor ID 0x00 0x1000 0x1000 – 0x1000
Device ID 0x02 0x000F 0x000F – 0x000F
Subsystem Vendor ID 0x2C 0x0000 0x0000 – 0x1000
Subsystem ID 0x2E 0x0000 0x0000 – 0x1000

1. The chip revisions before Revision G of the LSI53C825A (PCI Rev ID 0x14) do not support different
Subsystem Data Configurations. The Subsystem ID (SSID) and Subsystem Vendor ID (SSVID)
registers are hardwired to zero values.

1

Normal

4-hi, 6-hi

Normal

4-hi, 6-hi

Read/Write

4-hi, 6-lo

Read/Write

4-hi, 6-lo

Reserved

4-low, 6-hi

Reserved

4-low, 6-hi

LSI Logic

4-low, 6-lo

LSI Logic

4-low, 6-lo

• MAD[3:1] – used to set the size of the external expansion ROM

device attached. Encoding for these pins are listed in Table 3.13.

3-16 Signal Descriptions

Table 3.13 External Memory Support

MAD[3:1] Available Memory Space

000 16 Kbytes
001 32 Kbytes
010 64 Kbytes
011 128 Kbytes
100 256 Kbytes
101 512 Kbytes
110 1024 Kbytes
111 No external memory present

• MAD[0] – the slow ROM pin. When pulled down, it enables two extra

clock cycles of data access time to allow use of slower memory
devices.

Note: All MAD pins have internal pull-up resistors.

MAD Bus Programming 3-17

3-18 Signal Descriptions

Chapter 4
Registers

This chapter describes all LSI53C825A registers and is divided into the
following sections:

• Section 4.1, “Configuration Registers”

• Section 4.2, “Operating Registers”

4.1 Configuration Registers

The Configuration registers are accessible only by the system BIOS
during PCI configuration cycles, and they are not available to the user at
any time. These registers can be accessed by SCRIPTS or the host
processor. The lower 128 bytes hold configuration data while the upper
128 bytes hold the LSI53C825A operating registers, which are described
in Chapter 5, “SCSI SCRIPTS Instruction Set.” Please note that the
information about lower and upper bytes only applies to the LSI53C825A
and not the LSI53C825AE.

Note: The configuration register descriptions provide general

information only, to indicate which PCI configuration
addresses are supported in the LSI53C825A. For detailed
information, refer to the PCI Specification.

Table 4.1 shows the PCI configuration registers implemented by the

LSI53C825A/825AE.
All PCI-compliant devices, such as the LSI53C825A, must support the

Vendor ID, Device ID, Command, and Status registers. Support of other

PCI-compliant registers is optional. In the LSI53C825A, registers that are
not supported are not writable and return all zeros when read. Only those
registers and bits that are currently supported by the LSI53C825A are
described in this chapter. Reserved bits should not be accessed.

LSI53C825A/825AE PCI to SCSI I/O Processor 4-1

Table 4.1 PCI Configuration Register Map

31 16 15 0

Device ID Vendor ID 0x00

Status Command 0x04

Class Code Revision ID 0x08

Not Supported Header Type Latency Timer Cache Line Size 0x0C

Base Address Zero (I/O)1SCSI Operating Registers

Base Address One (Memory)2SCSI Operating Registers

Base Address Two (Memory) SCRIPTS RAM

Not Supported 0x1C
Not Supported 0x20
Not Supported 0x24

Reserved 0x28

Subsystem ID (SSID) Subsystem Vendor ID (SSVID) 0x2C

Expansion ROM Base Address

Reserved Capability Pointer 0x34

Reserved 0x38

Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0x3C

Power Management Capabilities Next Item Pointer Capability ID 0x40

Data

Bridge Support

Extension

Power Management Control/Status 0x44

3

4

1. I/O Base is supported.

2. Memory Base is supported.

3. This register powers up enabled and can be disabled by pull-down resistors on the MAD5 pin.

4. If expansion memory is enabled through pull-down resistors on the MAD[7:0] bus.

Note: Addresses 0x40–7F are not defined for the LSI53C825A. Addresses 0x48–7F are not defined for

the LSI53C825AE. All unsupported registers are not writable and return all zeros when read.
Reserved registers also return zeros when read.

0x10
0x14
0x18

0x30

4-2 Registers

Register: 0x00

Vendor ID
Read Only

15 0

VID

1111000000000000

VID Vendor ID [15:0]

This field identifies the manufacturer of the device. The
Vendor ID is 0x1000.

Register: 0x02

Device ID
Read Only

15 0

DID

0000000000000000

DID Device ID [15:0]

This field identifies the particular device. The
LSI53C825A device ID is 0x0003. This value is the same
as in the LSI53C825, since the LSI53C825A is a drop in
replacement. The devices are uniquely identified in the
upper nibble of the Revision ID register.

Register: 0x04

Command
Read/Write

15 9 8 7 6 5 4 3 2 1 0

RSER EPER R WIE R EBM EMS EIS

0 0 0 0 0 0 00000000 00

The Command register provides coarse control over a device’s ability to
generate and respond to PCI cycles. When a zero is written to this
register, the LSI53C825A is logically disconnected from the PCI bus for
all accesses except configuration accesses.

In the LSI53C825A, bits 3 through 5 and bit 7 and 9 are not
implemented. Bits 10 through 15 are reserved.

Configuration Registers 4-3

R Reserved [15:9]
SE SERR/Enable 8

This bit enables the SERR/ driver. SERR/ is disabled
when this bit is clear. The default value of this bit is zero.
This bit and bit 6 must be set to report address parity
errors.

R Reserved 7
EPER Enable Parity Error Response 6

This bit allows the LSI53C825A to detect parity errors on
the PCI bus and report these errors to the system. Only
data parity checking is enabled. The LSI53C825A always
generates parity for the PCI bus.

R Reserved 5
WIE Write and Invalidate Mode 4

This bit, when set, causes Memory Write and Invalidate
cycles to be issued on the PCI bus after certain
conditions have been met. For more information on these
conditions, refer to Section 2.1.2.7, “Memory Write and

Invalidate Command.” To enable Write and Invalidate

Mode, bit 10 in the Chip Test Three (CTEST3) register
(operating register set) must also be set.

R Reserved 3
EBM Enable Bus Mastering 2

EMS Enable Memory Space 1

4-4 Registers

This bit controls the ability of the LSI53C825A to act as
a master on the PCI bus. A value of zero disables the
device from generating PCI bus master accesses. A
value of one allows the LSI53825A to behave as a bus
master. The LSI53C825A must be a bus master in order
to fetch SCRIPTS instructions and transfer data.

This bit controls the ability of the LSI53C825A to respond
to Memory Space accesses. A value of zero disables the
device response. A value of one allows the LSI53C825A
to respond to Memory Space accesses at the address
specified by Base Address One (Memory).

EIS Enable I/O Space 0

This bit controls the LSI53C825A response to I/O space
accesses. A value of zero disables the response. A value
of one allows the LSI53C825A to respond to I/O space
accesses at the address specified in Base Address One

(Memory).

Register: 0x06

Status
Read/Write

15 14 13 12 11 10 9 8 7 5 4 3 0

DPE SSE RMA RTA R DT[1:0] DPR RNC R

000000000 0 010 0 0 0

The Status register is used to record status information for PCI bus
related events.

In the LSI53C825A, bits 0 through 4 are reserved and bits 5, 6, 7, and
11 are not implemented by the LSI53C825A.

Reads to this register behave normally. Writes are slightly different in that
bits can be cleared, but not set. A bit is reset whenever the register is
written, and the data in the corresponding bit location is a one. For
instance, to clear bit 15 and not affect any other bits, write the value
0x8000 to the register.

DPE Detected Parity Error (from Slave) 15

This bit is set by the LSI53C825A whenever it detects a
data parity error, even if parity error handling is disabled.

SSE Signaled System Error 14

This bit is set whenever a device asserts the SERR/
signal.

RMA Received Master Abort (from Master) 13

A master device should set this bit whenever its
transaction (except for Special Cycle) is terminated with
master abort.

RTA Received Target Abort (from Master) 12

A master device should set this bit whenever its
transaction is terminated with a target abort.

Configuration Registers 4-5

R Reserved 11
DT[1:0] DEVSEL/ Timing [10:9]

These bits encode the timing of DEVSEL/. These are
encoded as:

0b00 Fast
0b01 Medium
0b10 Slow
0b11 Reserved

These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. In the LSI53C825A, 0b01 is supported.

DPR Data Parity Reported 8

This bit is set when the following three conditions are
met:

• The bus agent asserted PERR/ itself or observed

PERR/ asserted and;

• The agent setting this bit acted as the bus master for

the operation in which the error occurred and;

• The Parity Error Response bit in the Command

register is set.

R Reserved [7:5]
NC New Capabilities (NC) 4

R Reserved [3:0]

4-6 Registers

This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is Read Only,
and applies to the LSI53C825AE only.

Register: 0x08

Revision ID
Read Only

7 0

RID

LSI53C825AE

00100110

LSI53C825A

00010100

RID Revision ID [7:0]

This register specifies a device specific revision identifier.
For revision A of the LSI53C825AE, the value of this
register is 0x26.

Register: 0x09

Class Code
Read Only

23 0

CC[23:0]

000011110000000000000000

CC[23:0] Class Code [23:0]

This register is used to identify the generic function of the
device. The upper byte of this register is a base class
code, the middle byte is a subclass code, and the lower
byte identifies a specific register-level programming
interface. The value of this register is 0x010000, which
identifies a SCSI controller.

Configuration Registers 4-7

Register: 0x0C

Cache Line Size
Read/Write

7 0

CLS

00000000

CLS Cache Line Size [7:0]

This register specifies the system cache line size in units
of 32-bit words. Cache mode is enabled and disabled by
the Cache Line Size Enable (CLSE) bit, bit 7 in the DMA

Control (DCNTL) register. Setting this bit causes the

LSI53C825A to align to cache line boundaries before
allowing any bursting, except during Memory Moves in
which the read and write addresses are not aligned to a
burst size boundary. For more information on this register,
see Section 2.1.3.1, “Support for PCI Cache Line Size

Register.”

Register: 0x0D

Latency Timer
Read/Write

7 0

00000000

LT[7:0] Latency Timer [7:0]

4-8 Registers

LT

The Latency Timer register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. The LSI53C825A supports this timer. All eight
bits are writable, allowing latency values of 0–255 PCI
clocks. Use the following equation to calculate an
optimum latency value for the LSI53C825A:

Latency = 2 + (Burst Size * (typical wait states +1)).
Values greater than optimum are also acceptable.

Register: 0x0E

Header Type
Read Only

7 0

HT

00000000

HT[7:0] Header Type [7:0]

This register identifies the layout of bytes 0x10 through
0x3F in configuration space and also whether or not the
device contains multiple functions. The value of this
register is 0x00.

Register: 0x10

Base Address Zero (I/O)
Read/Write

31 0

BARZ

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1

BARZ Base Address Register Zero (I/O) [31:0]

This 32-bit register has bit zero hardwired to one. Bit 1 is
reserved and must return a zero on all reads, and the
other bits are used to map the device into I/O space.

Register: 0x14

Base Address One (Memory)
Read/Write

31 0

BARO

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0

BARO Base Address Register One [31:0]

This register has bit 0 hardwired to zero. For detailed
information on the operation of this register, refer to the
PCI Specification.

Configuration Registers 4-9

Register: 0x18

RAM Base Address Two (Memory) SCRIPTS RAM
Read/Write

31 0

BART

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0

BART Base Address Register Two [31:0]

This register holds the memory base address of the
4 Kbyte internal RAM. The user can read this register
through the Scratch Register B (SCRATCHB) register in
the operating register set when bit 3 of the Chip Test Two

(CTEST2) register is set.

Register: 0x2C

Subsystem Vendor ID (SSVID)
Read Only

15 0

SSVID

LSI53C825AE

1111000000000000

LSI53C825A

0000000000000000

SSVID Subsystem Vendor ID [15:0]

4-10 Registers

This register supports subsystem identification, which
has a default value of 0x1000 in the LSI53C825AE
(Section 3.2, “MAD Bus Programming”). To write to this
register, connect a 4.7 kΩ resistor between the MAD[6]
pin and VSSand leave the MAD[4] pin unconnected. The
MAD[6] and MAD[4] pins have internal pull-up resistors
and are sensed shortly after the deassertion of chip
reset. In revisions before Rev. G of the LSI53C825A, the
MAD[6] and MAD[4] pins do not support the SSID and
SSVID configurations, and only values of 0x0000 can be
found in the Subsystem Data register.

Register: 0x2E

Subsystem ID (SSID)
Read Only

15 0

SSID

LSI53C825AE

1111000000000000

LSI53C825A

0000000000000000

SSID Subsystem ID [15:0]

This register supports subsystem identification, which
has a default value of 0x1000 in the LSI53C825AE
(Section 3.2, “MAD Bus Programming”). To write to this
register, connect a 4.7 kΩ resistor between the MAD[6]
pin and VSSand leave the MAD[4] pin unconnected. The
MAD[6] and MAD[4] pins have internal pull-up resistors
and are sensed shortly after the deassertion of chip
reset. In revisions before Revision G of the LSI53C825A,
the MAD[6] and MAD[4] pins do not support the SSID
and SSVID configurations, and only valuesof 0x0000 can
be found in the Subsystem Data register.

Register: 0x30

Expansion ROM Base Address
Read/Write

31 0

ERBA

00000000000000000000000000000000

ERBA Expansion ROM Base Address [31:0]

This four-byte register handles the base address and size
information for expansion ROM. It functions exactly like
the Base Address Zero (I/O) and Base Address One

(Memory) registers, except that the encoding of the bits

is different. The upper 21 bits correspond to the upper
21 bits of the expansion ROM base address.

Configuration Registers 4-11

The Expansion ROM Enable bit, bit 0, is the only bit
defined in this register. This bit is used to control whether
or not the device accepts accesses to its expansion
ROM. When the bit is set, address decoding is enabled,
and a device can be used with or without an expansion
ROM depending on the system configuration. To access
the external memory interface, the Memory Space bit in
the Command register must also be set.

The host system detects the size of the external memory
by first writing the Expansion ROM Base Address register
with all ones and then reading back the register. The
LSI53C825A will respond with zeros in all don’t care
locations. The ones in the remaining bits represent the
binary version of the external memory size. For example,
to indicate an external memory size of 32 Kbytes, this
register,when written with ones and read back, will return
ones in the upper 17 bits.

Register: 0x34

Capability Pointer
Read Only

7 0

CP

01000000

CP Capabilities Pointer [7:0]

4-12 Registers

This register provides an offset into the function’s PCI
Configuration Space for the location of the first item in the
capabilities linked list. Only the LSI53C825AE sets this
register to 0x40. The capability pointer replaces the
General Purpose Pin Control register in earlier revisions
of the LSI53C825A.