Avago Technologies LSI53C810AE User Manual

Addendum to the SYM53C810A
Data Manual Version 2.0

December, 1997

This addendum contains new and changed information for the SYM53C810A Data Manual
Version 2.0, published in August 1996. The information will be added to the next version of the
manual. The changes are listed in the order in which their appropriate chapters appear in the data
manual. The Power Management features of the SYM53C810AE enable it to comply with
Microsoft’s PC 97 Hardware Design Guide. This addendum applies to both devices,
SYM53C810A and SYM53C810AE, except where noted.

Chapter 2, Functional Description

Figure 2-4, “Determining the Synchronous Transfer Rate,” was inadvertently omitted. See the
reference to this figure under the main heading “Synchronous Operation.” The
below.

drawing appears

SCF2 SCF1 SCF0 SCF

Divisor

001 1
0 1 0 1.5
011 2
100 3
000 3

SCF

Divider

SCLK

CCF

Divider

CF2 CCF1 CCF0 SCSI Clock

(MHz)

0 0 0 50.1-66.00
0 0 1 16.67-25.00
0 1 0 25.01-37.50
0 1 1 37.51-50.00
1 0 0 50.01-66.00

This point
must not

exceed 50
MHz

TP2 TP1 TP0 XFERP

Divisor

000 4
001 5
010 6
011 7
100 8
101 9
11010
11111

Divide by 4

Synchronous

Divider

Asynchronous

SCSI Logic

Receive
Clock

Send Clock
(to SCSI bus)

Example:

SCLK= 40 MHz, SCF = 1(/1), XFERP = 0(/4),
CCF = 3(37.51-50.00MHz)
Synchronous send rate = (SCLK/SCF)/XFERP =
(40/1)/4=10MB/s
Synchronous receive rate = (SCLK/SCF)/4 =
(40/1)/4=10MB/s

Figure 2-4: Determining the Synchronous Transfer
Rate

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Achieving Optimal SCSI Send Rates

In this section on page 2-11, the example at the end of the paragraph is incomplete. The TP and
SCF bit settings given in the example will achieve a synchronous send rate of 5 MB/s.

Power Management

The SYM53C810AE complies with the PCI Bus Power Management Interface Specification,
Revision 1.0. The PCI Function Power States are defined in that specification: D0, D1, D2, and
D3. D0 and D3 are required by specification and D1 and D2 are optional. D0 is the maximum
powered state, and D3 is the minimum powered state. Power state D3 is further categorized as
D3hot or D3cold. A function that is powered off is said to be in the D3cold power state.

The power states for the SCSI function are independently controlled through two power state bits
that are located in the PCI Configuration Space Register 44h. The bits are encoded as: 00b –
power state D0, 01b - reserved, 10b - reserved, and 11b - power state D3.

The power states--D0 and D3--are described below. Power states D1 and D2 are not implemented
for this device.

Power State D0

Power state D0 is the maximum power state and is the power-up default state for each function.

Power State D3

Power state D3 is the minimum power state, which includes subsettings called D3hot and
D3cold. The devices are considered to be in power state D3cold when power is removed from
them. D3cold can transition to D0 by applying Vcc and resetting the device. D3hot allows the
device to transition to D0 via software. To obtain power reduction in D3hot, the SCSI clock and
the SCSI clock doubler Phase Lock Loop (PLL) are disabled. Furthermore, soft reset is
continually asserted while in power state D3hot, which clears all pending interrupts and tristates
the SCSI bus. In addition, the function’s PCI command register is cleared.

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Chapter 3, PCI Functional Description

Configuration Registers

Figure 3-1

31 16 15 0

Note:

: PCI Configuration Register Map

Device ID Vendor ID = 1000h 00h

Status Command 04h

Class Code Rev ID 08h

Not Supported Header Type Latency Timer Cache Line Size 0Ch

Base Address Zero (I/O), SCSI Operating Registers 10h

Base Address One (Memory), SCSI Operating Registers 14h

Base Address Two (Memory) SCRIPTS RAM 18h

Not Supported 1Ch
Not Supported 20h
Not Supported 24h

Reserved 28h

Subsystem ID Subsystem Vendor ID 2Ch

Expansion ROM Base Address 30h

Reserved Capabilities Pointer 34h

Reserved 38h

Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3Ch

Power Management Capabilities Next Item Pointer Capability ID 40h

Data Bridge Support Ext Pwr. Mgmt. Control/Status Register 44h

Shaded areas are reserved or represent the SYM53C810AE capabilities.

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