Avago Technologies LSI53C180 User Manual
TECHNICAL
MANUAL
LSI53C180
Ultra160 SCSI
Bus Expander
Version 1.3
June 2001
®
S14041.C
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000118-03, Fourth Edition (June 2001)
This document describes the LSI Logic Corporation LSI53C180 Ultra160 SCSI
Bus Expander and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 2000-2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, LVD Link, and TolerANT are trademarks or registered
trademarks of LSI Logic Corporation. All other brand and product names may be
trademarks of their respective companies.
MH
ii
Audience
Preface
This manual provides a description of the LSI53C180 Ultra160 SCSI Bus
Expander chip that supports all combinations of Single-Ended and Low
Voltage Differential SCSI bus conversions.
Currently the LSI53C140 is offered in a 192-BGA package so that
customers who are designing Ultra2 can easily upgrade to Ultra160.
Refer to System Engineering Note S11006 for design considerations
using the LSI53C140 and LSI53C180.
This manual assumes some prior knowledge of current and proposed
SCSI standards. For background information, please contact:
ANSI
11 West 42nd Street
New York, NY 10036
(212) 642-4900
Ask for document number X3.131-199X (SCSI-2)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
(800) 854-7179 or (303) 397-7956 (outside U.S.)
FAX (303) 397-2740
Ask for document number X3.131-1994 (SCSI-2) or
X3.253 (SCSI Parallel Interface-3 (SPI-3))
Preface iii
Organization
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
(408) 867-6642
Document names: SCSI Bench Reference, SCSI Encyclopedia,
SCSI Tutor
Prentice Hall
113 Sylvan Avenue
Englewood Cliffs, NJ 07632
(800) 947-7700
Ask for document number ISBN 0-13-796855-8,
SCSI: Understanding the Small Computer System Interface
LSI Logic World Wide Web Home Page
www.lsil.com
This document has the following chapters and appendixes:
• Chapter 1, Introduction, contains the general information about the
LSI53C180 product.
• Chapter 2, Functional Descriptions, describes the main functional
areas of the chip in more detail, including the interfaces to the SCSI
bus and external memory.
• Chapter 3, Specifications, contains the pin diagram, signal
descriptions, electrical characteristics, AC timing diagrams, and
mechanical drawing of the LSI53C180.
• Appendix A, Wiring Diagrams, contains wiring diagrams that show
typical LSI53C180 usage.
• Appendix B, Glossary, contains commonly used terms and their
definitions.
iv Preface
Revision Record
Date Version Remarks
2/00 1.0 Version 1.0
11/00 1.1 All product names changed from SYM to LSI.
4/01 1.2 Changes in Chapter 2 to how Warm Swap Enable is
6/01 1.3 Changes to wiring diagrams in Appendix A.
designated. Changes in Chapter 3 to DC
Characteristics.
Preface v
vi Preface
Contents
Chapter 1 Introduction
1.1 General Description 1-1
1.1.1 Applications 1-3
1.1.2 Features 1-5
1.1.3 Specifications 1-6
1.2 Ultra160 SCSI 1-6
1.2.1 Double Transition (DT) Clocking 1-6
1.2.2 Cyclic Redundancy Check (CRC) 1-6
1.2.3 Domain Validation 1-7
1.2.4 Parallel Protocol Request 1-7
1.2.5 Benefits of LVD Link 1-7
Chapter 2 Functional Descriptions
2.1 Interface Signal Descriptions 2-1
2.1.1 SCSI A Side and B Side Control Blocks 2-2
2.1.2 Retiming Logic 2-4
2.1.3 Precision Delay Control 2-4
2.1.4 State Machine Control 2-4
2.1.5 DIFFSENS Receiver 2-5
2.1.6 Dynamic Transmission Mode Changes 2-5
2.1.7 SCSI Signal Descriptions 2-5
2.1.8 Control Signals 2-11
2.1.9 SCSI Termination 2-13
2.2 Internal Control Descriptions 2-14
2.2.1 Self-Calibration 2-14
2.2.2 Delay Line Structures 2-14
2.2.3 Busy Filters 2-15
Contents vii
Chapter 3 Specifications
3.1 Signal Descriptions 3-1
3.2 Electrical Characteristics 3-7
3.2.1 DC Characteristics 3-8
3.2.2 TolerANT Technology Electrical Characteristics 3-12
3.2.3 AC Characteristics 3-16
3.2.4 SCSI Interface Timing 3-16
3.3 Mechanical Drawings 3-19
3.3.1 LSI53C180 192-Pin BGA Mechanical Drawing 3-20
Appendix A Wiring Diagrams
A.1 LSI53C180 Wiring Diagrams A-1
Appendix B Glossary
Index
Customer Feedback
Figures
1.1 LSI53C180 SCSI Bus Modes 1-2
1.2 LSI53C180 Server Clustering 1-3
1.3 LSI53C180 SCSI Bus Device 1-4
2.1 LSI53C180 Block Diagram 2-2
2.2 LSI53C180 Signal Grouping 2-6
3.1 Left Half of LSI53C180 192-Pin BGA Top View 3-2
3.2 Right Half of LSI53C180 192-Pin BGA Top View 3-3
3.3 LSI53C180 Functional Signal Grouping 3-4
3.4 LVD Driver 3-9
3.5 LVD Receiver 3-10
3.6 External Reset Circuit 3-12
3.7 Rise and Fall Time Test Conditions 3-14
3.8 SCSI Input Filtering 3-14
3.9 Hysteresis of SCSI Receivers 3-14
3.10 Input Current as a Function of Input Voltage 3-15
viii Contents
Tables
3.11 Output Current as a Function of Output Voltage 3-15
3.12 Clock Timing 3-16
3.13 Input/Output Timing - Single Transition 3-17
3.14 Input/Output Timing - Double Transition 3-18
3.15 192-Pin PBGA (IJ, I2) Mechanical Drawing 3-20
A.1 LSI53C180 Wiring Diagram 1 of 4 A-2
A.2 LSI53C180 Wiring Diagram 2 of 4 A-3
A.3 LSI53C180 Wiring Diagram 3 of 4 A-4
A.4 LSI53C180 Wiring Diagram 4 of 4 A-5
1.1 Types of Operation 1-2
1.2 SCSI Bus Distance Requirements 1-4
1.3 Transmission Mode Distance Requirements 1-4
2.1 DIFFSENS Voltage Levels 2-5
2.2 Mode Sense Control Voltage Levels 2-11
2.3 RESET/ Control Signal Polarity 2-12
2.4 WS_ENABLE Signal Polarity 2-12
2.5 XFER_ACTIVE Signal Polarity 2-13
3.1 SCSI A Side Interface Pins 3-5
3.2 SCSI B Side Interface Pins 3-6
3.3 Chip Interface Control Pins 3-6
3.4 Power and Ground Pins 3-7
3.5 Absolute Maximum Stress Ratings 3-8
3.6 Operating Conditions 3-8
3.7 LVD Driver SCSI Signals—B_SD[15:0]±, B_SDP[1:0]±,
B_SCD±, B_SIO±, B_SMSG±, B_SREQ±, B_SACK±,
B_SBSY±, B_SATN±, B_SSEL±, B_SRST± 3-9
3.8 LVD Receiver SCSI Signals—B_SD[15:0]±, B_SDP[1:0]±,
B_SCD±, B_SIO±, B_SMSG±, B_SREQ±, B_SACK±,
B_SBSY±, B_SATN±, B_SSEL±, B_SRST± 3-9
3.9 DIFFSENS SCSI Signal 3-10
3.10 Input Capacitance 3-10
3.11 Bidirectional SCSI Signals—A_SD[15:0]/, A_SDP[1:0]/,
A_SREQ/, A_SACK/, B_SD[15:0]±, B_SDP[1:0]±,
B_SREQ±, B_SACK± 3-11
Contents ix
3.12 Bidirectional SCSI Signals—A_SCD/, A_SIO/,
A_SMSG/, A_SBSY/, A_SATN/, A_SSEL/, A_SRST/,
B_SCD±, B_SIO±, B_SMSG±, B_SBSY±, B_SATN±,
B_SSEL±, B_SRST± 3-11
3.13 Input Control Signals—CLOCK, RESET/, WS_ENABLE 3-11
3.14 Output Control Signals—BSY_LED, XFER_ACTIVE 3-12
3.15 TolerANT Technology Electrical Characteristics 3-12
3.16 Clock Timing 3-16
3.17 Input Timing - Single Transition 3-16
3.18 Output Timing - Single Transition 3-17
3.19 Input Timing - Double Transition 3-17
3.20 Output Timing - Double Transition 3-18
x Contents
Chapter 1
Introduction
This chapter describes the LSI53C180 Ultra160 SCSI Bus Expander and
its applications. It includes these sections:
• Section 1.1, “General Description,” page 1-1
• Section 1.2, “Ultra160 SCSI,” page 1-6
1.1 General Description
The LSI53C180 Ultra160 SCSI Bus Expander is a single chip solution
allowing the extension of SCSI device connectivity and/or cable length
limits. A SCSI bus expander couples bus segments together without any
impact to the SCSI protocol, software, or firmware. The LSI53C180
Ultra160 SCSI Bus Expander connects Single-Ended (SE) Ultra and Low
Voltage Differential (LVD) Ultra160 peripherals together in any
combination. The LSI53C180 does not support High Voltage Differential
(HVD) mode.
The LSI53C180 is capable of supporting any combination of SE or LVD
bus mode on either the A or B Side port. This provides the system
designer with maximum flexibility in designing SCSI backplanes to
accommodate any SCSI bus mode. The LSI53C180 has independent
RBIAS pins allowing margining for each bus. A 10 kΩ pull-up resistor on
RBIAS is required to provide the correct LVD levels.
LSI53C180 Ultra3 SCSI Bus Expander 1-1
Figure 1.1 LSI53C180 SCSI Bus Modes
A Side B Side
LVD
SE
LSI53C180
SCSI Expander
192 PBGA
LVD
SE
Figure 1.1 shows the two SCSI bus modes available on the A or B Side.
LVD Link™ transceivers provide the multimode LVD or SE capability. The
LSI53C180 operates as both an expander and converter. In both SCSI
Bus Expander and Converter modes, cable segments are isolated from
each other. This feature maintains the signal integrity of each cable
segment.
Table 1.1 shows the types of operational modes for the LSI53C180.
Table 1.1 Types of Operation
Signal Type Speed
LVD to LVD Ultra160
SE to SE Ultra
LVD to SE Ultra
SE to LVD Ultra
The LSI53C180 provides additional control capability through the pin
level isolation mode (Warm Swap Enable). This feature permits logical
disconnection of both the A Side bus and the B Side bus without
disrupting SCSI transfers currently in progress. For example, devices on
the logically disconnected B Side can be swapped out while the A Side
bus remains active.
The LSI53C180 is based on previous bus expander technology, which
includes signal filtering along with retiming to maintain skew budgets.
The LSI53C180 is independent of software.
1-2 Introduction
1.1.1 Applications
• Server clustering environments
• Expanders creating distinct SCSI cable segments that are isolated
Figure 1.2 LSI53C180 Server Clustering
from each other
Primary Server
Segment A
SCSI Bus
Expander
SCSI Bus
Expander
Segment C
Shared Disk Subsystem
Segment B
Secondary Server
Figure 1.2 demonstrates how SCSI bus expanders are used to couple
bus segments together without any impact on the SCSI protocol or
software. Configurations that use the LSI53C180 SCSI Bus Expander in
the Ultra160 mode (LVD to LVD) allow the system designer to take
advantage of the inherent cable distance, device connectivity, data
reliability, and increased transfer rate benefits of LVD signaling with
Ultra160 SCSI peripherals.
In the Figure 1.2 example, two LSI53C180 expanders are used to
configure three segments. This configuration allows segment A to be
treated as a point-to-point segment. Segments B and C are treated as
load segments with at least 8 inches between every node. Table 1.2
shows the various distance requirements for each SCSI bus mode.
General Description 1-3
Table 1.2 SCSI Bus Distance Requirements
Segment Mode Length Limit
A LVD (Ultra160) 25 meters
SE (Ultra) 3 meters
1
B LVD (Ultra160) 12 meters
SE (Ultra) 1.5 meters
C LVD (Ultra160) 12 meters
SE (Ultra) 1.5 meters
1. The length may be more, possibly 6 meters, as no devices are
attached to it.
In the second example, Figure 1.3, the LSI53C180 is cascaded to
achieve four distinct SCSI segments. Segments A and D can be treated
as point-to-point segments. Segments B and C are treated as load
segments with at least 8-inch spacing between every node.
Figure 1.3 LSI53C180 SCSI Bus Device
Segment A Segment B Segment C
Primary
Server
Table 1.3 Transmission Mode Distance Requirements
Segment Mode Length Limit
A, D LVD (Ultra160) 25 meters
B, C LVD (Ultra160) 12 meters
1-4 Introduction
SCSI Bus
Expander
Shared Disk
Subsystem
SCSI Bus
Expander
Shared Disk
Subsystem
SCSI Bus
Expander
SE (Ultra) 1.5 meters
SE (Ultra) 1.5 meters
Segment D
Secondary
Server
1.1.2 Features
• A flexible SCSI bus expander that supports any combination of LVD
or SE transceivers
• Creates distinct SCSI bus segments that are isolated from each
other
• Integrated LVD Link transceivers for direct attachment to either LVD
or SE bus segments
• Operates as a SCSI Bus Expander
– LVD to LVD (Ultra160 SCSI)
– SE to SE (Ultra SCSI)
• Operates as a SCSI Bus Converter
– LVD to SE (Ultra SCSI)
– SE to LVD (Ultra SCSI)
• Targets and initiators may be located on either the A or B Side of the
device
• Accepts any asynchronous or synchronous transfer speed up to
Ultra160 SCSI (for LVD to LVD mode only)
• Supports dynamic addition/removal of SCSI bus segments using the
isolation mode
• Does not consume a SCSI ID
• Propagates the RESET/ signal from one side to the other regardless
of the SCSI bus state
• Notifies initiator(s) of changes in transmission mode (SE/LVD) on A
or B Side segments by using the SCSI bus RESET/
• SCSI Busy LED driver for activity indicator
• Up to four LSI53C180s may be cascaded
• Does not require software
• Supports Double Transition (DT) clocking
• Supports Cyclic Redundancy Check (CRC) in DT data phases
• Supports Domain Validation
General Description 1-5
1.1.3 Specifications
• 40 MHz Input Clock
• 192-pin Plastic Ball Grid Array package (PBGA). This package is a
drop in replacement for the LSI53C140 when the design uses the
LSI53C180 pinout.
• Compliant with the SCSI Parallel Interface-3 (SPI-3)
• Compliant with SCSI Enhanced Parallel Interface (EPI) Specifications
1.2 Ultra160 SCSI
The LSI53C180 SCSI Bus Expander supports Ultra160 SCSI. This
interface is an extension of the SCSI-3 standards that expands the
bandwidth of the SCSI bus to allow faster synchronous data transfers,
up to 160 Mbytes/s. Ultra160 SCSI provides a doubling of the data rate
over the Ultra2 SCSI interface. All new speeds after Ultra2 are wide.
1.2.1 Double Transition (DT) Clocking
Ultra160 provides DT clocking for LVD transfers where clocking is
defined on the rising and falling edges of the clock. The latching of data
on both the assertion edge and the negation edge of the REQ/ACK
signal represents DT data phases. DT data phase encompasses both the
DT Data In and the DT Data Out phase. DT data phases use only 16bit, synchronous transfers.
Information unit and data group transfers use DT data phases to transfer
data. Information unit transferstransmitallnexus, task management, task
attribute, command, data, and protection. Data group transfers transmit
all data and protection. The number of bytes transferred for an
information unit or data group is always a multiple of four. Refer to the
SCSI Parallel Interface-3 (SPI-3) for more detailed information about
DT clocking.
1.2.2 Cyclic Redundancy Check (CRC)
Ultra160 supports CRC, which represents error checking code to detect
the validity of data. CRC increases the reliability of data transfers since
four bytes of code are transferred along with data. All single bit errors,
1-6 Introduction
two bits in error, or other error types within a single 32-bit range are
detected. Refer to SPI-3 to see how CRC generation and transmission
occur during data transfers.
1.2.3 Domain Validation
Domain Validation is a procedure that allows a host computer and target
SCSI peripheral to negotiate and find the optimal transfer speed. This
procedure improves overall reliability of the system by ensuring integrity
of the data transferred.
1.2.4 Parallel Protocol Request
Parallel Protocol Request (PPR) messages negotiate a synchronous
data transfer agreement, a wide data transfer agreement, and set the
protocol options between two SCSI devices. This message exchange
negotiates limits about data transmission and establishes an agreement
between the two SCSI devices. This agreement applies to ST Data In,
ST Data Out, DT Data In, and DT Data Out phases.
For example, a SCSI device could initiate a PPR message whenever it
is appropriate to negotiate a data transfer agreement. If the target device
is capable of supporting any of the PPR options, it will respond with a
PPR message. If not, it responds with a Message Reject message and
the two SCSI devices use either SDTR or WDTR messages to negotiate
an agreement.
1.2.5 Benefits of LVD Link
The LSI53C180 supports LVD technology for SCSI, a signaling
technology that increases the reliability of SCSI data transfers over
longer distances than those supported by SE SCSI technology. The low
current output of LVD allows the I/O transceivers to be integrated directly
onto the chip. LVD provides the reliability of HVD SCSI technology
without the added cost of external differential transceivers. LVD allows a
longer SCSI cable and more devices on the bus. LVD provides a
long-term migration path to even faster SCSI transfer rates without
compromising signal integrity, cable length, or connectivity.
For backward compatibility to existing SE devices, the LSI53C180
features multimode LVD Link transceivers that can switch between LVD
and SE modes.
Ultra160 SCSI 1-7
Some features of integrated LVD Link multimode transceivers are:
• Supports SE or LVD technology
• Allows greater device connectivity and longer cable length
• LVD Link transceivers save the cost of external differential
transceivers
• Supports a long-term performance migration path
1-8 Introduction
Chapter 2
Functional
Descriptions
This chapter describes all signals, their groupings, and their functions. It
includes these topics:
• Section 2.1, “Interface Signal Descriptions,” page 2-1
• Section 2.2, “Internal Control Descriptions,” page 2-14
2.1 Interface Signal Descriptions
The LSI53C180 has no programmable registers, and therefore, no
software requirements. SCSI control signals control all LSI53C180
functions. Figure 2.1 shows a block diagram of the LSI53C180 device,
which is divided into these specific areas:
• A Side SCSI Control Block
– LVD and SE Drivers and Receivers
• B Side SCSI Control Block
– LVD and SE Drivers and Receivers
• Retiming Logic
• Precision Delay Control
• State Machine Control
LSI53C180 Ultra3 SCSI Bus Expander 2-1
Figure 2.1 LSI53C180 Block Diagram
Control
Signals
LVD, Single-ended,
Wide Ultra SCSI Bus
(A Side)
ansceivers
VD Link Tr
L
ol Block
SCSI Contr
Retiming
Logic
k
ol Bloc
LVD Link Transceivers
SCSI Contr
LVD, Single-ended
Wide Ultra SCSI Bus
(B Side)
Precision
er
A_DIFFSENS B_DIFFSENS
VD
L
Control
Receiv
DIFFSENS
Delay
40 MHz Clock Input
In its simplest form, the LSI53C180 passes data and parity from a source
bus to a load bus. The side asserting, deasserting, or releasing the SCSI
signals is the source side. The model of the LSI53C180 represents
pieces of wire that allow corresponding SCSI signals to flow from one
side to the other side. The LSI53C180 monitors arbitration and selection
by devices on the bus so it can enable the proper drivers to pass the
signals along. In addition, the LSI53C180 does signal retiming to
maintain the signal skew budget from the source bus to the load bus.
2.1.1 SCSI A Side and B Side Control Blocks
The SCSI A Side pins are connected internally to the corresponding
SCSI B Side pins, forming bidirectional connections to the SCSI bus.
In the LVD/LVD mode, the SCSI A Side and B Side control blocks
connect to both targets and initiators and accept any asynchronous or
synchronous data transfer rates up to the 160 Mbytes/s rate of Wide
Ultra160 SCSI. TolerANT®and LVD Link technologies are part of both
the A Side and B Side control blocks.
State
Machine
Control
LVD
Receiver
DIFFSENS
2.1.1.1 LSI53C180 Requirements for Synchronous Negotiation
The LSI53C180 builds a table of information regarding devices on the
bus in on-chip RAM. The PPR, SDTR, and WDTR information for each
2-2 Functional Descriptions
device is taken from the MSG bytes during negotiation. For all devices
in the configuration to communicate accurately through the LSI53C180
at Ultra160 (Fast-80) rates, it is necessary for a complete synchronous
negotiation to take place between the initiator and target(s) prior to any
data transfer. On a 16-bit bus, the LSI53C180 at Ultra160 approaches
rates of 160 Mbytes/s. The LSI53C180 defaults to Fast-20 rates when a
valid negotiation between the initiator and target has not occurred.
2.1.1.2 TolerANT Technology
In SE mode, the LSI53C180 features TolerANT technology, which
includes active negation on the SCSI drivers and input signal filtering on
the SCSI receivers. Active negation causes the SCSI Request,
Acknowledge, Data, and Parity signals to be actively driven HIGH rather
than passively pulled up by terminators.
TolerANT receiver technology improves data integrity in unreliable
cabling environments, where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions without the long signal delays associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations.
The benefits of TolerANT technology include increased immunity to noise
on the deasserting signal edge, better performance due to balanced duty
cycles, and improved SCSI transfer rates. In addition, TolerANT SCSI
devices prevent glitches on the SCSI bus at power-up or power-down, so
other devices on the bus are also protected from data corruption.
2.1.1.3 LVD Link Technology
To support greater device connectivity and longer SCSI cables, the
LSI53C180 features LVD Link technology, the LSI Logic implementation
of multimode LVD SCSI. LVD Link transceivers provide the inherent
reliability of differential SCSI, and a long-term migration path of faster
SCSI transfer rates.
LVD Link technology is based on current drive. Its low output current
reduces the power needed to drive the SCSI bus. Therefore, the I/O
drivers can be integrated directly onto the chip. This reduces the cost and
complexity compared to traditional (high power) differential designs.
Interface Signal Descriptions 2-3
LVD Link lowers the amplitude of noise reflections and allows higher
transmission frequencies.
The LVD Link transceivers in Side A and Side B operate in the LVD or
SE modes. The LSI53C180 automatically detects the type of signal
connected, based on the voltages detected by A_DIFFSENS and
B_DIFFSENS.
2.1.2 Retiming Logic
The SCSI signals, as they propagate from one side of the LSI53C180 to
the other side, are processed by logic circuits that retime the bus signals,
as needed, to guarantee or improve the required SCSI timings. The
retiming logic is governed by the State Machine Controls that keep track
of SCSI phases, the location of initiator and target devices, and various
timing functions. In addition, the retiming logic contains numerous delay
elements that are periodically calibrated by the Precision Delay Control
block in order to guarantee specified timing such as output pulse widths,
setup and hold times, and other elements.
When a synchronous negotiation takes place between devices, a nexus
is formed, and the corresponding information on that nexus is stored in
the on-chip RAM. This information remains in place until a chip reset,
power down, or renegotiation occurs. This enables the chip to make
more accurate retiming adjustments.
2.1.3 Precision Delay Control
The Precision Delay Control block provides calibration information to the
precision delay elements in the Retiming Logic block. This calibration
information provides precise timing as signals propagate through the
device. As the LSI53C180 voltage and temperature vary over time, the
Precision Delay Control block periodically updates the delay settings in
the Retiming Logic. The purpose of these updates is to maintain constant
and precise control over bus timing.
2.1.4 State Machine Control
The State Machine Control tracks the SCSI bus phase protocol and other
internal operating conditions. This block provides signals to the Retiming
Logic that identify how to properly handle SCSI bus signal retiming based
on SCSI protocol.
2-4 Functional Descriptions
2.1.5 DIFFSENS Receiver
The LSI53C180 contains LVD DIFFSENS receivers that detect the
voltage level on the A Side or B Side DIFFSENS lines to inform the
LSI53C180 of the transmission mode being used by the SCSI buses. A
device does not change its present signal driver or receiver mode based
on the DIFFSENS voltage levels unless a new mode is sensed
continuously for at least 100 ms.
Transmission mode detection for SE or LVD is accomplished through the
use of the DIFFSENS lines. Table 2.1 shows the voltages on the
DIFFSENS lines and modes they will cause.
Table 2.1 DIFFSENS Voltage Levels
Voltage Mode
−0.35 to +0.5 SE
+0.7 to +1.9 LVD
2.1.6 Dynamic Transmission Mode Changes
Any dynamic mode change (SE/LVD) on a bus segment is considered to
be a significant event that requires the initiator to determine whether the
mode change meets the requirements for that bus segment.
The LSI53C180 supports dynamic transmission mode changes by
notifying the initiator(s) of changes in transmission mode (SE/LVD) on A
or B Side segments by using the SCSI bus RESET. The DIFFSENS line
detects a valid mode switch on the bus segments. After the DIFFSENS
state is present for 100 ms, the LSI53C180 generates a SCSI reset on
the opposite bus from the one that the transmission mode change
occurred on. This reset informs any initiators residing on the opposite
segment about the change in the transmission mode. The initiator(s) then
renegotiates synchronous transfer rates with each device on that segment.
2.1.7 SCSI Signal Descriptions
For a description of a specific signal, see Section 3.1, “Signal
Descriptions,” in Chapter 3. For signal electrical characteristics, see
Section 3.2, “Electrical Characteristics.” For SCSI bus signal timing, see
Interface Signal Descriptions 2-5
Section 3.2.4, “SCSI Interface Timing.” Figure 2.2 shows the LSI53C180
signal grouping. A description of the signal groups follows.
Figure 2.2 LSI53C180 Signal Grouping
A Side
LVD or SE
SCSI Interface
Control Signals
2.1.7.1 Data and Parity (SD and SDP)
A_SSEL+
A_SSELA_SBSY+
A_SBSYA_SRST+
A_SRSTA_SREQ+
A_SREQA_SACK+
A_SACKA_SMSG+
A_SMSGA_SCD+
A_SCDA_SIO+
A_SIOA_SATN+
A_SATNA_SDP[1:0]+
A_SDP[1:0]A_SD[15:0]+
A_SD[15:0]-
A_DIFFSENS
A_RBIAS B_RBIAS
RESET/
WS_ENABLE
XFER_ACTIVE
CLOCK
LSI53C180
B_SSEL+
B_SSEL-
B_SBSY+
B_SBSY-
B_SRST+
B_SRST-
B_SREQ+
B_SREQB_SACK+
B_SACK-
B_SMSG+
B_SMSG-
B_SCD+
B_SCD-
B_SIO+
B_SIO-
B_SATN+
B_SATN-
B_SDP[1:0]+
B_SDP[1:0]-
B_SD[15:0]+
B_SD[15:0]-
B_DIFFSENS
BSY_LED
B Side
LVD or SE
SCSI Interface
The signals named A_SD[15:0] and A_SDP[1:0] are the data and parity
signals from the A Side, and B_SD[15:0] and B_SDP[1:0] are the data
and parity signals from the B Side of the LSI53C180. These signals are
sent and received from the LSI53C180 by using SCSI compatible drivers
and receiver logic designed into the LSI53C180 interfaces. This logic
provides the multimode LVD and SE interfaces in the chip. This logic also
provides the necessary drive, sense thresholds, and input hysteresis to
function correctly in a SCSI bus environment.
The LSI53C180 receives data and parity signals and passes them from
the source bus to the load bus and provides any necessary edge shifting
to guarantee the skew budget for the load bus. Either side of the
LSI53C180 may be the source bus or the load bus. The side that is
2-6 Functional Descriptions
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