Avago Technologies LSI53C140 User Manual

TECHNICAL

MANUAL

LSI53C140 Ultra2 SCSI Bus Expander

Version 2.1

September 2001

DB14-000087-02

This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an ofﬁcer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic ofﬁcer is prohibited.

Document DB14-000087-02, Third Edition (September 2001) This document describes the LSI Logic LSI53C140 Ultra2 SCSI Bus Expander and will remain the ofﬁcial reference source for all revisions/releases of this product until rescinded by an update.

LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.

The LSI Logic logo design, LVDlink, and TolerANT are trademarks or registered trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies.

To receive product literature, visit us at http://www.lsilogic.com. For a current list of our distributors, sales ofﬁces, and design resource

centers, view our web page located at http://www.lsilogic.com/contacts/na_salesofﬁces.html

Audience

Preface

This manual provides a description and electrical characteristics of the LSI53C140 Ultra2 SCSI Bus Expander chip that supports all combinations of Single-Ended, Low Voltage Differential, and High Voltage Differential SCSI bus conversions.

This document assumes that you have some familiarity with microprocessors and related support devices. The people who beneﬁt from this book are:

• Engineers and managers who are evaluating the processor for

possible use in a system

• Engineers who are designing the processor into a system

Organization

This document has the following chapters and appendixes:

• Chapter 1, Using the LSI53C140, contains general information

about the LSI53C140.

• Chapter 2, Functional Descriptions, describes the main functional

areas of the chip in more detail, including the interfaces to the SCSI bus and external memory.

• Chapter 3, LSI53C140 Speciﬁcations, contains the pin diagram,

BGA diagram, signal descriptions, electrical characteristics, AC timing diagrams, and mechanical drawing of the LSI53C140.

• Appendix A, Wiring Diagrams, contain wiring diagrams that show

typical LSI53C140 usage. It also contains an LSI53C140 Differential Mode wiring diagram.

LSI53C140 Ultra2 SCSI Bus Expander iii

Revision Record

• Appendix B, Board Design Considerations, describes LSI53C180

as a drop in replacement for the LSI53C140.

• Appendix C, Glossary, contains commonly used terms and their

deﬁnitions.

Version Date Description

0.5 5/98 First draft of complete technical manual.

1.0 6/99 Miscellaneous. changes/corrections for product information

2.0 4/01 All product names changed from a SYM to an LSI preﬁx.

2.1 9/01 Add differential mode wiring diagram to Appendix A per

Conventions Used in This Manual

The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Signals that are active

LOW end in an “n.”

192-ball BGA information added in Chapter 3. Refer to Appendix B for more detailed information. Updated DC electrical speciﬁcations and test conditions.

system engineer.

iv Preface

Contents

Chapter 1 Using the LSI53C140

1.1 General Description 1-1

1.2 Applications 1-3

1.2.1 Features 1-6

1.2.2 Speciﬁcations 1-7

1.3 Beneﬁts of LVDlink 1-7

Chapter 2 Functional Descriptions

2.1 Interface Signal Descriptions 2-1

2.1.1 SCSI A Side and B Side Control Blocks 2-2

2.1.2 Retiming Logic 2-4

2.1.3 Precision Delay Control 2-5

2.1.4 State Machine Control 2-5

2.1.5 DIFFSENS Receiver 2-5

2.1.6 Dynamic Transmission Mode Changes 2-6

2.2 SCSI Signal Descriptions 2-6

2.2.1 Data and Parity (SD and SDP) 2-7

2.2.2 SCSI Bus Activity LED (BSY_LED) 2-8

2.2.3 Select Control (SSEL) 2-8

2.2.4 Busy Control (SBSY) 2-9

2.2.5 Reset Control (SRST) 2-9

2.2.6 Request and Acknowledge Control (SREQ and SACK) 2-10

2.2.7 Control/Data, Input/Output, Message, and Attention Controls (SCD, SIO, SMSG, and SATN) 2-11

2.2.8 Differential Direction Control 2-11

2.2.9 A and B HVD Mode (A_HVD_MODE and B_HVD_MODE) 2-12

LSI53140 Ultra2 SCSI Bus Expander v

2.2.10 A and B Differential Sense (A_DIFFSENS and B_DIFFSENS) 2-12

2.2.11 Control Signals 2-13

2.2.12 SCSI Termination 2-15

Chapter 3 LSI53C140 Speciﬁcations

3.1 General Description 3-2

3.1.1 Signal Descriptions 3-6

3.2 Electrical Characteristics 3-11

3.2.1 DC Characteristics 3-11

3.2.2 TolerANT Technology Electrical Characteristics 3-17

3.2.3 AC Characteristics 3-21

3.2.4 SCSI Interface Timing 3-21

3.3 Mechanical Drawings 3-23

3.3.1 LSI53C140 160-Pin PQFP Mechanical Drawing 3-24

3.3.2 LSI53C140 192-Ball PBGA Mechanical Drawing 3-26

Appendix A Wiring Diagrams

Appendix B Board Design Considerations

Appendix C Glossary

Index

Customer Feedback

vi Contents

Figures

1.1 LSI53C140 SCSI Bus Modes 1-2

1.2 LSI53C140 SCSI Bus Modes 1-2

1.3 LSI53C140 Server Clustering 1-4

1.4 LSI53C140 SCSI Bus Device 1-5

2.1 LSI53C140 Block Diagram 2-2

2.2 LSI53C140 Signal Grouping 2-7

3.1 LSI53C140 160-Pin PQFP Pin Diagram 3-3

3.2 LSI53C140 192-Ball PBGA Top View 3-4

3.3 LSI53C140 Functional Signal Grouping 3-6

3.4 LVD Driver 3-13

3.5 LVD Receiver 3-13

3.6 External Reset Circuit 3-15

3.7 Rise and Fall Time Test Conditions 3-19

3.8 SCSI Input Filtering 3-19

3.9 Hysteresis of SCSI Receivers 3-19

3.10 Input Current as a Function of Input Voltage 3-20

3.11 Output Current as a Function of Output Voltage 3-20

3.12 Clock Timing 3-21

3.13 Input/Output Timing 3-22

3.14 LSI53C140 160-Pin PQFP (PF) Mechanical Drawing 3-24

3.15 192-Ball PBGA (IJ, I2) Mechanical Drawing 3-26 A.1 LSI53C140 Wiring Diagram 1 of 4 A-2 A.2 LSI53C140 Differential Wiring Diagram A-6

vii

viii

Tables

1.1 Types of Operation 1-3

1.2 SCSI Bus Distance Requirements 1-5

1.3 Transmission Mode Distance Requirements 1-6

2.1 DIFFSENS Voltage Levels 2-5

2.2 Direction Control Signal Polarity 2-12

2.3 HVD_MODE Control Signal Polarities 2-12

2.4 Mode Sense Control Voltage Levels 2-13

2.5 RESET/ Control Signal Polarity 2-13

2.6 WS_ENABLE/ Signal Polarity 2-14

2.7 XFER_ACTIVE Signal Polarity 2-14

3.1 SCSI A Side Interface Pins 3-7

3.2 SCSI B Side Interface Pins 3-8

3.3 Chip Interface Control Pins 3-9

3.4 Power and Ground Pins 3-10

3.5 Absolute Maximum Stress Ratings 3-11

3.6 Operating Conditions 3-12

3.7 LVD Driver SCSI Signals—A_SD[15:0]±, A_SDP[1:0]±, A_SCD, A_SIO±, A_SMSG±, A_SREQ±, A_SACK±, A_SBSY±, A_SATN±, A_SSEL±, A_SRST±, B_SD[15:0]±, B_SDP[1:0]±, B_SCD, B_SIO±, B_SMSG±, B_SREQ±, B_SACK±, B_SBSY±, B_SATN±, B_SSEL±, B_SRST± 3-12

3.8 LVD Receiver SCSI Signals—A_SD[15:0]±, A_SDP[1:0]±, A_SCD±, A_SIO±, A_SMSG±, A_SREQ±, A_SACK±, A_SBSY±, A_SATN±, A_SSEL±, A_SRST±, B_SD[15:0]±, B_SDP[1:0]±, B_SCD±, B_SIO±, B_SMSG±, B_SREQ±, B_SACK±, B_SBSY±, B_SATN±, B_SSEL±, B_SRST± 3-13

3.9 DIFFSENS SCSI Signal 3-14

3.10 Input Capacitance 3-14

3.11 Bidirectional SCSI Signals—A_SD[15:0]±, A_SDP[1:0]±, A_SREQ±, A_SACK±, B_SD[15:0]±, B_SDP[1:0]±, B_SREQ±, B_SACK± 3−14

3.12 Bidirectional SCSI Signals—A_SCD, A_SIO±, A_SMSG±, A_SBSY±, A_SATN±, A_SSEL±, A_SRST±, B_SCD±, B_SIO±, B_SMSG, B_SBSY±, B_SATN, B_SSEL±, B_SRST 3-15

3.13 Input Control Signals—CLOCK, RESET/, WS_ENABLE 3-15

3.14 Output Control Signals—BSY_LED, XFER_ACTIVE 3-16

3.15 TolerANT Technology Electrical Characteristics 3-17

3.16 Clock Timing 3-21

3.17 Input Timing 3-21

3.18 Output Timing 3-22

B.1 Pin Adjustments B-1 B.2 No Connect Pins B-2

Chapter 1 Using the LSI53C140

This chapter describes the LSI53C140 Ultra2 SCSI Bus Expander and its applications. It includes these topics:

• Section 1.1, “General Description,” page 1-1

• Section 1.2, “Applications,” page 1-3

• Section 1.3, “Beneﬁts of LVDlink,” page 1-7

1.1 General Description

The LSI53C140 is a single chip solution allowing the extension of SCSI device connectivity and/or cable length limits. A SCSI bus expander couples bus segments together without any impact to the SCSI protocol, software, or ﬁrmware. The LSI53C140 connects Single-Ended (SE) Ultra, Low Voltage Differential (LVD) Ultra2, or High Voltage Differential (HVD) peripherals together in any combination.

The LSI53C140 is capable of supporting any combination of bus mode SE, HVD, or LVD on either the A or B Side port. This provides the system designer with maximum ﬂexibility in designing SCSI backplanes to accommodate any SCSI bus mode.

Figure 1.1 shows the three SCSI bus modes available on the A or B

Side. LVDlink™transceivers provide the multimode LVD, SE, or HVD capability.

LSI53C140 Ultra2 SCSI Bus Expander 1-1

Figure 1.1 LSI53C140 SCSI Bus Modes

A-Side B-Side

LVD

HVD (*)

* All HVD requires external differential transceivers and terminations.

LSI53C140

SCSI Expander

160 PQFP

LVD HVD (*) SE

The LSI53C140 is also capable of supporting any combination of SE or LVD bus mode on either the A or B Side port when using a 192-ball Plastic Ball Grid Array (PBGA) package. Figure 1.1 illustrates the three SCSI bus modes available on the A or B Side.

Figure 1.2 LSI53C140 SCSI Bus Modes

A Side B Side

LVD

HVD (*)

LSI53C140

SCSI Expander

192 PBGA

LVD HVD (*) SE

* All HVD requires external differential transceivers and terminations.

Refer to the Board Design Considerations in Appendix B about the LSI53C140 to LSI53C180 as a drop in replacement along with board design information.

The LSI53C140 operates as both an expander and converter. In both SCSI bus expander and converter modes, cable segments are electrically isolated from each other. This feature maintains the signal integrity of each cable segment.

1-2 Using the LSI53C140

Table 1.1 shows the types of operations for the LSI53C140 160 Plastic

Quad Flat Pack (PQFP).

Table 1.1 Types of Operation

Signal Type Mode Speed

LVD to LVD Repeater Ultra2 HVD to HVD SE to SE Repeater Ultra Or any combination above for Repeater. LVD to HVD LVD to SE Converter Ultra

HVD Or any combination above for Converter.

1. All HVD requires external differential transceivers and terminations.

to SE Converter Ultra

Repeater Ultra

Converter Ultra

The LSI53C140 provides additional control capability through the pin level isolation mode (Warm Swap Enable). This feature permits logical disconnection of both the A Side bus and the B Side bus without disrupting SCSI transfers currently in progress. For example, devices on the logically disconnected B Side can be swapped out while the A Side bus remains active.

The LSI53C140 is based on previous bus expander technology resulting in some signal ﬁltering and retiming to maintain signal skew budgets. The LSI53C140 is independent of software.

1.2 Applications

The LSI53C140 supports these applications:

• Server clustering environments

• Expanders creating distinct SCSI cable segments which are

Applications 1-3

electrically isolated from each other

Figure 1.3 shows two LSI53C140 expanders that conﬁgure three

segments. This conﬁguration allows segments A and B to be treated as a point-to-point segment. Segment C is treated as a load segment with at least 8 inches between every node.

Figure 1.3 LSI53C140 Server Clustering

Primary Server

Segment A

SCSI Bus Expander

Segment C

Shared Disk Subsystem

Segment B

Secondary Server

Figure 1.3 demonstrates how SCSI bus expanders are used to couple

bus segments together without any impact of the SCSI protocol or software. Conﬁgurations that use the LSI53C140 in the Ultra2 mode (LVD to LVD) allow the system designer to take advantage of the inherent cable distance, device connectivity, data reliability, and increased transfer rate beneﬁts of LVD signaling with Ultra2 SCSI peripherals.

Table 1.2 shows the various distance requirements for each SCSI bus

mode.

1-4 Using the LSI53C140

Table 1.2 SCSI Bus Distance Requirements

Segment Mode Length Limit

A LVD (Ultra2) 25 meters

SE (Ultra) 3 meters

HVD (Ultra) 25 meters

B LVD (Ultra2) 12 meters

SE (Ultra) 1.5 meters HVD (Ultra 12 meters

C LVD (Ultra2) 12 meters

SE (Ultra) 1.5 meters HVD (Ultra) 12 meters

1. The length may be more, possibly 6 meters, as no devices are attached to it.

Figure 1.4 illustrates the cascading of the LSI53C140 to achieve four

distinct SCSI segments. Segments A and D can be treated as point-topoint segments. Segments B and C are treated as load segments with at least 8-inch spacing between every node.

Figure 1.4 LSI53C140 SCSI Bus Device

Segment A Segment B Segment C

Primary Server

SCSI Bus Expander

Shared Disk

Subsystem

SCSI Bus Expander

Shared Disk

Subsystem

SCSI Bus Expander

Applications 1-5

Segment D

Secondary

Server

1.2.1 Features

Table 1.3 shows the various distance requirements for each transmission

mode.

Table 1.3 Transmission Mode Distance Requirements

Segment Mode Length Limit

A, D LVD (Ultra2) 25 meters

SE (Ultra) 1.5 meters HVD (Ultra) 25 meters

B, C LVD (Ultra2) 12 meters

SE (Ultra) 1.5 meters HVD (Ultra) 12 meters

The LSI53C140 supports these features:

• Any combination of LVD, SE, or HVD transceivers

• Creates distinct SCSI bus segments that are electrically isolated

from each other

• Integrated LVDlink transceivers for direct attachment to either LVD,

SE, or HVD bus segments

• Operates as a SCSI Bus Expander

– LVD to LVD (Ultra2 SCSI) – HVD to HVD (Ultra SCSI) – SE to SE (Ultra SCSI)

• Operates as a SCSI Bus Converter

– LVD to HVD (Ultra SCSI) – LVD to SE (Ultra SCSI) – HVD to SE (Ultra SCSI)

• Targets and initiators may be located on either the A or B Side of the

device

1-6 Using the LSI53C140

• Accepts any asynchronous or synchronous transfer speed up to

Ultra2 SCSI (for LVD to LVD mode only)

• Dynamic addition/removal of SCSI bus segments by using the

electrical isolation mode

• Does not consume a SCSI ID

• Propagates the RESET/ signal from one side to the other regardless

of the SCSI bus state

• Notiﬁes initiator(s) of changes in transmission mode (SE/LVD/HVD)

on A or B side segments by using SCSI bus RESET/

• SCSI Busy LED driver for activity indicator

• Up to four LSI53C140s may be cascaded

• Does not require software

1.2.2 Speciﬁcations

The LSI53C140 speciﬁcations are:

• 40 MHz Input Clock

• 160-pin PQFP

• 192-ball PBGA; This package is a drop in replacement for the

LSI53C180 when the design uses the LSI53C180 pinout.

• Compliant with the SCSI Parallel Interface (SPI-2)

• Compliant with SCSI Enhanced Parallel Interface (EPI)

Speciﬁcations

1.3 Beneﬁts of LVDlink

The LSI53C140 supports LVD technology for SCSI, a signaling technology that increases the reliability of SCSI data transfers over longer distances than those supported by SE SCSI technology. The low current output of LVD allows the I/O transceivers to be integrated directly onto the chip. LVD provides the reliability of HVD SCSI technology without the added cost of external differential transceivers. LVD allows a longer SCSI cable and more devices on the bus. LVD provides a long-term migration path to even faster SCSI transfer rates without compromising signal integrity, cable length, or connectivity.

Beneﬁts of LVDlink 1-7

For backward compatibility to existing SE devices, the LSI53C140 features multimode LVDlink transceivers that can switch between LVD and SE modes.

Some features of integrated LVDlink Multimode transceivers are:

• Supports SE, LVD, or HVD technology (HVD must have external

transceivers)

• Allows greater device connectivity and longer cable length

• LVDlink transceivers save the cost of external differential transceivers

• Supports a long-term performance migration path

1-8 Using the LSI53C140

Chapter 2 Functional Descriptions

This chapter describes all signals, their groupings, and their functions. It includes these topics:

• Section 2.1, “Interface Signal Descriptions,” page 2-1

• Section 2.2, “SCSI Signal Descriptions,” page 2-6

2.1 Interface Signal Descriptions

The LSI53C140 has no programmable registers, and therefore, no software requirements. SCSI control signals control all LSI53C140 functions. Figure 2.1 shows a block diagram of the LSI53C140 device divided into the following blocks:

• A Side SCSI Control Block

– LVD, SE, and HVD drivers and receivers

• B Side SCSI Control Block

– LVD, SE, and HVD drivers and receivers

• Retiming Logic

• Precision Delay Control

• State Machine Control

LSI53C140 Ultra2 SCSI Bus Expander 2-1

Figure 2.1 LSI53C140 Block Diagram

Control Signals

LVD, SE, HVD

Wide Ultra SCSI Bus

(A Side)

ansceivers

VDink T

ol Block

SCSI Contr

Retiming

Logic

ol Bloc

LVDink Transceivers

SCSI Contr

LVD, SE, HVD

Wide Ultra SCSI Bus

(B Side)

Precision

A_DIFFSENS B_DIFFSENS

Control

Receiv

DIFFSENS

Delay

40 MHz Clock Input

In its simplest form, the LSI53C140 passes data and parity from a source bus to a load bus. The side asserting, deasserting, or releasing the SCSI signals is the source side. This model of the LSI53C140 represents pieces of wire that allow corresponding SCSI signals to ﬂow from one side to the other side. The LSI53C140 monitors arbitration and selection by devices on the bus so it can enable the proper drivers to pass the signals along. In addition, the LSI53C140 does signal retiming to maintain the signal skew budget from the source bus to the load bus.

2.1.1 SCSI A Side and B Side Control Blocks

The SCSI A Side pins are connected internally to the corresponding SCSI B Side pins, forming bidirectional connections to the SCSI bus.

In the LVD/LVD mode, the SCSI A Side and B Side control blocks connect to both targets and initiators and accept any asynchronous or synchronous data transfer rates up to the 80 Mbytes/s rate of Wide Ultra2 SCSI. TolerANT®and LVDlink technologies are part of both the A Side and B Side control blocks.

State

Machine

Control

LVD

Receiver

DIFFSENS

2-2 Functional Descriptions

2.1.1.1 LSI53C140 Requirements for Synchronous Negotiation

The LSI53C140 builds a table of information regarding devices on the bus in on-chip RAM. The Synchronous Data Transfer Request (SDTR) and Wide Data Transfer Request (WDTR) information for each device is taken from the MSG bytes during negotiation. For all devices in the conﬁguration to communicate accurately with each other through the LSI53C140 at Ultra2 (Fast-40) rates, it is necessary for a complete synchronous negotiation to take place between the initiator and target(s) prior to any data transfer. On a 16-bit bus, the LSI53C140 at Ultra2 approaches rates of 80 Mbytes/s. The LSI53C140 defaults to Fast-20 rates when a valid negotiation between the initiator and target has not occurred.

2.1.1.2 TolerANT Technology

In the SE mode, the LSI53C140 features TolerANT technology, which includes active negation on the SCSI drivers and input signal ﬁltering on the SCSI receivers. Active negation causes the SCSI Request, Acknowledge, Data, and Parity signals to be actively driven HIGH rather than passively pulled up by terminators.

TolerANT receiver technology improves data integrity in unreliable cabling environments, where other devices would be subject to data corruption. TolerANT receivers ﬁlter the SCSI bus signals to eliminate unwanted transitions without the long signal delays associated with RC-type input ﬁlters. This improved driver and receiver technology helps eliminate double clocking of data, which is the single biggest reliability issue with SCSI operations.

The beneﬁts of TolerANT technology include increased immunity to noise on the deasserting signal edge, better performance due to balanced duty cycles, and improved SCSI transfer rates. In addition, TolerANT SCSI devices prevent glitches on the SCSI bus at power-up or power-down, so other devices on the bus are also protected from data corruption.

Interface Signal Descriptions 2-3

2.1.1.3 LVDlink Technology

To support greater device connectivity and longer SCSI cables, the LSI53C140 features LVDlink technology, the LSI Logic implementation of multimode LVD SCSI. LVDlink transceivers provide the inherent reliability of differential SCSI, and a long-term migration path of faster SCSI transfer rates.

LVDlink technology is based on current drive. Its low output current reduces the power needed to drive the SCSI bus. Therefore, the I/O drivers can be integrated directly onto the chip. This reduces the cost and complexity compared to traditional (high power) differential designs. LVDlink lowers the amplitude of noise reﬂections and allows higher transmission frequencies.

The LVDlink transceivers in side A and side B operate in the LVD, HVD (external differential transceivers), or SE modes. The LSI53C140 automatically detects the type of signal connected, based on the voltages detected by A_DIFFSENS and B_DIFFSENS.

2.1.2 Retiming Logic

As SCSI signals propagate from one side of the LSI53C140 to the other side, the logic circuits that retime the bus signals process the SCSI signals, as needed. This guarantees or improves the required SCSI timings. The State Machine Controls govern the retiming logic that keeps track of SCSI phases, the location of initiator and target devices, and various timing functions. In addition, the retiming logic contains numerous delay elements that are periodically calibrated by the Precision Delay Control block. This calibration occurs in order to guarantee speciﬁed timing such as output pulse widths, setup and hold times, and others.

When a synchronous negotiation takes place between devices, a nexus is formed, and the on-chip RAM stores the corresponding information for that nexus. This information remains in place until a chip reset, power down, or renegotiation occurs. This enables the chips to make more accurate retiming adjustments.

2-4 Functional Descriptions

2.1.3 Precision Delay Control

The Precision Delay Control block provides calibration information to the precision delay elements in the retiming logic block in order to maintain precise timing as signals propagate through the device. As the LSI53C140 operating conditions (such as voltage and temperature) vary over time, the Precision Delay Control block periodically updates the delay settings in the retiming logic to maintain constant and precise control over bus timing.

2.1.4 State Machine Control

The State Machine Control keeps track of the SCSI bus phase protocol and other internal operating conditions. This block provides signals to the retiming logic that identify how to properly handle SCSI bus signal retiming and protocol, based on observed bus conditions.

2.1.5 DIFFSENS Receiver

The LSI53C140 contains LVD DIFFSENS receivers that detect the voltage level on the A Side or B Side DIFFSENS lines to inform the LSI53C140 of the transmission mode being used by the SCSI buses. The LVD DIFFSENS receivers are capable of detecting the voltage level of incoming SCSI signals to determine whether it is from an SE, LVD, or HVD device. A device does not change its present signal driver or receiver mode based on the DIFFSENS voltage levels unless a new mode is sensed continuously for at least 100 ms.

Transmission mode detection for SE, LVD, or HVD is accomplished through the use of the DIFFSENS lines. Table 2.1 shows the voltages on the DIFFSENS lines and modes they will cause.

Table 2.1 DIFFSENS Voltage Levels

Voltage Mode

−0.35 to +0.5 SE +0.7 to +1.9 LVD +2.4 to +5.5 HVD

Interface Signal Descriptions 2-5

2.1.6 Dynamic Transmission Mode Changes

Any dynamic mode change (SE/LVD/HVD) on a bus segment is considered to be a signiﬁcant event that requires the initiator to determine whether the mode change meets the requirements for that bus segment.

The LSI53C140 supports dynamic transmission mode changes by notifying the initiator(s) of changes in transmission mode (SE/LVD/HVD) on A or B side segments by using SCSI bus RESET. The DIFFSENS line detects a valid mode switch on the bus segments. After the DIFFSENS state is present for 100 ms, the LSI53C140 generates a SCSI reset on the opposite bus from the one that the transmission mode change occurred on. This reset informs any initiators residing on the opposite segment about the change in the transmission mode. Then, the initiator(s) renegotiates synchronous transfer rates with each device on that segment to ensure that there is a valid bus segment for that mode.

2.2 SCSI Signal Descriptions

Figure 2.2 shows the LSI53C140 signal grouping. A description of the

signal groups follows. For a description of a speciﬁc signal, refer to

Section 3.1, “General Description,” in Chapter 3. For information about

signal electrical characteristics, refer to Section 3.2, “Electrical

Characteristics,” in Chapter 3. For SCSI bus signal timing, see Section 3.2.4, “SCSI Interface Timing,” in Chapter 3.

2-6 Functional Descriptions

Figure 2.2 LSI53C140 Signal Grouping

A_SSEL+ A_SSEL− A_SBSY+ A_SBSY−

A-Side

LVD, HVD, or SE

SCSI Interface

Control Signals

A_SRST+ A_SRST− A_SREQ+ A_SREQ− A_SACK+ A_SACK− A_SMSG+ A_SMSG− A_SCD+ A_SCD− A_SIO+ A_SIO− A_SATN+ A_SATN− A_SDP[1:0]+ A_SDP[1:0]− A_SD[15:0]+ A_SD[15:0]−

A_DIFFSENS A_HVD_MODE

RESET/ WS_ENABLE/ XFER_ACTIVE CLOCK

2.2.1 Data and Parity (SD and SDP)

LSI53C140

B_SSEL+

B_SSEL− B_SBSY+ B_SBSY− B_SRST+ B_SRST−

B_SREQ+ B_SREQ−

B_SACK+ B_SACK−

B_SMSG+ B_SMSG−

B_SCD+ B_SCD−

B_SIO+

B_SIO− B_SATN+ B_SATN−

B_SDP[1:0]+ B_SDP[1:0]−

B_SD[15:0]+ B_SD[15:0]−

B_DIFFSENS

B_HVD_MODE

BSY_LED

B-Side

LVD, HVD, or SE

SCSI Interface

The signals named A_SD[15:0]± and A_SDP[1:0]± are the data and parity signals from the A Side, and B_SD[15:0]± and B_SDP[1:0]± are the data and parity signals from the B Side of the LSI53C140. The LSI53C140 sends and receives these signals by using SCSI compatible drivers and receiver logic designed into the LSI53C140 interfaces. This logic provides the multimode LVD and SE interfaces in the chip. This logic also provides the necessary drive, sense thresholds, and input hysteresis to function correctly in a SCSI bus environment.

The LSI53C140 receives data and parity signals and passes them from the source bus to the load bus and provides any necessary edge shifting to guarantee the skew budget for the load bus. Either side of the LSI53C140 may be the source bus or the load bus. The side that is asserting, deasserting, or releasing the SCSI signals is the source side. These steps describe the LSI53C140 data processing:

SCSI Signal Descriptions 2-7

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Avago Technologies LSI53C140 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 General Description

Table 1.1 Types of Operation

1.2 Applications

Table 1.2 SCSI Bus Distance Requirements

1.2.1 Features

Table 1.3 Transmission Mode Distance Requirements

2.1 Interface Signal Descriptions

2.1.1 SCSI A Side and B Side Control Blocks

2.1.2 Retiming Logic

2.1.3 Precision Delay Control

2.1.4 State Machine Control

2.1.5 DIFFSENS Receiver

Table 2.1 DIFFSENS Voltage Levels

2.1.6 Dynamic Transmission Mode Changes

2.2 SCSI Signal Descriptions

2.2.1 Data and Parity (SD and SDP)