Avago Technologies LSI53C1030 User Manual

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TECHNICAL

MANUAL

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller

September 2003

Version 2.2

DB14-000156-05

This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an ofﬁcer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic ofﬁcer is prohibited.

Document DB14-000156-05, Version 2.2 (September 2003) This document describes LSI Logic Corporation’s LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller and will remain the ofﬁcial reference source for all revisions/releases of this product until rescinded by an update.

LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.

LSI Logic, the LSI Logic logo design, Fusion-MPT, Integrated Mirroring, Integrated Striping, LVDlink, SDMS, SureLINK, and TolerANT are trademarks or registered trademarks of LSI Logic Corporation. ARM and Multi-ICE are registered trademarks of ARM Ltd., used under license. Windows is a registered trademarks of Microsoft Corporation. NetWare is a registered trademarks of Novell Corporation. Linux is a registered trademark of Linus Torvalds. Solaris is a trademark of Sun Microsystems, Inc. SCO Openserver is a trademark of Caldera International, Inc. UnixWare is a trademark of The Open Group. All other brand and product names may be trademarks of their respective companies.

To receive product literature, visit us at http://www.lsilogic.com. For a current list of our distributors, sales ofﬁces, and design resource

centers, view our web page located at http://www.lsilogic.com/contacts/index.html

Audience

Preface

This book is the primary reference and technical manual for the LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller. It contains a functional description for the LSI53C1030 and the physical and electrical speciﬁcations for the LSI53C1030.

This document assumes that you have some familiarity with microprocessors and related support devices. The people who beneﬁt from this book are:

• Engineers and managers who are evaluating the LSI53C1030 for use

in a system

• Engineers who are designing the LSI53C1030 into a system

Organization

This document has the following chapters and appendixes:

• Chapter 1, Introduction, provides an overview of the LSI53C1030

features and capabilities.

• Chapter 2, Functional Description, provides a detailed functional

description of the LSI53C1030 operation. This chapter describes how the LSI53C1030 implements the PCI, PCI-X, and SCSI bus speciﬁcations.

• Chapter 3, Signal Description, provides a detailed signal

description for the LSI53C1030.

• Chapter 4, PCI Host Register Description, provides a bit level

description of the host register set of the LSI53C1030.

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller iii

• Chapter 5, Speciﬁcations, provides the electrical and physical

• Appendix A, Register Summary, provides a register map for the

Related Publications

LSI Logic Documents

Fusion-MPT Device Management User’s Guide, Version 2.0, DB15-000186-02 Integrated RAID User’s Guide, Version 1.0, DB15-000292-00

LSI Logic World Wide Web Home Page

www.lsilogic.com

ANSI

11 West 42nd Street New York, NY 10036 (212) 642-4900

Global Engineering Documents

15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740

speciﬁcations for the device.

LSI53C1030.

ENDL Publications

14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI

Tutor

Prentice Hall

113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding

the Small Computer System Interface

SCSI Electronic Bulletin Board

(719) 533-7950

iv Preface

PCI Special Interest Group

2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344

Conventions Used in This Manual

The ﬁrst time a word or phrase is deﬁned in this manual, it is italicized. The word assert means to drive a signal true or active. The word

deassert means to drive a signal false or inactive. Signals that are active LOW end with a “/.”

Hexadecimal numbers are indicated by the preﬁx “0x” —for example, 0x32CF. Binary numbers are indicated by the preﬁx “0b” —for example, 0b0011.0010.1100.1111.

Revision History

Revision Date Remarks

Version 2.2 9/2003 Corrected SCSI clock period and LOW/HIGH times in Table 5.13.

Version 2.1 6/2003 Updated the external memory timing diagrams.

Version 2.0 4/2002 Added register summary appendix.

Preliminary Version 1.0

12/2001 Updated the description of Fusion-MPT architecture in Chapter 1.

Updated references to Integrated RAID (IR).

Updated the default Subsystem ID value. Updated the ZCR behavior description. Updated the Multi-ICE test interface description.

Updated the electrical characteristics. Updated the Index.

Updated External Memory Interface descriptions in Chapter 2. Added Test Interface description to Chapter 2. Added Zero Channel RAID interface description to Chapters 2 and 3. Updated the MAD Power-On Sense pin description in Chapter 3. Updated signal descriptions and lists to include the ZCR-related pins. Updated electrical and environmental characteristics in Chapter 5. Removed ﬁgures relating to SE SCSI electrical and timing characteristics from Chapter 5. Removed SCSI timing information from Chapter 5 and referred readers to the SCSI speciﬁcation. Removed PSBRAM interface and all related information.

Preface v

Revision Date Remarks

Advance Version 0.1

2/2001 Initial release of document.

vi Preface

Chapter 1 Introduction

1.1 General Description 1-1

1.2 Beneﬁts of the Fusion-MPT Architecture 1-5

1.3 Beneﬁts of PCI-X 1-6

1.4 Beneﬁts of Ultra320 SCSI 1-7

1.5 Beneﬁts of SureLINK (Ultra320 SCSI Domain Validation) 1-8

1.6 Beneﬁts of LVDlink Technology 1-8

1.7 Beneﬁts of TolerANT®Technology 1-9

1.8 Summary of LSI53C1030 Features 1-10

1.8.1 SCSI Performance 1-10

1.8.2 PCI Performance 1-11

1.8.3 Integration 1-12

1.8.4 Flexibility 1-12

1.8.5 Reliability 1-13

1.8.6 Testability 1-13

Chapter 2 Functional Description

2.1 Block Diagram Description 2-2

2.1.1 Host Interface Module Description 2-3

2.1.2 SCSI Channel Module Description 2-6

2.2 Fusion-MPT Architecture Overview 2-6

2.3 PCI Functional Description 2-8

2.3.1 PCI Addressing 2-8

2.3.2 PCI Commands and Functions 2-9

2.3.3 PCI Arbitration 2-15

2.3.4 PCI Cache Mode 2-15

2.3.5 PCI Interrupts 2-15

2.3.6 Power Management 2-16

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller vii

2.4 Ultra320 SCSI Functional Description 2-18

2.4.1 Ultra320 SCSI Features 2-18

2.4.2 SCSI Bus Interface 2-23

2.5 External Memory Interface 2-24

2.5.1 Flash ROM Interface 2-24

2.5.2 NVSRAM Interface 2-26

2.6 Serial EEPROM Interface 2-27

2.7 Zero Channel RAID 2-28

2.8 Multi-ICE Test Interface 2-30

Chapter 3 Signal Description

3.1 Signal Organization 3-2

3.2 PCI Bus Interface Signals 3-4

3.2.1 PCI System Signals 3-4

3.2.2 PCI Address and Data Signals 3-5

3.2.3 PCI Interface Control Signals 3-6

3.2.4 PCI Arbitration Signals 3-7

3.2.5 PCI Error Reporting Signals 3-7

3.2.6 PCI Interrupt Signals 3-8

3.3 PCI-Related Signals 3-9

3.4 SCSI Interface Signals 3-10

3.4.1 SCSI Channel [0] Signals 3-10

3.4.2 SCSI Channel [1] Signals 3-13

3.5 Memory Interface 3-14

3.6 Zero Channel RAID Interface 3-16

3.7 Test Interface 3-17

3.8 GPIO and LED Signals 3-19

3.9 Power and Ground Pins 3-20

3.10 Power-On Sense Pins Description 3-21

3.11 Internal Pull-Ups and Pull-Downs 3-25

Chapter 4 PCI Host Register Description

4.1 PCI Conﬁguration Space Register Description 4-1

4.2 PCI I/O Space and Memory Space Register Description 4-28

Chapter 5 Speciﬁcations

5.1 DC Characteristics 5-1

viii Contents

5.2 TolerANT Technology Electrical Characteristics 5-7

5.3 AC Characteristics 5-9

5.4 External Memory Timing Diagrams 5-11

5.4.1 NVSRAM Timing 5-11

5.4.2 Flash ROM Timing 5-15

5.5 Package Drawings 5-18

Appendix A Register Summary

Index

Customer Feedback

Contents ix

x Contents

Figures

1.1 Typical LSI53C1030 Board Application 1-3

1.2 Typical LSI53C1030 System Application 1-4

2.1 LSI53C1030 Block Diagram 2-3

2.2 Paced Transfer Example 2-20

2.3 Example of Precompensation 2-21

2.4 Flash ROM Block Diagram 2-25

2.5 NVSRAM Diagram 2-27

2.6 ZCR Circuit Diagram for LSI53C1030 and LSI53C1010R 2-29

3.1 LSI53C1030 Functional Signal Grouping 3-3

5.1 LVD Driver 5-3

5.2 LVD Receiver 5-4

5.3 Rise and Fall Time Test Condition 5-8

5.4 SCSI Input Filtering 5-9

5.5 External Clock 5-10

5.6 Reset Input 5-10

5.7 Interrupt Output 5-11

5.8 NVSRAM Read Cycle 5-12

5.8 NVSRAM Read Cycle (Cont.) 5-12

5.9 NVSRAM Write Cycle 5-14

5.9 NVSRAM Write Cycle (Cont.) 5-14

5.10 Flash ROM Read Cycle 5-15

5.10 Flash ROM Read Cycle (Cont.) 5-16

5.11 Flash ROM Write Cycle 5-17

5.11 Flash ROM Write Cycle (Cont.) 5-17

5.12 LSI53C1030 456-Pin BGA Top View 5-20

5.12 LSI53C1030 456-Pin BGA Top View (Cont.) 5-21

5.13 456-Pin EPBGA (KY) Mechanical Drawing 5-26

Contents xi

xii Contents

Tables

2.1 PCI/PCI-X Bus Commands and Encodings 2-10

2.2 Power States 2-16

2.3 Flash ROM Size Programming 2-24

2.4 Flash Signature Value 2-26

2.5 PCI Conﬁguration Record in Serial EEPROM 2-28

2.6 20-Pin Multi-ICE Header Pinout 2-30

3.1 PCI System Signals 3-4

3.2 PCI Address and Data Signals 3-5

3.3 PCI Interface Control Signals 3-6

3.4 PCI Arbitration Signals 3-7

3.5 PCI Error Reporting Signals 3-7

3.6 PCI Interrupt Signals 3-8

3.7 PCI-Related Signals 3-9

3.8 SCSI Bus Clock Signal 3-10

3.9 SCSI Channel [0] Interface Signals 3-10

3.10 SCSI Channel [0] Control Signals 3-12

3.11 SCSI Channel [1] Interface Signals 3-13

3.12 SCSI Channel [1] Control Signals 3-14

3.13 Flash ROM/NVSRAM Interface Pins 3-14

3.14 Serial EEPROM Interface Pins 3-16

3.15 ZCR Conﬁguration Pins 3-16

3.16 JTAG, ICE, and Debug Pins 3-17

3.17 LSI Logic Test Pins 3-18

3.18 GPIO and LED signals 3-19

3.19 Power and Ground Pins 3-20

3.20 MAD Power-On Sense Pin Options 3-21

3.21 PCI-X Function to SCSI Channel Conﬁgurations 3-24

3.22 Flash ROM Size Programming 3-24

3.23 Pull-Up and Pull-Down Conditions 3-25

4.1 LSI53C1030 PCI Conﬁguration Space Address Map 4-2

4.2 Subsystem ID Register Download Conditions and Values 4-13

4.3 Multiple Message Enable Field Bit Encoding 4-22

4.4 Maximum Outstanding Split Transactions 4-25

4.5 Maximum Memory Read Count 4-25

4.6 PCI I/O Space Address Map 4-29

4.7 PCI Memory [0] Address Map 4-29

Contents xiii

4.8 PCI Memory [1] Address Map 4-29

4.9 Interrupt Signal Routing 4-36

5.1 Absolute Maximum Stress Ratings 5-2

5.2 Operating Conditions 5-2

5.3 LVD Driver SCSI Signals— SACK±,SATN±, SBSY±, SCD±, SD[15:0]±, SDP[1:0]±, SIO±, SMSG±, SREQ±, SRST±, SSEL± 5-3

5.4 LVD Receiver SCSI Signals— SACK±,SATN±, SBSY±, SCD±, SD[15:0]±, SDP[1:0]±, SIO±, SMSG±, SREQ±, SRST±, SSEL± 5-3

5.5 A_DIFFSENS and B_DIFFSENS SCSI Signals 5-4

5.6 Input Capacitance 5-4

5.7 8 mA Bidirectional Signals — GPIO[7:0], MAD[15:0], MADP[1:0], SerialDATA 5-5

5.8 8 mA PCI Bidirectional Signals — ACK64/, AD[63:0], C_BE[7:0]/, DEVSEL/, FRAME/, IRDY/, PAR, PAR64, PERR/, REQ64/, SERR/, STOP/, TRDY/ 5-5

5.9 Input Signals — CLK, CLKMODE_0, CLKMODE_1, DIS_PCI_FSN/, DIS_SCSI_FSN/, GNT/, IDDTN, IDSEL, IOPD_GNT/, PVT1, PVT2, SCANEN, SCANMODE, SCLK, TCK_CHIP, TCK_ICE, TESTACLK, TESTCLKEN, TESTHCLK, TDI_CHIP, TDI_ICE, TMS_CHIP, TMS_ICE, TN, TRST_ICE/, TST_RST/, ZCR_EN/ 5-6

5.10 8 mA Output Signals — ADSC/, ADV/, ALT_INTA/, ALT_INTB/, BWE[1:0]/, FLSHALE[1:0]/, FLSHCE/, INTA/, INTB/, MCLK, MOE/, PIPESTAT[2:0], RAMCE/, REQ/, RTCK_ICE, SerialCLK, SERR/, TDO_CHIP, TDO_ICE, TRACECLK, TRACEPKT[7:0], TRACESYNC 5-6

5.11 12 mA Output Signals — A_LED/, B_LED/, HB_LED/ 5-6

5.12 TolerANT Technology Electrical Characteristics for SE SCSI Signals 5-7

5.13 External Clock 5-9

5.14 Reset Input 5-10

5.15 Interrupt Output 5-10

5.16 NVSRAM Read Cycle Timing 5-11

5.17 NVSRAM Write Cycle 5-13

5.18 Flash ROM Read Cycle Timing 5-15

5.19 Flash ROM Write Cycle 5-16

A.1 LSI53C1030 PCI Registers A-1

xiv Contents

A.2 LSI53C1030 PCI I/O Space Registers A-3 A.3 LSI53C1030 PCI I/O Space Registers A-4

Contents xv

xvi Contents

Chapter 1 Introduction

This chapter provides a general overview of the LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller. This chapter contains the following sections:

• Section 1.1, “General Description”

• Section 1.2, “Beneﬁts of the Fusion-MPT Architecture”

• Section 1.3, “Beneﬁts of PCI-X”

• Section 1.4, “Beneﬁts of Ultra320 SCSI”

• Section 1.5, “Beneﬁts of SureLINK (Ultra320 SCSI Domain

Validation)”

• Section 1.6, “Beneﬁts of LVDlink Technology”

• Section 1.7, “Beneﬁts of TolerANT® Technology”

• Section 1.8, “Summary of LSI53C1030 Features”

1.1 General Description

The LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller brings Ultra320 SCSI performance to host adapter, workstation, and server designs, making it easy to add a high-performance SCSI bus to any PCI or PCI-X system. The LSI53C1030 supports both the PCI Local Bus Speciﬁcation, Revision

2.2, and the PCI-X Addendum to the PCI Local Bus Speciﬁcation,

Revision 1.0a.

1. In some instances, this manual references PCI-X explicitly. References to the PCI

bus may be inclusive of both the PCI speciﬁcation and PCI-X addendum, or they may refer only to the PCI bus depending on the operating mode of the device.

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller 1-1

The LSI53C1030 is pin compatible with the LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller to provide an easy and safe migration path to Ultra320 SCSI. The LSI53C1030 supports up to a 64-bit, 133 MHz PCI-X bus. The Ultra320 SCSI features for the LSI53C1030 include: double transition (DT) clocking, packetized protocol, paced transfers, quick arbitrate and select (QAS), skew compensation, intersymbol interference (ISI) compensation, cyclic redundancy check (CRC), and domain validation technology. These features comply with the American National Standard Institute (ANSI) T10 SCSI Parallel Interface-4 (SPI-4) draft speciﬁcation.

DT clocking enables the LSI53C1030 to achieve data transfer rates of up to 320 megabytes per second (Mbytes/s) on each SCSI channel, for a total bandwidth of 640 Mbytes/s on both SCSI channels. Packetized protocol increases data transfer capabilities with SCSI information units. QAS minimizes SCSI bus latency by allowing the bus to directly enter the arbitration/selection bus phase after a SCSI disconnect and skip the bus free phase. Skew compensation permits the LSI53C1030 to adjust for cable and bus skew on a per-device basis. Paced transfers enable high speed data transfers during DT data phases by using the REQ/ACK transition as a free running data clock. Precompensation enables the LSI53C1030 to adjust the signal drive strength to compensate for the charge present on the cable. CRC improves the SCSI data transmission integrity through enhanced detection of communication errors. SureLINK™ Domain Validation detects the SCSI bus conﬁguration and adjusts the SCSI transfer rate to optimize bus interoperability and SCSI data transfer rates. SureLINK Domain Validation provides three levels of domain validation, assuring robust system operation.

The LSI53C1030 supports a local memory bus, which supports a standard serial EEPROM and allows local storage of the BIOS in Flash ROM memory. The LSI53C1030 supports programming of local Flash ROM memory for BIOS updates. Figure 1.1 shows a typical LSI53C1030 board application connected to external ROM memory.

1-2 Introduction

Figure 1.1 Typical LSI53C1030 Board Application

Channel [0]

68 Pin Wide SCSI Connector

and

Terminator

Channel [1]

68 Pin Wide SCSI Connector

and

Terminator

Memory Control

Block

Flash ROM/

NVSRAM

Serial EEPROM

SCSI Bus

LSI53C1030

64 Bit, 133 MHz

Multifunction PCI-X

Dual Channel

Ultra320 SCSI

Controller

Function [1]Function [0]

PCI-X Interface

Memory

Address/Data

Bus

Serial Data

Serial Clock

The LSI53C1030 integrates two high-performance SCSI Ultra320 cores and a 64-bit, 133 MHz PCI-X bus master DMA core. The LSI53C1030 employs three ARM966E-S processors to meet the data transfer ﬂexibility requirements of the Ultra320 SCSI, PCI, and PCI-X speciﬁcations. Separate ARM®processors support each SCSI channel and the PCI/PCI-X interface.

These processors implement the LSI Logic Fusion-MPT™ architecture, a multithreaded I/O algorithm that supports data transfers between the host system and SCSI devices with minimal host processor intervention. Fusion-MPT technology provides an efﬁcient architecture that solves the protocol overhead problems of previous intelligent and nonintelligent adapter designs.

LVDlink™ technology is the LSI Logic implementation of Low Voltage Differential (LVD) SCSI. LVDlink transceivers allow the LSI53C1030 to perform either Single-Ended (SE) or LVD transfers. Figure 1.2 illustrates a typical LSI53C1030 system application.

General Description 1-3

Figure 1.2 Typical LSI53C1030 System Application

PCI-X Bus

Interface

Controller

Processor Bus

Central

Processing

Unit

(CPU)

PCI-X Bus

LSI53C1030 PCI-X

to Ultra320 SCSI

Channel [0]

and

LSI53C1030 PCI-X

to Ultra320 SCSI

Channel [1]

One PCI Bus Load

PCI Graphic Accelerator

PCI Fast Ethernet

Memory

Controller

Memory

SCSI Bus

Fixed Disk, Optical Disk,

Printer, Tape, and Other

SCSI Peripherals

Fixed Disk, Optical Disk,

Printer, Tape, and Other

SCSI Peripherals

The LSI Logic Integrated RAID solution provides cost beneﬁts for the server or workstation market where the extra performance, storage capacity, and/or redundancy of a RAID conﬁguration are required. The two components of Integrated RAID are:

• Integrated Mirroring™ (IM), which provides features of RAID 1 and

RAID 1E. IM provides physical mirroring of the boot volume through LSI53C1030 ﬁrmware. This feature provides extra reliability for the system’s boot volume without burdening the host CPU. The runtime mirroring of the boot drive is transparent to the BIOS, drivers, and operating system.

• Integrated Striping™ (IS), which provides features of RAID 0. The IS feature writes data across multiple disks instead of onto one disk. This is accomplished by partitioning each disk’s storage space into

1-4 Introduction

64 Kbyte stripes. These stripes are interleaved round-robin, so that the combined storage space is composed alternately of stripes from each disk.

The LSI Logic Fusion-MPT architecture provides the interface to the SCSI chip/ﬁrmware to enable Integrated Striping and Integrated Mirroring. LSI Logic’s CIM interface software is used to continuously monitor IM volumes and IS volumes and to report status and error conditions as they arise.

A BIOS-based conﬁguration utility is provided to create the IM and IS volumes. A DOS-based conﬁguration utility is also provided for use on the manufacturing ﬂoor.

For more information about the LSI Logic Integrated RAID solution, see the Integrated RAID User’s Guide, DB15-000292-00.

1.2 Beneﬁts of the Fusion-MPT Architecture

The Fusion-MPT architecture provides an open architecture that is ideal for SCSI, Fibre Channel, and other emerging interfaces.The I/O interface is interchangable at the system and application level; embedded software uses the same device interface for SCSI and Fibre Channel implementations just as application software uses the same storage management interfaces for SCSI and Fibre Channel implementations. LSI Logic provides Fusion-MPT device drivers that are binary compatible between Fibre Channel and Ultra320 SCSI interfaces.

The Fusion-MPT architecture improves overall system performance by requiring only a thin device driver, which off loads the intensive work of managing SCSI I/Os from the system processor to the LSI53C1030. Developed from the proven LSI Logic SDMS™ solution, the Fusion-MPT architecture delivers unmatched performance of up to 100,000 Ultra320 SCSI I/Os per second with minimal system overhead or device maintenance. The use of thin, easy to develop, common OS device drivers accelerates time to market by reducing device driver development and certiﬁcation times.

The Fusion-MPT architecture provides an interrupt coalescing feature. Interrupt coalescing allows an I/O controller to send multiple reply messages in a single interrupt to the host processor. Sending multiple

Beneﬁts of the Fusion-MPT Architecture 1-5

reply messages per interrupt reduces context switching of the host processor and maximizes the host processor efﬁciency, which results in a signiﬁcant improvement of system performance. To use the interrupt coalescing feature, the host processor must be able to accept and manage multiple replies per interrupt.

The Fusion-MPT architecture also provides built-in device driver stability since the device driver need not change for each revision of the LSI53C1030 silicon or ﬁrmware. This architecture is a reliable, constant interface between the host device driver and the LSI53C1030. Changes within the LSI53C1030 are transparent to the host device driver, operating system, and user. The Fusion-MPT architecture also saves the user signiﬁcant development and maintenance effort since it is not necessary to alter or redevelop the device driver when a revision of the LSI53C1030 device or ﬁrmware occurs.

1.3 Beneﬁts of PCI-X

PCI-X doubles the maximum clock frequency of the conventional PCI bus. The PCI-X Addendum to the PCI Local Bus Speciﬁcation,

Revision 1.0a, deﬁnes enhancements to the proven PCI Local Bus Speciﬁcation, Revision 2.2. PCI-X provides more efﬁcient data transfers

by enabling registered inputs and outputs, improves buffer management by including transaction information with each data transfer, and reduces bus overheadby restricting the use of wait states and disconnects. PCI-X also reduces host processor overhead by providing a wide range of error recovery implementations.

The LSI53C1030 supports up to a 133 MHz, 64-bit PCI-X bus and is backward compatible with previous versions of the PCI/PCI-X speciﬁcation. The LSI53C1030 is a true multifunction PCI-X device and presents a single electrical load to the PCI bus. The LSI53C1030 uses a single REQ/-GNT/ pair to arbitrate for PCI bus mastership. Separate interrupt signals for PCI Function [0] and PCI Function [1] allow independent control of the two PCI functions.

Per the PCI-X addendum, the LSI53C1030 includes transaction information with all PCI-X transactions to enable more efﬁcient buffer management schemes. Each PCI-X transaction contains a transaction sequence identiﬁer (Tag), the identity of the initiator, and the number of

1-6 Introduction

bytes in the sequence. The LSI53C1030 clocks PCI-X data directly into and out of registers, which creates a more efﬁcient data path. The LSI53C1030 increases bus efﬁciency since it does not insert wait states after the initial data phase when acting as a PCI-X target and never inserts wait states when acting as a PCI-X initiator.

1.4 Beneﬁts of Ultra320 SCSI

Ultra320 SCSI is an extension of the SPI-4 draft speciﬁcation that allows faster synchronous SCSI data transfer rates than Ultra160 SCSI. When enabled, Ultra320 SCSI performs 160 megatransfers per second resulting in approximately double the synchronous data transfer rates of Ultra160 SCSI. The LSI53C1030 performs 16-bit, Ultra320 SCSI synchronous data transfers as fast as 320 Mbytes/s on each SCSI channel. This advantage is most noticeable in heavily loaded systems or large block size applications, such as video on-demand and image processing.

Ultra320 SCSI doubles both the data and clock frequencies from Ultra160 SCSI. Due to the increased data and clock speeds, Ultra320 SCSI introduces skew compensation and intersymbol interference (ISI) compensation. These new features simplify system design by resolving timing issues at the chip level. Skew compensation adjusts for timing differences between data and clock signals caused by cabling, board traces, etc. ISI compensation enhances the ﬁrst pulse after a change in state to ensure data integrity.

Ultra320 SCSI includes CRC, which offers higher levels of data reliability by ensuring complete integrity of transferred data. CRC is a 32-bit scheme, referred to as CRC-32. CRC guarantees detection of all single or double bit errors, as well as any combination of bit errors within a single 32-bit range.

Beneﬁts of Ultra320 SCSI 1-7

1.5 Beneﬁts of SureLINK (Ultra320 SCSI Domain Validation)

SureLINK Domain Validation software ensures robust SCSI interconnect management and low risk Ultra320 SCSI implementations by extending the domain validation guidelines documented in the SPI-4 speciﬁcations. Domain validation veriﬁes that the system is capable of transferring data at Ultra320 SCSI speeds, allowing the LSI53C1030 to renegotiate to a lower data transfer speed and bus width if necessary. SureLINK Domain Validation is the software control for the domain validation manageability enhancements in the LSI53C1030. SureLINK Domain Validationsoftware provides domain validation management at boot time as well as during system operation.

SureLINK Domain Validation ensures robust system operation by providing 3 levels of integrity checking on a per-device basis: Basic (Level 1) with inquiry command, Enhanced (Level 2) with read/write buffer and Margined (Level 3) with margining of drive strength and slew rates.

1.6 Beneﬁts of LVDlink Technology

The LSI53C1030 supports Low Voltage Differential (LVD) through LVDlink technology. This signalling technology increases the reliability of SCSI data transfers over longer distances than are supported by SE (Single Ended) SCSI. The low current output of LVD allows the I/O transceivers to be integrated directly onto the chip. To allow the use of the LSI53C1030 in both legacy and Ultra320 SCSI applications, this device features universal LVDlink transceivers that support LVD SCSI and SE SCSI.

1-8 Introduction

1.7 Beneﬁts of TolerANT®Technology

The LSI53C1030 features TolerANT technology, which provides active negation on the SCSI drivers and input signal ﬁltering on the SCSI receivers. Active negation causes the SCSI Request, Acknowledge, Data, and Parity signals to be actively driven high rather than passively pulled up by terminators.

TolerANT receiver technology improves data integrity in unreliable cabling environments where other devices would be subject to data corruption. TolerANT receivers ﬁlter the SCSI bus signals to eliminate unwanted transitions, without the long signal delay associated with RC-type input ﬁlters. This improved driver and receiver technology helps ensure correct clocking of data. TolerANT input signal ﬁltering is a built-in feature of the LSI53C1030 and all LSI Logic Fast SCSI, Ultra SCSI, Ultra2 SCSI, Ultra160 SCSI, and Ultra320 SCSI devices.

TolerANT technology increases noise immunity, balances duty cycles, and improves SCSI transfer rates. In addition, TolerANT SCSI devices do not cause glitches on the SCSI bus at power-up or power-down, which protects other devices on the bus from data corruption. When used with the LVDlink transceivers, TolerANT technology provides excellent signal quality and data reliability in real world cabling environments. TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute.

Beneﬁts of TolerANT®Technology 1-9

1.8 Summary of LSI53C1030 Features

This section provides a summary of the LSI53C1030 features and beneﬁts. It contains information on SCSI Performance, PCI Performance,

Integration, Flexibility, Reliability, and Testability.

1.8.1 SCSI Performance

The LSI53C1030 contains the following SCSI performance features:

• Supports Ultra320 SCSI – Paced transfers using a free running clock – 320 Mbyte/s data transfer rate on each SCSI channel – Mandatory packetized protocol – Quick arbitrate and select (QAS) – Skew compensation with bus training – Transmitter precompensation to overcome ISI effects for SCSI

data signals

– Retained training information (RTI)

• Offers a performance optimized architecture – Three ARM966E-S processors provide high performance with

low latency – Two independent Ultra320 SCSI channels – Designed for optimal packetized performance

• Uses provenintegrated LVDlink transceivers for direct attach to either LVD or SE SCSI buses with precision-controlled slew rates

• Supports expander communication protocol (ECP)

• Uses the Fusion-MPT (Message Passing Technology) drivers to provide support for Windows, Linux, Solaris, SCO Openserver, UnixWare, OpenUnix 8, and NetWare operating systems

1-10 Introduction

1.8.2 PCI Performance

The LSI53C1030 supports these PCI features:

• Has a 133 MHz, 64-bit PCI/PCI-X interface that: – Operates at 33 MHz or 66 MHz PCI – Operates at up to 133 MHz PCI-X – Supports 32-bit or 64-bit data – Supports 32-bit or 64-bit addressing through Dual Address

– Provides a theoretical 1066 Mbytes/s zero wait state transfer rate – Complies with the PCI Local Bus Speciﬁcation, Revision 2.2 – Complies with the PCI-X Addendum to the PCI Local Bus

– Complies with PCI Power Management Interface Speciﬁcation,

– Complies with PC2001 System Design Guide

• Offers unmatched performance through the Fusion-MPT architecture

• Provides high throughput and low CPU utilization to off load the host processor

Cycles (DAC)

Speciﬁcation, Revision 1.0a

Revision 1.1

• Presents a single electrical load to the PCI Bus (True PCI Multifunction Device)

• Uses SCSI Interrupt Steering Logic (SISL) to provide alternate interrupt routing for RAID applications

• Reduces Interrupt Service Routine (ISR) overhead with interrupt coalescing

• Supports 32-bit or 64-bit data bursts with variable burst lengths

• Supports the PCI Cache Line Size register

• Supports the PCI Memory Write and Invalidate, Memory Read Line, and Memory Read Multiple commands

• Supports the PCI-X Memory Read Dword, Split Completion, Memory Read Block, and Memory Write Block commands

• Supports up to 8 PCI-X outstanding split transactions

• Supports Message Signalled Interrupts (MSI)

Summary of LSI53C1030 Features 1-11

1.8.3 Integration

1.8.4 Flexibility

These features make the LSI53C1030 easy to integrate:

• Is backward compatible with previous revisions of the PCI and SCSI

speciﬁcations

• Is pin compatible with the LSI53C1010R PCI to Dual Channel

Ultra160 SCSI Multifunction Controller

• Provides a low-risk migration path to Ultra320 SCSI from the

LSI53C1010R

• Is a dual channel Ultra320 SCSI to PCI/PCI-X multifunction controller

• Supports a 32-bit or 64-bit PCI/PCI-X DMA bus master

• Reduces time to market with the Fusion-MPT architecture

– Single driver binary for SCSI and Fibre Channel products – Thin, easy to develop drivers – Reduced integration and certiﬁcation effort

• Provides integrated LVDlink transceivers

These features increase the ﬂexibility of the LSI53C1030:

• Universal LVD transceivers are backward compatible with SE devices

• Provides a ﬂexible programming interface to tune I/O performance or to adapt to unique SCSI devices

• Supports MSI or pin-based (INTx/ or ALT_INTx/) interrupt signalling

• Can respond with multiple SCSI IDs

• Is compatible with 3.3 V and 5.0 V PCI signalling – Drives and receives 3.3 V PCI signals – Receives 5.0 V PCI if the PCI5VBIAS pin connects to 5 V, but

does not drive 5.0 V signals on the PCI bus

1-12 Introduction

1.8.5 Reliability

These features enhance the reliability of the LSI53C1030:

• Supports intersymbol interference (ISI) compensation

• Provides 2 kV ESD protection on SCSI signals

• Provides latch-up protection greater than 150 mA

• Provides voltage feed-through protection

• Supports LSI Logic Integrated RAID (IR) solution to provide physical mirroring or striping of the boot volume

• Has a high proportion of power and ground pins

• Provides power and ground isolation of I/O pads and internal chip logic

• Supports CRC checking and generation in Double Transition (DT) phases

• Provides comprehensive SureLINK Domain Validation technology: – Basic (Level 1) with inquiry command – Enhanced (Level 2) with read/write buffer – Margined (Level 3) with margining of drive strength and slew

rates

1.8.6 Testability

• Supports TolerANT technology, which provides: – Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved SCSI transfer rates

– Input signal ﬁltering on SCSI receivers for improved data

integrity, even in noisy cabling environments

These features enhance the testability of the LSI53C1030:

• Allows all SCSI signals to be accessed through programmed I/O

• Supports JTAG boundary scan

• Provides ARM Multi-ICE®for debugging purposes

Summary of LSI53C1030 Features 1-13

1-14 Introduction

Chapter 2 Functional Description

This chapter provides a subsytem level overview of the LSI53C1030, a discussion of the Fusion-MPT architecture, and a functional description of the LSI53C1030 interfaces. This chapter contains the following sections:

• Section 2.1, “Block Diagram Description”

• Section 2.2, “Fusion-MPT Architecture Overview”

• Section 2.3, “PCI Functional Description”

• Section 2.4, “Ultra320 SCSI Functional Description”

• Section 2.5, “External Memory Interface”

• Section 2.6, “Serial EEPROM Interface”

• Section 2.7, “Zero Channel RAID”

• Section 2.8, “Multi-ICE Test Interface”

The LSI53C1030 is a high performance, intelligent PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller. The LSI53C1030 supports the PCI Local Bus Speciﬁcation, Revision 2.2, the PCI-X Addendum to the PCI Local Bus Speciﬁcation, Revision 1.0a, and the proposed SCSI Parallel Interface-4 (SPI-4) draft standard.

The LSI53C1030 employs the LSI Logic Fusion-MPT architecture to ensure robust system performance, to support binary compatibility of host software between the LSI Logic SCSI and Fibre Channel products, and to signiﬁcantly reduce software development time. Refer to the Fusion-MPT Device Management User’s Guide for more information on the Fusion-MPT architecture.

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller 2-1

2.1 Block Diagram Description

The LSI53C1030 consists of three major modules: a host interface module and two independent Ultra320 SCSI channel modules. The modules consist of the following components:

• Host Interface Module

– Up to a 64-bit, 133 MHz PCI/PCI-X Interface – System Interface – I/O Processor (IOP) – DMA Arbiter and Router – Shared RAM – External Memory Interface

◊ Flash ROM Memory Controller ◊ NVSRAM

– Timer and Conﬁguration Control

◊ Device Conﬁguration Controller ◊ Serial EEPROM Interface Controller ◊ GPIO Interface ◊ Chip Timer

• Two independent Ultra320 SCSI Channel Modules

– Datapath Engine – Context Manager – Ultra320 SCSI Core

Figure 2.1 illustrates the relationship between these modules.

2-2 Functional Description

Figure 2.1 LSI53C1030 Block Diagram

Host Interface Module

PCI/

PCI-X

PCI/PCI-X

(ARM966E-S)

Interface

System

Interface

IOP

Primary Bus

DMA

Arbiter

and

Router

Bus to Bus

Bridge

Bus to Bus

Bridge

Shared

RAM

SCSI Channel [0] Module

Datapath Engine

Secondary [0] Bus

Context Manager

(ARM966E-S)

SCSI Channel [1] Module

Datapath Engine

Secondary [1] Bus

U320 SCSI

Core

U320

SCSI Core

U320 SCSI

External Memory

Flash ROM/

NVSRAM

Timer, GPIO,

and EEPROM

SerialGPIO

EEPROM

2.1.1 Host Interface Module Description

The host interface module provides an interface between the host driver and the two SCSI channels. The host interface module controls system DMA transfers and the host side of the LSI Logic Fusion-MPT architecture. It also supports the external memory, serial EEPROM, and General Purpose I/O (GPIO) interfaces. This section provides a detailed explanation of the host interface submodules.

Block Diagram Description 2-3

Context Manager

(ARM966E-S)

2.1.1.1 PCI Interface

The LSI53C1030 provides a PCI-X interface that supports up to a 64-bit, 133 MHz PCI-X bus. The interface is compatible with all previous implementations of the PCI speciﬁcation. For more information on the PCI interface, refer to Section 2.3, “PCI Functional Description.”

2.1.1.2 System Interface

The system interface efﬁciently passes messages between the LSI53C1030 and other I/O agents using a high performance, packetized, mailbox architecture. The system interface coalesces PCI interrupts to minimize trafﬁc on the PCI bus and maximize system performance.

All host accesses to the IOP, external memory, and timer and conﬁguration subsystems pass through the system interface and use the primary bus. The host system initiates data transactions on the primary bus with the system interface registers. PCI Memory Space [0] and the PCI I/O Base Address registers identify the location of the system interface register set. Chapter 4, “PCI Host Register Description,” provides a bit level description of the system interface register set.

2.1.1.3 I/O Processor (IOP)

The LSI53C1030 I/O processor (IOP) is a 32-bit ARM966E-S RISC processor. The IOP controls the system interface and uses the LSI Logic Fusion-MPT architecture to manage the host side of non-DMA accesses to the Ultra320 SCSI bus. The context manager uses the Fusion-MPT architecture to control the SCSI side of data transfers. The IOP and Context Manager completely manage all SCSI I/Os without host intervention. Refer to Section 2.2, “Fusion-MPT Architecture Overview,” for more information on the Fusion-MPT architecture.

2.1.1.4 DMA Arbiter and Router

The descriptor based DMA Arbiter and Router subsystem manages the transfer of memory blocks between local memory and the host system. The DMA channel includes PCI bus master interface logic, the internal bus interface logic, and a 256-byte system DMA FIFO.

2-4 Functional Description

2.1.1.5 Shared RAM

The host interface module physically contains the 96 Kbyte shared RAM. However, both the host interface module and the SCSI channel modules access the shared RAM. The shared RAM holds a portion of the IOP and context manager ﬁrmware, as well as the request message queue and reply message queue. All non-DMA data transfers that use the request and reply message queues pass through the shared RAM.

2.1.1.6 External Memory Controller

The external memory control subsystem provides a direct interface between the primary bus and the external memory subsystem. MAD[7:0] and MADP[0] comprise the external memory bus. The LSI53C1030 supports the Flash ROM and NVSRAM interfaces through the external memory controller. The Flash ROM is optional if the LSI53C1030 is not the boot device and a suitable driver exists to initialize the device. The LSI53C1030 uses the NVSRAM for write journaling when an Integrated Mirroring (IM) volume is deﬁned. Write journaling is used to verify that the mirrored disks in the IM volume are synchronized with each other. For a detailed description of this block refer to Section 2.5, “External

Memory Interface.”

During power up or reset the LSI53C1030 uses the MAD[15:0] and MADP[1:0] signals as Power-On Sense pins, which conﬁgure the LSI53C1030 through their pull-up or pull-down settings. Refer to

Section 3.10, “Power-On Sense Pins Description,”for a description of the

Power-On Sense pin conﬁguration options.

2.1.1.7 Timer, GPIO, and Conﬁguration

This subsystem provides a free running timer to allow event time stamping and also controls the general purpose I/O (GPIO), LED, and serial EEPROM interfaces. The LSI53C1030 uses the free running timer to aid in tracking and managing SCSI I/Os. The LSI53C1030 generates the free running timer’s microsecond time base by dividing the SCSI reference clock by 40.

The LSI53C1030 provides eight GPIO pins (GPIO[7:0]). These pins are under the control of the LSI53C1030 and default to the input mode upon PCI reset. The LSI53C1030 also provides three LED pins: A_LED/, B_LED/, and HB_LED/. Either ﬁrmware or hardware control A_LED/ and

Block Diagram Description 2-5

B_LED/. The LSI53C1030 ﬁrmware controls HB_LED/ (heartbeat LED), which indicates that the IOP is operational.

A 2-wire serial interface provides a connection to a nonvolatile external serial EEPROM. The serial EEPROM stores PCI conﬁguration parameters for the LSI53C1030. Refer to Section 2.6, “Serial EEPROM

Interface,” for more information concerning the serial EEPROM.

2.1.2 SCSI Channel Module Description

The LSI53C1030 provides two independent Ultra320 SCSI bus channels. Separate Ultra320 SCSI cores, datapath engines, and context managers support each SCSI channel. Refer to Section 2.4, “Ultra320 SCSI

Functional Description,” for an operational description of the LSI53C1030

SCSI bus channels.

2.1.2.1 Ultra320 SCSI Cores

The Ultra320 SCSI cores control their individual SCSI bus interface.

2.1.2.2 Datapath Engines

The datapath engines manage the SCSI side of DMA transactions between their individual SCSI bus and the host system.

2.1.2.3 Context Managers

The context managers are ARM966E-S processors. Each context manager controls the SCSI channel side of the LSI53C1030 Fusion-MPT architecture for their individual SCSI bus. The context managers control the outbound queues, target mode I/O mapping, disconnect and reselect sequences, scatter/gather lists, and status reports.

2.2 Fusion-MPT Architecture Overview

The Fusion-MPT architecture provides two I/O methods for the host system to communicate with the IOP: the system interface doorbell and the message queues.

The system interface doorbell is a simple message passing mechanism that allows the PCI host system and IOP to exchange single 32-bit Dword

2-6 Functional Description

messages. When the host system writes to the doorbell, the LSI53C1030 hardware generates a maskable interrupt to the IOP, which can then read the doorbell value and take the appropriate action. When the IOP writes a value to the doorbell, the LSI53C1030 hardware generates a maskable interrupt to the host system. The host system can then read the doorbell value and take the appropriate action.

There are two 32-bit message queues: the request message queue and the reply message queue. The host uses the request queue to request an action by the LSI53C1030, and the LSI53C1030 uses the reply queue to return status information to the host. The request message queue consists of only the request post FIFO. The reply message queue consists of both the reply post FIFO and the reply free FIFO. The shared RAM contains the message queues.

Communication using the message queues occurs through request messages and reply messages. Request message frame descriptors are pointers to the request message frames and are passed through the request post FIFO. The request message frame data structure is up to 128 bytes in length and includes a message header and a payload. The header uniquely identiﬁes the message. The payload contains information that is speciﬁc to the request. Reply message frame descriptors have one of two formats and are passed through the reply post FIFO. When indicating the successful completion of a SCSI I/O, the IOP writes the reply message frame descriptor using the Context Reply format, which is a message context. If a SCSI I/O does not complete successfully, the IOP uses the Address Reply format. In this case, the IOP pops a reply message frame from the reply free FIFO, generates a reply message describing the error, writes the reply message to system memory, and writes the address of the reply message frame to the reply post FIFO. The host can then read the reply message and take the appropriate action.

The doorbell mechanism provides both a high-priority communication path that interrupts the host system device driver and an alternative communication path to the message queues. Since data transport through the system doorbell occurs a single Dword at a time, use the LSI53C1030 message queues for normal operation and data transport.

Fusion-MPT Architecture Overview 2-7

2.3 PCI Functional Description

The host PCI interface complies with the PCI Local Bus Speciﬁcation, Revision 2.2, and the PCI-X Addendum to the PCI Local Bus Speciﬁcation, Revision 1.0a. The LSI53C1030 supports up to a 133 MHz,

64-bit PCI-X bus. The LSI53C1030 provides support for 64-bit addressing with Dual Address Cycle (DAC).

The LSI53C1030 is a true multifunction PCI-X device and presents a single electrical load to the PCI bus. The LSI53C1030 uses a single REQ/-GNT/ pair to arbitrate for PCI bus mastership. Separate interrupt signals for PCI Function [0] and PCI Function [1] allow independent control of the two PCI functions.

2.3.1 PCI Addressing

The three physical address spaces the PCI speciﬁcation deﬁnes are:

• PCI Conﬁguration Space

• PCI I/O Space for operating registers

• PCI Memory Space for operating registers

The following sections describe the PCI address spaces.

2.3.1.1 PCI Conﬁguration Space

The LSI53C1030 deﬁnes an independent set of PCI Conﬁguration Space registers for each PCI function. Each conﬁguration space is a contiguous 256 x 8-bit set of addresses. The system BIOS initializes the conﬁguration registers using PCI conﬁguration cycles. The LSI53C1030 decodes C_BE[3:0]/ to determine if a PCI cycle intends to access the conﬁguration register space. The IDSEL signal behaves as a chip select signal that enables access to the conﬁguration register space only. The LSI53C1030 ignores conﬁguration read/write cycles when IDSEL is not asserted.

Since the LSI53C1030 is a multifunction PCI device, bits AD[10:8] decode either the PCI Function [0] Conﬁguration Space (AD[10:8] = 0b000) or the PCI Function [1] Conﬁguration Space (AD[10:8] = 0b001). The LSI53C1030 does not respond to any other encodings of AD[10:8].

2-8 Functional Description

Bits AD[7:2] select one of the sixty-four Dword registers in the device’s PCI Conﬁguration Space. Bits AD[1:0] determine if the conﬁguration command is a Type 0 Conﬁguration Command (AD[1:0] = 0b00) or a Type 1 Conﬁguration Command (AD[1:0] = 0b01). Since the LSI53C1030 is not a PCI Bridge device, all PCI Conﬁguration Commands designated for the LSI53C1030 must be Type 0. C_BE[3:0]/ address the individual bytes within each Dword and determine the type of access to perform.

2.3.1.2 PCI I/O Space

The PCI speciﬁcation deﬁnes I/O Space as a contiguous 32-bit I/O address that all system resources share, including the LSI53C1030. The

I/O Base Address register determines the 256-byte PCI I/O area that the

PCI device occupies.

2.3.1.3 PCI Memory Space

The LSI53C1030 contains two PCI memory spaces: PCI Memory Space [0] and PCI Memory Space [1]. PCI Memory Space [0] supports normal memory accesses, while PCI Memory Space [1] supports diagnostic memory accesses. The LSI53C1030 requires 64 Kbytes of memory space.

The PCI speciﬁcation deﬁnes memory space as a contiguous 64-bit memory address that all system resources share. The Memory [0] Low and Memory [0] High registers determine which 64 Kbyte memory area PCI Memory Space [0] occupies. The Memory [1] Low and Memory [1]

High registers determine which 64 Kbyte memory area PCI Memory

Space [1] occupies.

2.3.2 PCI Commands and Functions

Bus commands indicate to the target the type of transaction the master is requesting. The master encodes the bus commands on the C_BE[3:0]/ lines during the address phase. The PCI bus command encodings appear in Table 2.1.

PCI Functional Description 2-9

Table 2.1 PCI/PCI-X Bus Commands and Encodings

C_BE[3:0]/ PCI Command PCI-X Command

Supports

as Master

Supports

0b0000 Interrupt Acknowledge Interrupt Acknowledge No No 0b0001 Special Cycle Special Cycle No No 0b0010 I/O Read I/O Read Yes Yes 0b0011 I/O Write I/O Write Yes Yes 0b0100 Reserved Reserved N/A N/A 0b0101 Reserved Reserved N/A N/A 0b0110 Memory Read Memory Read Dword Yes Yes 0b0111 Memory Write Memory Write Yes Yes 0b1000 Reserved Alias to

Memory Read Block

0b1001 Reserved Alias to

Memory Write Block

PCI: N/A

PCI-X: No

PCI: N/A

PCI-X: No

PCI-X: Yes

PCI-X: Yes 0b1010 Conﬁguration Read Conﬁguration Read No Yes 0b1011 Conﬁguration Write Conﬁguration Write No Yes 0b1100 Memory Read Multiple Split Completion Yes Yes

as Slave

PCI: N/A

0b1101 Dual Address Cycle Dual Address Cycle Yes Yes 0b1110 Memory Read Line Memory Read Block Yes Yes 0b1111 Memory Write and Invalidate Memory Write Block Yes Yes

1. The LSI53C1030 ignores reserved commands as a slave and never generates them as a master.

2. When acting as a slave in the PCI mode, the LSI53C1030 supports this command as the PCI Memory Read command.

3. When acting as a slave in the PCI mode, the LSI53C1030 supports this command as the PCI Memory Write command.

The following sections describe how the LSI53C1030 implements these commands.

2.3.2.1 Interrupt Acknowledge Command

The LSI53C1030 ignores this command as a slave and never generates it as a master.

2-10 Functional Description

2.3.2.2 Special Cycle Command

The LSI53C1030 ignores this command as a slave and never generates it as a master.

2.3.2.3 I/O Read Command

The I/O Read command reads data from an agent mapped in the I/O address space. When decoding I/O commands, the LSI53C1030 decodes the lower 32 address bits and ignores the upper 32 address bits. The LSI53C1030 supports this command when operating in either the PCI or PCI-X bus mode.

2.3.2.4 I/O Write Command

The I/O Write command writes data to an agent mapped in the I/O address space. When decoding I/O commands, the LSI53C1030 decodes the lower 32 address bits and ignores the upper 32 address bits. The LSI53C1030 supports this command when operating in either the PCI or PCI-X bus mode.

2.3.2.5 Memory Read Command

The LSI53C1030 uses the Memory Read command to read data from an agent mapped in the memory address space. The target can perform an anticipatory read if such a read produces no side effects. The LSI53C1030 supports this command when operating in the PCI bus mode.

2.3.2.6 Memory Read Dword Command

The Memory Read Dword command reads up to a single Dword of data from an agent mapped in the memory address space and can only be initiated as a 32-bit transaction. The target can perform an anticipatory read if such a read produces no side effects. The LSI53C1030 supports this command when operating in the PCI-X bus mode.

2.3.2.7 Memory Write Command

The Memory Write command writes data to an agent mapped in the memory address space. The target assumes responsibility for data coherency when it returns “ready.” The LSI53C1030 supports this command when operating in either the PCI or PCI-X bus mode.

PCI Functional Description 2-11

2.3.2.8 Alias to Memory Read Block Command

This command is reserved for future implementations of the PCI speciﬁcation. The LSI53C1030 never generates this command as a master.When a slave, the LSI53C1030 supports this command using the Memory Read Block command.

2.3.2.9 Alias to Memory Write Block Command

2.3.2.10 Conﬁguration Read Command

The Conﬁguration Read command reads the conﬁguration space of a device. The LSI53C1030 nevergenerates this command as a master, but does respond to it as a slave. A device on the PCI bus selects the LSI53C1030 by asserting its IDSEL signal when AD[1:0] equal 0b00. During the address phase of a conﬁguration cycle, AD[7:2] address one of the 64 Dword registers in the conﬁguration space of each device. C_BE[3:0]/ address the individual bytes within each Dword register and determine the type of access to perform. Bits AD[10:8] address either the PCI Function [0] Conﬁguration Space (AD[10:8] = 0b000) or the PCI Function [1] Conﬁguration Space (AD[10:8] = 0b001). The LSI53C1030 treats AD[63:11] as logical don’t cares.

2.3.2.11 Conﬁguration Write Command

The Conﬁguration Write command writes the conﬁguration space of a device. The LSI53C1030 nevergenerates this command as a master, but does respond to it as a slave. A device on the PCI bus selects the LSI53C1030 by asserting its IDSEL signal when bits AD[1:0] equal 0b00. During the address phase of a conﬁguration cycle, bits AD[7:2] address one of the 64 Dword registers in the conﬁguration space of each device. C_BE[3:0]/ address the individual bytes within each Dword register and determine the type of access to perform. Bits AD[10:8] decode either the PCI Function [0] Conﬁguration Space (AD[10:8] = 0b000) or the PCI Function [1] Conﬁguration Space (AD[10:8] = 0b001). The LSI53C1030 treats AD[63:11] as logical don’t cares.

2-12 Functional Description

2.3.2.12 Memory Read Multiple Command

The Memory Read Multiple command is identical to the Memory Read command, except it additionally indicates that the master intends to fetch multiple cache lines before disconnecting. The LSI53C1030 supports PCI Memory Read Multiple functionality when operating in the PCI mode and determines when to issue a Memory Read Multiple command instead of a Memory Read command.

Burst Size Selection – The Read Multiple command reads multiple cache lines of data during a single bus ownership. The number of cache lines the LSI53C1030 reads is a multiple of the cache line size, which Revision 2.2 of the PCI speciﬁcation provides. The LSI53C1030 selects the largest multiple of the cache line size based on the amount of data to transfer.

2.3.2.13 Split Completion Command

Split transactions in PCI-X replace the delayed transactions in conventional PCI. The LSI53C1030 supports up to eight outstanding split transactions when operating in the PCI-X mode. A split transaction consists of at least two separate bus transactions: a split request, which the requester initiates, and one or more split completion commands, which the completer initiates. Revision 1.0a of the PCI-X addendum permits split transaction completion for the Memory Read Block, Alias to Memory Read Block, Memory Read Dword, Interrupt Acknowledge, I/O Read, I/O Write, Conﬁguration Read, and Conﬁguration Write commands. When operating in the PCI-X mode, the LSI53C1030 supports the Split Completion command for all of these commands except the Interrupt Acknowledge command, which the LSI53C1030 neither responds to nor generates.

2.3.2.14 Dual Address Cycles (DAC) Command

The LSI53C1030 performs Dual Address Cycles (DAC), per the PCI Local Bus Speciﬁcation, Revision 2.2. The LSI53C1030 supports this

command when operating in either the PCI or PCI-X bus mode.

PCI Functional Description 2-13

2.3.2.15 Memory Read Line Command

This command is identical to the Memory Read command except it additionally indicates that the master intends to fetch a complete cache line. The LSI53C1030 supports this command when operating in the PCI mode.

2.3.2.16 Memory Read Block Command

The LSI53C1030 uses this command to read from memory. The LSI53C1030 supports this command when operating in the PCI-X mode.

2.3.2.17 Memory Write and Invalidate Command

The Memory Write and Invalidate command is identical to the Memory Write command, except it additionally guarantees a minimum transfer of one complete cache line. The master uses this command when it intends to write all bytes within the addressed cache line in a single PCI transaction unless interrupted by the target. This command requires implementation of the PCI Cache Line Size register. The LSI53C1030 determines when to issue a Write and Invalidate command instead of a Memory Write command and supports this command when operating in the PCI bus mode.

Alignment – The LSI53C1030 uses the calculated line size value to determine if the current address aligns to the cache line size. If the address does not align, the LSI53C1030 bursts data using a noncache command. If the starting address aligns, the LSI53C1030 issues a Memory Write and Invalidate command using the cache line size as the burst size.

Multiple Cache Line Transfers – The Memory Write and Invalidate command can write multiple cache lines of data in a single bus ownership. The LSI53C1030 issues a burst transfer as soon as it reaches a cache line boundary. The PCI Local Bus speciﬁcation states that the transfer size must be a multiple of the cache line size. The LSI53C1030 selects the largest multiple of the cache line size based on the transfer size. When the DMA buffer contains less data than the value

Cache Line Size register speciﬁes, the LSI53C1030 issues a Memory

Write command on the next cache boundary to complete the data transfer.

2-14 Functional Description

2.3.2.18 Memory Write Block Command

The LSI53C1030 uses this command to burst data to memory. The LSI53C1030 supports this command when operating in the PCI-X bus mode.

2.3.3 PCI Arbitration

The LSI53C1030 contains independent bus mastering functions for each of the SCSI functions and for the system interface. The system interface bus mastering function manages DMA operations as well as the request and reply message frames. The SCSI channel bus mastering functions manage data transfers across the SCSI channels.

The LSI53C1030 uses a single REQ/-GNT/ signal pair to arbitrate for access to the PCI bus. To ensure fair access to the PCI bus, the internal arbiter uses a round robin arbitration scheme to decide which of the three internal bus mastering functions can arbitrate for access to the PCI bus.

2.3.4 PCI Cache Mode

The LSI53C1030 supports an 8-bit Cache Line Size register. The Cache

Line Size register provides the ability to sense and react to nonaligned

addresses corresponding to cache line boundaries. The LSI53C1030 determines when to issue a PCI cache command (Memory Read Line, Memory Read Multiple, and Memory Write and Invalidate), or PCI noncache command (Memory Read or Memory Write command).

2.3.5 PCI Interrupts

The LSI53C1030 signals an interrupt to the host processor either using PCI interrupt pins, INTx/ and ALT_INTx/, or using Message Signalled Interrupts (MSI). If using the PCI interrupt pins, the Interrupt Request Routing Mode bits in the Host Interrupt Mask register conﬁgure the routing of each interrupt to either the INTx/ and/or the ALT_INTx/ pin. The Interrupt Pin register conﬁgures the routing of each PCI function’s interrupt signals to either the interrupt A pins (INTA/, ALT_INTA/) or the interrupt B pins (INTB/ or ALT_INTB/).

If using MSI, the LSI53C1030 does not signal interrupts on INTx/ or ALT_INTx/. Note that enabling MSI to mask PCI interrupts is a violation of the PCI speciﬁcation. Each PCI function of the LSI53C1030

PCI Functional Description 2-15

implements its own MSI register set. The LSI53C1030 supports one requested message and disables MSI after the chip powers-up or resets.

The Host Interrupt Mask register also prevents the assertion of a PCI interrupt to the host processor by selectively masking reply interrupts and system doorbell interrupts. This register masks both pin-based and MSIbased interrupts.

2.3.6 Power Management

The LSI53C1030 complies with the PCI Power Management Interface Speciﬁcation, Revision 1.1, and the PC2001 System Design Guide. The

LSI53C01030 supports the D0, D1, D2, D3 D0 is the maximum power state, and D3 is the minimum power state. Power State D3 is further categorized as D3 function off places it in the D3

Bits [1:0] of the Power Management Control/Status register independently control the power state of each PCI device on the LSI53C1030. Table 2.2 provides the power state bit settings.

Table 2.2 Power States

Power Management Control and

Status Register, Bits [1:0] Power State Function

Power State.

cold

, and D3

hot

or D3

power states.

cold

. Powering a

cold

0b00 D0 Maximum Power 0b01 D1 Snooze Mode 0b10 D2 Coma Mode 0b11 D3 Minimum Power

The following sections describe the PCI Function Power States D0, D1, D2, and D3. As the device transitions from one power level to a lower one, the attributes that occur in the higher power state level carry into the lower power state level. For example, Power State D2 includes the attributes for Power State D1, as well as the attributes deﬁned for Power State D2. The following sections describe the PCI Function power states in conjunction with each SCSI function. Power state actions are separate for each SCSI function.

2-16 Functional Description

2.3.6.1 Power State D0

Power State D0 is the maximum power state and is the power-up default state for each function. The LSI53C1030 is fully functional in this state.

2.3.6.2 Power State D1

Per the PCI Power Management Interface Speciﬁcation, Power State D1 must have an equal or lower power level than Power State D0. A function in Power State D1 places the SCSI core in the snooze mode. In the snooze mode, a SCSI reset does not generate an IRQ/ signal.

2.3.6.3 Power State D2

Per the PCI Power Management Interface Speciﬁcation, Power State D2 must have an equal or lower power level than Power State D1. A function in this state places the SCSI core in the coma mode. Placing the PCI Function in Power State D2 disables the SCSI and DMA interrupts, and suppresses the following PCI Conﬁguration Space Command register enable bits:

• I/O Space Enable

• Memory Space Enable

• Bus Mastering Enable

• SERR/Enable

• Enable Parity Error Response

Therefore, the function's memory and I/O spaces cannot be accessed, and the PCI function cannot be a PCI bus master.

If the PCI function is changed from Power State D2 to Power State D1 or D0, the PCI function restores the previous values of the PCI

Command register and asserts any interrupts that were pending before

the function entered Power State D2.

2.3.6.4 Power State D3

Per the PCI Power Management Interface Speciﬁcation, Power State D3 must have an equal or lower power level than Power State D2. Power State D3 is the minimum power state and includes the D3 settings. D3

PCI Functional Description 2-17

hot

allows the device to transition to D0 using software. D3

hot

and D3

cold cold

removes power from the LSI53C1030. D3 applying VCC and resetting the device.

Placing a function in Power State D3 puts the LSI53C1030 core in the coma mode, clears the function's PCI Command register, and continually asserts the function's soft reset. Asserting soft reset clears all pending interrupts and 3-states the SCSI bus.

2.4 Ultra320 SCSI Functional Description

The LSI53C1030 provides two independent Ultra320 SCSI channels on a single chip. Each channel supports wide SCSI synchronous transfer rates up to 320 Mbytes/s across an SE or LVD SCSI bus. The integrated LVDlink transceivers support both LVD and SE signals and do not require external transceivers. The LSI53C1030 controller supports the Ultra320 SCSI, Ultra160 SCSI, Ultra2 SCSI, Ultra SCSI, and Fast SCSI interfaces.

2.4.1 Ultra320 SCSI Features

This section describes how the LSI53C1030 implements the features in the SPI-4 draft speciﬁcation.

can transition to D0 by

cold

2.4.1.1 Parallel Protocol Request (PPR)

A SCSI extended message negotiates the PPR parameters. The PPR parameters include the (1) transfer period, (2) maximum REQ/ACK offset, (3) QAS, (4) margin control settings (MCS), (5) transfer width, (6) IU_Request, (7) write ﬂow, (8) read streaming, (9) RTI, (10) precompensation enable, (11) information unit transfers, and the (12) DT data phases between an initiator and a target.

2.4.1.2 Double Transition (DT) Clocking

Ultra160 SCSI and Ultra320 SCSI implement DT clocking to provide speeds up to 80 megatransfers per second (megatransfers/s) for Ultra160 SCSI, and up to 160 megatransfers/s for Ultra320 SCSI. When implementing DT clocking, a SCSI device samples data on both the asserting and deasserting edge of REQ/ACK. DT clocking is only valid using an LVD SCSI bus.

2-18 Functional Description

2.4.1.3 Intersymbol Interference (ISI) Compensation

ISI Compensation uses paced transfers and precompensation to enable high data transfer rates. Ultra320 SCSI data transfers require the use of ISI Compensation.

Paced Transfers – The initiator and target must establish a paced transfer agreement that speciﬁes the REQ/ACK offset and the transfer period before using this feature. Devices can only perform paced transfers during Ultra320 SCSI DT data phases. In paced transfers, the device sourcing the data drives the REQ/ACK signal as a free running clock. The transition of the REQ/ACK signal, either the assertion or the negation, clocks data across the bus. For successful completion of a paced transfer, the number of ACK transitions must equal the number of REQ transitions and both the REQ and ACK lines must be negated.

The P1 line indicates valid data in 4-byte quantities by using its phase. The transmitting device indicates the start of valid data state by holding the state of the P1 line for the ﬁrst two data transfer periods. Beginning on the third data transfer period, the transmitting device continues the valid data state by toggling the state of the P1 line every two data transfer periods for as long as the data is valid. The transmitting device must toggle the P1 line coincident with the REQ/ACK assertion. The method provides a minimum data valid period of two transfer periods.

To pause the data transfer, the transmitting device reverses the phase of P1 by withholding the next transition of P1 at the start of the ﬁrst two invalid data transfer periods. Beginning with the third invalid data transfer period, the transmitting device toggles the P1 line every two invalid data transfer periods until it sends valid data. The transmitting device returns to the valid data state by reversing the phase of the P1 line. The invalid data state must experience at least one P1 transition before returning to the valid data state. This method provides a minimum data invalid period of four transfer periods.

Figure 2.2 provides a waveform diagram of paced data transfers and

illustrates the use of the P1 line.

Ultra320 SCSI Functional Description 2-19

Figure 2.2 Paced Transfer Example

Data Not ValidData Valid Data Valid Data Not Valid

REQ

ACK

DATA

The LSI53C1030 uses the PPR negotiation that the SPI-4 draft standard describes to establish a paced transferagreement for each initiator-target pair.

Precompensation – When transmitting in the Ultra320 SCSI mode, the LSI53C1030 uses precompensation to adjust the strength of the REQ, ACK, parity, and data signals. When a signal transitions to HIGH or LOW, the LSI53C1030 boosts the signal drive strength for the ﬁrst data transfer period, and then lowers the signal drive strength on the second data transfer period if the signal remains in the same state. The LSI53C1030 maintains the lower signal drive strength until the signal again transitions HIGH or LOW. Figure 2.3 illustrates the drivers performance with precompensation enabled and disabled.

2-20 Functional Description

Figure 2.3 Example of Precompensation

a. Drivers with Precompensation Disabled

Normal Drive Strength

b. Drivers with Precompensation Enabled

Boosted Drive Strength

2.4.1.4 Packetized Transfers

Packetized transfers are also referred to as information unit transfers. They reduce overhead on the SCSI bus by merging several of the SCSI bus phases. Packetized transfers can only occur in DT Data phases. The initiator and target must establish either a DT synchronous transfer agreement or a paced transfer agreement before performing packetized transfers.

The number of bytes in an information unit transfer is always a multiple of four. If the number of bytes to transfer in the information unit is not a multiple of four, the LSI53C1030 transmits pad bytes to bring the byte count to a multiple of four.

2.4.1.5 Quick Arbitration and Selection (QAS)

When using packetized transfers, QAS allows devices to arbitrate for the bus immediately after the message phase. QAS reduces the bus

Normal Drive Strength

Ultra320 SCSI Functional Description 2-21

overhead and maximizes bus bandwidth by skipping the bus free phase that normally follows a SCSI connection.

To perform QAS, the target sends a QAS request message to the initiator during the message phase of the bus. QAS capable devices snoop the SCSI bus for the QAS request message. If a QAS request message is seen, devices can immediately move to the arbitration phase without going to the bus free phase. The LSI53C1030 employs a fairness algorithm to ensure that all devices have equal bus access.

2.4.1.6 Skew Compensation

The LSI53C1030 provides a method to account for and control system skew between the clock and data signals. Skew compensation is only available when the device operates in the Ultra320 SCSI mode. The initiator-target pair uses the training sequences in the SPI-4 draft standard to determine the skew compensation. Depending on the state of the RTI bit in the PPR negotiation, the LSI53C1030 can either execute this training pattern during each connection, or can execute the training pattern, store the adjustment parameters, and recall them on subsequent connections with the given device. The target determines when to execute the training pattern.

2.4.1.7 Cyclic Redundancy Check (CRC)

Ultra320 SCSI and Ultra160 SCSI devices employ CRC as an error detection code during the DT Data phases. These devices transfer four CRC bytes during the DT Data phases to ensure reliable data transfers.

2.4.1.8 SureLINK Domain Validation

SureLINK Domain Validation establishes the integrity of a SCSI bus connection between an initiator and a target. Under the SureLINK Domain Validation procedure, a host queries a device to determine its ability to communicate at the negotiated data transfer rate.

SureLINK Domain Validation provides 3 levels of integrity checking: Basic (Level 1) with inquiry command, Enhanced (Level 2) with read/write buffer, and Margined (Level 3) with drive strength margining and slew rate control. The basic check consists of an inquiry command to detect gross problems. The enhanced check sends a known data pattern using the read and write buffer commands to detect additional problems. The

2-22 Functional Description

margined check veriﬁes that the physical parameters have a reasonable operating margin. Use SureLINK Domain Validation only during the diagnostic system checks and not during normal system operation. If transmission errors occur during any of these checks, the system can reduce the transmission rate on a per-target basis to ensure robust system operation.

2.4.2 SCSI Bus Interface

This section describes the SCSI bus modes that the LSI53C1030 supports and the SCSI bus termination methods necessary to operate a high speed SCSI bus.

2.4.2.1 SCSI Bus Modes

The LSI53C1030 supports SE and LVD transfers. To increase device connectivity and SCSI cable length, the LSI53C1030 features LVDlink technology, which is the LSI Logic implementation of LVD SCSI. LVDlink transceivers provide the inherent reliability of differential SCSI and a long-term migration path for faster SCSI transfer rates.

The A_DIFFSENS or B_DIFFSENS signals detect the different input voltages for HVD, LVD, and SE. The LSI53C1030 drivers are tolerant of HVD signal strengths, but do not support the HVD bus mode. The LSI53C1030 SCSI device 3-states its SCSI drivers when it detects an HVD signal level.

2.4.2.2 SCSI Termination

The terminator networks pull signals to an inactive voltage level and match the impedance seen at the end of the cable to the characteristic impedance of the cable. Install terminators at the extreme ends of the SCSI chain, and only at the ends; all SCSI buses must have exactly two terminators.

Note: If using the LSI53C1030 in a design with an 8-bit SCSI bus,

Ultra320 SCSI Functional Description 2-23

designers must terminate all 16 data lines.

2.5 External Memory Interface

The LSI53C1030 provides Flash ROM, NVSRAM, and serial EEPROM interfaces. The Flash ROM interface stores the SCSI BIOS and ﬁrmware image. The Flash ROM is optional if the LSI53C1030 is not the boot device and a suitable driver exists to initialize the LSI53C1030. Integrated Mirroring (IM) technology requires an NVSRAM for write journaling. The nonvolatile external serial EEPROM stores conﬁguration parameters for the LSI53C1030.

2.5.1 Flash ROM Interface

The Flash ROM interface multiplexes the 8-bit address and data buses on the MAD[7:0] pins. The interface latches the address into three 8-bit latches to support up to 1 Mbyte of address space. The interface supports byte, word, and Dword accesses. The LSI53C1030 Dword aligns Dword reads, word aligns word reads, and byte aligns byte reads. The remaining bits from word and byte reads are meaningless.

The MAD[2:1] Power-On sense pin conﬁgurations deﬁne the size of the Flash ROM address space. Table 2.3 provides the pin encoding for these pins. By default, internal logic pulls these pins down to indicate that no Flash ROM is present.

Table 2.3 Flash ROM Size Programming

MAD[2:1] Options Flash ROM Size

0b00 No Flash ROM present (Default) 0b01 Up to 1024 Kbytes 0b10 0b11

1. Choose this setting for a 128 Kbyte or 512 Kbyte Flash ROM.

The LSI53C1030 deﬁnes only the middle (MA[15:8]) and lower (MA[7:0]) address ranges if the Flash ROM addressable space is 64 Kbytes or less. The LSI53C1030 deﬁnes the upper (MA[21:16]), middle (MA[15:8]), and lower (MA[7:0]) address ranges if the Flash ROM addressable space

2-24 Functional Description

Reserved

is 128 Kbytes or more. Figure 2.4 provides an example of a Flash ROM conﬁguration.

Figure 2.4 Flash ROM Block Diagram

FLSHALE[1]/ FLSHALE[0]/

FLSHALE[1]/

FLSHALE[0]/

MAD[7:0]

FLSHCE/

MOE/

BWE[0]/

Upper Address

Middle Address CK

Lower Address

A[21:16]

A[15:8]

A[7:0]

Flash ROM (512 K x 8)

D[7:0]

CE/ OE/ WE/

The LSI53C1030 implements a Flash signature recognition mechanism to determine if the Flash contains a valid image. The Flash can be present and not contain a valid image either before its initial programming or during board testing. The ﬁrst access to the Flash is a 16-byte burst read beginning at Flash address 0x000000. The LSI53C1030 compares the values read to the Flash signature values that

Table 2.4 provides. If the signature values match, the LSI53C1030

performs the instruction located at Flash address 0x000000. If the signature values do not match, the LSI53C1030 records an error and ignores the Flash instruction. The Flash signature does not include the ﬁrst three bytes of Flash memory as these bytes contain a branch offset instruction.

External Memory Interface 2-25

Table 2.4 Flash Signature Value

Flash Address Flash Signature Values

Bytes [3:0] 0xEA Bytes [7:4] 0x5A 0xEA 0xA5 0x5A

Bytes [11:8] 0xA5 0x5A 0xEA 0xA5

Bytes [15:12] 0x5A 0xA5 0x5A 0xEA

2.5.2 NVSRAM Interface

The LSI53C1030 Fusion-MPT ﬁrmware is capable of maintaining an Integrated Mirroring (IM) volume of the boot drive. IM ﬁrmware requires a 32 Kbyte NVSRAM in order to perform write journaling. Write journaling is used to verify that the mirrored disks in the IM volume are synchronized with each other. The NVSRAM also stores additional code and data used for error and exception handling, and it stores IM conﬁguration information during serial EEPROM updates. The disk write log uses approximately 4 Kbytes of the NVSRAM.

Figure 2.5 provides a block diagram illustrating how to connect the

NVSRAM. This design employs the CPLD to latch the address instead of using separate address latches.

When using an NVSRAM, pull the MAD[3] Power-On Sense pin HIGH during board boot-up. This conﬁgures the external memory interface as an NVSRAM interface. During operation, RAMCE/ selects the NVSRAM when MAD[3] is pulled HIGH.

XX XX XX

2-26 Functional Description

Figure 2.5 NVSRAM Diagram

FLSHALE[1:0]/

MAD[7:0]

RAMCE/

MOE/

BWE[0]/

2.6 Serial EEPROM Interface

The nonvolatile external serial EEPROM stores conﬁguration ﬁelds for the LSI53C1030. The serial EEPROM contains ﬁelds for the Subsystem ID(s), Subsystem Vendor ID(s), and the size of the PCI Diagnostic Memory Space. The LSI53C1030 must establish each of these parameters prior to reading system BIOS and loading the PCI Conﬁguration Space registers. The power-on option settings enable the download of PCI conﬁguration data from the serial EEPROM. For more information on the setting of the power-on options, refer to Section 3.10,

“Power-On Sense Pins Description.”

CPLD

CY37032

MAS[1:0]

MAD[7:0]

MAD[14:0] A[14:0]

D[7:0] CE/

OE/ WE/

3.3 V

NVSRAM (32 K x 8)

A 2-wire serial interface provides the connection to the serial EEPROM. During initialization, the ﬁrmware checks if a serial EEPROM exists. Firmware uses the checksum byte to determine if the conﬁguration held in the serial EEPROM is valid. If the checksum fails the ﬁrmware checks for a valid NVData signature. If a valid NVData signature is found the ﬁrmware individually checksums each persistent conﬁguration page to ﬁnd the invalid page or pages. Table 2.5 provides the structure of the conﬁguration record in the serial EEPROM.

Serial EEPROM Interface 2-27

Table 2.5 PCI Conﬁguration Record in Serial EEPROM

EEPROM Address Conﬁguration Data

0x00 PCI Function [0] Subsystem ID, bits [7:0] 0x01 PCI Function [0] Subsystem ID, bits [15:8] 0x02 PCI Function [0] Subsystem Vendor ID, bits [7:0] 0x03 PCI Function [0] Subsystem Vendor ID, bits [15:8] 0x04 PCI Diagnostic Memory Size 0x05 Reserved 0x06 PCI Function [1] Subsystem ID, bits [7:0] 0x07 PCI Function [1] Subsystem ID, bits [15:8] 0x08 PCI Function [1] Subsystem Vendor ID, bits [7:0] 0x09 PCI Function [1] Subsystem Vendor ID, bits [15:8] 0x0A Checksum

2.7 Zero Channel RAID

Zero channel RAID (ZCR) capabilities enable the LSI53C1030 to respond to accesses from a PCI RAID controller card or chip that is able to generate ZCR cycles. The LSI53C1030’s ZCR functionality is controlled through the ZCR_EN/ and the IOPD_GNT/ signals. Both of these signals have internal pull-ups and are active LOW.

The ZCR_EN/ signal enables ZCR support on the LSI53C1030. Pulling ZCR_EN/ HIGH disables ZCR support on the LSI53C1030 and causes the LSI53C1030 to behave as a normal PCI-X to Ultra320 SCSI controller. When ZCR is disabled, the IOPD_GNT/ signal has no effect on the LSI53C1030 operation.

Pulling ZCR_EN/ LOW enables ZCR operation. When ZCR is enabled, the LSI53C1030 responds to PCI conﬁguration cycles when the IOPD_GNT/ and IDSEL signal are asserted. Connect the IOPD_GNT/ pin on the LSI53C1030 to the PCI GNT/ signal of the external I/O processor. This allows the I/O processor to perform PCI conﬁguration

2-28 Functional Description

cycles to the LSI53C1030 when the I/O processor is granted the PCI bus. This conﬁguration also prevents the system processor from accessing the LSI53C1030 PCI conﬁguration registers.

LSI53C1030 based designs do not use the M66EN pin to determine the PCI bus speed.

Figure 2.6 illustrates how to connect the LSI53C1030 to enable ZCR.

This ﬁgure also contains information for connecting the LSI53C1010R based designs to a ZCR design and migrating from LSI53C1010R based designs to LSI53C1030 based designs. Notice that the LSI53C1030 does not require the 2:1 mux.

Figure 2.6 ZCR Circuit Diagram for LSI53C1030 and LSI53C1010R

ZCR PCI

Slot

Int A/ (A6) Int B/ (B7) Int C/ (A7) Int D/ (B8)

Vdd

0.1 kΩ

Vdd

0.1 kΩ

4.7 kΩ

TDI (A4)

GNT/ (A17)

TMS (A3)

IDSEL (A26)

AD21 (B29)

Host System

Int A/ Int B/

Int C/

Int D/

AD21 AD19

Note: To maintain proper interrupt mapping, select the address line for use as IDSEL on the

LSI53C1010R/LSI53C1030 to be +2 address lines above IDSEL on ZCR slot.

Vdd

0.1 kΩ Vdd

0.1 kΩ

4.7 kΩ

No Pop for LSI53C1030

0.1 kΩ

220 Ω

2:1 Mux

A1 S0

0 Ω No Pop for LSI53C1010R

No Pop for LS53C1010R

Zero Channel RAID 2-29

0 Ω

LSI53C1010R/ LSI53C1030

INTA/ (AC8) INTB/ (AE7)

ZCR_EN/ (N23) IOPD_ GNT/ (AC5)

IDSEL (AC13)

LSI53C1030 Only

2.8 Multi-ICE Test Interface

This section describes the LSI Logic requirements for the Multi-ICE test interface. LSI Logic recommends that all test signals be routed to a header on the board.

The Multi-ICE test interface header is a 20-pin header for Multi-ICE debugging through the ICE JTAG port. This header is essential for debugging both the ﬁrmware and the design functionality and must be included in board designs. The connector is a 20-pin header that mates with the IDC sockets mounted on a ribbon cable. Table 2.6 details the pinout of the 20 pin header.

Table 2.6 20-Pin Multi-ICE Header Pinout

Pin Number Signal Pin Number Signal

1 VDD 2 VDD 3 TRST_ICE/ 5 TDI_ICE 7 TMS_ICE 9 TCK_ICE

4 VSS 6 VSS 8 VSS

10 VSS 11 RTCK_ICE 12 VSS 13 TDO_ICE 14 VSS 15 No Connect 16 VSS 17 No Connect 18 VSS 19 No Connect 20 VSS

1. The designer must connect a 4.7 kΩ resistor from this signal to 3.3 V.

2-30 Functional Description

Chapter 3 Signal Description

This chapter describes the input and output signals of the LSI53C1030. The chapter consists of the following sections:

• Section 3.1, “Signal Organization”

• Section 3.2, “PCI Bus Interface Signals”

• Section 3.3, “PCI-Related Signals”

• Section 3.4, “SCSI Interface Signals”

• Section 3.5, “Memory Interface”

• Section 3.6, “Zero Channel RAID Interface”

• Section 3.7, “Test Interface”

• Section 3.8, “GPIO and LED Signals”

• Section 3.9, “Power and Ground Pins”

• Section 3.10, “Power-On Sense Pins Description”

• Section 3.11, “Internal Pull-Ups and Pull-Downs”

A slash (/) at the end of a signal indicates that the signal is active LOW. When the slash is absent, the signal is active HIGH. NC designates a No Connect signal.

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller 3-1

3.1 Signal Organization

The LSI53C1030 has six major interfaces:

• PCI Bus Interface

• SCSI Bus Interface

• Memory Bus Interface

• ZCR Interface

• Test Interface

• General Purpose I/O (GPIO) Interface

There are ﬁve signal types: I Input, a standard input-only signal O Output, a standard output driver (typically a Totem Pole output) I/O Input and output (bidirectional) PPower G Ground

Figure 3.1 contains the functional signal groupings of the LSI53C1030. Figure 5.12 on page 5-20 provides a diagram of the LSI53C1030

456 Ball Grid Array (BGA). Table 5.20 and Table 5.21 on page 5-22 and

page 5-24 provide pinout listings for the LSI53C1030.

3-2 Signal Description

Figure 3.1 LSI53C1030 Functional Signal Grouping

PCI Bus

Interface

System

Address

and Data

Interface

Control

Arbitration

Error

Reporting

Interrupt

PCI Bus

Related Signals

GPIO

Interface

Memory

Interface

ZCR Interface

CLK RST/

AD[63:0] C_BE[7:0]/ PAR PAR64

ACK64/ REQ64/ FRAME/ IRDY/ TRDY/ DEVSEL/ STOP/ IDSEL

REQ/ GNT/

PERR/ SERR/

INTA/ INTB/

ALT_INTA/ ALT_INTB/ PVT1 PVT2

GPIO[7:0] A_LED/ B_LED/ HB_LED/

ADSC/

ADV/

BWE[1:0]/ FLSHALE[1:0]/ FLSHCE/ MAD[15:0]

MADP[1:0] MCLK MOE/

RAMCE/ SerialCLK SerialDATA

ZCR_EN/ IOPD_GNT/

LSI53C1030

A_SCTRL/

B_SCTRL/

SCLK A_SD[15:0] A_SDP[1:0]

A_DIFFSENS

A_RBIAS

A_SCD±

A_SIO±

A_SMSG±

A_SREQ±

A_SACK± A_SBSY± A_SATN± A_SRST± A_SSEL±

B_SD[15:0]± B_SDP[1:0]

B_DIFFSENS

B_RBIAS

B_SCD±

B_SIO±

B_SMSG±

B_SREQ±

B_SACK± B_SBSY± B_SATN± B_SRST B_SSEL±

TST_RST/

TCK_CHIP

TDI_CHIP TDO_CHIP TMS_CHIP RTCK_ICE TRST_ICE/

TCK_ICE

TDI_ICE TDO_ICE TMS_ICE

TRACECLK

TRACEPKT[7:0]

TRACESYNC

PIPESTAT[2:0]

SCANEN

SCANMODE

IDDTN CLKMODE_0 CLKMODE_1

DIS_PCI_FSN/

DIS_SCSI_FSN/

TESTACLK TESTHCLK

TESTCLKEN

SCSI Function A

SCSI Bus Interface

SCSI Function B

Test Interface

Signal Organization 3-3

3.2 PCI Bus Interface Signals

This section describes the PCI interface. The PCI interface consists of the System, Address and Data, Interface Control, Arbitration, Error Reporting, and Interrupt signal groups.

3.2.1 PCI System Signals

Table 3.1 describes the PCI System signals group.

Table 3.1 PCI System Signals

Signal Name BGA Position Type Strength Description

CLK AC22 I N/A Refer to the PCI Local Bus Speciﬁcation,

RST/ AB10 I N/A Refer to the PCI Local Bus Speciﬁcation,

Version 2.2, and the PCI-X Addendum to the PCI Local Bus Speciﬁcation, Version 1.0a,for

this signal description.

Version 2.2, and the PCI-X Addendum to the PCI Local Bus Speciﬁcation, Version 1.0a,for

this signal description.

3-4 Signal Description

3.2.2 PCI Address and Data Signals

Table 3.2 describes the PCI Address and Data signals group.

Table 3.2 PCI Address and Data Signals

Signal Name BGA Position Type Strength Description

AD[63:0] W22, AB25, AC26,

AA25, W23, Y25, Y26, V22, U22, V24, V23, U24, V25, W26, U23, U25, T22, T23, T25, R25, R22, P22, P23, R23, P24, P25, T26, R26, M26, L26, N25, N24, AE9, AF8, AE10, AB11, AC11, AE11, AE12, AB12, AC12, AD13, AE13, AF11, AF16, AE14, AC15, AC14, AD17, AE19, AC18, AB17, AB18, AF20, AE20, AC19, AF23, AE22, AB19, AD21, AF24, AC20, AE23, AC21

C_BE[7:0]/ AA23, AC25, Y23,

AD26, AB13, AB14, AE18, AE21

PAR AF19 I/O 8 mA

I/O 8 mA

PCI

I/O 8 mA

PCI

Refer to the PCI Local Bus

Speciﬁcation, Version 2.2, and the PCI-X Addendum to the PCI Local Bus Speciﬁcation, Version 1.0a,for

this signal description.

Refer to the PCI Local Bus

Speciﬁcation, Version 2.2, and the PCI-X Addendum to the PCI Local Bus Speciﬁcation, Version 1.0a,for

this signal description. Refer to the PCI Local Bus

Speciﬁcation, Version 2.2, and the PCI-X Addendum to the PCI Local Bus Speciﬁcation, Version 1.0a,for

this signal description.

PAR64 AA24 I/O 8 mA

PCI

PCI Bus Interface Signals 3-5

Refer to the PCI Local Bus Speciﬁcation, Version 2.2, and the PCI-X Addendum to the PCI Local Bus Speciﬁcation, Version 1.0a,for

this signal description.

3.2.3 PCI Interface Control Signals

Table 3.3 describes the PCI Interface Control signals group.

Table 3.3 PCI Interface Control Signals

Signal Name BGA Position Type Strength Description

ACK64/ AB20 I/O 8 mA

PCI

REQ64/ AD22 I/O 8 mA

PCI

FRAME/ AB15 I/O 8 mA

PCI

IRDY/ AE15 I/O 8 mA

PCI

TRDY/ AE16 I/O 8 mA

PCI

DEVSEL/ AC16 I/O 8 mA

PCI

Refer to the PCI Local Bus Speciﬁcation,

Version 2.2, and the PCI-X Addendum to the PCI Local Bus Speciﬁcation, Version 1.0a,for

this signal description. Refer to the PCI Local Bus Speciﬁcation,