Avago Technologies LSI53C1030 User Manual

TECHNICAL

MANUAL

LSI53C1030 PCI-X to
Dual Channel Ultra320
SCSI Multifunction
Controller

September 2003

Version 2.2

®

DB14-000156-05

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000156-05, Version 2.2 (September 2003)
This document describes LSI Logic Corporation’s LSI53C1030 PCI-X to
Dual Channel Ultra320 SCSI Multifunction Controller and will remain the official
reference source for all revisions/releases of this product until rescinded by an
update.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

LSI Logic, the LSI Logic logo design, Fusion-MPT, Integrated Mirroring,
Integrated Striping, LVDlink, SDMS, SureLINK, and TolerANT are trademarks or
registered trademarks of LSI Logic Corporation. ARM and Multi-ICE are
registered trademarks of ARM Ltd., used under license. Windows is a registered
trademarks of Microsoft Corporation. NetWare is a registered trademarks of
Novell Corporation. Linux is a registered trademark of Linus Torvalds. Solaris is
a trademark of Sun Microsystems, Inc. SCO Openserver is a trademark of
Caldera International, Inc. UnixWare is a trademark of The Open Group. All other
brand and product names may be trademarks of their respective companies.

KL

To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource

centers, view our web page located at
http://www.lsilogic.com/contacts/index.html

ii

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

Audience

Preface

This book is the primary reference and technical manual for the
LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction
Controller. It contains a functional description for the LSI53C1030 and
the physical and electrical specifications for the LSI53C1030.

This document assumes that you have some familiarity with
microprocessors and related support devices. The people who benefit
from this book are:

• Engineers and managers who are evaluating the LSI53C1030 for use

in a system

• Engineers who are designing the LSI53C1030 into a system

Organization

This document has the following chapters and appendixes:

• Chapter 1, Introduction, provides an overview of the LSI53C1030

features and capabilities.

• Chapter 2, Functional Description, provides a detailed functional

description of the LSI53C1030 operation. This chapter describes
how the LSI53C1030 implements the PCI, PCI-X, and SCSI bus
specifications.

• Chapter 3, Signal Description, provides a detailed signal

description for the LSI53C1030.

• Chapter 4, PCI Host Register Description, provides a bit level

description of the host register set of the LSI53C1030.

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller iii

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

• Chapter 5, Specifications, provides the electrical and physical

• Appendix A, Register Summary, provides a register map for the

Related Publications

LSI Logic Documents

Fusion-MPT Device Management User’s Guide, Version 2.0,
DB15-000186-02
Integrated RAID User’s Guide, Version 1.0, DB15-000292-00

LSI Logic World Wide Web Home Page

www.lsilogic.com

ANSI

11 West 42nd Street
New York, NY 10036
[phone]

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]

specifications for the device.

LSI53C1030.

ENDL Publications

14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI

Tutor

Prentice Hall

113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding

the Small Computer System Interface

SCSI Electronic Bulletin Board

[phone]

iv Preface

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

PCI Special Interest Group

2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]

Conventions Used in This Manual

The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word

deassert means to drive a signal false or inactive. Signals that are active
LOW end with a “/.”

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision History

Revision Date Remarks

Version 2.2 9/2003 Corrected SCSI clock period and LOW/HIGH times in Table 5.13.

Version 2.1 6/2003 Updated the external memory timing diagrams.

Version 2.0 4/2002 Added register summary appendix.

Preliminary
Version 1.0

12/2001 Updated the description of Fusion-MPT architecture in Chapter 1.

Updated references to Integrated RAID (IR).

Updated the default Subsystem ID value.
Updated the ZCR behavior description.
Updated the Multi-ICE test interface description.

Updated the electrical characteristics.
Updated the Index.

Updated External Memory Interface descriptions in Chapter 2.
Added Test Interface description to Chapter 2.
Added Zero Channel RAID interface description to Chapters 2 and 3.
Updated the MAD Power-On Sense pin description in Chapter 3.
Updated signal descriptions and lists to include the ZCR-related pins.
Updated electrical and environmental characteristics in Chapter 5.
Removed figures relating to SE SCSI electrical and timing characteristics
from Chapter 5.
Removed SCSI timing information from Chapter 5 and referred readers to
the SCSI specification.
Removed PSBRAM interface and all related information.

Preface v

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

Revision Date Remarks

Advance
Version 0.1

2/2001 Initial release of document.

vi Preface

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

Contents

Chapter 1 Introduction

1.1 General Description 1-1

1.2 Benefits of the Fusion-MPT Architecture 1-5

1.3 Benefits of PCI-X 1-6

1.4 Benefits of Ultra320 SCSI 1-7

1.5 Benefits of SureLINK (Ultra320 SCSI Domain Validation) 1-8

1.6 Benefits of LVDlink Technology 1-8

1.7 Benefits of TolerANT®Technology 1-9

1.8 Summary of LSI53C1030 Features 1-10

1.8.1 SCSI Performance 1-10

1.8.2 PCI Performance 1-11

1.8.3 Integration 1-12

1.8.4 Flexibility 1-12

1.8.5 Reliability 1-13

1.8.6 Testability 1-13

Chapter 2 Functional Description

2.1 Block Diagram Description 2-2

2.1.1 Host Interface Module Description 2-3

2.1.2 SCSI Channel Module Description 2-6

2.2 Fusion-MPT Architecture Overview 2-6

2.3 PCI Functional Description 2-8

2.3.1 PCI Addressing 2-8

2.3.2 PCI Commands and Functions 2-9

2.3.3 PCI Arbitration 2-15

2.3.4 PCI Cache Mode 2-15

2.3.5 PCI Interrupts 2-15

2.3.6 Power Management 2-16

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller vii

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

2.4 Ultra320 SCSI Functional Description 2-18

2.4.1 Ultra320 SCSI Features 2-18

2.4.2 SCSI Bus Interface 2-23

2.5 External Memory Interface 2-24

2.5.1 Flash ROM Interface 2-24

2.5.2 NVSRAM Interface 2-26

2.6 Serial EEPROM Interface 2-27

2.7 Zero Channel RAID 2-28

2.8 Multi-ICE Test Interface 2-30

Chapter 3 Signal Description

3.1 Signal Organization 3-2

3.2 PCI Bus Interface Signals 3-4

3.2.1 PCI System Signals 3-4

3.2.2 PCI Address and Data Signals 3-5

3.2.3 PCI Interface Control Signals 3-6

3.2.4 PCI Arbitration Signals 3-7

3.2.5 PCI Error Reporting Signals 3-7

3.2.6 PCI Interrupt Signals 3-8

3.3 PCI-Related Signals 3-9

3.4 SCSI Interface Signals 3-10

3.4.1 SCSI Channel [0] Signals 3-10

3.4.2 SCSI Channel [1] Signals 3-13

3.5 Memory Interface 3-14

3.6 Zero Channel RAID Interface 3-16

3.7 Test Interface 3-17

3.8 GPIO and LED Signals 3-19

3.9 Power and Ground Pins 3-20

3.10 Power-On Sense Pins Description 3-21

3.11 Internal Pull-Ups and Pull-Downs 3-25

Chapter 4 PCI Host Register Description

4.1 PCI Configuration Space Register Description 4-1

4.2 PCI I/O Space and Memory Space Register Description 4-28

Chapter 5 Specifications

5.1 DC Characteristics 5-1

viii Contents

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

5.2 TolerANT Technology Electrical Characteristics 5-7

5.3 AC Characteristics 5-9

5.4 External Memory Timing Diagrams 5-11

5.4.1 NVSRAM Timing 5-11

5.4.2 Flash ROM Timing 5-15

5.5 Package Drawings 5-18

Appendix A Register Summary

Index

Customer Feedback

Contents ix

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x Contents

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

Figures

1.1 Typical LSI53C1030 Board Application 1-3

1.2 Typical LSI53C1030 System Application 1-4

2.1 LSI53C1030 Block Diagram 2-3

2.2 Paced Transfer Example 2-20

2.3 Example of Precompensation 2-21

2.4 Flash ROM Block Diagram 2-25

2.5 NVSRAM Diagram 2-27

2.6 ZCR Circuit Diagram for LSI53C1030 and LSI53C1010R 2-29

3.1 LSI53C1030 Functional Signal Grouping 3-3

5.1 LVD Driver 5-3

5.2 LVD Receiver 5-4

5.3 Rise and Fall Time Test Condition 5-8

5.4 SCSI Input Filtering 5-9

5.5 External Clock 5-10

5.6 Reset Input 5-10

5.7 Interrupt Output 5-11

5.8 NVSRAM Read Cycle 5-12

5.8 NVSRAM Read Cycle (Cont.) 5-12

5.9 NVSRAM Write Cycle 5-14

5.9 NVSRAM Write Cycle (Cont.) 5-14

5.10 Flash ROM Read Cycle 5-15

5.10 Flash ROM Read Cycle (Cont.) 5-16

5.11 Flash ROM Write Cycle 5-17

5.11 Flash ROM Write Cycle (Cont.) 5-17

5.12 LSI53C1030 456-Pin BGA Top View 5-20

5.12 LSI53C1030 456-Pin BGA Top View (Cont.) 5-21

5.13 456-Pin EPBGA (KY) Mechanical Drawing 5-26

Contents xi

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xii Contents

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

Tables

2.1 PCI/PCI-X Bus Commands and Encodings 2-10

2.2 Power States 2-16

2.3 Flash ROM Size Programming 2-24

2.4 Flash Signature Value 2-26

2.5 PCI Configuration Record in Serial EEPROM 2-28

2.6 20-Pin Multi-ICE Header Pinout 2-30

3.1 PCI System Signals 3-4

3.2 PCI Address and Data Signals 3-5

3.3 PCI Interface Control Signals 3-6

3.4 PCI Arbitration Signals 3-7

3.5 PCI Error Reporting Signals 3-7

3.6 PCI Interrupt Signals 3-8

3.7 PCI-Related Signals 3-9

3.8 SCSI Bus Clock Signal 3-10

3.9 SCSI Channel [0] Interface Signals 3-10

3.10 SCSI Channel [0] Control Signals 3-12

3.11 SCSI Channel [1] Interface Signals 3-13

3.12 SCSI Channel [1] Control Signals 3-14

3.13 Flash ROM/NVSRAM Interface Pins 3-14

3.14 Serial EEPROM Interface Pins 3-16

3.15 ZCR Configuration Pins 3-16

3.16 JTAG, ICE, and Debug Pins 3-17

3.17 LSI Logic Test Pins 3-18

3.18 GPIO and LED signals 3-19

3.19 Power and Ground Pins 3-20

3.20 MAD Power-On Sense Pin Options 3-21

3.21 PCI-X Function to SCSI Channel Configurations 3-24

3.22 Flash ROM Size Programming 3-24

3.23 Pull-Up and Pull-Down Conditions 3-25

4.1 LSI53C1030 PCI Configuration Space Address Map 4-2

4.2 Subsystem ID Register Download Conditions and Values 4-13

4.3 Multiple Message Enable Field Bit Encoding 4-22

4.4 Maximum Outstanding Split Transactions 4-25

4.5 Maximum Memory Read Count 4-25

4.6 PCI I/O Space Address Map 4-29

4.7 PCI Memory [0] Address Map 4-29

Contents xiii

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

4.8 PCI Memory [1] Address Map 4-29

4.9 Interrupt Signal Routing 4-36

5.1 Absolute Maximum Stress Ratings 5-2

5.2 Operating Conditions 5-2

5.3 LVD Driver SCSI Signals— SACK±,SATN±, SBSY±,
SCD±, SD[15:0]±, SDP[1:0]±, SIO±, SMSG±, SREQ±,
SRST±, SSEL± 5-3

5.4 LVD Receiver SCSI Signals— SACK±,SATN±, SBSY±,
SCD±, SD[15:0]±, SDP[1:0]±, SIO±, SMSG±, SREQ±,
SRST±, SSEL± 5-3

5.5 A_DIFFSENS and B_DIFFSENS SCSI Signals 5-4

5.6 Input Capacitance 5-4

5.7 8 mA Bidirectional Signals — GPIO[7:0], MAD[15:0],
MADP[1:0], SerialDATA 5-5

5.8 8 mA PCI Bidirectional Signals — ACK64/, AD[63:0],
C_BE[7:0]/, DEVSEL/, FRAME/, IRDY/, PAR, PAR64,
PERR/, REQ64/, SERR/, STOP/, TRDY/ 5-5

5.9 Input Signals — CLK, CLKMODE_0, CLKMODE_1,
DIS_PCI_FSN/, DIS_SCSI_FSN/, GNT/, IDDTN, IDSEL,
IOPD_GNT/, PVT1, PVT2, SCANEN, SCANMODE,
SCLK, TCK_CHIP, TCK_ICE, TESTACLK, TESTCLKEN,
TESTHCLK, TDI_CHIP, TDI_ICE, TMS_CHIP, TMS_ICE,
TN, TRST_ICE/, TST_RST/, ZCR_EN/ 5-6

5.10 8 mA Output Signals — ADSC/, ADV/, ALT_INTA/,
ALT_INTB/, BWE[1:0]/, FLSHALE[1:0]/, FLSHCE/, INTA/,
INTB/, MCLK, MOE/, PIPESTAT[2:0], RAMCE/, REQ/,
RTCK_ICE, SerialCLK, SERR/, TDO_CHIP, TDO_ICE,
TRACECLK, TRACEPKT[7:0], TRACESYNC 5-6

5.11 12 mA Output Signals — A_LED/, B_LED/, HB_LED/ 5-6

5.12 TolerANT Technology Electrical Characteristics for SE
SCSI Signals 5-7

5.13 External Clock 5-9

5.14 Reset Input 5-10

5.15 Interrupt Output 5-10

5.16 NVSRAM Read Cycle Timing 5-11

5.17 NVSRAM Write Cycle 5-13

5.18 Flash ROM Read Cycle Timing 5-15

5.19 Flash ROM Write Cycle 5-16

A.1 LSI53C1030 PCI Registers A-1

xiv Contents

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

A.2 LSI53C1030 PCI I/O Space Registers A-3
A.3 LSI53C1030 PCI I/O Space Registers A-4

Contents xv

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xvi Contents

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

Chapter 1
Introduction

This chapter provides a general overview of the LSI53C1030 PCI-X to
Dual Channel Ultra320 SCSI Multifunction Controller. This chapter
contains the following sections:

• Section 1.1, “General Description”

• Section 1.2, “Benefits of the Fusion-MPT Architecture”

• Section 1.3, “Benefits of PCI-X”

• Section 1.4, “Benefits of Ultra320 SCSI”

• Section 1.5, “Benefits of SureLINK (Ultra320 SCSI Domain

Validation)”

• Section 1.6, “Benefits of LVDlink Technology”

• Section 1.7, “Benefits of TolerANT® Technology”

• Section 1.8, “Summary of LSI53C1030 Features”

1.1 General Description

The LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction
Controller brings Ultra320 SCSI performance to host adapter,
workstation, and server designs, making it easy to add a
high-performance SCSI bus to any PCI or PCI-X system. The
LSI53C1030 supports both the PCI Local Bus Specification, Revision

2.2, and the PCI-X Addendum to the PCI Local Bus Specification,

Revision 1.0a.

1. In some instances, this manual references PCI-X explicitly. References to the PCI

bus may be inclusive of both the PCI specification and PCI-X addendum, or they
may refer only to the PCI bus depending on the operating mode of the device.

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller 1-1

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

1

The LSI53C1030 is pin compatible with the LSI53C1010R PCI to Dual
Channel Ultra160 SCSI Multifunction Controller to provide an easy and
safe migration path to Ultra320 SCSI. The LSI53C1030 supports up to a
64-bit, 133 MHz PCI-X bus. The Ultra320 SCSI features for the
LSI53C1030 include: double transition (DT) clocking, packetized protocol,
paced transfers, quick arbitrate and select (QAS), skew compensation,
intersymbol interference (ISI) compensation, cyclic redundancy check
(CRC), and domain validation technology. These features comply with
the American National Standard Institute (ANSI) T10 SCSI Parallel
Interface-4 (SPI-4) draft specification.

DT clocking enables the LSI53C1030 to achieve data transfer rates of up
to 320 megabytes per second (Mbytes/s) on each SCSI channel, for a
total bandwidth of 640 Mbytes/s on both SCSI channels. Packetized
protocol increases data transfer capabilities with SCSI information units.
QAS minimizes SCSI bus latency by allowing the bus to directly enter the
arbitration/selection bus phase after a SCSI disconnect and skip the bus
free phase. Skew compensation permits the LSI53C1030 to adjust for
cable and bus skew on a per-device basis. Paced transfers enable high
speed data transfers during DT data phases by using the REQ/ACK
transition as a free running data clock. Precompensation enables the
LSI53C1030 to adjust the signal drive strength to compensate for the
charge present on the cable. CRC improves the SCSI data transmission
integrity through enhanced detection of communication errors.
SureLINK™ Domain Validation detects the SCSI bus configuration and
adjusts the SCSI transfer rate to optimize bus interoperability and SCSI
data transfer rates. SureLINK Domain Validation provides three levels of
domain validation, assuring robust system operation.

The LSI53C1030 supports a local memory bus, which supports a
standard serial EEPROM and allows local storage of the BIOS in Flash
ROM memory. The LSI53C1030 supports programming of local Flash
ROM memory for BIOS updates. Figure 1.1 shows a typical LSI53C1030
board application connected to external ROM memory.

1-2 Introduction

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

Figure 1.1 Typical LSI53C1030 Board Application

Channel [0]

68 Pin
Wide SCSI
Connector

and

Terminator

Channel [1]

68 Pin
Wide SCSI
Connector

and

Terminator

Memory Control

Block

Flash ROM/

NVSRAM

Serial EEPROM

SCSI Bus

SCSI Bus

LSI53C1030

64 Bit, 133 MHz

Multifunction PCI-X

Dual Channel

Ultra320 SCSI

Controller

Function [1]Function [0]

PCI-X Interface

Memory

Address/Data

Bus

Serial Data

Serial Clock

The LSI53C1030 integrates two high-performance SCSI Ultra320 cores
and a 64-bit, 133 MHz PCI-X bus master DMA core. The LSI53C1030
employs three ARM966E-S processors to meet the data transfer flexibility
requirements of the Ultra320 SCSI, PCI, and PCI-X specifications.
Separate ARM®processors support each SCSI channel and the
PCI/PCI-X interface.

These processors implement the LSI Logic Fusion-MPT™ architecture,
a multithreaded I/O algorithm that supports data transfers between the
host system and SCSI devices with minimal host processor intervention.
Fusion-MPT technology provides an efficient architecture that solves the
protocol overhead problems of previous intelligent and nonintelligent
adapter designs.

LVDlink™ technology is the LSI Logic implementation of Low Voltage
Differential (LVD) SCSI. LVDlink transceivers allow the LSI53C1030 to
perform either Single-Ended (SE) or LVD transfers. Figure 1.2 illustrates
a typical LSI53C1030 system application.

General Description 1-3

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

Figure 1.2 Typical LSI53C1030 System Application

PCI-X Bus

Interface

Controller

Processor Bus

Central

Processing

Unit

(CPU)

PCI-X Bus

LSI53C1030 PCI-X

to Ultra320 SCSI

Channel [0]

and

LSI53C1030 PCI-X

to Ultra320 SCSI

Channel [1]

One PCI Bus Load

PCI Graphic Accelerator

PCI Fast Ethernet

Memory

Controller

Memory

SCSI Bus

SCSI Bus

Fixed Disk, Optical Disk,

Printer, Tape, and Other

SCSI Peripherals

Fixed Disk, Optical Disk,

Printer, Tape, and Other

SCSI Peripherals

The LSI Logic Integrated RAID solution provides cost benefits for the
server or workstation market where the extra performance, storage
capacity, and/or redundancy of a RAID configuration are required. The
two components of Integrated RAID are:

• Integrated Mirroring™ (IM), which provides features of RAID 1 and

RAID 1E. IM provides physical mirroring of the boot volume through
LSI53C1030 firmware. This feature provides extra reliability for the
system’s boot volume without burdening the host CPU. The runtime
mirroring of the boot drive is transparent to the BIOS, drivers, and
operating system.

• Integrated Striping™ (IS), which provides features of RAID 0. The
IS feature writes data across multiple disks instead of onto one disk.
This is accomplished by partitioning each disk’s storage space into

1-4 Introduction

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

64 Kbyte stripes. These stripes are interleaved round-robin, so that
the combined storage space is composed alternately of stripes from
each disk.

The LSI Logic Fusion-MPT architecture provides the interface to the
SCSI chip/firmware to enable Integrated Striping and Integrated
Mirroring. LSI Logic’s CIM interface software is used to continuously
monitor IM volumes and IS volumes and to report status and error
conditions as they arise.

A BIOS-based configuration utility is provided to create the IM and IS
volumes. A DOS-based configuration utility is also provided for use on
the manufacturing floor.

For more information about the LSI Logic Integrated RAID solution, see
the Integrated RAID User’s Guide, DB15-000292-00.

1.2 Benefits of the Fusion-MPT Architecture

The Fusion-MPT architecture provides an open architecture that is ideal
for SCSI, Fibre Channel, and other emerging interfaces.The I/O interface
is interchangable at the system and application level; embedded software
uses the same device interface for SCSI and Fibre Channel
implementations just as application software uses the same storage
management interfaces for SCSI and Fibre Channel implementations.
LSI Logic provides Fusion-MPT device drivers that are binary compatible
between Fibre Channel and Ultra320 SCSI interfaces.

The Fusion-MPT architecture improves overall system performance by
requiring only a thin device driver, which off loads the intensive work of
managing SCSI I/Os from the system processor to the LSI53C1030.
Developed from the proven LSI Logic SDMS™ solution, the Fusion-MPT
architecture delivers unmatched performance of up to 100,000 Ultra320
SCSI I/Os per second with minimal system overhead or device
maintenance. The use of thin, easy to develop, common OS device
drivers accelerates time to market by reducing device driver development
and certification times.

The Fusion-MPT architecture provides an interrupt coalescing feature.
Interrupt coalescing allows an I/O controller to send multiple reply
messages in a single interrupt to the host processor. Sending multiple

Benefits of the Fusion-MPT Architecture 1-5

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

reply messages per interrupt reduces context switching of the host
processor and maximizes the host processor efficiency, which results in
a significant improvement of system performance. To use the interrupt
coalescing feature, the host processor must be able to accept and
manage multiple replies per interrupt.

The Fusion-MPT architecture also provides built-in device driver stability
since the device driver need not change for each revision of the
LSI53C1030 silicon or firmware. This architecture is a reliable, constant
interface between the host device driver and the LSI53C1030. Changes
within the LSI53C1030 are transparent to the host device driver,
operating system, and user. The Fusion-MPT architecture also saves the
user significant development and maintenance effort since it is not
necessary to alter or redevelop the device driver when a revision of the
LSI53C1030 device or firmware occurs.

1.3 Benefits of PCI-X

PCI-X doubles the maximum clock frequency of the conventional PCI
bus. The PCI-X Addendum to the PCI Local Bus Specification,

Revision 1.0a, defines enhancements to the proven PCI Local Bus
Specification, Revision 2.2. PCI-X provides more efficient data transfers

by enabling registered inputs and outputs, improves buffer management
by including transaction information with each data transfer, and reduces
bus overheadby restricting the use of wait states and disconnects. PCI-X
also reduces host processor overhead by providing a wide range of error
recovery implementations.

The LSI53C1030 supports up to a 133 MHz, 64-bit PCI-X bus and is
backward compatible with previous versions of the PCI/PCI-X
specification. The LSI53C1030 is a true multifunction PCI-X device and
presents a single electrical load to the PCI bus. The LSI53C1030 uses
a single REQ/-GNT/ pair to arbitrate for PCI bus mastership. Separate
interrupt signals for PCI Function [0] and PCI Function [1] allow
independent control of the two PCI functions.

Per the PCI-X addendum, the LSI53C1030 includes transaction
information with all PCI-X transactions to enable more efficient buffer
management schemes. Each PCI-X transaction contains a transaction
sequence identifier (Tag), the identity of the initiator, and the number of

1-6 Introduction

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

bytes in the sequence. The LSI53C1030 clocks PCI-X data directly into
and out of registers, which creates a more efficient data path. The
LSI53C1030 increases bus efficiency since it does not insert wait states
after the initial data phase when acting as a PCI-X target and never
inserts wait states when acting as a PCI-X initiator.

1.4 Benefits of Ultra320 SCSI

Ultra320 SCSI is an extension of the SPI-4 draft specification that allows
faster synchronous SCSI data transfer rates than Ultra160 SCSI. When
enabled, Ultra320 SCSI performs 160 megatransfers per second
resulting in approximately double the synchronous data transfer rates of
Ultra160 SCSI. The LSI53C1030 performs 16-bit, Ultra320 SCSI
synchronous data transfers as fast as 320 Mbytes/s on each SCSI
channel. This advantage is most noticeable in heavily loaded systems or
large block size applications, such as video on-demand and image
processing.

Ultra320 SCSI doubles both the data and clock frequencies from
Ultra160 SCSI. Due to the increased data and clock speeds, Ultra320
SCSI introduces skew compensation and intersymbol interference (ISI)
compensation. These new features simplify system design by resolving
timing issues at the chip level. Skew compensation adjusts for timing
differences between data and clock signals caused by cabling, board
traces, etc. ISI compensation enhances the first pulse after a change in
state to ensure data integrity.

Ultra320 SCSI includes CRC, which offers higher levels of data reliability
by ensuring complete integrity of transferred data. CRC is a 32-bit
scheme, referred to as CRC-32. CRC guarantees detection of all single
or double bit errors, as well as any combination of bit errors within a
single 32-bit range.

Benefits of Ultra320 SCSI 1-7

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

1.5 Benefits of SureLINK (Ultra320 SCSI Domain Validation)

SureLINK Domain Validation software ensures robust SCSI interconnect
management and low risk Ultra320 SCSI implementations by extending
the domain validation guidelines documented in the SPI-4 specifications.
Domain validation verifies that the system is capable of transferring data
at Ultra320 SCSI speeds, allowing the LSI53C1030 to renegotiate to a
lower data transfer speed and bus width if necessary. SureLINK Domain
Validation is the software control for the domain validation manageability
enhancements in the LSI53C1030. SureLINK Domain Validationsoftware
provides domain validation management at boot time as well as during
system operation.

SureLINK Domain Validation ensures robust system operation by
providing 3 levels of integrity checking on a per-device basis: Basic
(Level 1) with inquiry command, Enhanced (Level 2) with read/write
buffer and Margined (Level 3) with margining of drive strength and slew
rates.

1.6 Benefits of LVDlink Technology

The LSI53C1030 supports Low Voltage Differential (LVD) through
LVDlink technology. This signalling technology increases the reliability of
SCSI data transfers over longer distances than are supported by SE
(Single Ended) SCSI. The low current output of LVD allows the I/O
transceivers to be integrated directly onto the chip. To allow the use of
the LSI53C1030 in both legacy and Ultra320 SCSI applications, this
device features universal LVDlink transceivers that support LVD SCSI
and SE SCSI.

1-8 Introduction

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

1.7 Benefits of TolerANT®Technology

The LSI53C1030 features TolerANT technology, which provides active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation causes the SCSI Request, Acknowledge,
Data, and Parity signals to be actively driven high rather than passively
pulled up by terminators.

TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
ensure correct clocking of data. TolerANT input signal filtering is a built-in
feature of the LSI53C1030 and all LSI Logic Fast SCSI, Ultra SCSI,
Ultra2 SCSI, Ultra160 SCSI, and Ultra320 SCSI devices.

TolerANT technology increases noise immunity, balances duty cycles,
and improves SCSI transfer rates. In addition, TolerANT SCSI devices do
not cause glitches on the SCSI bus at power-up or power-down, which
protects other devices on the bus from data corruption. When used with
the LVDlink transceivers, TolerANT technology provides excellent signal
quality and data reliability in real world cabling environments. TolerANT
technology is compatible with both the Alternative One and Alternative
Two termination schemes proposed by the American National Standards
Institute.

Benefits of TolerANT®Technology 1-9

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

1.8 Summary of LSI53C1030 Features

This section provides a summary of the LSI53C1030 features and
benefits. It contains information on SCSI Performance, PCI Performance,

Integration, Flexibility, Reliability, and Testability.

1.8.1 SCSI Performance

The LSI53C1030 contains the following SCSI performance features:

• Supports Ultra320 SCSI
– Paced transfers using a free running clock
– 320 Mbyte/s data transfer rate on each SCSI channel
– Mandatory packetized protocol
– Quick arbitrate and select (QAS)
– Skew compensation with bus training
– Transmitter precompensation to overcome ISI effects for SCSI

data signals

– Retained training information (RTI)

• Offers a performance optimized architecture
– Three ARM966E-S processors provide high performance with

low latency
– Two independent Ultra320 SCSI channels
– Designed for optimal packetized performance

• Uses provenintegrated LVDlink transceivers for direct attach to either
LVD or SE SCSI buses with precision-controlled slew rates

• Supports expander communication protocol (ECP)

• Uses the Fusion-MPT (Message Passing Technology) drivers to
provide support for Windows, Linux, Solaris, SCO Openserver,
UnixWare, OpenUnix 8, and NetWare operating systems

1-10 Introduction

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

1.8.2 PCI Performance

The LSI53C1030 supports these PCI features:

• Has a 133 MHz, 64-bit PCI/PCI-X interface that:
– Operates at 33 MHz or 66 MHz PCI
– Operates at up to 133 MHz PCI-X
– Supports 32-bit or 64-bit data
– Supports 32-bit or 64-bit addressing through Dual Address

– Provides a theoretical 1066 Mbytes/s zero wait state transfer rate
– Complies with the PCI Local Bus Specification, Revision 2.2
– Complies with the PCI-X Addendum to the PCI Local Bus

– Complies with PCI Power Management Interface Specification,

– Complies with PC2001 System Design Guide

• Offers unmatched performance through the Fusion-MPT architecture

• Provides high throughput and low CPU utilization to off load the host
processor

Cycles (DAC)

Specification, Revision 1.0a

Revision 1.1

• Presents a single electrical load to the PCI Bus (True PCI
Multifunction Device)

• Uses SCSI Interrupt Steering Logic (SISL) to provide alternate
interrupt routing for RAID applications

• Reduces Interrupt Service Routine (ISR) overhead with interrupt
coalescing

• Supports 32-bit or 64-bit data bursts with variable burst lengths

• Supports the PCI Cache Line Size register

• Supports the PCI Memory Write and Invalidate, Memory Read Line,
and Memory Read Multiple commands

• Supports the PCI-X Memory Read Dword, Split Completion, Memory
Read Block, and Memory Write Block commands

• Supports up to 8 PCI-X outstanding split transactions

• Supports Message Signalled Interrupts (MSI)

Summary of LSI53C1030 Features 1-11

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1.8.3 Integration

1.8.4 Flexibility

These features make the LSI53C1030 easy to integrate:

• Is backward compatible with previous revisions of the PCI and SCSI

specifications

• Is pin compatible with the LSI53C1010R PCI to Dual Channel

Ultra160 SCSI Multifunction Controller

• Provides a low-risk migration path to Ultra320 SCSI from the

LSI53C1010R

• Is a dual channel Ultra320 SCSI to PCI/PCI-X multifunction controller

• Supports a 32-bit or 64-bit PCI/PCI-X DMA bus master

• Reduces time to market with the Fusion-MPT architecture

– Single driver binary for SCSI and Fibre Channel products
– Thin, easy to develop drivers
– Reduced integration and certification effort

• Provides integrated LVDlink transceivers

These features increase the flexibility of the LSI53C1030:

• Universal LVD transceivers are backward compatible with SE devices

• Provides a flexible programming interface to tune I/O performance or
to adapt to unique SCSI devices

• Supports MSI or pin-based (INTx/ or ALT_INTx/) interrupt signalling

• Can respond with multiple SCSI IDs

• Is compatible with 3.3 V and 5.0 V PCI signalling
– Drives and receives 3.3 V PCI signals
– Receives 5.0 V PCI if the PCI5VBIAS pin connects to 5 V, but

does not drive 5.0 V signals on the PCI bus

1-12 Introduction

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.

1.8.5 Reliability

These features enhance the reliability of the LSI53C1030:

• Supports intersymbol interference (ISI) compensation

• Provides 2 kV ESD protection on SCSI signals

• Provides latch-up protection greater than 150 mA

• Provides voltage feed-through protection

• Supports LSI Logic Integrated RAID (IR) solution to provide physical
mirroring or striping of the boot volume

• Has a high proportion of power and ground pins

• Provides power and ground isolation of I/O pads and internal chip
logic

• Supports CRC checking and generation in Double Transition (DT)
phases

• Provides comprehensive SureLINK Domain Validation technology:
– Basic (Level 1) with inquiry command
– Enhanced (Level 2) with read/write buffer
– Margined (Level 3) with margining of drive strength and slew

rates

1.8.6 Testability

• Supports TolerANT technology, which provides:
– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved SCSI transfer rates

– Input signal filtering on SCSI receivers for improved data

integrity, even in noisy cabling environments

These features enhance the testability of the LSI53C1030:

• Allows all SCSI signals to be accessed through programmed I/O

• Supports JTAG boundary scan

• Provides ARM Multi-ICE®for debugging purposes

Summary of LSI53C1030 Features 1-13

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1-14 Introduction

Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.