Avago Technologies LSI53C1020 User Manual

TECHNICAL

MANUAL

LSI53C1020/1020A
PCI-X to Ultra320
SCSI Controller

February 2004

Version 2.4

®

DB14-000176-06

This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.

Document DB14-000176-06, Version 2.4 (February 2004)
This document describes LSI Logic Corporation’s LSI53C1020 and
LSI53C1020A PCI-X to Ultra320 SCSI Controllers and will remain the official
reference source for all revisions/releases of these products until rescinded by an
update.

LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.

Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT

LSI Logic, the LSI Logic logo design, Fusion-MPT, Integrated Mirroring,
Integrated RAID, Integrated Striping, LVDlink, SDMS, SureLINK, and TolerANT
are trademarks or registered trademarks of LSI Logic Corporation. ARM,
ARM966E-S, and Multi-ICE are trademarks or registered trademarks of ARM
Ltd., used under license. Windows is a registered trademarks of Microsoft
Corporation. NetWare is a registered trademarks of Novell Corporation. Linux is
a registered trademark of Linus Torvalds. Solaris is a trademark of Sun
Microsystems, Inc. SCO OpenServer is a trademark of Caldera International, Inc.
UnixWare is a trademark of The Open Group. All other brand and product names
may be trademarks of their respective companies.

KL

To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource

centers, view our web page located at

http://www.lsilogic.com/contacts/index.html

ii

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Audience

Preface

This book is the primary reference and technical manual for the
LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller. It contains a
functional description and electrical specifications for the
LSI53C1020/1020A.

This document assumes that you have some familiarity with
microprocessors and related support devices. The people who benefit
from this book are:

Organization

• Engineers and managers who are evaluating the LSI53C1020/1020A

for use in a system

• Engineers who are designing the LSI53C1020/1020A into a system

This document has the following chapters and appendix:

• Chapter 1, Introduction, provides an overview of the

LSI53C1020/1020A features and capabilities.

• Chapter 2, Functional Description, provides a detailed functional

description of the LSI53C1020/1020A operation. This chapter
describes how the LSI53C1020/1020A implements the PCI/PCI-X
and SCSI bus specifications.

• Chapter 3, Signal Description, provides detailed descriptions of all

LSI53C1020/1020A signals.

• Chapter 4, PCI Host Register Description, provides a bit level

description of the LSI53C1020/1020A host register set.

LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller Technical Manual iii

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

• Chapter 5, Specifications, provides the electrical and physical

• Appendix A, Register Summary, provides a register map for the

Related Publications

LSI Logic Documents

Fusion-MPT Device Management User’s Guide, Version 2.0,
DB15-000186-02

ANSI

11 West 42nd Street
New York, NY 10036
[phone]

Global Engineering Documents

15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]

characteristics of the LSI53C1020/1020A. It also includes
LSI53C1020/1020A pinout tables and mechanical drawings.

LSI53C1020/1020A.

ENDL Publications

14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI Tutor

Prentice Hall

113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for SCSI: Understanding the Small Computer System Interface,
ISBN 0-13-796855-8

SCSI Electronic Bulletin Board

[phone]

PCI Special Interest Group

2575 N. E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]

iv Preface

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Conventions Used in This Manual

The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word

deassert means to drive a signal false or inactive. Signals that are active
LOW end with a “/.”

Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Revision History

Revision Date Remarks

v2.4 2/2004 Corrected PCI support information and package/pin compatibility information

in Chapter 1.

v2.3 2/2004 Added 384-pin entries to signal description tables in Chapter 3.

Corrected and updated pin/signal names and ball assignments throughout
the document. Verified that this data is now consistent for the 384-pin and
456-pin packages.
Added a statement that LSI53C1020A controller supports v2.3 of the PCI
spec.
Added descriptions of the Interrupt Disable and Interrupt Status bits to the
PCI Command Register and PCI Status Register sections in Chapter 4 and
noted that the LSI53C1020A controller supports these functions.
Deleted this sentence from section 2.7: “LSI53C1020 based designs do not
use the M66EN pin to determine the PCI bus speed.” (The sentence was not
relevant, since the chip has no M66EN pin.)
Made this correction in description of Diagnostic Read/Write Address regis­ter: “The address increments by a dword whenever the host system
accesses the Diagnostic Read/Write

Data register.”

v2.2 12/2003 Updated references to Integrated RAID throughout the document.

Corrected SCSI clock, SCLK LOW, and SCLK HIGH timings in Table 5.13.
Added pinout information for 448 EPBGA and 384 EPBGA packages of the
LSI53C1020A chip. Edited descriptions of Request Queue and Reply Queue
registers (formerly called “Request FIFO” and “Reply FIFO,” respectively).

v2.1 6/2003 Updated the external memory timing diagrams.

Updated the default Subsystem ID value.
Updated the ZCR behavior description.
Updated the Multi-ICE test interface description.

Preface v

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Revision Date Remarks

v2.0 4/2002 Added the register summary appendix.

Updated the electrical characteristics.
Updated the Index.

Prelim v1.0 2/2002 Updated the description of Fusion-MPT architecture in Chapter 1.

Updated the External Memory Interface descriptions in Chapter 2.
Added the Test Interface description to Chapter 2.
Added the Zero Channel RAID interface description to Chapters 2 and 3.
Updated the MAD Power-On Sense pin description in Chapter 3.
Updated the signal descriptions and lists to include the ZCR-related pins.
Updated the electrical and environmental characteristics in Chapter 5.
Removed SE SCSI electrical/timing characteristics figures from Chapter 5.
Removed SCSI timing information from Chapter 5 and referred readers to
the SCSI spec.
Removed the PSBRAM interface and all related information.

Adv v0.1 4/2001 Initial release of document.

vi Preface

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Contents

Chapter 1 Introduction

1.1 General Description 1-1

1.2 Benefits of the Fusion-MPT Architecture 1-5

1.3 Benefits of PCI-X 1-6

1.4 Benefits of Ultra320 SCSI 1-7

1.5 Benefits of SureLINK (Ultra320 SCSI Domain Validation) 1-7

1.6 Benefits of LVDlink Technology 1-8

1.7 Benefits of TolerANT®Technology 1-8

1.8 Summary of LSI53C1020 Features 1-9

1.8.1 SCSI Performance 1-9

1.8.2 PCI Performance 1-10

1.8.3 Integration 1-11

1.8.4 Flexibility 1-11

1.8.5 Reliability 1-11

1.8.6 Testability 1-12

Chapter 2 Functional Description

2.1 Block Diagram Description 2-2

2.1.1 Host Interface Module Description 2-3

2.1.2 SCSI Channel Module Description 2-6

2.2 Fusion-MPT Architecture Overview 2-7

2.3 PCI Functional Description 2-8

2.3.1 PCI Addressing 2-8

2.3.2 PCI Commands and Functions 2-9

2.3.3 PCI Arbitration 2-15

2.3.4 PCI Cache Mode 2-15

2.3.5 PCI Interrupts 2-15

2.3.6 Power Management 2-16

LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller Technical Manual vii

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

2.4 Ultra320 SCSI Functional Description 2-18

2.4.1 Ultra320 SCSI Features 2-18

2.4.2 SCSI Bus Interface 2-22

2.5 External Memory Interfaces 2-23

2.5.1 Flash ROM Interface 2-23

2.5.2 NVSRAM Interface 2-26

2.6 Serial EEPROM Interface 2-27

2.7 Zero Channel RAID 2-28

2.8 Multi-ICE Test Interface 2-29

Chapter 3 Signal Description

3.1 Signal Organization 3-2

3.2 PCI Bus Interface Signals 3-4

3.2.1 PCI System Signals 3-4

3.2.2 PCI Address and Data Signals 3-5

3.2.3 PCI Interface Control Signals 3-6

3.2.4 PCI Arbitration Signals 3-6

3.2.5 PCI Error Reporting Signals 3-7

3.2.6 PCI Interrupt Signals 3-7

3.3 PCI-Related Signals 3-8

3.4 SCSI Interface Signals 3-9

3.5 Memory Interface 3-12

3.6 Zero Channel RAID (ZCR) Interface 3-13

3.7 Test Interface 3-14

3.8 GPIO and LED Signals 3-16

3.9 Power and Ground Pins 3-16

3.10 Power-On Sense Pins Description 3-18

3.11 Internal Pull-Ups and Pull-Downs 3-22

Chapter 4 PCI Host Register Description

4.1 PCI Configuration Space Register Descriptions 4-1
Vendor ID 4-3
Device ID 4-3
Command 4-3
Status 4-5
Revision ID 4-7
Class Code 4-7

viii Contents

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Cache Line Size 4-8
Latency Timer 4-8
Header Type 4-9
I/O Base Address 4-9
Memory [0] Low 4-10
Memory [0] High 4-10
Memory [1] Low 4-11
Memory [1] High 4-11
Subsystem Vendor ID 4-13
Subsystem ID 4-14
Expansion ROM Base Address 4-15
Capabilities Pointer 4-16
Interrupt Line 4-17
Interrupt Pin 4-17
Minimum Grant 4-18
Maximum Latency 4-18
Power Management Capability ID 4-19
Power Management Next Pointer 4-19
Power Management Capabilities 4-20
Power Management Control/Status 4-21
Power Management Bridge Support Extensions 4-22
Power Management Data 4-22
MSI Capability ID 4-22
MSI Next Pointer 4-23
Message Control 4-23
Message Address 4-25
Message Upper Address 4-25
Message Data 4-26
PCI-X Capability ID 4-26
PCI-X Next Pointer 4-27
PCI-X Command 4-27
PCI-X Status 4-29

4.2 I/O Space and Memory Space Register Descriptions 4-32
System Doorbell 4-34
Write Sequence 4-35
Host Diagnostic 4-36
Test Base Address 4-37
Diagnostic Read/Write Data 4-38

Contents ix

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Diagnostic Read/Write Address 4-39
Host Interrupt Status 4-40
Host Interrupt Mask 4-41
Request Queue 4-42
Reply Queue 4-42

Chapter 5 Specifications

5.1 DC Characteristics 5-1

5.2 TolerANT Technology Electrical Characteristics 5-7

5.3 AC Characteristics 5-9

5.4 External Memory Timing Diagrams 5-12

5.4.1 NVSRAM Timing 5-12

5.4.2 Flash ROM Timing 5-16

5.5 Pinout Information and Mechanical Drawings 5-20

Appendix A Register Summary

Index

Customer Feedback

x Contents

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Figures

1.1 Typical LSI53C1020 Board Application 1-3

1.2 Typical LSI53C1020 System Application 1-4

2.1 LSI53C1020 Block Diagram 2-3

2.2 Paced Transfer Example 2-19

2.3 Example of Precompensation 2-20

2.4 Flash ROM Block Diagram 2-25

2.5 NVSRAM Diagram 2-26

2.6 ZCR Circuit Diagram for the LSI53C1020 and

LSI53C1000R 2-29

3.1 LSI53C1020/1020A Functional Signal Grouping 3-3

5.1 LVD Driver 5-3

5.2 LVD Receiver 5-4

5.3 Rise and Fall Time Test Condition 5-8

5.4 SCSI Input Filtering 5-8

5.5 External Clock 5-9

5.6 Reset Input 5-10

5.7 Interrupt Output 5-11

5.8 NVSRAM Read Cycle 5-13

5.9 NVSRAM Write Cycle 5-15

5.10 Flash ROM Read Cycle 5-17

5.11 Flash ROM Write Cycle 5-19

5.12 LSI53C1020 456-Pin BGA Top View 5-21

5.13 LSI53C1020A 384-Pin BGA, Top View 5-26

5.14 456-Pin EPBGA (KY) Mechanical Drawing 5-31

5.15 384-Ball Count EPBGA (HT) Mechanical Drawing

(Sheet 1 of 2) 5-32

5.16 448-Ball Count EPBGA (5B) Mechanical Drawing

(Sheet 1 of 2) 5-34

Contents xi

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

xii Contents

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Tables

2.1 PCI/PCI-X Bus Commands and Encodings 2-10

2.2 Power States 2-16

2.3 Flash ROM Size Programming 2-24

2.4 Flash Signature Value 2-26

2.5 PCI Configuration Record in Serial EEPROM 2-27

2.6 20-Pin Multi-ICE Header Pinout 2-30

3.1 PCI System Signals 3-4

3.2 PCI Address and Data Signals 3-5

3.3 PCI Interface Control Signals 3-6

3.4 PCI Arbitration Signals 3-6

3.5 PCI Error Reporting Signals 3-7

3.6 PCI Interrupt Signal 3-7

3.7 PCI-Related Signals 3-8

3.8 SCSI Bus Clock Signal 3-9

3.9 SCSI Channel Interface Signals 3-9

3.10 SCSI Channel Control Signals 3-11

3.11 Flash ROM/NVSRAM Interface Signals 3-12

3.12 Serial EEPROM Interface Signals 3-13

3.13 ZCR Configuration Signals 3-13

3.14 JTAG, ICE, and Debug Signals 3-14

3.15 LSI Logic Test Signals 3-15

3.16 GPIO and LED Signals 3-16

3.17 Power and Ground Pins 3-16

3.18 No Connect Pins 3-18

3.19 MAD Power-On Sense Pin Options 3-19

3.20 Flash ROM Size Programming 3-21

3.21 Pull-Up and Pull-Down Signal Conditions 3-22

4.1 LSI53C1020 PCI Configuration Space Address Map 4-2

4.2 Subsystem ID Register Download Conditions and Values 4-15

4.3 PCI I/O Space Address Map 4-32

4.4 PCI Memory [0] Address Map 4-33

4.5 PCI Memory [1] Address Map 4-33

5.1 Absolute Maximum Stress Ratings 5-2

5.2 Operating Conditions 5-2

Contents xiii

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

5.3 LVD Driver SCSI Signals – SACK±,SATN±, SBSY±,

SCD±, SD[15:0]±, SDP[1:0]±, SIO±, SMSG±, SREQ±,
SRST±, SSEL± 5-3

5.4 LVD Receiver SCSI Signals – SACK±,SATN±, SBSY±,

SCD±, SD[15:0]±, SDP[1:0]±, SIO±, SMSG±, SREQ±,
SRST±, SSEL± 5-4

5.5 DIFFSENS SCSI Signal 5-4

5.6 Input Capacitance 5-4

5.7 8 mA Bidirectional Signals – GPIO[7:0], MAD[15:0],

MADP[1:0], SerialDATA 5-5

5.8 8 mA PCI Bidirectional Signals – ACK64/, AD[63:0],

C_BE[7:0]/, DEVSEL/, FRAME/, IRDY/, PAR, PAR64,
PERR/, REQ64/, SERR/, STOP/, TRDY/ 5-5

5.9 Input Signals – CLK, DIS_PCI_FSN/, DIS_SCSI_FSN/,

GNT/, IDDTN, IDSEL, IOPD_GNT, BZRESET, BZVDD,
JtagMode, SCANEN, SCAN_MODE, SCLK, TCK_CHIP,
TCK_ICE, TESTACLK, TM, TESTHCLK, TDI_CHIP,
TDI_ICE, TMS_CHIP, TMS_ICE, TN, TRST_ICE/,
TST_RST/, ZCR_EN/ 5-6

5.10 8 mA Output Signals – ALT_INTA/, RAMWE[1:0]/,

FLSHALE[1:0]/, FLSHCE/, INTA/, RAMOE/, RAMCE/,
REQ/, RTCK_ICE, SerialCLK, TDO_CHIP, TDO_ICE 5-6

5.11 12 mA Output Signals – A_LED/, HB_LED/ 5-6

5.12 TolerANT Technology Electrical Characteristics for

SE SCSI Signals 5-7

5.13 External Clock 5-9

5.14 Reset Input 5-10

5.15 Interrupt Output 5-11

5.16 NVSRAM Read Cycle Timing 5-12

5.17 NVSRAM Write Cycle 5-14

5.18 Flash ROM Read Cycle Timing 5-16

5.19 Flash ROM Write Cycle 5-18

5.20 LSI53C1020 456-Pin Pinout by Signal Name 5-22

5.21 LSI53C1020 456-Pin Pinout by BGA Position 5-24

5.22 LSI53C1020A 384-Pin Pinout by Signal Name 5-27

5.23 LSI53C1020A 384-Pin Pinout by BGA Position 5-29

A.24 LSI53C1020 PCI Registers A-1
A.25 LSI53C1020 PCI I/O Space Registers A-3
A.26 LSI53C1020 PCI Memory [0] Registers A-4

xiv Contents

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Chapter 1
Introduction

This chapter provides a general overview of the LSI53C1020/1020A
PCI-X to Ultra320 SCSI Controller. This chapter contains the following
sections:

• Section 1.1, “General Description”

• Section 1.2, “Benefits of the Fusion-MPT Architecture”

• Section 1.3, “Benefits of PCI-X”

• Section 1.4, “Benefits of Ultra320 SCSI”

• Section 1.5, “Benefits of SureLINK (Ultra320 SCSI Domain

Validation)”

• Section 1.6, “Benefits of LVDlink Technology”

• Section 1.7, “Benefits of TolerANT® Technology”

• Section 1.8, “Summary of LSI53C1020 Features”

1.1 General Description

The LSI53C1020/1020A PCI-X to Single Channel Ultra320 SCSI
Controllers bring Ultra320 SCSI performance to host adapter,
workstation, and server designs, making it easy to add a high­performance SCSI bus to any PCI or PCI-X system.

The LSI53C1020 SCSI controller is available in a 456-pin BGA package.
The LSI53C1020A SCSI controller is available in a 448-pin BGA package
that is pin-compatible with the LSI53C1020 controller and also in a
smaller 384-pin BGA package.

LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller Technical Manual 1-1

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

The LSI53C1020 controller and the 448-pin BGA package of the
LSI53C1020A controller are pin compatible with the LSI53C1000R PCI
to Ultra160 SCSI Controller, to provide an easy and safe migration path
to Ultra320 SCSI. The LSI53C1020/1020A supports up to a 64-bit, 133
MHz PCI-X bus. The Ultra320 SCSI features for the LSI53C1020/1020A
include: double transition (DT) clocking, packetized protocol, paced
transfers, quick arbitrate and select (QAS), skew compensation,
intersymbol interference (ISI) compensation, cyclic redundancy check
(CRC), and domain validation technology. These features comply with
the American National Standard Institute (ANSI) T10 SCSI Parallel
Interface-4 (SPI-4) draft specification.

DT clocking enables the LSI53C1020/1020A to achieve data transfer
rates of up to 320 megabytes per second (Mbytes/s). Packetizedprotocol
increases data transfer capabilities with SCSI information units. QAS
minimizes SCSI bus latency by allowing the bus to directly enter the
arbitration/selection bus phase after a SCSI disconnect and skip the bus­free phase. Skew compensation permits the LSI53C1020/1020A to
adjust for cable and bus skew on a per-device basis. Paced transfers
enable high-speed data transfers during DT data phases by using the
REQ/ACK transition as a free-running data clock. Precompensation
enables the LSI53C1020/1020A to adjust the signal drive strength to
compensate for the charge present on the cable. CRC improves the
SCSI data transmission integrity through enhanced detection of
communication errors. SureLINK™ Domain Validation detects the SCSI
bus configuration and adjusts the SCSI transfer rate to optimize bus
interoperability and SCSI data transfer rates. SureLINK Domain
Validation provides three levels of domain validation, assuring robust
system operation.

The LSI53C1020/1020A supports a local memory bus, which supports a
standard serial EEPROM and allows local storage of the BIOS in Flash
ROM memory. The LSI53C1020/1020A supports programming of local
Flash ROM memory for BIOS updates. Figure 1.1 shows a typical
LSI53C1020/1020A board application connected to external ROM
memory.

Note: In the rest of this document, LSI53C1020 refers to both the

1-2 Introduction

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

LSI53C1020 SCSI controller and the LSI53C1020A SCSI
controller, unless specifically noted. Chapter 5 includes
pinout diagrams and mechanical drawings for both of these
SCSI controllers.

Figure 1.1 Typical LSI53C1020 Board Application

Memory Control

Block

68-Pin­Wide SCSI
Connector

and

Terminator

Memory

Address/Data

Bus

Serial Data

Serial Clock

Flash ROM

NVSRAM

Serial EEPROM

SCSI Signals

LSI53C1020

64-Bit, 133 MHz

PCI-X to

Ultra320 SCSI

Controller

PCI-X Interface

The LSI53C1020 integrates a high-performance Ultra320 SCSI core and
a 64-bit, 133 MHz PCI-X bus master direct memory access (DMA) core.
The LSI53C1020 employs two ARM966E-S

™

processors to meet the
data transfer flexibility requirements of the Ultra320 SCSI, PCI, and PCI­X specifications. Separate ARM®processors support the SCSI channel
and the PCI/PCI-X interface.

These processors implement the Fusion-MPT™ architecture, a
multithreaded I/O algorithm that supports data transfers between the host
system and SCSI devices with minimal host processor intervention.
Fusion-MPT technology provides an efficient architecture that solves the
protocol overhead problems of previous intelligent and nonintelligent
adapter designs.

LVDlink™ technology is the LSI Logic implementation of Low Voltage
Differential (LVD) SCSI. LVDlink transceivers allow the LSI53C1020 to
perform either Single-Ended (SE) or LVD transfers. Figure 1.2 illustrates
a typical LSI53C1020 system application.

General Description 1-3

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Figure 1.2 Typical LSI53C1020 System Application

LSI53C1020

PCI-X Bus

Interface

Controller

Processor Bus

Central

Processing

Unit

(CPU)

PCI-X Bus

LSI53C1020 PCI-X

to Ultra320 SCSI

PCI Graphic Accelerator

PCI Fast Ethernet

Memory

Controller

Memory

SCSI Bus

Fixed Disk, Optical Disk,

Printer, Tape, and Other

SCSI Peripherals

The LSI53C1020 supports the Integrated RAID™ solution. The
Integrated RAID solution provides cost benefits for the server or
workstation market where the extra performance, storage capacity,
and/or redundancy of a RAID configuration are required. The two
components of the Integrated RAID solution are:

• Integrated Mirroring™ (IM), which provides features of RAID 1 and

RAID 1E. The Integrated Mirroring feature provides physical
mirroring of the boot volume through LSI53C1020 firmware. This
feature provides extra reliability for the system’s boot volume without
burdening the host CPU. The runtime mirroring of the boot drive is
transparent to the BIOS, drivers, and operating system.

• Integrated Striping™ (IS), which provides features of RAID 0. The

IS feature writes data across multiple disks instead of onto one disk.
This is accomplished by partitioning each disk’s storage space into

1-4 Introduction

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

64 Kbyte stripes. These stripes are interleaved round-robin, so that
the combined storage space is composed alternately of stripes from
each disk.

The Fusion-MPT architecture provides the interface to the SCSI
chip/firmware to enable the Integrated Striping and Integrated Mirroring
features. LSI Logic’s CIM interface software is used to continuously
monitor IM volumes and IS volumes and to report status and error
conditions as they arise.

A BIOS-based configuration utility is provided to create the IM and IS
volumes. A DOS-based configuration utility is also provided for use on
the manufacturing floor.

For more information about the Integrated RAID solution, see the
Integrated RAID User’s Guide, DB15-000292.

1.2 Benefits of the Fusion-MPT Architecture

The Fusion-MPT architecture provides an open architecture that is ideal
for SCSI, Fibre Channel, and other emerging interfaces. The I/O interface
is interchangeable at the system and application level; embedded
software uses the same device interface for SCSI and Fibre Channel
implementations, just as application software uses the same storage
management interfaces for SCSI and Fibre Channel implementations.
LSI Logic provides Fusion-MPT device drivers that are binary compatible
between Fibre Channel and Ultra320 SCSI interfaces.

The Fusion-MPT architecture improves overall system performance by
requiring only a thin device driver, which offloads the intensive work of
managing SCSI I/Os from the system processor to the LSI53C1020.
Developed from the proven SDMS™ solution, the Fusion-MPT
architecture delivers unmatched performance of up to 50,000 Ultra320
SCSI I/Os per second with minimal system overhead or device
maintenance. The use of thin, easy-to-develop, common OS device
drivers accelerates time to market by reducing device driver development
and certification times.

The Fusion-MPT architecture provides an interrupt coalescing feature.
Interrupt coalescing allows an I/O controller to send multiple reply
messages in a single interrupt to the host processor. Sending multiple

Benefits of the Fusion-MPT Architecture 1-5

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

reply messages per interrupt reduces context switching of the host
processor and maximizes the host processor efficiency, which results in
a significant improvement of system performance. To use the interrupt
coalescing feature, the host processor must be able to accept and
manage multiple replies per interrupt.

The Fusion-MPT architecture also provides built-in device driver stability
because the device driver need not change for each revision of the
LSI53C1020 silicon or firmware. This architecture is a reliable, constant
interface between the host device driver and the LSI53C1020. Changes
within the LSI53C1020 are transparent to the host device driver,
operating system, and user. The Fusion-MPT architecture also saves the
user significant development and maintenance effort because it is not
necessary to alter or redevelop the device driver when a revision of the
LSI53C1020 device or firmware occurs.

1.3 Benefits of PCI-X

PCI-X doubles the maximum clock frequency of the conventional PCI
bus. The PCI-X Addendum to the PCI Local Bus Specification,

Revision 1.0a, defines enhancements to the proven PCI Local Bus
Specification, Revision 2.2. PCI-X provides more efficient data transfers

by enabling registered inputs and outputs, improves buffer management
by including transaction information with each data transfer, and reduces
bus overheadby restricting the use of wait states and disconnects. PCI-X
also reduces host processor overhead by providing a wide range of error
recovery implementations.

The LSI53C1020 supports up to a 133 MHz, 64-bit PCI-X bus and is
backward compatible with previous versions of the PCI/PCI-X bus. The
LSI53C1020 includes transaction information with all PCI-X transactions
to enable more efficient buffer management schemes. Each PCI-X
transaction contains a transaction sequence identifier (Tag), the identity
of the initiator, and the number of bytes in the sequence. The
LSI53C1020 clocks PCI-X data directly into and out of registers, which
creates a more efficient data path. The LSI53C1020 increases bus
efficiency because it does not insert wait states after the initial data
phase when acting as a PCI-X target and never inserts wait states when
acting as a PCI-X initiator.

1-6 Introduction

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

1.4 Benefits of Ultra320 SCSI

Ultra320 SCSI is an extension of the SPI-4 draft specification that allows
faster synchronous SCSI data transfer rates than Ultra160 SCSI. When
enabled, Ultra320 SCSI performs 160 megatransfers per second,
resulting in approximately double the synchronous data transfer rates of
Ultra160 SCSI. The LSI53C1020 performs 16-bit, Ultra320 SCSI
synchronous data transfers as fast as 320 Mbytes/s. This advantage is
most noticeable in heavily loaded systems or large block size
applications, such as video on-demand and image processing.

Ultra320 SCSI doubles both the data and clock frequencies from
Ultra160 SCSI. Due to the increased data and clock speeds,
Ultra320 SCSI introduces skew compensation and ISI compensation.
These new features simplify system design by resolving timing issues at
the chip level. Skew compensation adjusts for timing differences between
data and clock signals caused by cabling, board traces, and so on. ISI
compensation enhances the first pulse after a change in state to ensure
data integrity.

Ultra320 SCSI includes CRC, which offers higher levels of data reliability
by ensuring complete integrity of transferred data. CRC is a 32-bit
scheme, referred to as CRC-32. CRC guarantees detection of all single
or double bit errors, as well as any combination of bit errors within a
single 32-bit range.

1.5 Benefits of SureLINK (Ultra320 SCSI Domain Validation)

SureLINK Domain Validation software ensures robust SCSI interconnect
management and low-risk Ultra320 SCSI implementations by extending
the domain validation guidelines documented in the SPI-4 specifications.
Domain validation verifies that the system is capable of transferring data
at Ultra320 SCSI speeds, allowing the LSI53C1020 to renegotiate to a
lower data transfer speed and bus width if necessary. SureLINK Domain
Validation is the software control for the domain validation manageability
enhancements in the LSI53C1020. SureLINK Domain Validationsoftware
provides domain validation management at boot time as well as during
system operation.

Benefits of Ultra320 SCSI 1-7

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

SureLINK Domain Validation provides three levels of integrity checking
on a per-device basis: Basic (Level 1) with inquiry command; Enhanced
(Level 2) with read/write buffer; and Margined (Level 3) with margining
of drive strength and slew rates.

1.6 Benefits of LVDlink Technology

The LSI53C1020 supports LVD through LVDlink technology. This
signaling technology increases the reliability of SCSI data transfers over
longer distances than are supported by SE SCSI. The low current output
of LVD allows the I/O transceivers to be integrated directly onto the chip.
To allow the use of the LSI53C1020 in both legacy and Ultra320 SCSI
applications, this device features universal LVDlink transceivers that
support LVD SCSI and SE SCSI.

1.7 Benefits of TolerANT®Technology

The LSI53C1020 features TolerANT technology, which provides active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation causes the SCSI Request, Acknowledge,
Data, and Parity signals to be actively driven HIGH rather than passively
pulled up by terminators.

TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
ensure correct clocking of data. TolerANT input signal filtering is a built­in feature of the LSI53C1020 and all LSI Logic Fast SCSI, Ultra SCSI,
Ultra2 SCSI, Ultra160 SCSI, and Ultra320 SCSI devices.

TolerANT technology increases noise immunity, balances duty cycles,
and improves SCSI transfer rates. In addition, TolerANT SCSI devices
do not cause glitches on the SCSI bus at power-up or power-down,
which protects other devices on the bus from data corruption. When used
with the LVDlink transceivers, TolerANT technology provides excellent
signal quality and data reliability in real world cabling environments.

1-8 Introduction

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

TolerANT technology is compatible with both the Alternative One and
Alternative Two termination schemes proposed by ANSI.

1.8 Summary of LSI53C1020 Features

This section provides a summary of the LSI53C1020 features and
benefits. It contains information on SCSI Performance, PCI Performance,

Integration, Flexibility, Reliability, and Testability.

1.8.1 SCSI Performance

The LSI53C1020 contains the following SCSI performance features:

• Supports Ultra320 SCSI

– Paced transfers using a free-running clock
– 320 Mbytes/s SCSI data transfer rate
– Mandatory packetized protocol
– Quick arbitrate and select (QAS)
– Skew compensation with bus training
– Transmitter precompensation to overcome ISI effects for SCSI

data signals

– Retained training information (RTI)

• Offers a performance-optimized architecture

– Two ARM966E-S processors provide high performance with low

latency

– Designed for optimal packetized performance

• Uses proven integrated LVDlink transceivers for direct attach to either

LVD or SE SCSI buses with precision-controlled slew rates

• Supports expander communication protocol (ECP)

• Uses the Fusion-MPT (Message Passing Technology) drivers to

provide full operating system support for the Windows, Linux,Solaris,
SCO OpenServer, UnixWare, OpenUnix 8, and NetWare operating
systems

Summary of LSI53C1020 Features 1-9

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

1.8.2 PCI Performance

The LSI53C1020 supports the following PCI features:

• Has a 133 MHz, 64-bit PCI/PCI-X interface that:

– Operates at 33 MHz or 66 MHz PCI
– Operates at up to 133 MHz PCI-X
– Supports 32-bit or 64-bit data
– Supports 32-bit or 64-bit addressing through Dual Address Cycles

(DA Cs)
– Provides a theoretical 1066 Mbytes/s zero wait state transfer rate
– Complies with PCI Local Bus Specification, Revision 2.2

(LSI53C1020) or Revision 2.3 (LSI53C1020A)
– Complies with the PCI-X Addendum to the PCI Local Bus

Specification, Revision 1.0a
– Complies with the PCI Power Management Interface

Specification, Revision 1.1

– Complies with the PC2001 System Design Guide

• Offers unmatched performance through the Fusion-MPT architecture

• Provides high throughput and low CPU utilization to offload the host
processor

• Uses SCSI Interrupt Steering Logic (SISL) to provide alternate
interrupt routing for RAID applications

• Reduces Interrupt Service Routine (ISR) overhead with interrupt
coalescing

• Supports 32-bit or 64-bit data bursts with variable burst lengths

• Supports the PCI Cache Line Size register

• Supports the PCI Memory Write and Invalidate, Memory Read Line,
and Memory Read Multiple commands

• Supports the PCI-X Memory Read Dword, Split Completion, Memory
Read Block, and Memory Write Block commands

• Supports up to eight PCI-X outstanding split transactions

• Supports Message Signaled Interrupts (MSIs)

1-10 Introduction

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

1.8.3 Integration

The following features make the LSI53C1020 easy to integrate:

• Is backward compatible with previous revisions of the PCI and SCSI

• 448-pin and 456-pin BGA packages are pin compatible with the

• Provides a low-risk migration path to Ultra320 SCSI from the

• Supports a full 32-bit or 64-bit PCI/PCI-X DMA bus master

• Reduces time to market with the Fusion-MPT architecture

• Provides integrated LVDlink transceivers

specifications

LSI53C1000R SCSI controller

LSI53C1000R

– Single driver binary for SCSI and Fibre Channel products
– Thin, easy to develop drivers
– Reduced integration and certification effort

1.8.4 Flexibility

The following features increase the flexibility of the LSI53C1020:

• Universal LVD transceivers are backward compatible with SE

• Provides a flexible programming interface to tune I/O performance or

• Supports MSI or pin-based (INTA/ or ALT_INTA/) interrupt signaling

• Can respond with multiple SCSI IDs

• Is compatible with 3.3 V and 5.0 V PCI signaling

1.8.5 Reliability

devices

to adapt to unique SCSI devices

– Drives and receives 3.3 V PCI signals
– Receives 5.0 V PCI if the PCI5VBIAS pin connects to 5.0 V, but

does not drive 5.0 V signals on the PCI bus

The following features enhance the reliability of the LSI53C1020:

• Supports ISI compensation

Summary of LSI53C1020 Features 1-11

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

• Provides 2 kV electrostatic discharge (ESD) protection on SCSI
signals

• Provides latch-up protection greater than 150 mA

• Provides voltage feed-through protection

• Supports the Integrated RAID (IR) solution to provide physical
mirroring or striping of the boot volume

• Has a high proportion of power and ground pins

• Provides power and ground isolation of I/O pads and internal chip
logic

• Supports CRC checking and generation in double transition (DT)
phases

• Provides comprehensive SureLINK Domain Validation technology:
– Basic (Level 1) with inquiry command
– Enhanced (Level 2) with read/write buffer
– Margined (Level 3) with margining of drive strength and slew

rates

• Supports TolerANT technology, which provides:

1.8.6 Testability

These features enhance the testability of the LSI53C1020:

• Allows all SCSI signals to be accessed through programmed I/O

• Supports JTAG boundary scan

• Provides ARM Multi-ICE®test interface for debugging purposes

– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved SCSI transfer rates

– Input signal filtering on SCSI receivers for improved data

integrity, even in noisy cabling environments

1-12 Introduction

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Chapter 2
Functional Description

This chapter provides a subsytem level overview of the LSI53C1020, a
discussion of the Fusion-MPT architecture, and a functional description
of the LSI53C1020 interfaces. This chapter contains the following
sections:

• Section 2.1, “Block Diagram Description”

• Section 2.2, “Fusion-MPT Architecture Overview”

• Section 2.3, “PCI Functional Description”

• Section 2.4, “Ultra320 SCSI Functional Description”

• Section 2.5, “External Memory Interfaces”

• Section 2.6, “Serial EEPROM Interface”

• Section 2.7, “Zero Channel RAID”

• Section 2.8, “Multi-ICE Test Interface”

The LSI53C1020 is a high-performance, intelligent PCI-X to Ultra320
SCSI Controller. The LSI53C1020 controller supports the PCI Local Bus
Specification, Revision 2.2; the LSI53C1020A controller supports
Revision 2.3 of this spec. Both controllers support the PCI-X Addendum

to the PCI Local Bus Specification, Revision 1.0a and the proposed SCSI
Parallel Interface-4 (SPI-4) draft standard.

Note: In the rest of this chapter, LSI53C1020 refers to both the

LSI53C1020 SCSI controller and the LSI53C1020A SCSI
controller, unless specifically noted.

The LSI53C1020 employs the Fusion-MPT architecture to ensure robust
system performance, to support binary compatibility of host software
between the LSI Logic SCSI and Fibre Channel products, and to
significantly reduce software development time. Refer to the Fusion-MPT

Device Management User’s Guide for more information on the

LSI53C1020/1020A PCI-X to Ultra320 SCSI Controller Technical Manual 2-1

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Fusion-MPT architecture and how to control the LSI53C1020 using
Fusion-MPT technology.

2.1 Block Diagram Description

The LSI53C1020 consists of two major modules: a host interface module
and an Ultra320 SCSI channel module. The modules consist of the
following components:

• Host Interface Module

– Up to a 64-bit, 133 MHz PCI/PCI-X Interface
– System Interface
– I/O Processor (IOP)
– DMA Arbiter and Router
– Shared RAM
– External Memory Interface

◊ Flash ROM Memory Controller
◊ NVSRAM

– Timer and Configuration Control

◊ Device Configuration Controller
◊ Serial EEPROM Interface Controller
◊ General Purpose I/O (GPIO) Interface
◊ Chip Timer

• Ultra320 SCSI Channel Module

– Datapath Engine
– Context Manager
– Ultra320 SCSI Core

Figure 2.1 illustrates the relationship between these modules.

2-2 Functional Description

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

Figure 2.1 LSI53C1020 Block Diagram

Host Interface Module

PCI/

PCI-X

PCI/PCI-X

Interface

DMA

Arbiter

and

Router

SCSI Channel Module

System Interface

IOP

(ARM966E-S

Processor)

Primary Bus

External
Memory

Flash ROM/

NVSRAM

Timer, GPIO,

and EEPROM

SerialGPIO

EEPROM

Bus to Bus

Bridge

Shared

RAM

Datapath Engine

Secondary Bus

Context Manager

(ARM966E-S

Processor)

Ultra320

SCSI

Ultra320 SCSI

Core

2.1.1 Host Interface Module Description

The host interface module provides an interface between the host driver
and the SCSI channel. The host interface module controls system DMA
transfers and the host side of the Fusion-MPT architecture. It also
supports the external memory, serial EEPROM, and GPIO interfaces.
This subsection provides a detailed explanation of the host interface
submodules.

Block Diagram Description 2-3

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.

2.1.1.1 PCI Interface

The LSI53C1020 provides a PCI-X interface that supports up to a 64-bit,
133 MHz PCI-X bus. The interface is compatible with all previous
implementations of the PCI specification. For more information on the
PCI interface, refer to Section 2.3, “PCI Functional Description,”

page 2-8.

2.1.1.2 System Interface

The system interface efficiently passes messages between the
LSI53C1020 and other I/O agents using a high-performance, packetized,
mailbox architecture. The LSI53C1020 system interface coalesces PCI
interrupts to minimize traffic on the PCI bus and maximize system
performance.

All host accesses to the IOP, external memory, and timer and
configuration subsystems pass through the system interface and use the
primary bus. The host system initiates data transactions on the primary
bus with the system interface registers. PCI Memory Space [0] and the
PCI I/O Base Address registers identify the location of the system
interface register set. Chapter 4, “PCI Host Register Description,”
provides a bit-level description of the system interface register set.

2.1.1.3 I/O Processor (IOP)

The LSI53C1020 I/O processor (IOP) is a 32-bit ARM966E-S RISC
processor. The IOP controls the system interface and uses the
Fusion-MPT architecture to manage the host side of non-DMA accesses
to the Ultra320 SCSI bus. The context manager uses the Fusion-MPT
architecture to control the SCSI side of data transfers. The IOP and
Context Manager completely manage all SCSI I/Os without host
intervention. Refer to Section 2.2, “Fusion-MPT Architecture Overview,”

page 2-7, for more information on the Fusion-MPT architecture.

2.1.1.4 DMA Arbiter and Router

The descriptor-based DMA Arbiter and Router subsystem manages the
transfer of memory blocks between local memory and the host system.
The DMA channel includes PCI bus master interface logic, the internal
bus interface logic, and a 256-byte system DMA FIFO.

2-4 Functional Description

Version 2.4 Copyright © 2001–2004 by LSI Logic Corporation. All rights reserved.