Avago Technologies LSI53C1010R User Manual

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TECHNICAL

MANUAL

LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller

August 2003

Version 2.2

DB14-000153-04

This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an ofﬁcer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic ofﬁcer is prohibited.

Document DB14-000153-04, Version 2.2 (August 2003) This document describes the LSI Logic LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller and will remain the ofﬁcial reference source for all revisions/releases of this product until rescinded by an update.

LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.

Ultra/Ultra2/Ultra3/Ultra160 SCSI are terms used by the SCSI Trade Association (STA) to describe various SCSI speciﬁcations. Refer to the

subsection entitled “Related Publications,” for details on SCSI speciﬁcations.

LSI Logic, the LSI Logic logo design, LVDlink, SCRIPTS, SDMS, SURElink, and TolerANT are registered trademarks or trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies.

To receive product literature, visit us at http://www.lsilogic.com. For a current list of our distributors, sales ofﬁces, and design resource

centers, view our web page located at http://www.lsilogic.com/contacts/index.html

Audience

Organization

Preface

This book is the primary reference and technical manual for the LSI Logic LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller. It contains a complete functional description for the product and includes complete physical and electrical speciﬁcations.

This document was prepared for system designers and programmers who are using this device to design an Ultra160 SCSI port for PCI-based personal computers, workstations, servers or embedded applications.

This document has the following chapters and appendixes:

• Chapter 1, Introduction, describes the general information about the

LSI53C1010R.

• Chapter 2, Functional Description, describes the main functional

areas of the chip in greater detail, including the interfaces to the SCSI bus and external memory.

• Chapter 3, Signal Descriptions, contains the pin diagram and signal

descriptions.

• Chapter 4, Registers, describes each bit in the operating registers,

and is organized by register address.

• Chapter 5, SCSI SCRIPTS Instruction Set, deﬁnes all of the SCSI

SCRIPTS™ instructions that are supported by the LSI53C1010R.

• Chapter 6, Speciﬁcations, contains the electrical characteristics and

AC timing diagrams.

• Appendix A, Register Summary, is a register summary.

Preface iii

• Appendix B, External Memory Interface Diagram Examples,

Related Publications

For background please contact:

ANSI

www.ansi.org

11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

www.global.ihs.com

15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740 Ask for document number X3.131-1994 (SCSI-2) or X3.253

(SCSI-3 Parallel Interface)

contains several example interface drawings for connecting the LSI53C1010R to external ROMs.

ENDL Publications

www.rahul.net/endl/

14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI Tutor

Prentice Hall

113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding

the Small Computer System Interface

iv Preface

LSI Logic World Wide Web Home Page

www.lsil.com

SCSI SCRIPTS™ Processors Programming Guide, Document No. DB15-000159-01

PCI Special Interest Group

www.pcisig.org

2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344

Conventions Used in This Manual

The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the preﬁx “0x”—for example, 0x32CF. Binary numbers are indicated by the preﬁx “0b”—for example, 0b0011.0010.1100.1111.

Revision Record

Revision Date Remarks

1.0 6/2000 Preliminary version for engineering review.

2.0 11/2000 Final version.

2.1 5/2001 Changes to Chapter 3 and Chapter 6 pertaining to pinouts.

2.2 7/2003 Added instructions for setting the GPIO registers. Changed Vih (max) to

11.0 V in Table 6.10. Corrected VSSC ball assignment to C26 in Table

6.52. In Table 3.1, changed GPIO[4:0] pins to “Pulled down internally.”

Preface v

vi Preface

Contents

Chapter 1 Introduction

1.1 General Description 1-1

1.2 Beneﬁts of Ultra160 SCSI 1-4

1.3 Beneﬁts of SURElink (Ultra160 SCSI Domain Validation) Technology 1-5

1.4 Beneﬁts of LVDlink Technology 1-5

1.5 Beneﬁts of TolerANT®Technology 1-6

1.6 Summary of LSI53C1010R Beneﬁts 1-7

1.6.1 SCSI Performance 1-7

1.6.2 PCI Performance 1-8

1.6.3 Integration 1-9

1.6.4 Ease of Use 1-9

1.6.5 Flexibility 1-10

1.6.6 Reliability 1-11

1.6.7 Testability 1-11

Chapter 2 Functional Description

2.1 PCI Functional Description 2-2

2.1.1 PCI Addressing 2-3

2.1.2 PCI Bus Commands and Functions Supported 2-4

2.1.3 Internal Arbiter 2-11

2.1.4 PCI Cache Mode 2-11

2.2 SCSI Functional Description 2-18

2.2.1 SCRIPTS Processor 2-19

2.2.2 Internal SCRIPTS RAM 2-20

2.2.3 64-Bit Addressing in SCRIPTS 2-21

2.2.4 Hardware Control of SCSI Activity LED 2-21

2.2.5 Designing an Ultra160 SCSI System 2-22

2.2.6 Prefetching SCRIPTS Instructions 2-31

Contents vii

2.2.7 Opcode Fetch Burst Capability 2-32

2.2.8 Load and Store Instructions 2-33

2.2.9 JTAG Boundary Scan Testing 2-33

2.2.10 Parity/CRC/AIP Options 2-34

2.2.11 DMA FIFO 2-36

2.2.12 SCSI Data Paths 2-37

2.2.13 SCSI Bus Interface 2-39

2.2.14 Select/Reselect during Selection/Reselection 2-41

2.2.15 Synchronous Operation 2-41

2.2.16 Interrupt Handling 2-45

2.2.17 Interrupt Routing 2-53

2.2.18 Chained Block Moves 2-55

2.3 Parallel ROM Interface 2-59

2.4 Serial EEPROM Interface 2-60

2.4.1 Default Download Mode 2-60

2.4.2 No Download Mode 2-61

2.5 Power Management 2-61

2.5.1 Power State D0 2-62

2.5.2 Power State D1 2-62

2.5.3 Power State D2 2-63

2.5.4 Power State D3 2-63

Chapter 3 Signal Descriptions

3.1 Signal Organization 3-1

3.2 Internal Pull-ups and Pull-downs on LSI53C1010R Signals 3-4

3.3 PCI Bus Interface Signals 3-5

3.3.1 System Signals 3-5

3.3.2 Address and Data Signals 3-6

3.3.3 Interface Control Signals 3-7

3.3.4 Arbitration Signals 3-8

3.3.5 Error Reporting Signals 3-8

3.3.6 Interrupt Signals 3-9

3.4 SCSI Bus Interface Signals 3-10

3.4.1 SCSI Function A Signals 3-10

3.4.2 SCSI Function B Signals 3-13

3.5 General Purpose I/O (GPIO) Signals 3-16

3.6 Flash ROM and Memory Interface Signals 3-18

viii Contents

3.7 Test Interface Signals 3-19

3.8 Power and Ground Signals 3-20

3.9 MAD Bus Programming 3-22

Chapter 4 Registers

4.1 PCI Conﬁguration Registers 4-1

4.2 SCSI Registers 4-22

4.3 SCSI Shadow Registers 4-125

Chapter 5 SCSI SCRIPTS Instruction Set

5.1 SCSI SCRIPTS 5-1

5.2 Block Move Instructions 5-5

5.2.1 First Dword 5-5

5.2.2 Second Dword 5-15

5.2.3 Third Dword 5-15

5.3 I/O Instructions 5-16

5.3.1 First Dword 5-16

5.3.2 Second Dword 5-24

5.4 Read/Write Instructions 5-24

5.4.1 First Dword 5-24

5.4.2 Second Dword 5-26

5.4.3 Read-Modify-Write Cycles 5-26

5.4.4 Move to/from SFBR Cycles 5-26

5.5 Transfer Control Instructions 5-28

5.5.1 First Dword 5-28

5.5.2 Second Dword 5-35

5.5.3 Third Dword 5-35

5.6 Memory Move Instructions 5-36

5.6.1 Read/Write System Memory from a SCRIPT 5-37

5.6.2 Second Dword 5-38

5.6.3 Third Dword 5-38

5.7 Load and Store Instructions 5-39

5.7.1 First Dword 5-40

5.7.2 Second Dword 5-42

Contents ix

Chapter 6 Speciﬁcations

6.1 DC Characteristics 6-1

6.2 TolerANT Technology Electrical Characteristics 6-7

6.3 AC Characteristics 6-10

6.4 PCI and External Memory Interface Timing Diagrams 6-13

6.4.1 Target Timing 6-14

6.4.2 Initiator Timing 6-21

6.4.3 External Memory Timing 6-37

6.5 SCSI Timing Diagrams 6-58

6.6 Package Drawings 6-67

Appendix A Register Summary

Appendix B External Memory Interface Diagram Examples

Index

Customer Feedback

x Contents

Figures

1.1 Typical LSI53C1010R Board Application 1-2

1.2 Typical LSI53C1010R System Application 1-3

2.1 LSI53C1010R Block Diagram 2-2

2.2 DMA FIFO Sections 2-36

2.3 LSI53C1010R Host Interface SCSI Data Paths 2-37

2.4 Regulated Termination for Ultra160 SCSI 2-40

2.5 Determining the Synchronous Transfer Rate 2-45

2.6 Interrupt Routing Hardware Using the LSI53C1010R 2-54

2.7 Block Move and Chained Block Move Instructions 2-55

3.1 LSI53C1010R Functional Signal Grouping 3-3

4.1 Single Transition Transfer Waveforms 4-106

4.2 Double Transition Transfer Waveforms

(XCLKS Examples) 4-107

4.3 Double Transition Transfer Waveforms

(XCLKH Examples) 4-108

5.1 SCRIPTS Overview 5-4

5.2 Block Move Instruction – First Dword 5-5

5.3 Block Move Instruction – Second Dword 5-15

5.4 Block Move Instruction – Third Dword 5-15

5.5 First 32-Bit Word of the I/O Instruction 5-16

5.6 Second 32-Bit Word of the I/O Instruction 5-24

5.7 Read/Write Instruction – First Dword 5-24

5.8 Read/Write Instruction – Second Dword 5-26

5.9 Transfer Control Instructions – First Dword 5-28

5.10 Transfer Control Instructions – Second Dword 5-35

5.11 Transfer Control Instructions – Third Dword 5-35

5.12 Memory Move Instructions – First Dword 5-37

5.13 Memory Move Instructions – Second Dword 5-38

5.14 Memory Move Instructions – Third Dword 5-38

5.15 Load and Store Instruction – First Dword 5-40

5.16 Load and Store Instructions – Second Dword 5-42

6.1 LVD Driver 6-3

6.2 LVD Receiver 6-4

6.3 Rise and Fall Time Test Condition 6-8

6.4 SCSI Input Filtering 6-8

6.5 Hysteresis of SCSI Receivers 6-9

6.6 Input Current as a Function of Input Voltage 6-9

6.7 Output Current as a Function of Output Voltage 6-10

6.8 External Clock 6-11

6.9 Reset Input 6-12

6.10 Interrupt Output 6-12

6.11 PCI Conﬁguration Register Read 6-15

6.12 PCI Conﬁguration Register Write 6-16

6.13 Operating Registers/SCRIPTS RAM Read, 32 Bits 6-17

6.14 Operating Register/SCRIPTS RAM Read, 64 Bits 6-18

6.15 Operating Register/SCRIPTS RAM Write, 32 Bits 6-19

6.16 Operating Register/SCRIPTS RAM Write, 64 Bits 6-20

6.17 Nonburst Opcode Fetch, 32-Bit Address and Data 6-22

6.18 Burst Opcode Fetch, 32-Bit Address and Data 6-24

6.19 Back to Back Read, 32-Bit Address and Data 6-26

6.20 Back to Back Write, 32-Bit Address and Data 6-28

6.21 Burst Read, 32-Bit Address and Data 6-30

6.22 Burst Read, 64-Bit Address and Data 6-32

6.23 Burst Write, 32-Bit Address and Data 6-34

6.24 Burst Write, 64-Bit Address and Data 6-36

6.25 External Memory Read 6-38

6.26 External Memory Write 6-42

6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte

Access Read Cycle 6-45

6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte

Access Write Cycle 6-47

6.29 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte

Access Read Cycle 6-48

6.30 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte

Access Write Cycle 6-50

6.31 Slow Memory (≥ 128 Kbytes) Read Cycle 6-53

6.32 Slow Memory (≥ 128 Kbytes) Write Cycle 6-55

6.33 ≤ 64 Kbytes ROM Read Cycle 6-56

6.34 ≤ 64 Kbytes ROM Write Cycle 6-57

6.35 Initiator Asynchronous Send 6-58

6.36 Initiator Asynchronous Receive 6-59

6.37 Target Asynchronous Send 6-59

6.38 Target Asynchronous Receive 6-60

6.39 Initiator and Target ST Synchronous Transfer 6-62

xii

6.40 Initiator and Target DT Synchronous Transfer 6-65

6.41 LSI53C1010R 456 BGA Chip – Top View 6-68

6.42 LSI53C1010R 456 BGA Mechanical Drawing 6-74

B.1 16 Kbyte Interface with 200 ns Memory B-1 B.2 64 Kbyte Interface with 150 ns Memory B-2 B.3 128, 256, 512 Kbyte or 1 Mbyte Interface

with 150 ns Memory B-3

B.4 512 Kbyte Interface with 150 ns Memory B-4

xiii

xiv

Tables

2.1 PCI Bus Commands and Encoding Types 2-5

2.2 PCI Cache Mode Alignment 2-12

2.3 New Phases on SCSI Bus 2-24

2.4 Bits Used for Parity/CRC/AIP Control and Generation 2-34

2.5 SCSI Parity Errors and Interrupts 2-36

2.6 SCF Divisor Values 2-42

2.7 Parallel ROM Support 2-59

2.8 Default Download Mode Serial EEPROM Data Format 2-61

2.9 Power States 2-62

3.1 LSI53C1010R Internal Pull-ups and Pull-downs 3-4

3.2 System Signals 3-5

3.3 Address and Data Signals 3-6

3.4 Interface Control Signals 3-7

3.5 Arbitration Signals 3-8

3.6 Error Reporting Signals 3-8

3.7 Interrupt Signals 3-9

3.8 SCSI Bus Interface Signal 3-10

3.9 SCSI Function A Signals 3-10

3.10 SCSI Function A Control Signals 3-12

3.11 SCSI Function B Signals 3-13

3.12 SCSI Function B Control Signals 3-15

3.13 SCSI Function A GPIO Signals 3-16

3.14 SCSI Function B GPIO Signals 3-17

3.15 Flash ROM and Memory Interface Signals 3-18

3.16 Test Interface Signals 3-19

3.17 Power and Ground Signals 3-20

3.18 MAD[3:1] Pin Decoding 3-23

4.1 PCI Conﬁguration Register Map 4-2

4.2 SCSI Register Map 4-23

4.3 Maximum Synchronous Offset 4-35

4.4 Double Transition Transfer Rates 4-109

4.5 Single Transition Transfer Rates 4-111

5.1 Read/Write Instructions 5-27

6.1 Absolute Maximum Stress Ratings 6-2

6.2 Operating Conditions 6-2

6.3 LVD Driver SCSI Signals – SD[15:0], SDP[1:0], SREQ/,

SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ 6-3

6.4 LVD Receiver SCSI Signals – SD[15:0], SDP[1:0], SREQ/,

SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ 6-3

6.5 A and B DIFFSENS SCSI Signals 6-4

6.6 Input Capacitance 6-4

6.7 8 mA Bidirectional Signals – GPIO0_FETCH/,

GPIO1_MASTER/, GPIO2, GPIO3, GPIO4 6-5

6.8 4 mA Bidirectional Signals – MAD[7:0] 6-5

6.9 4 mA Output Signals – MAS[1:0]/, MCE/,

MOE/_TESTOUT, MWE/, TDO 6-5

6.10 8 mA PCI Bidirectional Signals – AD[63:0], C_BE[7:0]/,

FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64, REQ64/, ACK64/ 6-6

6.11 Input Signals – CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI,

TEST_HSC, TEST_RST/, TMS 6-6

6.12 8 mA Output Signals – INTA/, INTB,/ ALT_INTA/,

ALT_INTB/, REQ/, SERR/ 6-6

6.13 TolerANT Technology Electrical Characteristics

for SE SCSI Signals 6-7

6.14 External Clock 6-11

6.15 Reset Input 6-12

6.16 Interrupt Output 6-12

6.17 PCI Conﬁguration Register Read 6-15

6.18 PCI Conﬁguration Register Write 6-16

6.19 Operating Register/SCRIPTS RAM Read, 32 Bits 6-17

6.20 Operating Register/SCRIPTS RAM Read, 64 Bits 6-18

6.21 Operating Register/SCRIPTS RAM Write, 32 Bits 6-19

6.22 Operating Register/SCRIPTS RAM Write, 64 Bits 6-20

6.23 Nonburst Opcode Fetch, 32-Bit Address and Data 6-21

6.24 Burst Opcode Fetch, 32-Bit Address and Data 6-23

6.25 Back to Back Read, 32-Bit Address and Data 6-25

6.26 Back to Back Write, 32-Bit Address and Data 6-27

6.27 Burst Read, 32-Bit Address and Data 6-29

6.28 Burst Read, 64-Bit Address and Data 6-31

6.29 Burst Write, 32-Bit Address and Data 6-33

6.30 Burst Write, 64-Bit Address and Data 6-35

6.31 External Memory Read 6-37

xvi

6.32 External Memory Write 6-41

6.33 Normal/Fast Memory (≥ 128 Kbytes) Single Byte

Access Read Cycle 6-44

6.34 Normal/Fast Memory (≥ 128 Kbytes) Single Byte

Access Write Cycle 6-46

6.35 Slow Memory (≥ 128 Kbytes) Read Cycle 6-52

6.36 Slow Memory (≥ 128 Kbytes) Write Cycle 6-54

6.37 ≤ 64 Kbytes ROM Read Cycle 6-56

6.38 ≤ 64 Kbytes ROM Write Cycle 6-57

6.39 Initiator Asynchronous Send 6-58

6.40 Initiator Asynchronous Receive 6-59

6.41 Target Asynchronous Send 6-59

6.42 Target Asynchronous Receive 6-60

6.43 SCSI-1 Transfers (SE 5.0 Mbytes) 6-60

6.44 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers)

or 20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-61

6.45 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers)

or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6-61

6.46 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers)

or 80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6-62

6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers)

or 20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-63

6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers)

or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6-63

6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers)

or 80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6-64

6.50 Ultra160 SCSI Transfers 160 Mbyte (16-Bit Transfers)

Quadrupled 40 MHz Clock 6-65

6.51 Alphanumeric List by Signal Name 6-70

6.52 Alphanumeric List by BGA Position 6-72

A.1 LSI53C1010R PCI Register Map A-1 A.2 LSI53C1010R SCSI Register Map A-3

xvii

xviii

Chapter 1 Introduction

This chapter provides a general overview of the LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller. This chapter contains the following sections:

• Section 1.1, “General Description”

• Section 1.2, “Beneﬁts of Ultra160 SCSI”

• Section 1.3, “Benefits of SURElink (Ultra160 SCSI Domain Validation)

Technology”

• Section 1.4, “Beneﬁts of LVDlink Technology”

• Section 1.5, “Beneﬁts of TolerANT® Technology”

• Section 1.6, “Summary of LSI53C1010R Beneﬁts”

1.1 General Description

The LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller brings Ultra160 SCSI performance to host adapter, workstation, and server designs, making it easy to add a high-performance SCSI bus to any PCI system. Features incorporated in this chip include double transition (DT) clocking, cyclic redundancy check (CRC), and domain validation. These features comply with the Utra160 SCSI industry initiative.

DT clocking permits the LSI53C1010R to transfer data up to 160 Mbytes/s on each channel, for a total of 320 Mbytes/s. CRC improves the integrity of the SCSI data transmission through enhanced detection of communication errors. Asynchronous Information Protection (AIP) augments CRC to protect all nondata phases, providing complete end-to-end protection of the SCSI I/O. The SURElink™ domain validation

LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller 1-1

technology detects the SCSI bus configuration and automatically tests and adjusts the SCSI transfer rate to optimize interoperability.Three levels of domain validation are provided, assuring robust system operation.

The LSI53C1010R has a local memory bus. This allows local storage of the device’s BIOS ROM in ﬂash memory or standard EPROMs. The LSI53C1010R supports programming of local ﬂash memory for BIOS updates. The chip is packaged in a 456 Ball Grid Array (BGA). Figure 1.1 shows a typical LSI53C1010R board application connected to external ROM or ﬂash memory.

Figure 1.1 Typical LSI53C1010R Board Application

Function A

68 Pin Wide SCSI Connector

and

Terminator

Function B

68 Pin Wide SCSI Connector

and

Terminator

SCSI Data,

Parity, and

Control Signals

SCSI Data,

Parity, and

Control Signals

LSI53C1010R 64-Bit/66 MHz

PCI to

Dual Channel Ultra160 SCSI

Controller

PCI Interface

PCI Address, Data, Parity

and Control Signals

Memory

Address/Data

Bus

A_GPIO/[1:0]

B_GPIO/[1:0]

Memory Control

Block

Flash EEPROM

Serial EEPROM

Function A

Serial EEPROM

Function B

LVDlink™ technology is the LSI Logic implementation of Low Voltage Differential (LVD). LVDlink transceivers allow the LSI53C1010R to perform either Single-Ended (SE) or LVD transfers. The LSI53C1010R integrates two high-performance SCSI cores, a 64-bit/66 MHz PCI bus master DMA core, and the SCSI SCRIPTS processor to meet the ﬂexibility requirements of Ultra160 SCSI standards. It implements multithreaded I/O algorithms with minimum processor intervention,

1-2 Introduction

solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. Figure 1.2 illustrates a typical LSI53C1010R system application.

Figure 1.2 Typical LSI53C1010R System Application

Typical PCI Computer System Architecture

PCI Bus

Interface

Controller

Processor Bus

PCI Bus

LSI53C1010R PCI

to Wide Ultra160 SCSI

Function A

and

LSI53C1010R PCI

to Wide Ultra160 SCSI

Function B

One PCI Bus Load

PCI Graphic Accelerator

PCI Fast Ethernet

Memory

Controller

SCSI Bus

Fixed Disk, Optical Disk,

Printer, Tape, and Other

SCSI Peripherals

Fixed Disk, Optical Disk,

Printer, Tape, and Other

SCSI Peripherals

Central

Processing

Unit

(CPU)

Memory

The LSI53C1010R is pin compatible with the LSI53C1030 PCI to Dual Channel Ultra320 SCSI Multifunction Controller. Proper board design, using LSI Logic Design Considerations for the LSI53C1010R and LSI53C1030, SEN S11019, allows seamless, low risk upgrade from the Ultra160 LSI53C1010R to the Ultra320 LSI53C1030.

General Description 1-3

1.2 Beneﬁts of Ultra160 SCSI

Ultra160 SCSI delivers data up to two times faster than Ultra2 SCSI. Ultra160 SCSI is a subset of Ultra3 SCSI, which is an extension of the SPI-3 draft standard. When enabled, Ultra160 SCSI performs 80 megatransfers/s), resulting in approximately double the synchronous data transfer rates of Ultra2 SCSI. The LSI53C1010R performs 16-bit, Ultra160 SCSI synchronous data transfers as fast as 160 Mbytes/s on each channel providing a total bandwidth of 320 Mbytes/s. This advantage is most noticeable in heavily loaded systems, or large block size applications such as video on-demand and image processing.

The Ultra160 data transfer speed is accomplished using DT clocking. DT clocking refers to transferring data on both polarity edges of the request or acknowledge signals. Data is clocked on both rising and falling edges of the request and acknowledge signals. Double-edge clocking doubles data transfer speeds without increasing the clock rate.

Ultra160 SCSI also includes CRC, which offers higher levels of data reliability by ensuring complete integrity of transferred data. CRC is a 32-bit scheme, referred to as CRC-32. CRC is guaranteed to detect all single bit errors, any two bits in error, or any combination of errors within a single 32-bit range.

AIP is also supported by the LSI53C1010R, protecting all nondata phases, including command, status, and messages. CRC, along with AIP, provides end-to-end protection of the SCSI I/O.

SURElink domain validation provides three levels of integrity checking: Basic (level 1), Enhanced (level 2), and Margined (level 3). Further information on SURElink technology is available in Section 1.3, “Beneﬁts

of SURElink (Ultra160 SCSI Domain Validation) Technology.”

An advantage of Ultra160 SCSI is that it significantly improves SCSI bandwidth while preserving existing hardware and software investments. The primary software changes required are to enable the chip to perform synchronous negotiations for Ultra160 SCSI rates and to enable the clock quadrupler. Ultra160 SCSI uses the same connectors as Ultra SCSI and Ultra2 SCSI. Chapter 2 contains more information on migrating an Ultra SCSI or Ultra2 SCSI design to an Ultra160 SCSI design.

1-4 Introduction

1.3 Beneﬁts of SURElink (Ultra160 SCSI Domain Validation) Technology

SURElink technology represents the very latest SCSI interconnect management solution. It ensures robust and low risk Ultra160 SCSI implementations by extending the domain validation guidelines documented in the ANSI T10 SPI-3 speciﬁcations. Domain validation veriﬁes that the system is capable of transferring data at Ultra160 speeds, allowing it to renegotiate to lower speed and bus width if necessary. SURElink technology is the software control for the manageability enhancements in the LSI53C1010R. Fully integrated in the SDMS™ (Storage Device Management System) software solution, SURElink technology provides domain validation at boot time as well as throughout system operation. SURElink technology extends to the Desktop Management Interface (DMI)-based System Management components of the SDMS software solution, providing the network administrator remote management capability.

SURElink domain validation provides three levels of integrity checking: Basic (level1), Enhanced (level2), and Margined (level3). The basic check consists of an inquiry command to detect gross problems. The enhanced check sends a known data pattern using the Read and Write Buffer commands to detect additional problems. Margined check verifies that the physical parameters have some degree of margin. By varying L VD drive strength and REQ/ACK timing characteristics, level 3 verifies that no errors occur on the transfers. These altered signals are only used during the diagnostic check and not during normal system operation. If errors occur with any of these checks, the system can drop back to a lower transmission speed, on a per-target basis, to ensure robust system operation.

1.4 Beneﬁts of LVDlink Technology

The LSI53C1010R supports LVD through LVDlink technology. This signaling technology increases the reliability of SCSI data transfers over longer distances than are supported by SE SCSI. The low current output of LVD allows the I/O transceivers to be integrated directly onto the chip. LVD provides the reliability of High Voltage Differential (HVD) SCSI without the added cost of external differential transceivers. Ultra160 SCSI with LVD

Beneﬁts of SURElink (Ultra160 SCSI Domain Validation) Technology 1-5

allows a longer SCSI cable and more devices on the bus, with the same cables defined in the SCSI-3 Parallel Interface standard for Ultra SCSI. LVD provides a long-term migration path to even faster SCSI transfer rates without compromising signal integrity, cable length, or connectivity.

For backward compatibility to existing SE devices, the LSI53C1010R features universal LVDlink transceivers that support LVD SCSI and SE SCSI. This allows use of the LSI53C1010R in both legacy and Ultra160 SCSI applications.

1.5 Beneﬁts of TolerANT®Technology

The LSI53C1010R features TolerANT technology, which includes active negation on the SCSI drivers and input signal ﬁltering on the SCSI receivers. Active negation causes the SCSI Request, Acknowledge, Data, and Parity signals to be actively driven HIGH rather than passively pulled up by terminators.

TolerANT receiver technology improves data integrity in unreliable cabling environments where other devices would be subject to data corruption. TolerANT receivers ﬁlter the SCSI bus signals to eliminate unwanted transitions, without the long signal delay associated with RC-type input ﬁlters. This improved driver and receiver technology helps eliminate double clocking of data, which is the single biggest reliability issue with SCSI operations. TolerANT input signal ﬁltering is a built-in feature of the LSI53C1010R and all LSI Logic Fast, Ultra, Ultra2, and Ultra160 SCSI devices.

The beneﬁts of TolerANT technology include increased noise immunity when the signal transitions to HIGH, better performance due to balanced duty cycles, and improved fast SCSI transfer rates. In addition, TolerANT SCSI devices do not cause glitches on the SCSI bus at power-up or power-down. This protects other devices on the bus from data corruption. When used with the LVDlink transceivers, TolerANT technology provides excellent signal quality and data reliability in real world cabling environments. TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute.

1-6 Introduction

1.6 Summary of LSI53C1010R Beneﬁts

This section provides a summary of the LSI53C1010R features and beneﬁts. It contains information on SCSI Performance, PCI Performance, Integration, Ease of Use, Flexibility, Reliability, and Testability.

1.6.1 SCSI Performance

The LSI53C1010R:

• Performs wide, Ultra160 SCSI synchronous data transfers as fast as

160 Mbytes/s on each SCSI channel for a total of 320 Mbytes/s using DT clocking.

• Supports CRC checking and generation in DT phases.

• Protects nondata phases with AIP.

• Supports domain validation:

– Basic (level 1) – Enhanced (level 2) – Margined (level 3)

• Includes integrated LVDlink universal transceivers:

– Supports SE and LVD signals. – Allows greater device connectivity and longer cable length. – LVDlink transceivers save the cost of external differential

transceivers.

– Supports a long-term performance migration path.

• Bursts of up to 512 bytes across the PCI bus with an independent

896–920 byte FIFO on each SCSI channel.

• Includes two separate SCSI channels on one chip.

• Handles phase mismatches in SCRIPTS without interrupting the

system processor.

• Includes an on-chip SCSI clock quadrupler that allows the chip to

achieve Ultra160 SCSI transfer rates with an input frequency of 40 MHz.

Summary of LSI53C1010R Beneﬁts 1-7

• Includes 8 Kbytes of internal RAM for SCRIPTS instruction storage

for each SCSI channel.

• Supports 31 levels of SCSI synchronous offset in the

Single Transition (ST) mode and 62 levels in the DT mode.

• Supports variable block size and scatter/gather data transfers.

• Performs sustained Memory-to-Memory DMA transfers to

approximately 100 Mbytes/s.

• Minimizes the SCSI I/O start latency.

• Performs complex bus sequences without interrupts, including

restoring data pointers.

• Reduces Interrupt Service Routine (ISR) overhead through a unique

interrupt status reporting method.

• Includes SCSI Interrupt Steering Logic (SISL) for RAID Ready SCSI

on mainboard applications with a separate interrupt for routing to a RAID adapter.

• Supports Load/Store SCRIPTS instructions to increase the

performance of data transfers to and from the chip registers without using PCI cycles.

• Includes SCRIPTS support of 64-bit addressing.

• Supports target disconnect and later reconnect with no interrupt to

the system processor.

• Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast

I/O context switching.

• Supports expanded Register Move instruction to support additional

arithmetic capability.

1.6.2 PCI Performance

The LSI53C1010R:

• Complies with PCI 2.2 speciﬁcation.

• Supports a 64-bit/66 MHz PCI interface for 528 Mbyte/s bandwidth that:

– Can function in a 32-bit or 64-bit PCI slot – Operates at 33 or 66 MHz

1-8 Introduction

1.6.3 Integration

– Supports dual address cycle (DAC) generation for all SCRIPTS – Presents a single electrical load to the PCI Bus (True PCI

Multifunction Device)

• Bursts 4/8, 8/16, 16/32, 32/64, or 64/128 Qword/Dword transfers

across the PCI bus.

• Supports 32-bit or 64-bit word data bursts with variable burst lengths.

• Prefetches up to 8 Dwords of SCRIPTS instructions.

• Bursts SCRIPTS opcode fetches across the PCI bus.

• Performs zero wait-state bus master data bursts up to 528 Mbytes/s

(@ 66 MHz).

• Supports PCI Cache Line Size (CLS) register.

• Supports PCI Write and Invalidate, Read Line, and Read Multiple

commands.

• Complies with PCI Bus Power Management Speciﬁcation Rev 1.1.

• Complies with PC99.

The following features ease integration of the LSI53C1010R into a system.

• Dual channel Ultra160 SCSI PCI multifunction controller.

• Integrated LVD transceivers.

• Full 32-bit or 64-bit PCI DMA bus master.

• Memory-to-Memory Move instructions allow use as a third-party PCI

• Integrated SCRIPTS processor.

1.6.4 Ease of Use

The following features of the LSI53C1010R make the device user friendly.

• The LSI53C1010R is pin compatible with the LSI53C1030 PCI to

• Up to 1 Mbyte of add-in memory support for BIOS and SCRIPTS

Summary of LSI53C1010R Beneﬁts 1-9

bus DMA controller.

Dual Channel Ultra320 SCSI Multifunction Controller.

storage.

1.6.5 Flexibility

• Reduced SCSI development effort.

• Compiler-compatible with existing LSI Logic SCSI SCRIPTS

processors.

• Direct connection to PCI and SCSI SE and LVD.

• Development tools and sample SCSI SCRIPTS available.

• Maskable and pollable interrupts.

• Wide SCSI, A or P cable, and up to 15 devices per SCSI channel

are supported.

• Three programmable SCSI timers: Select/Reselect,

Handshake-to-Handshake, and General Purpose.

• Software for PC-based operating system support.

• Support for relative jumps.

• SCSI Selected As ID bits for responding with multiple IDs.

The following features increase the ﬂexibility of the LSI53C1010R:

• Universal LVD transceivers are backward compatible with SE devices.

• High level programming interface (SCSI SCRIPTS).

• Programs local and bus ﬂash memory.

• Tailored SCSI sequences execute from main system RAM or internal

SCRIPTS RAM.

• Flexible programming interface to tune I/O performance or to adapt

to unique SCSI devices.

• Support for changes in the logical I/O interface deﬁnition.

• Low level access to all registers and all SCSI bus signals.

• Fetch, Master, and Memory Access control pins.

• Separate SCSI and system clocks.

• SCSI clock quadrupler bits enable Ultra160 SCSI transfer rates with

a 40 MHz SCSI clock input.

• Selectable IRQ pin disable bit.

• Compatible with 3.3 V and 5 V PCI.

1-10 Introduction

1.6.6 Reliability

The following features enhance the reliability of the LSI53C1010R:

• CRC and AIP provide end-to-end SCSI I/O protection.

• 2 kV ESD protection on SCSI signals.

• Protection against bus reﬂections due to impedance mismatches.

• Controlled bus assertion times (reduces RFI, improves reliability, and

eases FCC certiﬁcation).

• Latch-up protection greater than 150 mA.

• Voltage feed-through protection (minimum leakage current through

SCSI pads).

• A high proportion of pins are power and ground.

• Power and ground isolation of I/O pads and internal chip logic.

• TolerANT technology provides:

– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved fast SCSI transfer rates.

– Input signal ﬁltering on SCSI receivers improves data integrity,

even in noisy cabling environments.

1.6.7 Testability

The following features enhance the testability of the LSI53C1010R:

• All SCSI signals accessible through programmed I/O.

• SCSI bus signal continuity checking.

• Support for single-step mode operation.

• JTAG boundary scan.

Summary of LSI53C1010R Beneﬁts 1-11

1-12 Introduction

Chapter 2 Functional Description

This chapter provides a functional description of the LSI53C1010R. This chapter is divided into the following sections:

• Section 2.1, “PCI Functional Description”

• Section 2.2, “SCSI Functional Description”

• Section 2.3, “Parallel ROM Interface”

• Section 2.4, “Serial EEPROM Interface”

• Section 2.5, “Power Management”

The LSI53C1010R is composed of the following modules:

• 64-bit PCI Interface

• Two independent PCI to Wide Ultra160 SCSI Controllers

• ROM/Flash Memory Controller

• Serial EEPROM Controller

Figure 2.1 illustrates the relationship between these modules.

LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller 2-1

Figure 2.1 LSI53C1010R Block Diagram

64-Bit PCI Interface, PCI Conﬁguration Registers (2 Sets)

PCI Bus

Wide Ultra160 SCSI Channel

8 Kbyte

SCRIPTS RAM

944 Byte

DMA FIFO

SCSI FIFO and SCSI Control Block

JTAG

Bus

8 Dword SCRIPTS

Prefetch Buffer

Registers

Operating

Processor

SCSI SCRIPTS

Universal TolerANT

Drivers and Receivers

SCSI Function A

Wide Ultra160

SCSI Bus

ROM/Flash

Memory

Bus

ROM/Flash Memory Control

Local

Memory

Bus

2-Wire Serial

EEPROM Bus

(Function A)

SCRIPTS RAM

and Autoconﬁguration

Serial EEPROM Controller

SCSI FIFO and SCSI Control Block

2-Wire Serial

EEPROM Bus

(Function B)

Wide Ultra160 SCSI Channel

8 Kbyte

Registers

Operating

8 Dword SCRIPTS

Prefetch Buffer

920 Byte

Processor

SCSI SCRIPTS

Universal TolerANT

Drivers and Receivers

SCSI Function B

Wide Ultra160

SCSI Bus

DMA FIFO

The LSI53C1010R has two wide Ultra160 SCSI channels in a single package. Each SCSI channel (A and B) incorporates an independent DMA FIFO and a separate internal 8 Kbyte SCRIPTS RAM.

2.1 PCI Functional Description

The LSI53C1010R implements two PCI to Wide Ultra160 SCSI controllers in a single package. This conﬁguration presents only one load to the PCI bus and uses only one REQ/ - GNT/ pair for PCI bus arbitration. Separate interrupt signals are generated for SCSI Function A and SCSI Function B.

2-2 Functional Description

2.1.1 PCI Addressing

There are three physical address spaces deﬁned in the PCI speciﬁcation:

• PCI Conﬁguration space

• I/O space for operating registers

• Memory space for operating registers

2.1.1.1 Conﬁguration Space

The host processor uses this conﬁguration space to initialize the LSI53C1010R. Two independent sets of conﬁguration space registers are deﬁned, one set for each SCSI function. Each SCSI function contains the same register set with identical default values except for the Interrupt Pin. The conﬁguration registers are initialized by the system BIOS using PCI conﬁguration cycles. Each conﬁguration space is a contiguous 256 x 8-bit set of addresses. Decoding C_BE[3:0]/ determines whether a PCI cycle is intended to access the conﬁguration register space. The IDSEL bus signal is a “chip select” that allows access to the conﬁguration register space only. A conﬁguration read/write cycle without IDSEL is ignored. The host processor uses the eight lower order address bits (AD[7:0]) to select a speciﬁc 8-bit register. Because the LSI53C1010R is a PCI Multifunction device, bits AD[10:8] decode either SCSI Function A Conﬁguration register (AD[10:8] = 0b000) or SCSI Function B Conﬁguration register (AD[10:8] = 0b001). Table 4.1 on page 4-2 is an illustration of the PCI Conﬁguration Register Map.

At initialization time, each PCI device is assigned a base address for memory and I/O accesses. In the LSI53C1010R, the upper 24 bits of the address are selected. On every access, the LSI53C1010R compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase. If the upper 24 bits match, the access is designated for the LSI53C1010R. The low order eight bits deﬁne the register to be accessed. A decode of C_BE[3:0]/ determines which register and what type of access is performed.

PCI Functional Description 2-3

2.1.1.2 I/O Space

The PCI speciﬁcation deﬁnes I/O space as a contiguous 32-bit I/O address that is shared by all system resources, including the LSI53C1010R. Base Address Register Zero (BAR0) (I/O) determines which 256-byte I/O area this device occupies.

2.1.1.3 Memory Space

The PCI speciﬁcation deﬁnes memory space as a contiguous 64-bit memory address that is shared by all system resources.

Base Address Register One (BAR1) (MEMORY) determines which

1 Kbyte memory area this device occupies. Each SCSI function uses an 8 Kbyte SCRIPTS RAM memory space.

Base Address Register Two (BAR2) (MEMORY) determines the 8 Kbyte

memory area the SCRIPTS RAM occupies.

2.1.2 PCI Bus Commands and Functions Supported

Bus commands indicate to the target the type of transaction the master is requesting. Bus commands are encoded on the C_BE[3:0]/ lines during the address phase. PCI bus commands and encoding types appear in Table 2.1.

2-4 Functional Description

Table 2.1 PCI Bus Commands and Encoding Types

C_BE[3:0]/ Command Type

as Master

0000 Interrupt Acknowledge No No 0001 Special Cycle No No 0010 I/O Read Yes Yes 0011 I/O Write Yes Yes 0100 Reserved N/A N/A 0101 Reserved N/A N/A 0110 Memory Read Yes Yes 0111 Memory Write Yes Yes 1000 Reserved N/A N/A 1001 Reserved N/A N/A 1010 Conﬁguration Read No Yes 1011 Conﬁguration Write No Yes

Supported

1100 Memory Read Multiple Yes

Yes (defaults to 0110)

1101 Dual Address Cycle (DAC) Yes Yes

1110 Memory Read Line Yes 1111 Memory Write and

Yes

Yes (defaults to 0110)

Yes (defaults to 0111)

Invalidate

Supported

as Slave

1. Refer to the DMA Mode (DMODE) register.

2. Refer to the Chip Test Three (CTEST3) register.

2.1.2.1 Interrupt Acknowledge Command

The LSI53C1010R does not respond to this command as a slave and it never generates this command as a master.

2.1.2.2 Special Cycle Command

The LSI53C1010R does not respond to this command as a slave and it never generates this command as a master.

PCI Functional Description 2-5

2.1.2.3 I/O Read Command

The LSI53C1010R uses the I/O Read command to read data from an agent mapped in the I/O address space. When decoding I/O cycles, the LSI53C1010R decodes the lower 32 address bits and ignores the upper 32 address bits.

2.1.2.4 I/O Write Command

The LSI53C1010R uses the I/O Write command to write data to an agent mapped in the I/O address space. When decoding I/O cycles, the LSI53C1010R decodes the lower 32 address bits and ignores the upper 32 address bits.

2.1.2.5 Reserved Command

The given bus encoding is reserved.

2.1.2.6 Memory Read Command

The LSI53C1010R uses the Memory Read command to read data from an agent mapped in the Memory Address Space. The target may perform an anticipatory read if such a read produces no side effects.

2.1.2.7 Memory Write Command

The LSI53C1010R uses the Memory Write command to write data to an agent mapped in the Memory Address Space. When the target returns “ready”, it assumes responsibility for data coherency, which includes ordering.

2.1.2.8 Conﬁguration Read Command

The Conﬁguration Read command reads the conﬁguration space of a device. The LSI53C1010R never generates this command as a master, but does respond to it as a slave. A device on the PCI bus selects the LSI53C1010R by asserting its IDSEL signal when AD[1:0] are 0b00. During the address phase of a conﬁguration cycle, AD[7:2] address one of the 64 Dword registers in the conﬁguration space of each device. C_BE[3:0]/ address the individual bytes within each Dword. AD[10:8] indicate which device on the LSI53C1010R is being addressed. The LSI53C1010R treats AD[63:11] as logical don’t cares.

2-6 Functional Description

2.1.2.9 Conﬁguration Write Command

The Conﬁguration Write command writes the conﬁguration space of a device. The LSI53C1010R never generates this command as a master, but does respond to it as a slave. A device on the PCI bus selects the LSI53C1010R by asserting its IDSEL signal when AD[1:0] are 0b00. During the address phase of a conﬁguration cycle, AD[7:2] address one of the 64 Dword registers in the conﬁguration space of each device. C_BE[3:0]/ address the individual bytes within each Dword. AD[10:8] indicate which device on the LSI53C1010R is being addressed. The LSI53C1010R treats AD[63:11] as logical don’t cares.

2.1.2.10 Memory Read Multiple Command

This command is identical to the Memory Read command, except it additionally indicates that the master intends to fetch multiple cache lines before disconnecting. The LSI53C1010R supports PCI Memory Read Multiple functionality and issues Memory Read Multiple commands on the PCI bus when the Read Multiple mode is enabled. This mode is enabled by setting bit 2 (ERMP) of the DMA Mode (DMODE) register. If the cache mode is enabled, a Memory Read Multiple command is issued on all read cycles, except opcode fetches, when the following conditions are met:

• The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL)

• The ERMP bit (Enable Read Multiple, bit 2, DMA Mode (DMODE)

• The Cache Line Size (CLS) register for each function contains a

legal burst size value (8, 16, 32, 64, or 128 Dwords) that is less than or equal to the DMODE burst size.

• The transfer crosses a cache line boundary.

When these conditions are met, the chip issues a Memory Read Multiple command instead of a Memory Read during all PCI read cycles.

Burst Size Selection – The Read Multiple command reads in multiple cache lines of data during a single bus ownership. Revision 2.2 of the PCI specification specifies the number of cache lines to read as a multiple of the cache line size. The logic selects the largest multiple of the cache line

PCI Functional Description 2-7

size based on the amount of data to transfer. The maximum allowable burst size is determined from the DMA Mode (DMODE) burst size bits and the Chip Test Five (CTEST5) register, bit 2.

2.1.2.11 Dual Address Cycles (DACs) Command

When 64-bit addressing is required, the LSI53C1010R performs DACs, according to the PCI 2.2 speciﬁcation. If any of the selector registers contain a nonzero value, a DAC is generated.

2.1.2.12 Memory Read Line Command

This command is identical to the Memory Read command, except it additionally indicates that the master intends to fetch a complete cache line. This command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading to a cache line boundary rather than a single memory cycle. The Read Line function in the LSI53C1010R takes advantage of the PCI 2.2 speciﬁcation regarding issuance of this command.

If the cache mode is disabled, no Read Line commands are issued. If the cache mode is enabled, a Read Line command is issued on all

read cycles, except nonprefetch opcode fetches, when the following conditions are met:

• The CLSE bit (Cache Line Size Enable, bit 7, of the

DMA Control (DCNTL) register) is set.

• The ERL bit (Enable Read Line, bit 3, of the DMA Mode (DMODE)

• The Cache Line Size (CLS) register for each function must contain

a legal burst size value (8, 16, 32, 64, or 128 Dwords) that is less than or equal to the DMODE burst size.

• The transfer crosses a Dword boundary, but not a cache line boundary.

When these conditions are met, the chip issues a Read Line command instead of a Memory Read during all PCI read cycles. Otherwise, it issues a normal Memory Read command.

2-8 Functional Description

Read Multiple with Read Line Enabled – When both the Read Multiple and Read Line modes are enabled, the Read Line command is not issued if these conditions are met. Instead, a Read Multiple command is issued.

If the Read Multiple mode is enabled, Read Multiple commands are issued if the Read Multiple conditions are met.

2.1.2.13 Memory Write and Invalidate Command

The Memory Write and Invalidate command is identical to the Memory Write command, except it additionally guarantees a minimum transfer of one complete cache line. That is, the master intends to write all bytes within the addressed cache line in a single PCI transaction unless interrupted by the target. This command requires implementation of the PCI Cache Line Size (CLS) register. The LSI53C1010R enables Memory Write and Invalidate cycles when bit 0 (WRIE), in the

Chip Test Three (CTEST3) register, and bit 4 (WIE), in the PCI Command register, are set.

When the following conditions are met, Memory Write and Invalidate commands are issued:

• The following bits are set:

– The CLSE bit (Cache Line Size Enable, bit 7, of the

DMA Control (DCNTL) register),

– The WRIE bit (Write and Invalidate Enable, bit 0, of the

Chip Test Three (CTEST3) register),

– Bit 4 of the PCI Conﬁguration Command register.

• The Cache Line Size (CLS) register for each function contains a

legal burst size value (8, 16, 32, 64, or 128 Dwords) that is less than or equal to the DMA Mode (DMODE) burst size.

• The chip has enough bytes in the DMA FIFO to complete at least

one full cache line burst.

• The chip is aligned to a cache line boundary.

When these conditions are met, the LSI53C1010R issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles.

PCI Functional Description 2-9

Multiple Cache Line Transfers – The Memory Write and Invalidate command can write multiple cache lines of data in a single bus ownership. The chip issues a burst transfer as soon as it reaches a cache line boundary. The transfer size is not automatically the cache line size, but rather a multiple of the cache line size speciﬁed in Revision 2.2 of the PCI speciﬁcation. The logic selects the largest multiple of the cache line size based on the transfer size. The maximum allowable burst size is determined from the DMA Mode (DMODE) burst size bits, and bit 2 of the Chip Test Five (CTEST5) register. If multiple cache line size transfers are not desired, set the DMODE burst size to exactly the cache line size and the chip only issues single cache line transfers.

After each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer. It again selects the highest possible multiple of the cache line size, and no larger than the

DMA Mode (DMODE) burst size. Usually, the chip selects the DMODE

burst size after alignment and issues bursts of this size. The burst size is, in effect, throttled down toward the end of a long Memory Move or Block Move transfer until only the cache line size left is burst size. The chip ﬁnishes the transfer with this burst size.

Latency – In accordance with the PCI speciﬁcation, the latency timer is ignored when issuing a Memory Write and Invalidate command. Therefore, when a latency time-out occurs, the LSI53C1010R continues to transfer up to a cache line boundary. At that point, the chip relinquishes the bus, and ﬁnishes the transfer at a later time using another bus ownership. If the chip is transferring multiple cache lines, it continues to transfer until the next cache boundary is reached.

PCI Target Retry – A retry is deﬁned as a STOP with no TRDY/, indicating that no data was transferred. If the target issues a retry during a Memory Write and Invalidate transfer, the chip relinquishes the bus and immediately tries to ﬁnish the transfer on another bus ownership. The chip issues another Memory Write and Invalidate command on the next ownership, in accordance with the PCI speciﬁcation.

PCI Target Disconnect – If the target device issues a disconnect during a Memory Write and Invalidate transfer, the LSI53C1010R relinquishes the bus and immediately tries to ﬁnish the transfer on another bus ownership. The chip does not issue another Memory Write and Invalidate command on the next ownership unless the address is aligned.

2-10 Functional Description

2.1.3 Internal Arbiter

The PCI to SCSI controller uses a single REQ/ - GNT/ signal pair to arbitrate for access to the PCI bus. An internal arbiter circuit allows the different bus mastering functions resident in the chip to arbitrate among themselves for the privilege of arbitrating for PCI bus access. There are two independent bus mastering functions inside the LSI53C1010R, one for each of the SCSI functions.

The internal arbiter uses a round robin arbitration scheme to decide which internal bus mastering function may arbitrate for access to the PCI bus. This ensures that no function is starved for access to the PCI bus.

2.1.4 PCI Cache Mode

The LSI53C1010R supports the PCI specification for an 8-bit

Cache Line Size (CLS) register located in the PCI configuration space. The Cache Line Size (CLS) register provides the ability to sense and react to

nonaligned addresses corresponding to cache line boundaries. In conjunction with the Cache Line Size (CLS) register, the PCI commands Memory Read Line (MRL), Memory Read Multiple (MRM), and Memory Write and Invalidate (MWI) are individually software enabled or disabled. Table 2.2 provides information on the PCI cache mode alignment.

PCI Functional Description 2-11

Table 2.2 PCI Cache Mode Alignment

Host Memory

A 0x00

B 0x04

0x08 C 0x0C D 0x10

0x14

0x18

0x1C

E 0x20

0x24

0x28

0x2C

F 0x30

G 0x40

H 0x50

2-12 Functional Description

0x34

0x38

0x3C

0x44

0x48

0x4C

0x54

0x58

0x5C

0x60

2.1.4.1 Enabling Cache Mode

To enable the cache logic to issue PCI cache commands (Memory Read Line, Memory Read Multiple, and Memory Write and Invalidate) on any PCI master operation, the following conditions must be met:

• The Cache Line Size Enable bit in the DMA Control (DCNTL) register

must be set.

• The PCI Cache Line Size (CLS) register must contain a valid binary

cache size, that is, 8, 16, 32, 64, or 128 Dwords. These values are the only valid cache sizes.

• The programmed burst size (in Dwords) must be equal to or greater

than the cache line size register. The DMA Mode (DMODE) register, bits [7:6], and the Chip Test Five (CTEST5) register, bit 2, denote the burst length.

• The device must be performing a PCI Master transfer. The following

PCI Master transactions do not utilize the PCI cache logic, so no PCI cache commands are issued during these types of cycles: a nonprefetch SCRIPTS fetch, a Load/Store data transfer, and a data ﬂush operation. All other types of PCI Master transactions utilize the PCI cache logic.

Not only must these four conditions be met for the cache logic to control the type of PCI cache command that is issued, proper alignment is also necessary during write operations. If these conditions are not met for any given PCI Master transaction, a Memory Read or Memory Write is issued and no cache write alignment is done.

2.1.4.2 Issuing Cache Commands

To issue each type of PCI cache command, the corresponding enable bit(s) must be set.

• To issue Memory Read Line commands, the Enable Read Line

(ERL) bit in the DMA Mode (DMODE) register must be set.

• To issue Memory Read Multiples, the Enable Read Multiple (ERMP)

bit in the DMA Mode (DMODE) register must be set.

• To issue Memory Write and Invalidates, both the Write and Invalidate

Enable (WRIE) bit in the Chip Test Three (CTEST3) register and the Write and Invalidate Enable (WIE) bit in the PCI conﬁguration

Command register must be set.

PCI Functional Description 2-13

If the corresponding cache command is not enabled, the cache logic falls back to the next command enabled. For example, if the Memory Read Multiple command is not enabled and the Memory Read Line command is, Memory Read Line command is issued in place of Memory Read Multiple command. If no cache commands are enabled, cache write alignment still occurs but no cache commands are issued; only Memory Reads and Memory Writes are issued.

2.1.4.3 Memory Read Caching

The type of Memory Read command issued depends on the starting location of the transfer and the number of bytes to be transferred. During reads, no cache alignment is done, as it is neither required nor optional according to PCI 2.2 speciﬁcation. Reads are a programmed burst length in size, as set in the DMA Mode (DMODE) and Chip Test Five (CTEST5) registers. In the case of a transfer that is smaller than the burst length, all bytes for that transfer are read in one PCI burst transaction. If the transfer crosses a Dword boundary (A[1:0] = 0b00), a Memory Read Line command is issued. If the transfer crosses a cache boundary, as speciﬁed by the cache line size programmed into the PCI conﬁguration register, a Memory Read Multiple command is issued. If a transfer does not cross a Dword or cache boundary, or if cache mode is not enabled, a Memory Read command is issued.

2.1.4.4 Memory Write Caching

Memory Writes are aligned in a single burst transfer to reach a cache boundary .At that point, Memory Write and Invalidate commands are issued and continue at the burst length programmedinto the DMA Mode (DMODE) register. Memory Write and Invalidate commands continue to be issued as long as the remaining byte count is greater than the Memory Write and Invalidate threshold. When the remaining byte count drops below this threshold, a single Memory Write burst is issued to complete the transfer.

In summary, the general pattern for PCI writes is:

• A single Memory Write to align to a cache boundary

• Multiple Memory Write and Invalidates

• A single data residual Memory Write to complete the transfer

2-14 Functional Description

2.1.4.5 Examples

The examples in this section employ the following abbreviations: MR = Memory Read; MRL = Memory Read Line; MRM = Memory Read Multiple; MW = Memory Write; MWI = Memory Write and Invalidate.

Read Example 1 – Burst = 4 Dwords; Cache Line Size = 4 Dwords:

AtoB: MRL (6 bytes) AtoC: MRL (13 bytes) AtoD: MRM (16 bytes)

CtoD: MRM (5 bytes) CtoE: MRM (16 bytes)

DtoF: MRM (16 bytes)

AtoH: MRM (16 bytes)

AtoG: MRM (16 bytes)

MR (1 byte)

MRM (5 bytes)

MRM (16 bytes)

MRM (16 bytes) MRM (16 bytes) MRM (16 bytes) MRM (16 bytes) MR (1 byte)

MRM (16 bytes) MRM (16 bytes) MRM (16 bytes) MR (2 bytes)

PCI Functional Description 2-15

Read Example 2 – Burst = 8 Dwords; Cache Line Size = 4 Dwords:

AtoB: MRL (6 bytes) AtoC: MRL (13 bytes) AtoD: MRM (17 bytes) CtoD: MRM (5 bytes) CtoE: MRM (21 bytes) DtoF: MRM (32 bytes) AtoH: MRM (32 bytes)

MRM (32 bytes) MRM (17 bytes)

AtoG: MRM (32 bytes)

MRM (32 bytes) MR (2 bytes)

Read Example 3 – Burst = 16 Dwords; Cache Line Size = 8 Dwords:

AtoB: MRL (6 bytes) AtoC: MRL (13 bytes) AtoD: MRL (17 bytes) CtoD: MRL (5 bytes) CtoE: MRM (21 bytes) DtoF: MRM (32 bytes) AtoH: MRM (64 bytes)

AtoG: MRM (64 bytes)

MRL (17 bytes)

MR (2 bytes)

2-16 Functional Description

Write Example 1 – Burst = 4 Dwords; Cache Line Size = 4 Dwords:

AtoB: MW (6 bytes) AtoC: MW (13 bytes) AtoD: MW (17 bytes) CtoD: MW (5 bytes) CtoE: MW (3 bytes)

MWI (16 bytes) MW (2 bytes)

DtoF: MW (15 bytes)

MWI (16 bytes) MW (1 byte)

AtoH: MW (15 bytes)

MWI (16 bytes) MWI (16 bytes) MWI (16 bytes) MWI (16 bytes) MW (2 bytes)

AtoG: MW (15 bytes)

MWI (16 bytes) MWI (16 bytes) MWI (16 bytes) MW (3 bytes)

Write Example 2 – Burst = 8 Dwords; Cache Line Size = 4 Dwords:

AtoB: MW (6 bytes) AtoC: MW (13 bytes) AtoD: MW (17 bytes) CtoD: MW (5 bytes) CtoE: MW (3 bytes)

MWI (16 bytes) MW (2 bytes)

DtoF: MW (15 bytes)

MWI (16 bytes) MW (1 byte)

AtoH: MW (15 bytes)

MWI (32 bytes) MWI (32 bytes) MW (2 bytes)

AtoG: MW (15 bytes)

MWI (32 bytes) MWI (16 bytes) MW (3 bytes)

PCI Functional Description 2-17

Write Example 3 – Burst = 16 Dwords; Cache Line Size = 8 Dwords:

AtoB: MW (6 bytes) AtoC: MW (13 bytes) AtoD: MW (17 bytes) CtoD: MW (5 bytes) CtoE: MW (21 bytes) DtoF: MW (32 bytes) AtoH: MW (31 bytes)

AtoG: MW (31 bytes)

MWI (32 bytes) MW (18 bytes)

MWI (32 bytes) MW (3 bytes)

2.1.4.6 Memory-to-Memory Moves

Memory-to-Memory Moves also support PCI cache commands, as described, with one limitation: Memory Write and Invalidate on Memory-to-Memory Move writes are only supported if the source and destination address are quad word aligned. If the source and destination are not quad word aligned, that is, Source Address[2:0] == Destination Address[2:0], write alignment is not performed and Memory Write and Invalidates are not issued.

The LSI53C1010R is little endian. This mode assigns the least signiﬁcant byte to bits [7:0].

2.2 SCSI Functional Description

Both Ultra160 SCSI controllers on the LSI53C1010R support either an 8-bit or 16-bit SCSI bus. Each controller supports Wide Ultra160 SCSI synchronous transfer rates up to 160 Mbytes/s on an LVD SCSI bus. SCSI functions can be programmed with SCSI SCRIPTS, making it easy to “ﬁne tune” the system for speciﬁc mass storage devices or Ultra160 SCSI requirements. Figure 2.1 on page 2-2 illustrates the relationship between the LSI53C1010R modules.

2-18 Functional Description

The LSI53C1010R offers low level register access or a high level control interface. Like ﬁrst generation SCSI devices, the LSI53C1010R is accessed as a register-oriented device. The ability to sample and/or assert any signal on the SCSI bus is used in error recovery and diagnostic procedures.

The LSI53C1010R is controlled by the integrated SCRIPTS processor through a high level logical interface. Commands controlling the SCSI functions are fetched out of the main host memory or local memory. These commands instruct the SCSI functions to Select, Reselect, Disconnect, Wait for a Disconnect, Transfer Information, Change Bus Phases, and implement all other aspects of the SCSI protocol. The SCRIPTS processor is a special high speed processor optimized for SCSI protocol.

2.2.1 SCRIPTS Processor

The SCSI SCRIPTS processor allows fetches of both DMA and SCSI commands from host memory or internal SCRIPTS RAM. Algorithms written in SCSI SCRIPTS control the actions of the SCSI and DMA cores. The SCRIPTS processor, running off of the PCI clock, executes complex SCSI bus sequences independently of the host CPU.

Algorithms can be designed to tune SCSI bus performance to adjust to new bus device types such as scanners and communication gateways. They can also incorporate changes in the SCSI logical bus deﬁnitions without sacriﬁcing I/O performance. SCSI SCRIPTS are hardware independent, so they can be used interchangeably on any host or CPU system bus. SCSI SCRIPTS handle conditions such as Phase Mismatch.

Phase Mismatch Handling in SCRIPTS – The LSI53C1010R can handle phase mismatches due to drive disconnects without needing to interrupt the processor. The primary goal of this logic is to eliminate the need for CPU intervention during an I/O disconnect/reselect sequence.

SCRIPTS control the storage of appropriate information needed to restart the I/O state, eliminating the need for processor intervention during an I/O disconnect/reselect sequence. Calculations are performed such that the appropriate information is available to SCRIPTS so that an I/O state can be properly stored for restart later.

SCSI Functional Description 2-19

The Phase Mismatch Jump logic is disabled at power-up. To enable the phase mismatch jump logic, set the Phase Mismatch Jump Enable bit (ENPMJ, bit 7 in the Chip Control Zero (CCNTL0) register). Utilizing the information supplied in the Phase Mismatch Jump Address registers allows all overhead involved in a disconnect/reselect sequence to be handled with a modest amount of SCRIPTS instructions. These registers are described in detail in Chapter 4, “Registers.”

2.2.2 Internal SCRIPTS RAM

The LSI53C1010R has 8 Kbytes (2048 x 32 bits) of internal, general purpose RAM for each SCSI function. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information. When the chip fetches SCRIPTS instructions or Table Indirect information from the internal RAM, these fetches remain internal to the chip and do not use the PCI bus. In addition, any SCRIPTS instruction that contains a source or destination address residing in SCRIPTS RAM memory space remains internal to the chip and does not generate PCI cycles. SCRIPTS instructions able to access SCRIPTS RAM memory space in this manner include Memory-to-Memory Moves, Load/Stores, and Block Moves. While an internal cycle is occurring, any external PCI slave cycle is retried on the PCI bus. Setting the DISRC (Disable Internal SCRIPTS RAM Cycles) bit in the Chip Control Zero (CCNTL0) register disables this feature.

SCRIPTS RAM should be initialized before it is read. Reading SCRIPTS RAM before initialization sets the SCRIPTS RAM parity bit, bit 7, in the

Shadowed SCSI SGE Status 0 register.

PCI system BIOS can relocate the RAM anywhere in the 64-bit address space. Base Address Register Three (BAR3) (SCRIPTS RAM) and

Base Address Register Four (BAR4) (SCRIPTS RAM), in the PCI

configuration space, contain the base address of the internal RAM. T o simplify SCRIPTS instruction loading, the base address of the RAM appears in the Scratch Register B (SCRATCHB) register when bit 3 of the

Chip Test Two (CTEST2) register is set. The upper 32 bits of a 64-bit base

address are in the SCRIPT Fetch Selector (SFS) register. The RAM is byte accessible from the PCI bus and is visible to any bus mastering device on the bus. External, CPU accesses to the RAM follow the same timing sequence as a standard slave register access, except that the required

2-20 Functional Description

target wait states drop from 5 to 3. SCRIPTS RAM must first be written before being read in order to initialize SCRIPTS RAM parity. If a SCRIPTS RAM parity error is encountered, a SCSI Gross Error interrupt is signaled.

A complete set of development tools is available for writing custom drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS instructions supported by the LSI53C1010R, refer to

Chapter 5, “SCSI SCRIPTS Instruction Set.”

2.2.3 64-Bit Addressing in SCRIPTS

The PCI interface for the LSI53C1010R provides 64-bit address and data capability in the initiator mode. The chip can also respond to 64-bit addressing in the target mode.

DA Cscan be generated for all SCRIPTS operations. There are six selector registers that hold the upper Dword of a 64-bit address. All but one of these is static and requires manual loading using a CPU access, a Load and Store instruction, or a memory move instruction. One of the selector registers is dynamic and is used during 64-bit direct block moves only . All selectors default to zero, meaning the LSI53C1010R powers-up in a state where only Single Address Cycles (SACs) are generated. When any of the selector registers are written to a nonzero value, DACs are generated.

Direct, Table Indirect and Indirect Block Moves, Memory-to-Memory Moves, Load/Stores, and Jumps are all instructions with 64-bit address capability.

Note: Crossing the 4 Gbyte boundary on any one SCRIPTS

operation is not permitted. Therefore, software must handle all such transactions.

2.2.4 Hardware Control of SCSI Activity LED

The LSI53C1010R controls an LED through the GPIO_0 pin to indicate that it is connected to the SCSI bus. This function was previously handled by a software driver.

Bit 3 (CON), in the Interrupt Status Zero (ISTAT0) register, is presented at the GPIO_0 pin when the following occurs:

SCSI Functional Description 2-21

• Bit 5 (LED_CNTL) in the General Purpose Pin Control (GPCNTL)

• Bit 6 (Fetch Enable) in the General Purpose Pin Control (GPCNTL)

• The LSI53C1010R is not performing an EEPROM autodownload.

The CON (Connected) bit in Interrupt Status Zero (ISTAT0) is set anytime the LSI53C1010R is connected to the SCSI bus either as an initiator or a target. This happens after the LSI53C1010R has successfully completed a selection or when it has successfully responded to a selection or reselection. The CON bit is also set when the LSI53C1010R wins arbitration in low level mode.

2.2.5 Designing an Ultra160 SCSI System

Software modiﬁcations are needed to take advantage of the Ultra160 speed in the LSI53C1010R. Because Ultra160 SCSI is based on existing SCSI standards, it can use existing drivers if they are able to negotiate for Ultra160 synchronous transfer rates. Also, the target device must be able to communicate at Ultra160 speed. The LSI53C1010R uses domain validation to determine whether or not the system is capable of Ultra160 SCSI before activating DT clocking. Refer to

Section 2.2.5.1, “Ultra160 Features,” for more information on DT clocking.

LVD SCSI fulﬁlls the hardware requirements for Ultra160 SCSI transfer rates, increased cable lengths, and additional devices on the bus. All devices on the bus must have LVD SCSI capabilities to guarantee Ultra160 SCSI transfer rates. For details on Ultra160 SCSI, refer to the SCSI Parallel Interface-3 (SPI-3) working document that is available on the world wide web at the T10 Home Page, http://www.t10.org. Also, check the SCSI Trade Association web site at http://www.scsita.org/. Chapter 6, “Speciﬁcations,” contains Ultra160 SCSI timing information. In addition to the guidelines in the draft standard, make the following software adjustments to accommodate Ultra160 SCSI transfers.

2-22 Functional Description

2.2.5.1 Ultra160 Features

Domain Validation – Domain validation is a procedure in which a host

queries a device to determine its ability to communicate at the negotiated Ultra160 data rate. In software, the following steps are performed to ensure the selected device can successfully transfer data at the negotiated speed.

Step 1. Select a device. Step 2. Issue Inquiry command. Step 3. Issue Parallel Protocol Request (PPR) message. Step 4. Issue Write Buffer command. Step 5. Issue Read Buffer command. Step 6. Examine the data pattern to ensure validity.

If the commands complete successfully with no CRC errors, bus hangs, or data pattern errors, then the negotiated speed is valid.

CRC – CRC is the error detecting code used in Ultra160 SCSI. Four bytes are transferred with data to increase the reliability of data transfers. CRC is used in the DT Data-In and DT Data-Out phases only. Because CRC is implied with DT mode and only works with DT mode, the DT setting can be used for CRC.

DT Clocking – Ultra160 SCSI implements DT clocking to provide speeds up to 80 megatransfers/s. DT clocking means that the data is sampled on both the asserting and deasserting edge of REQ/ACK. DT clocking is only valid using a LVD SCSI bus.

In order to support DT clocking, there are two new phases for the SCSI bus. The old Data-In and Data-Out phases are now called single transition (ST) Data-In and ST Data-Out. The new phases are DT Data-In and DT Data-Out. The use of DT and ST phases implies that the SCRIPTS engine may use a different jump point for DT or ST.

Table 2.3 illustrates SCSI signal conﬁguration for these phases.

SCSI Functional Description 2-23

Table 2.3 New Phases on SCSI Bus

Phase MSG C/D I/O Description

ST Data-Out 0 0 0 – ST Data-In 0 0 1 – DT Data-Out 1 0 0 Previously reserved DT Data-In 1 0 1 Previously reserved

To indicate DT or ST mode, a bit is set in the current “selection” data reserved byte. BMOVE instructions identify the current BMOVE as either DT or ST through the phase bits.

2.2.5.2 Parallel Protocol Request

CRC, Sync/Wide, DT, Quick Arbitration and Selection (QAS), and “information units” are negotiated with a new SCSI extended message:

Byte 0 0x01 Extended message Byte 1 0x06 Length Byte 2 0x04 Parallel Protocol Request (PPR) Byte 3 0xXX Transfer Period Factor Byte 4 0x00 Reserved Byte 5 0xXX Req/ACK Offset Byte 6 0xXX Transfer Width Exponent Byte 7 0x0X Protocol options

2-24 Functional Description

Transfer Period Factor (Byte 3) – Transfer Period Factor is the old Synchronous Period value. These are the same with one addition for the 80 megatransfer/s rate:

0x09 = 12.5 ns (Ultra160 SCSI) only valid when using DT 0x0A = 25 ns (Ultra2 SCSI) 0x0B = 30.3 ns 0x0C = 50 ns (Ultra SCSI) 0x0D–0xFF = (in ns)

value 4× Period=

The transfer period depends on the data transfer speed, not the clock period. So, in DT mode, 0x09 means 12.5 ns between clock edges, which really means a 25 ns clock period. In DT mode, 0x0A means a clock period of 50 ns but a data rate of 40 megatransfers/s (25 ns). In ST mode, 0x0A means a clock period of 25 ns and a data rate of 40 megatransfers/s.

Req/ACK Offset (Byte 5) – Req/ACK Offset is the maximum SCSI offset. Transfer Width Exponent (Byte 6) – Transfer Width Exponent is the

old width value. It is set to 0 (8-bit SCSI width) or 1 (16-bit SCSI width).

Note: For DT mode or when the Protocol Options ﬁeld is nonzero,

the TransferWidth Exponent must be one indicating a SCSI width of 16 bits.

Note: The Table Indirect data (used during selection/reselection)

must be updated to enable certain control bits in the SCNTL4 register. Speciﬁc bits to look at include: bit 7, U3EN (Ultra160 Transfer Enable); bit 6, AIPEN (Asynchronous Information Protection Enable); and bits [3:0] (Extra Clock Setup/Hold).

SCSI Functional Description 2-25

Protocol Options (Byte 7) – A bus or device reset, power cycle, or change between LVD/SE modes invalidates these settings. A renegotiation resets the Protocol Options.

QAS_REQ DT_REQ IU_REQ Description

000

010

011

110

111

2.2.5.3 Asynchronous Information Protection (AIP)

The AIP feature provides error checking for asynchronous, nondata phases through BCH encoding. During the command, status, message in/out phases, the BCH code is transferred on the upper SCSI data bus. For details on the BCH code, refer to the T10 119 document, “Protection for the Asynchronous Phases”.

The AIP error status and the live AIP code values are captured in the

AIP Control Zero (AIPCNTL0) register for debug purposes. AIP checking

is enabled by setting bit 6 in the SCSI Control Four (SCNTL4) register. AIP generation occurs by default and may be disabled by setting bit 3, Disable AIP Code Generation, in AIP Control One (AIPCNTL1).

Use ST Data-In and ST Data-Out phase to transfer data.

Use DT Data-In and DT Data-Out phase to transfer data with CRC.

Use DT Data-In and DT Data-Out phase to transfer data with information units.

Use DT Data-In and DT Data-Out phase to transfer data with CRC and use the QAS method for arbitration.

Use DT Data-In and DT Data-Out phase to transfer data with information units and use the QAS method for arbitration.

The sequence ID is reset on any phase change, chip reset, bus free, or synchronous phase. It is also reset by writing the RAIPERR bit in the

AIP Control One (AIPCNTL1) register.

All AIP errors are treated in the same fashion as parity errors. Bit 0 of the

SCSI Interrupt Status Zero (SIST0) register indicates if SCSI parity, CRC,

or AIP errors are present. The AIPERR bit in the

AIP Control Zero (AIPCNTL0) register indicates if the error is an AIP error.

2-26 Functional Description

2.2.5.4 Register Considerations

The following is a summary of the registers and bits required to enable Ultra160 SCSI on the LSI53C1010R device.

• The PCI Device ID register value must be 0x21.

• The PCI Max_Lat (ML) register contains a value of 0x12, indicating

it requires the bus every 4.5 µs.

• The SCSI Control Zero (SCNTL0) register:

– Bit 3, EPC (Enable Parity/CRC/AIP Checking) is set to enable

the CRC feature.

– Bit 1, AAP (Assert SATN/ on Parity/CRC/AIP Error), is set in the

initiator mode to assert SATN/ automatically on the detection of an error.

• The SCSI Control One (SCNTL1) register:

– Bit 5, DHP (Disable Halt on Parity/CRC/AIP Error or ATN)

(Target Only), is set in accordance with user requirements. When bit 5 is cleared, a SCSI transfer halts if an error occurs. When bit 5 is set, a SCSI transfer continues if an error occurs.

• The SCSI Control Three (SCNTL3) register:

– Bit 7 is now reserved. It was previously the Ultra Enable bit. – Bits [6:4], SCF[2:0] (Synchronous Clock Conversion Factor),

select the divisor of the SCLK frequency. The SCLK is divided before its presentation to the synchronous SCSI control logic.

– Bit 3, EWS (Enable Wide SCSI), is set to enable wide SCSI.

Ultra160 requires wide SCSI. Therefore, this bit must be set during these transfers.

– Bits [2:0] are reserved.

• The SCSI Transfer (SXFER) register:

– Bits [7:6] are reserved. – Bits [5:0], MO[5:0] (Max SCSI synchronous offset), are set for

the maximum offset.

SCSI Functional Description 2-27

• The SCSI Status Two (SSTAT2) register:

– Bit 2 is reserved. HVD SCSI is not supported.

• The SCSI Interrupt Enable Zero (SIEN0) register:

– Bit 0, PAR (SCSI Parity/CRC/AIP Error), is set to detect a

parity/CRC/AIP error while receiving or sending SCSI data. For more information, refer to SCSI Control One (SCNTL1), bit 5.

• The Chip Control Three (CCNTL3) register:

– Bit 4, ENDSKEW (Enable REQ/ACK to Data skew control) is set

to enable control of the relative skew between the SCSI REQ/ACK signal and the data signals.

– Bits [3:2], DSKEW[1:0] (REQ/ACK – Data skew control), control

the amount of skew between the SCSI REQ/ACK signal and the SCSI data signals. These bits are used for Ultra160 SCSI domain validation only and control the skew only if bit 4 is set.

– Bits [1:0], LVDDL[1:0] (LVD Drive strength select), control the

drive levelof the LVD pad drivers. This feature is intended for use in Ultra160 SCSI domain validation testing environments only. Set these bits to 0b00 during normal operation.

• The SCSI Control Four (SCNTL4) register:

– Bit 7, U3EN (Ultra160 Transfer Enable) is set to enable Ultra160

transfers.

– Bit6, AIPCKEN (AIP Checking Enable), is set to enable checking

of the upper byte lane of protection information during

Command, Status, and Message Phases. – Bits [5:4] are reserved. – Bit3, XCLKH_DT (Extra Clock of Data Hold on DT Transfer Edge)

is set to add a clock of data hold to synchronous DT SCSI

transfers on the DT edge. – Bit 2, XCLKH_ST (Extra Clock of Data Hold on ST Transfer Edge)

is set to add a clock of data hold to synchronous DT or ST SCSI

transfers on the ST edge. This bit impacts both ST and DT

transfers because it affects data hold to the ST edge.

2-28 Functional Description

– Bit1, XCLKS_DT (Extra Clock of Data Setup on DT Transfer Edge)

is set to add a clock of data setup to synchronous DT SCSI

transfers on the DT edge. This bit only impacts DT transfers

because it affects data setup to the DT edge. – Bit 0, XCLKS_ST (Extra Clock of Data Setup on ST Transfer

Edge) is set to add a clock of data setup to synchronous DT or

ST SCSI transfers on the ST edge. This bit impacts both ST and

DT transfers because it affects data setup to the ST edge.

Note. The XCLKH_DT, XCLKH_ST, XCLKS_DT, and XCLKS_ST

bits do not affect CRC timings.

• The AIP Control Zero (AIPCNTL0) register:

– Bits [7:3] are reserved. – Bit 2, AIPERR_LIVE (AIP Error Status Live), represents the live

error status for the AIP checking logic. This is not a latched value. – Bit 1, AIPERR (AIP Error Status), represents the error status for

the AIP checking logic. – Bit 0, PARITYERR (Parity Error), represents the error status for

the parity error.

• The AIP Control One (AIPCNTL1) register:

– Bits [7:4] are reserved. – Bit 3, DISAIP (Disable AIP Code Generation), disables the AIP

code generation on the SCSI bus. – Bit 2, RAIPERR (Reset AIP Error), allows an AIP error condition

to be reset manually. – Bit 1, FBAIP (Force Bad AIP Value), causes bad AIP values to

be sent over the SCSI bus. – Bit 0, RSQ (Reset AIP Sequence Value), causes the sequence

value used in the calculation of the protection code to be reset.

• The CRC Pad Byte Value (CRCPAD) register:

– Bits [15:0], the CRC Pad byte value, contain the value placed

onto the bus for the CRC pad bytes.

• The CRC Control Zero (CRCCNTL0) register:

– Bit 7, DCRCC (Disable CRC Checking), is set to cause the

internal logic to not check or report CRC errors during Ultra160

transfers. The device continues to calculate and send CRCs as

requested by the target according to the SPI-3 speciﬁcation.

SCSI Functional Description 2-29

– Bit 6, DCRCPC (Disable CRC Protocol Checking) causes the

LSI53C1010R to not check for a CRC request prior to a phase

change on the SCSI bus. This condition creates a SCSI error

condition and makes the device noncompliant with the SPI-3

specification. Do not set this bit under normal operating conditions. – Bits [5:0] are reserved.

• The CRC Control One (CRCCNTL1) register:

– Bit 7, CRCERR (CRC Error), indicates whether or not a CRC

error has been detected during a DT Data In SCSI transfer. This

bit is independent of the DCRCC bit setting. To clear this

condition, either write this bit to a one or read the SIST0 and

SIST1 registers. When CRC checking and the Parity/CRC/AIP

Error interrupt are both enabled, CRCERR is mirrored in the

SIST0 register, bit 0, as a Parity/CRC/AIP error. – Bit 6 is reserved. – Bit 5, ENAS (Enable CRC Auto Seed), is set to cause the CRC

logic to reseed itself automatically after every CRC check

performed during DT Data In SCSI transfers. When this bit is

cleared, the SCSI control logic controls when the CRC logic is

reseeded. – Bit 4, TSTSD (Test CRC Seed), is set to cause the CRC logic to

reseed itself immediately. Do not set this bit during normal

operation because it may cause corrupt CRCs to be generated. – Bit 3, TSTCHK (Test CRC Check), is set to cause the CRC logic

to initiate a CRC check. Do not set this bit during normal

operation because it creates spurious CRC errors. – Bit 2, TSTADD (Test CRC Accumulate), is set to cause the CRC

blockto include the value present in the input register in the current

CRC calculation. A new output CRC value results. Do not set this

bit during normal operation because corrupt CRC values result. – Bits [1:0], CRCDSEL[1:0] (CRC Data Register Selector), control

the data visible in the CRC Data register.

• The CRC Data (CRCD) register:

– Bits [31:0] CRCDATA (CRC Data). The value in this register is

dependent upon the setting of the CRCDSEL bits.

2-30 Functional Description

2.2.5.5 Using the SCSI Clock Quadrupler

The LSI53C1010R can quadruple the frequency of a 40 MHz SCSI clock, allowing the system to perform Ultra160 SCSI transfers. This option is user-selectable with bit settings in the SCSI Test One (STEST1),

SCSI Test Three (STEST3), and SCSI Control Three (SCNTL3)

registers. At power-on or reset, the quadrupler is disabled and powered down. Follow these steps to use the clock quadrupler:

1. Set the SCLK Quadrupler Enable bit (SCSI Test One (STEST1) register, bit 3).

2. Do not poll bit 5 of the SCSI Test Four (STEST4) register. Bit 5 is reserved. Use a delay of 50 µs after the quadrupler enable bit is set in step 1.

3. Halt the SCSI clock by setting the Halt SCSI Clock bit (SCSI Test Three (STEST3) register, bit 5).

4. Set the clock conversion factor using the SCF (Synchronous clock Conversion Factor) ﬁeld in the SCSI Control Three (SCNTL3) register.

5. Set the SCLK Quadrupler Select bit (SCSI T est One (STEST1), bit 2).

6. Clear the Halt SCSI Clock bit.

2.2.6 Prefetching SCRIPTS Instructions

The prefetch logic in the LSI53C1010R fetches 8 Dwords of instructions when enabled by setting the Prefetch Enable bit (bit 5) in the

DMA Control (DCNTL) register. The maximum burst size that can be

performed is automatically determined using the burst length values in the DMA Mode (DMODE) register. If the unit cannot perform bursts of at least 4 Dwords, it disables itself. While the chip is prefetching SCRIPTS instructions, it uses the PCI cache commands Memory Read Line and Memory Read Multiple, if PCI caching is enabled.

Note: This feature is only useful when fetching SCRIPTS

instructions from main memory. Due to the short access time of SCRIPTS RAM, prefetching is not necessary when fetching instructions from SCRIPTS RAM.

SCSI Functional Description 2-31

To ensure the LSI53C1010R always operates from the current version of the SCRIPTS instruction, the contents of the prefetch unit may be ﬂushed under certain conditions. The contents of the prefetch unit are automatically ﬂushed under the following conditions:

• On every Memory Move instruction.

The Memory Move instruction places modiﬁed code into memory. To assure the device executes recent modiﬁcations, the prefetch unit ﬂushes its contents and reloads the code each time an instruction is issued. To avoid inadvertently ﬂushing the prefetch unit contents, use the No Flush option for all Memory Move operations that do not modify code within the next 8 Dwords. For more information refer to

Chapter 5, “SCSI SCRIPTS Instruction Set.”

• On every Store instruction.

The Store instruction may also place modiﬁed code directly into memory. To avoid inadvertently ﬂushing the prefetch unit contents, use the No Flush option for all Store operations that do not modify code within the next 8 Dwords.

• On every write to the DMA SCRIPTS Pointer (DSP) register.

• On all Transfer Control instructions, when the transfer conditions

are met. This is necessary because the next instruction to be executed is not

the sequential next instruction in the prefetch unit.

• When the Prefetch Flush bit (DMA Control (DCNTL) register, bit 6)

is set. The unit ﬂushes whenever this bit is set. This bit is self-clearing.

2.2.7 Opcode Fetch Burst Capability

Setting the Burst Opcode Fetch Enable bit (bit 1) in the

DMA Mode (DMODE) register (0x38) causes the LSI53C1010R to burst

in the ﬁrst two Dwords of all instruction fetches. If the instruction is a Memory-to-Memory Move, the third Dword is accessed in a separate ownership. If the instruction is an indirect type, the additional Dword is accessed in a subsequent bus ownership. If the instruction is a Table Indirect Block Move, the device uses two accesses, each a two Dword burst, to obtain the four Dwords required.

2-32 Functional Description

Note: This feature is only useful if Prefetching is disabled.

This feature is only useful if fetching SCRIPTS instructions from main memory. Due to the short access time of SCRIPTS RAM, burst opcode fetching is not necessary when fetching instructions from SCRIPTS RAM.

2.2.8 Load and Store Instructions

The LSI53C1010R supports the Load and Store instruction type, which simpliﬁes data movement between memory and the internal registers. It also enables the chip to transfer bytes to addresses relative to the

Data Structure Address (DSA) register. Load/Store data transfers to or

from the SCRIPTS RAM remain internal to the chip and do not generate PCI bus cycles. While a Load/Store to or from SCRIPTS RAM is occurring, any external PCI slave cycles that occur are retried on the PCI bus. Setting the DISRC (Disable Internal SCRIPTS RAM Cycles) bit in the Chip Control Zero (CCNTL0) register disables this feature. For more information on the Load and Store instructions, refer to

Chapter 5, “SCSI SCRIPTS Instruction Set.”

2.2.9 JTAG Boundary Scan Testing

With one exception, the LSI53C1010R includes support for JTAG boundary scan testing in accordance with the IEEE 1149.1 speciﬁcation. The exception concerns the TST_RSTN pin. This pin must not be toggled because it resets the JTAG TAP controller. For more information, refer to the Boundary Scan Descriptor Language (BSDL) ﬁle.

This device accepts all required boundary scan instructions including the optional CLAMP, HIGH-Z, and IDCODE instructions. The optional JTAG pin TRST is not implemented. Reset of the JTAG logic through the TAP controller occurs when TMS is held HIGH for at least 5 TCK clock cycles.

The LSI53C1010R uses an 8-bit instruction register to support all boundary scan instructions. The data registers included in the device are the Boundary Data register, the IDCODE register, and the Bypass register. This device can handle a 20 MHz TCK frequency with all TAP pins having a 50% duty cycle.

SCSI Functional Description 2-33

2.2.10 Parity/CRC/AIP Options

The LSI53C1010R implements a ﬂexible parity scheme that permits control of the parity sense, allows parity checking to be turned on or off, and can deliberately send a byte with bad parity over the SCSI bus.

Table 2.4 deﬁnes the bits that are involved in parity control and

observation. Table 2.5 describes the parity control function of the Enable Parity Checking and Assert SCSI Even Parity bits in the

SCSI Control One (SCNTL1) register, bit 2, and the options available

when a parity error occurs. SCRIPTS RAM must ﬁrst be written before being read in order to

initialize SCRIPTS RAM parity. If a SCRIPTS RAM parity error is encountered, a SCSI Gross Error interrupt is signaled.

The LSI53C1010R supports CRC checking and generation in DT phases and CRC checking and generation during DT Data Transfers.

The new CRC registers are: CRC Pad Byte Value (CRCPAD);

CRC Control Zero (CRCCNTL0); CRC Control One (CRCCNTL1); CRC Data (CRCD); SCSI Control Zero (SCNTL0), bit 3, EPC, and bit 1,

AAP; Chip Control One (CCNTL1), bit 5, DHP; and

SCSI Interrupt Enable Zero (SIEN0), bit 0 (SCSI Parity/CRC/AIP Error).

The new AIP registers are: SCSI Control Zero (SCNTL0),

AIP Control Zero (AIPCNTL0), and AIP Control One (AIPCNTL1).

Table 2.4 Bits Used for Parity/CRC/AIP Control and Generation

Bit Name Location Description

AAP (Assert SATN/ on Parity/CRC/AIP Errors)

EPC (Enable Parity/CRC/AIP Checking)

Assert Even SCSI Parity

Disable Halt on SATN/ orParity/CRC/AIPError (Target Mode Only)

2-34 Functional Description

SCSI Control Zero (SCNTL0), Bit 1

SCSI Control Zero (SCNTL0), Bit 3

SCSI Control One (SCNTL1), Bit 2

SCSI Control One (SCNTL1), Bit 5

When this bit is set, the LSI53C1010R SCSI function automatically asserts the SATN/ signal upon detection of a parity, CRC, or AIP error. SATN/ is only asserted in initiator mode.

When set, this bit enables parity checking on the LSI53C1010R. The LSI53C1010R checks for odd parity.

When set, this bit forces even SCSI parity on each byte sent to the SCSI bus from the LSI53C1010R.

This bit determines whether the LSI53C1010R halts operations when a parity error is detected in target mode.

Table 2.4 Bits Used for Parity/CRC/AIP Control and Generation (Cont.)

Bit Name Location Description

Enable Parity/CRC/AIP Error Interrupt

Parity Error SCSI Interrupt

Status of SCSI Parity Signal

SCSI SDP1 Signal SCSI Status Two

Latched SCSI Parity SCSI Status Two

Master Parity Error Enable

Master Data Parity Error

Master Data Parity Error Interrupt Enable

AIP Checking Enable SCSI Control Four

CRC Request OK SCSI Control Zero

Disable CRC Checking CRC Control Zero

Disable CRC Protocol Checking

SCSI Interrupt Enable Zero (SIEN0), Bit 0

Status Zero (SIST0),

Bit 0

SCSI Status Zero (SSTAT0), Bit 0

(SSTAT2), Bit 0

(SSTAT2), Bit 3 SCSI Status One (SSTAT1), Bit 3

Chip Test Four (CTEST4), Bit 3

DMA Status (DSTAT), Bit 6

DMA Interrupt Enable (DIEN), Bit 6

(SCNTL4), Bit 6

(SCNTL0), Bit 2

(CRCCNTL0), Bit 7 CRC Control Zero

(CRCCNTL0), Bit 6

This bit determines whether the LSI53C1010R generates an interrupt when it detects a SCSI parity/CRC/AIP error.

This status bit is set whenever the LSI53C1010R detects a parity/CRC/AIP error on the SCSI bus.

This status bit represents the active HIGH current state of the SCSI SDP0 parity signal.

This bit represents the active HIGH current state of the SCSI SDP1 parity signal.

These bits reﬂect the SCSI odd parity signal corresponding to the data latched into the

SCSI Input Data Latch (SIDL) register.

This bit enables parity checking during PCI master data phases.

This bit is set when the LSI53C1010R, as a PCI master, detects a target device signaling a parity error during a data phase.

By clearing this bit, a Master Data Parity Error does not cause assertion of INTA/ (or INTB/), but the status bit is set in the DMA Status (DSTAT) register.

Setting this bit enables the AIP checking of the upper byte lane of protection information during command, status, and message phases.

This bit indicates that it is acceptable to force a CRC request. This bit is set only if a CRC request has been sent and no data has been transferred since that request. This bit can determine whether it is necessary to send a CRC request at the end of a data transfer prior to changing phases in target mode. Use this bit to prevent back to back CRC conditions.

This bit is set to cause internal logic not to check or report CRC errors during Ultra160 transfers.

This bit is set to cause the device not to check for a CRC request prior to a phase change on the SCSI bus. This condition normally causes a SCSI error condition. Note: Setting this bit makes the LSI53C1010R noncompliant to the SPI-3 speciﬁcation. Do not set this bit under normal operating conditions.

SCSI Functional Description 2-35

Table 2.5 SCSI Parity Errors and Interrupts

DHP

PAR

Description

0 0 Halts when a parity error occurs in the target or initiator mode and

does not generate an interrupt.

0 1 Halts when a parity error occurs in the target mode and generates

an interrupt in the target or initiator mode.

1 0 Does not halt in target mode when a parity error occurs until the

end of the transfer. An interrupt is not generated.

1 1 Does not halt in target mode when a parity error occurs until the

end of the transfer. An interrupt is generated.

1. DHP = Disable Halt on SATN/ or Parity Error (bit 5 SCSI Control One (SCNTL1)).

2. PAR = Parity Error (bit 0 SCSI Interrupt Enable One (SIEN1)).

2.2.11 DMA FIFO

The DMA FIFO is 8 bytes wide by 112–115 transfers deep, depending on the type and direction of data transfer. The DMA FIFO is illustrated in

Figure 2.2. The small FIFO mode (112 bytes) is not supported by the

LSI53C1010R.

Figure 2.2 DMA FIFO Sections

8 Bytes Wide

112–115

Transfers

Deep

Byte Lane 7 Byte Lane 6 Byte Lane 5 Byte Lane 4 Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0

2-36 Functional Description

The LSI53C1010R supports 64-bit memory and automatically supports misaligned DMA transfers. The FIFO allows the LSI53C1010R to support 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface.

2.2.12 SCSI Data Paths

The data path through the LSI53C1010R is dependent on whether data is moved into or out of the chip and whether the SCSI data transfer is asynchronous or synchronous. Figure 2.3 illustrates how data is moved to and from the SCSI bus in each of the different modes. The following sections determine whether any bytes remain in the data path when the device halts an operation.

Figure 2.3 LSI53C1010R Host Interface SCSI Data Paths

Asynchronous

SCSI Send

PCI Interface

DMA FIFO

SODL Register

SCSI Interface

Asynchronous

SCSI Receive

PCI Interface

DMA FIFO

SWIDE Register

SIDL Register

SCSI Interface

2.2.12.1 Asynchronous SCSI Send

To determine the number of bytes remaining in the DMA FIFO when a phase mismatch occurs, read the DMA FIFO Byte Count (DFBC) register. This 16-bit, read-only register contains the actual number of bytes remaining in the DMA FIFO. In addition, the

SCSI Output Data Latch (SODL) register must be checked to determine

whether it contains any remaining bytes. If bit 5 (OLF) in the

SCSI Status Zero (SSTAT0) register is set, then the least significant byte

in the SODL register contains data. If bit 5 (OLF1) in the

Synchronous

SCSI Send

PCI Interface

DMA FIFO

Chain Byte

Holding Register

SCSI Interface

Synchronous

SCSI Receive

PCI Interface

DMA FIFO

Chain Byte

Holding Register

SCSI FIFO

SCSI Interface

SCSI Functional Description 2-37

SCSI Status Two (SSTAT2) register is set, then the most significant byte

in the SODL register contains data. Checking these bits also reveals bytes left in the SODL register from a Chained Move operation with an odd byte count. To recover from all other error conditions, clear the DMA FIFO by setting bit 2 (CLF) in Chip Test Three (CTEST3) and retry the I/O.

If the Wide SCSI Send (WSS) bit in the SCSI Control Two (SCNTL2) register is set when a phase mismatch occurs, then adjustments must be made to the previous block move, not the current block move loaded into DCMD/DBC. To recover the byte of chain data in the SODL register, set the previous block move byte count to 1 and set the address to the last data address for that block move.

2.2.12.2 Synchronous SCSI Send

The DMA FIFO is the only location where data can reside when a phase mismatch occurs during a synchronous SCSI send transfer. To determine the number of bytes remaining in the DMA FIFO, read the

DMA FIFO Byte Count (DFBC) register. This 16-bit, read only register

contains the actual number of bytes remaining in the DMA FIFO. To recover from all other error conditions, clear the DMA FIFO by setting bit 2 (CLF) in Chip Test Three (CTEST3) and retry the I/O.

If the Wide SCSI Send (WSS) bit in the SCSI Control Two (SCNTL2) register is set when a phase mismatch occurs, then adjustments must be made to the previous block move, not the current block move loaded into DCMD/DBC. Torecover the byte of chain data in the outbound chain byte holding register, set the previous block move byte count to one and set the address to the last data address for that block move.

2.2.12.3 Asynchronous SCSI Receive

When a phase mismatch occurs during an asynchronous SCSI receive, the only data that may remain in the device is a potential wide residue byte in the SCSI Wide Residue (SWIDE) register. If bit 0 (WSR) in

SCSI Control Two (SCNTL2) is set, then the SWIDE register contains a

residual byte. This byte can be ﬂushed by executing a block move instruction with a byte count of one. To recover from all other error conditions, set the DMA FIFO by setting bit 2 (CLF) in

Chip Test Three (CTEST3) and retry the I/O.

2-38 Functional Description

2.2.12.4 Synchronous SCSI Receive

When a phase mismatch occurs during a synchronous SCSI receive transfer, no data recovery operation is necessary .All data, including chain bytes from Chained Block Moves, is flushed from the device prior to the phase mismatch occurring. To recover from all other error conditions, clear the DMA FIFO by setting bit 2 (CLF) in Chip Test Three (CTEST3), clear the SCSI FIFO by setting bit 1 (CSF) in SCSI Test Three (STEST3), and retry the I/O.

2.2.13 SCSI Bus Interface

The LSI53C1010R performs SE and LVD transfers.

2.2.13.1 SCSI Bus Modes

To increase device connectivity and SCSI cable length, the LSI53C1010R features LVDlink technology, the LSI Logic implementation of LVD SCSI. LVDlink transceivers provide the inherent reliability of differential SCSI and a long-term migration path for faster SCSI transfer rates.

HVD is not supported by this device. Bit 2 (previously DIFF), of the

SCSI Status Two (SSTAT2) register, and bit 5 (previously DIF), of the SCSI Test Two (STEST2) register, are reserved. The A_DIFFSENS or

B_DIFFSENS signals still detect the different input voltages for HVD, LVD, and SE but the HVD feature is not present.

2.2.13.2 SCSI Termination

The terminator networks pull signals to an inactive voltage level and match the impedance seen at the end of the cable with the characteristic impedance of the cable. Terminators must be installed at the extreme ends of the SCSI chain, and only at the ends; no system should ever have more or less than two terminators. SCSI host adapters should provide a means of accommodating terminators. There should be a means of disabling the termination.

SE cables can use a 220 Ω pull-up resistor to the terminator power supply (Term Power) line and a 330 Ω pull-down resistor to ground. Because of the high-performance nature of the LSI53C1010R, regulated

SCSI Functional Description 2-39

(or active) termination is recommended. Figure 2.4 shows an active terminator. TolerANT technology active negation can be used with either termination network.

For information on terminators that support LVD, refer to the SPI-3 draft standard.

Note: If the LSI53C1010R is used in a design with an 8-bit SCSI

bus, all 16 data lines must be terminated.

Figure 2.4 Regulated Termination for Ultra160 SCSI

SD0+ SD0− SD1+ SD1− SD2+ SD2− SD3+ SD3− SD4+ SD4−

Notes:

1. DIFFSENS connects to the SCSI bus DIFFSENS line to detect what type of devices (SE, LVD, or HVD) are connected to the SCSI bus.

2. DISCONNECT shuts down the terminator when it is not at the end of the bus. The disconnect pin LOW enables the terminator.

Line1+

Line1−

Line2+

Line2−

Line3+

Line3−

Line4+

Line4−

Line5+

Line5−

DISCONNECT

Line9− Line9+ Line8− Line8+ Line7− Line7+ Line6− Line6+

LVD

HVD

DIFFSENS

DIFF B

32 31 30 29 25 24 23 22

33 34 35

SDP0− SDP0+ SD7− SD7+ SD6− SD6+ SD5− SD5+

To LED Drivers

51 K

4.7 µF

2-40 Functional Description

2.2.14 Select/Reselect during Selection/Reselection

In multithreaded SCSI I/O environments, it is not uncommon to be selected or reselected while trying to perform selection/reselection. This situation may occur when a SCSI controller (operating in the initiator mode) tries to select a target and is reselected by another. The Select SCRIPTS instruction has an alternate address to which the SCRIPTS jumps when this situation occurs. The analogous situation for target devices is being selected while trying to perform a reselection.

When a change in operating mode occurs, either the initiator SCRIPTS issues a Set Initiator instruction or the target SCRIPTS issues a Set Target instruction. The Selection and Reselection Enable bits (SCSI Chip ID (SCID) bits 5 and 6, respectively) should both be asserted, enabling the LSI53C1010R to respond as an initiator or as a target. If only selection is enabled, the LSI53C1010R cannot be reselected as an initiator. Status bits, in the SCSI Interrupt Status Zero (SIST0) register, and interrupt bits, in the SCSI Interrupt Enable Zero (SIEN0) register, indicate if the LSI53C1010R has been selected or reselected.

2.2.15 Synchronous Operation

The LSI53C1010R can transfer synchronous SCSI data in both the initiator and target modes. The LSI53C1010R SCLK input must be connected to a 40 MHz oscillator. The SCSI Transfer (SXFER) register controls the synchronous offset while the SCSI Control Three (SCNTL3) register controls the synchronous clock converters. These registers may be loaded by the CPU before SCRIPTS execution begins, from within SCRIPTS, with a Table Indirect I/O instruction, or with a Read-Modify-Write instruction.

The LSI53C1010R can receive data from the SCSI bus at a synchronous transfer period as short as 12.5 ns, regardless of the transfer period that sends data. The LSI53C1010R can receive data at one-fourth of the divided SCLK frequency. Depending on the SCLK frequency, the negotiated transfer period, and the synchronous clock divider, the LSI53C1010R can send synchronous data at intervals as short as

12.5 ns for Ultra160 SCSI, 25 ns for Ultra2 SCSI, 50 ns for Ultra SCSI, 100 ns for Fast SCSI, and 200 ns for SCSI-1.

Synchronous data transfer rates are controlled by bits in two different registers of the LSI53C1010R. Following is a brief description of these bits and the method that determines the data transfer rate.

SCSI Functional Description 2-41

2.2.15.1 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0]) Description

The SCF[2:0] bits select the factor by which the frequency of SCLK is divided before its presentation to the synchronous SCSI control logic.

The synchronous transfer speed is determined by the combination of the divided clock and the setting of the XCLKS_ST, XCLKS_DT, XCLKH_ST, and XCLKH_DT bits in the SCSI Control Four (SCNTL4) register.

Table 2.6 provides the SCF clock dividers available. Refer to Table 4.4,“Double Transition Transfer Rates,’’ and Table 4.5, "Single Transition Transfer Rates," located in the SCSI Control Four (SCNTL4) register description, for a full list of

available synchronous transfer rates.

Table 2.6 lists the SCF divisor values.

Table 2.6 SCF Divisor Values

SCF2 SCF1 SCF0 SCLK Divisor

0 0 0 SCLK/3 0 0 1 SCLK/1 0 1 0 SCLK/1.5 0 1 1 SCLK/2 1 0 0 SCLK/3 1 0 1 SCLK/4 1 1 0 SCLK/6 1 1 1 SCLK/8

2.2.15.2 SCSI Control Four (SCNTL4) Register, Bits [3:0] Description

The following extra clock bits add an extra clock of setup or hold to a ST or DT transaction.

Bit 3, XCLKH_DT (Extra Clock of Data Hold on DT transfer edge), adds a clock of data hold to synchronous DT SCSI transfers on the DT edge. This bit only impacts DT transfers because it only affects data hold to the

2-42 Functional Description

DT edge. Setting this bit reduces the synchronous transfer send rate but does not reduce the rate at which the LSI53C1010R receives outbound REQs, ACKs, or data.

Bit 2, XCLKH_ST (Extra Clock of Data Hold on ST transfer edge), adds a clock of data hold to synchronous DT or ST SCSI transfers on the ST edge. This bit impacts DT and ST transfers because it affects data hold to the ST edge. Setting this bit reduces the synchronous transfer send rate but does not reduce the rate at which the LSI53C1010R receives outbound REQs, ACKs, or data.

Bit 1, XCLKS_DT (Extra Clock of Data Setup on DT transfer edge), adds a clock of data setup to synchronous DT SCSI transfers on the DT edge. This bit only impacts DT transfers because it only affects data hold to the DT edge. Setting this bit reduces the synchronous transfer send rate but does not reduce the rate at which the LSI53C1010R receives outbound REQs, ACKs, or data.

Bit 0, XCLKS_ST (Extra Clock of Data Setup on ST transfer edge), adds a clock of data setup to synchronous DT or ST SCSI transfers on the ST edge. This bit impacts DT and ST transfers because it affects data hold to the ST edge. Setting this bit reduces the synchronous transfer send rate but does not reduce the rate at which the LSI53C1010R receives outbound REQs, ACKs, or data.

2.2.15.3 Determining the Data Transfer Rate

The synchronous receive rate can be calculated using the following formula:

Receive Rate (DT)

Receive Rate (ST)

Note: The receive rate is independent of the settings of the

XCLKS_DT, XCLKS_ST, XCLKH_DT, XCLKH_ST bits.

SCSI Functional Description 2-43

Input Clock Rate

----------------------------------------------

SCF Divisor 2×()

Input Clock Rate

----------------------------------------------

SCF Divisor 4×()

(Megatransfers/s)=

The synchronous send rate, in units of megatransfers/s, can be





calculated using the following formula:

Send Rate (DT)

To conﬁgure the LSI53C1010R for Ultra160 DT transfers, perform the following steps:

1. Enable the SCSI Clock Quadrupler – The LSI53C1010R can

2. Program the Transfer Rate – Using SCNTL3 and SCNTL4, program

3. Program the Maximum SCSI Offset – Using SXFER, program the

4. Enable TolerANT – Set the TolerANT Enable bit,

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

SCF Divisor 2

Send Rate (ST)

XCLKS_DT + XCLKS_ST + XCLKH_DT + XCLKH_ST



------------------------------------------------------------------------------------------------------------------------------------------------+



-------------------------------------------------------------------------------------------------------------------------=

SCF Divisor 4 XCLKS_ST + XCLKH_ST+()×

Input Clock Rate

quadruple the frequency of a 40 MHz SCSI clock, allowing the system to perform Ultra160 SCSI transfers. This option is user selectable through bit settings in the SCSI Test One (STEST1) register. At power-up or reset, the quadrupler is disabled and powered down. Follow the steps in the bit description to enable the clock quadrupler.

the register to the 160 Mbytes/s transfer rate.

maximum SCSI DT Synchronous offset to 0x3E.

SCSI Test Three (STEST3), bit 7. Active negation must be enabled

for the LSI53C1010R to perform Ultra160 SCSI transfers.

Figure 2.5 illustrates the clock division factors used in each register as

well as the role of the register bits in determining the transfer rate. An example of conﬁguring the Ultra160 SCSI transfer speed is:

1. Set SCNTL3 to 0x18.

2. Set SXFER to 0x3E.

3. Set SCNTL4 to 0x80. These settings program the LSI53C1010R SCSI clocks to send and

receive at 160 MHz with a synchronous SCSI offset of 0x3E.

2-44 Functional Description

Figure 2.5 Determining the Synchronous Transfer Rate

SCF2 SCF1 SCF0 SCF Divisor

0003 0011

0101.5 0112 1003 1014 1106

40 MHz

SCLK

Received Rate (DT)

Receive Rate (ST)

Send Rate (DT)

Send Rate (ST)

Clock

Quadrupler

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -=

SCF Divisor 2

------------------------------------------------------------------------------------------------------------------------ -=

SCF Divisor 4 XCLKS_ST XCLKH_ST++()×

Input Clock Rate

----------------------------------------------

SCF Divisor 2×()

Input Clock Rate

----------------------------------------------

SCF Divisor 4×()





Input Clock Rate

2.2.16 Interrupt Handling

The SCRIPTS processors in the LSI53C1010R perform most functions independently of the host microprocessor. However, certain interrupt situations must be handled by the external microprocessor. This section explains all aspects of interrupts as they apply to the LSI53C1010R.

SCF

Divider

Asynchronous

Divider

Divide by 4 (ST) Divide by 2 (DT)

Asynchronous

SCSI Logic

Receive/Send Rate

(Megatransfers/s)=

Input Clock Rate

XCLKS_DT XCLKS_ST XCLKH_DT XCLKH_ST+++

---------------------------------------------------------------------------------------------------------------------------------------------- -+

SCSI Functional Description 2-45

2.2.16.1 Polling and Hardware Interrupts

The external microprocessor is informed of an interrupt condition by polling or hardware interrupts. Polling means that the microprocessor must continually loop and read a register until it detects a bit that is set indicating an interrupt. This method is the fastest, but it diverts CPU time from other system tasks. The preferred method of detecting interrupts in most systems is hardware interrupts. In this case, the LSI53C1010R asserts the interrupt request (INTA/ or INTB/) line that interrupts the microprocessor, causing the microprocessor to execute an interrupt service routine. A hybrid approach uses hardware interrupts for long waits and polling for short waits.

SCSI Function A is routed to PCI Interrupt INTA/. SCSI Function B is normally routed to INTB/, but can be routed to INTA/ if a pull-up is connected to MAD[4]. Refer to Section 3.9, “MAD Bus Programming,” for details.

2.2.16.2 Registers

The registers in the LSI53C1010R used fordetecting or defining interrupts are Interrupt Status Zero (ISTAT0); Interrupt Status One (ISTAT1);

SCSI Interrupt Status Zero (SIST0); SCSI Interrupt Status One (SIST1); DMA Status (DSTAT); SCSI Interrupt Enable Zero (SIEN0); SCSI Interrupt Enable One (SIEN1); and DMA Interrupt Enable (DIEN).

Refer to the register descriptions in Chapter 4, “Registers,” for details. ISTAT – The ISTAT register includes the Interrupt Status Zero (ISTAT0),

Interrupt Status One (ISTAT1), Mailbox Zero (MBOX0), and Mailbox One (MBOX1) registers. It is the only register that can be

accessed as a slave during the SCRIPTS operation. Therefore, it is the register that is polled when polled interrupts are used. It is also the ﬁrst register that should be read after the INTA/ (or INTB/) pin is asserted in association with a hardware interrupt.

The INTF (Interrupt-on-the-Fly) bit should be the ﬁrst interrupt serviced. It must be written to one in order to clear it. This interrupt must be cleared before servicing any other interrupts indicated by SIP or DIP. Do not attempt to read the other chip status registers if the INTF bit is set, but SIP or DIP are not set.

2-46 Functional Description

If the SIP bit in the Interrupt Status Zero (ISTAT0) register is set, then a SCSI-type interrupt has occurred and the

SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers should be read.

If the DIP bit in the Interrupt Status Zero (ISTAT0) register is set, then a DMA-type interrupt has occurred and the DMA Status (DSTAT) register should be read.

SCSI-type and DMA-type interrupts may occur simultaneously, so in some cases both SIP and DIP may be set. To avoid missing a SCSI interrupt, the SIST0 and SIST1 registers should be read before the DSTAT register is read.

When set, the SIRQD bit in ISTAT1 disables the INT/ pin for the corresponding SCSI function. The interrupt is not lost or ignored but is merely masked at the pin. If the INT/ pin is already asserted when SIRQD is set, the INT/ pin remains asserted until the interrupt is serviced. Future interrupts are masked at the pin until SIRQD is cleared.

Note that the host can read ISTAT as the SCRIPTS code is writing to ISTAT. In this case the data is unstable, so the read should be retried.

SIST0 and SIST1 – The SCSI Interrupt Status Zero (SIST0) and

SCSI Interrupt Status One (SIST1) registers contain the status of

SCSI-type interrupts whether they are enabled in SIEN0 and SIEN1 or not. Reading these registers determines the conditions that caused the SCSI-type interrupt, clears any bits that are set in SIST0 and SIST1, and clears the SIP bit in ISTAT0. Because the LSI53C1010R SCSI functions stack interrupts, SIST0 and SIST1 are not necessarily cleared after a read; additional interrupts may still be pending.

If the LSI53C1010R is receiving data from the SCSI bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the DMA FIFO to memory before generating the interrupt. Reading

SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1)

clears the CRC Error bit (bit 7) in the CRC Control One (CRCCNTL1) register.

If the LSI53C1010R is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs, data could remain in the DMA FIFO. To determine whether the DMA FIFO is empty, check the DMA FIFO Empty (DFE) bit in DMA Status (DSTAT) register. If this bit is cleared, set the

SCSI Functional Description 2-47

CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits before continuing. The CLF bit is bit 2 in Chip Test Three (CTEST3) register. The CSF bit is bit 1 in SCSI Test Three (STEST3) register.

DSTAT. The DMA Status (DSTAT) register contains the status of DMA-type interrupts whether they are enabled in DIEN or not. Reading this register determines which condition(s) caused the DMA-type interrupt, clears any interrupt related bits in DSTAT, and clears the DIP bit in Interrupt Status Zero (ISTAT0) register. Because the LSI53C1010R SCSI functions stack interrupts, reading DSTAT does not necessarily clear the register as additional interrupts may be pending.

Bit 7 (DFE) in the DMA Status (DSTAT) register, is purely a status bit; it does not generate an interrupt and is not cleared when read. DMA interrupts do not ﬂush the DMA or SCSI FIFOs before generating the interrupt. Therefore, the DFE bit in the DSTAT register should be checked after any DMA interrupt. If the DFE bit is cleared, the FIFOs must either be cleared by setting the CLF (Clear DMA FIFO in CTEST3) and CSF (Clear SCSI FIFO in STEST3) bits, or ﬂushed by setting the FLF (Flush DMA FIFO in CTEST3) bit.

SIEN0 and SIEN1. The SCSI Interrupt Enable Zero (SIEN0) and

SCSI Interrupt Enable One (SIEN1) registers are the interrupt enable

registers for the SCSI interrupts in SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1). Clearing the appropriate mask bit masks an interrupt.

DIEN. The DMA Interrupt Enable (DIEN) register is the interrupt enable register for DMA interrupts in DMA Status (DSTAT). Clearing the appropriate mask bit masks an interrupt.

2.2.16.3 Fatal vs. Nonfatal Interrupts

A fatal interrupt, as the name implies, always causes the SCRIPTS to stop running. All nonfatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit. Interrupt masking is discussed in Section 2.2.16.4, “Masking.” All DMA interrupts are fatal. The DMA interrupts are indicated by the DIP bit in Interrupt Status Zero (ISTAT0) and one or more bits in DMA Status (DSTAT).

Some SCSI interrupts are nonfatal. The SCSI interrupts are indicated by the SIP bit in the Interrupt Status Zero (ISTAT0) register and one or more bits in SCSI Interrupt Status Zero (SIST0) register or

SCSI Interrupt Status One (SIST1) register.

2-48 Functional Description

2.2.16.4 Masking

When the LSI53C1010R is operating in the Initiator mode, Interrupt-onthe-Fly, Function Complete (CMP), Selected (SEL), Reselected (RSL), General Purpose Timer Expired (GEN), and Handshake-to-Handshake Timer Expired (HTH) interrupts are nonfatal.

When operating in the Target mode, Interrupt-on-the-Fly, SATN/ active (M/A), CMP, SEL, RSL, GEN, and HTH are nonfatal. Refer to the description for the Disable Halt on a Parity/CRC/AIP Error or SATN/ active (Target Mode Only) bit, DHP, in the SCSI Control One (SCNTL1) register to conﬁgure the chip’s behavior when the SATN/ interrupt is enabled during Target mode operation.

The reason for nonfatal interrupts is to prevent the SCRIPTS from stopping when an interrupt occurs that does not require service from the CPU. This prevents an interrupt when arbitration is complete (CMP set), when the LSI53C1010R is selected or reselected (SEL or RSL set), when the initiator asserts ATN (target mode: SATN/ active), or when the General Purpose or handshake-to-handshake timers expire. These interrupts are not needed for events that occur during high level SCRIPTS operation.

Masking an interrupt means disabling or ignoring that interrupt. Clearing bits in the SCSI Interrupt Enable Zero (SIEN0) and

SCSI Interrupt Enable One (SIEN1) registers mask SCSI interrupts.

Clearing bits in the DMA Interrupt Enable (DIEN) register mask DMA interrupts. Masking an interrupt after INTA/ (or INTB/) is asserted does not cause INTA/ (or INTB/) to be negated. How the chip responds to masked interrupts depends on whether polling or hardware interrupts are being used; whether the interrupt is fatal or nonfatal; and whether the chip is operating in the Initiator or Target mode.

If a nonfatal interrupt occurs while masked, SCRIPTS continues. The appropriate bit in the SCSI Interrupt Status Zero (SIST0) o r SCSI Interrupt Status One (SIST1) is still set, the SIP bit in the

Interrupt Status Zero (ISTAT0) is not set, and the INTA/ (or INTB/) pin is

not asserted.

SCSI Functional Description 2-49

If a fatal interrupt occurs while masked, SCRIPTS halts. The appropriate bit in the DMA Status (DSTAT), SCSI Interrupt Status Zero (SIST0),or

SCSI Interrupt Status One (SIST1) register is set, the SIP or DIP bit in

the Interrupt Status Zero (ISTAT0) register is set, but the INTA/ (or INTB/) pin is not asserted.

Setting the SIRQD bit in the Interrupt Status One (ISTAT1) register disables the interrupt pin for the corresponding SCSI function. If an interrupt pin is already asserted and SIRQD is then set, the interrupt pin remains asserted until serviced. Further interrupts are blocked from the interrupt pin.

When the LSI53C1010R is initialized, enable all fatal interrupts if hardware interrupts are being used. If a fatal interrupt is disabled and that interrupt condition occurs, the SCRIPTS halts and the system never knows it unless it times out and checks the Interrupt Status Zero (ISTAT0),

Interrupt Status One (ISTAT1), Mailbox Zero (MBOX0), and Mailbox One (MBOX1) registers after a certain period of inactivity.

If ISTAT is being polled instead of using hardware interrupts, then masking a fatal interrupt makes no difference because the SIP and DIP bits in the Interrupt Status Zero (ISTAT0) inform the system of interrupts, not the INTA/ (or INTB/) pin.

2.2.16.5 Stacked Interrupts

The LSI53C1010R stacks interrupts, if they occur, one after the other. If the SIP or DIP bits in the Interrupt Status Zero (ISTAT0) register are set (ﬁrst level), then there is already at least one pending interrupt. Any future interrupts are stacked in extra registers behind the

SCSI Interrupt Status Zero (SIST0), SCSI Interrupt Status One (SIST1),

and DMA Status (DSTAT) registers (second level). When two interrupts have occurred and the two levels of the stack are full, any further interrupts set additional bits in the extra registers behind SIST0, SIST1, and DSTAT. When the ﬁrst level of interrupts are cleared, all the later interrupts move into SIST0, SIST1, and DSTAT. After the ﬁrst interrupt is cleared, the INTA/ (or INTB/) pin is deasserted for a minimum of three CLKs; the stacked interrupts move into SIST0, SIST1, or DSTAT; and the INTA/ (or INTB/) pin is asserted again.

Because a masked nonfatal interrupt does not set the SIP or DIP bits, interrupt stacking does not occur. A masked, nonfatal interrupt still posts the interrupt in SCSI Interrupt Status Zero (SIST0), but does not assert

2-50 Functional Description

the INTA/ (or INTB/) pin. Because no interrupt is generated, future interrupts move into SCSI Interrupt Status Zero (SIST0) or

SCSI Interrupt Status One (SIST1) instead of stacking behind another

interrupt. When another interrupt condition occurs, the bit corresponding to the earlier masked nonfatal interrupt is set.

A related situation to interrupt stacking is when two interrupts occur simultaneously. Because stacking does not occur until the SIP or DIP bits are set, there is a small timing window in which multiple interrupts can occur but are not stacked. These could be multiple SCSI interrupts (SIP set), multiple DMA interrupts (DIP set), or multiple SCSI and multiple DMA interrupts (both SIP and DIP set).

As previously mentioned, DMA interrupts do not attempt to ﬂush the FIFOs before generating the interrupt. It is important to set either the Clear DMA FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA interrupt occurs and the DMA FIFO Empty (DFE) bit is not set. This is because any future SCSI interrupts are not posted until the DMA FIFO is cleared of data. These “locked out” SCSI interrupts are posted as soon as the DMA FIFO is empty.

2.2.16.6 Halting in an Orderly Fashion

When an interrupt occurs, the LSI53C1010R attempts to halt in an orderly fashion.

• If the interrupt occurs in the middle of an instruction fetch, the fetch

is completed, except in the case of a Bus Fault. Execution does not begin, but the DSP points to the next instruction because it is updated when the current instruction is fetched.

• If the DMA direction is a write to memory and a SCSI interrupt

occurs, the LSI53C1010R attempts to ﬂush the DMA FIFO to memory before halting. Under any other circumstances, only the current cycle is completed before halting, so the DFE bit in

DMA Status (DSTAT) should be checked to determine whether any

data remains in the DMA FIFO.

• SCSI SREQ/SACK handshakes that are in progress are completed

before halting.

• The LSI53C1010R attempts to clean up any outstanding

synchronous offset before halting.

SCSI Functional Description 2-51

• In the case of Transfer Control Instructions, when instruction

execution begins, it continues to completion before halting.

• In the case of a JUMP/CALL WHEN/IF <phase> instruction, the

DMA SCRIPTS Pointer (DSP) is updated to the transfer address

before halting.

• All other instructions may halt before completion.

2.2.16.7 Sample Interrupt Service Routine

The following is a sample of an interrupt service routine for the LSI53C1010R. It can be repeated if polling is used, or should be called when the INTA/ (or INTB/) pin is asserted if hardware interrupts are used.

1. Read Interrupt Status Zero (ISTAT0).

2. If the INTF bit is set, write it to a one to clear this status.

3. If only the SIP bit is set, read SCSI Interrupt Status Zero (SIST0) and

SCSI Interrupt Status One (SIST1) to clear the SCSI interrupt

condition and get the SCSI interrupt status. The bits in the SIST0 and SIST1 tell which SCSI interrupts occurred and determine what action is required to service the interrupts.

4. If only the DIP bit is set, read DMA Status (DSTAT) to clear the interrupt condition and determine the DMA interrupt status. The bits in the DSTAT register indicate which DMA interrupts occurred and determine what action is required to service the interrupts.

5. If both the SIP and DIP bits are set, read

SCSI Interrupt Status Zero (SIST0), SCSI Interrupt Status One (SIST1), and DMA Status (DSTAT) to clear

the SCSI and DMA interrupt condition and determine the interrupt status. If using 8-bit reads of the SIST0, SIST1, and DSTAT registers to clear interrupts, insert a 12 clock delay between the consecutive reads to ensure that the interrupts clear properly. Both the SCSI and DMA interrupt conditions should be handled before leavingthe Interrupt Service Routine (ISR). It is recommended that the DMA interrupt is serviced before the SCSI interrupt, because a serious DMA interrupt condition could influence how the SCSI interrupt is acted upon.

6. When using polled interrupts, go back to step 1 before leaving the ISR in case any stacked interrupts moved in when the ﬁrst interrupt was cleared. When using hardware interrupts, the INTA/ (or INTB/) pin is asserted again if there are any stacked interrupts. This should cause the system to re-enter the interrupt service routine.

2-52 Functional Description

2.2.17 Interrupt Routing

This section documents the recommended approach to RAID ready interrupt routing forthe LSI53C1010R. To be compatible with RAID upgrade products and the LSI53C1010R, the following requirements must be met:

• When a RAID upgrade card is installed in the upgrade slot, interrupts

from the mainboard SCSI controller(s) assigned to the RAID upgrade card must be routed to INTC/ and INTD/ of the upgrade slot and isolated from the mainboard interrupt controller. The system processor must not see interrupts from the SCSI controllers that are serviced by the RAID upgrade card. An upgrade slot is one that is connected to the interrupt routing logic for mainboard SCSI device(s). When a PCI RAID upgrade board is installed into the system, it is plugged into this slot if it is to control mainboard SCSI device(s).

• The TDI pin of the upgrade slot must be connected to the INT_DIR/

pin of the LSI53C1010R.

• When a RAID upgrade card is not installed, interrupts from a SCSI

core must not be presented to the system’s interrupt controller using multiple interrupt inputs.

Figure 2.6 shows an example conﬁguration. In this example the

LSI53C1010R contains the interrupt routing logic. The LSI53C1010R supports four different interrupt routing modes.

Details for these modes may be found in the register description of

SCSI Test One (STEST1) description in Chapter 4, “Registers.” Each

SCSI core within the chip may be conﬁgured independently by selecting the interrupt routing mode using bits [1:0] in the STEST1 register within each core. Mode 0 is the default mode and is compatible with RAID upgrade products.

If the implementation shown in Figure 2.6 is used, INTC/ and INTD/ of the PCI RAID upgrade slot cannot be used when a non-RAID upgrade card is installed in the slot. If this restriction is not acceptable, additional buffer logic must be implemented on the mainboard. As long as these interrupt routing requirements are satisﬁed, a mainboard designer could implement this design with external logic.

SCSI Functional Description 2-53

Figure 2.6 Interrupt Routing Hardware Using the LSI53C1010R

+ 5 V

INT_DIR

LSI53C1010

SCSI Core

10 K

ALT_INTA/

INTA/

ALT_INTB/

INTB/

+ 5 V

2.7 K

PCI RAID Upgrade Slot

2.7 K

INTB/

INTD/

Mbyte SCSI INTA/ Mbyte SCSI INTB/

A4 A6 A7

TDI INTA/ INTC/

PCI RAID Upgrade Slot INTA/

PCI RAID Upgrade Slot INTB/

These interrupt lines are connected to the other PCI slot interrupt lines as determined by the mainboard interrupt routing scheme.

There can only be one entity controlling a mainboard SCSI core, or conflicts occur. Typically, a SCSI core is controlled by the SCSI BIOS and an operating system driver. When a SCSI core is allocated to a RAID adapter,however, a mechanism must be implemented to prevent the SCSI BIOS and operating system driver from trying to access the SCSI core. The mainboard designer has several options to choose from for doing this.

• The ﬁrst option is to have the SCSI core load its PCI Subsystem ID

using a serial EPROM on power-up. If bit 15 in this ID is set, the LSI Logic BIOS and operating system drivers ignore the chip. This makes it possible to control the assignment of the mainboard SCSI cores using a conﬁguration utility.

• The second option is to provide mainboard and system BIOS

support for Nonvolatile Storage (NVS). The SCSI core may then be enabled or disabled using the SCSI BIOS conﬁguration utility. Not all versions of the LSI Logic drivers support this capability.

• The third option is to have the system BIOS not report the existence

of the SCSI controller chips when the SCSI BIOS and operating systems make PCI BIOS calls. This approach requires modiﬁcations to the system BIOS and assumes the operating system uses PCI BIOS calls when searching for PCI devices.

2-54 Functional Description

2.2.18 Chained Block Moves

Because the LSI53C1010R has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The Chained Move (CHMOV) SCRIPTS instruction, and the Wide SCSI Send (WSS) and Wide SCSI Receive (WSR) bits in the SCSI Control Two (SCNTL2) register, facilitate these situations. The Chained Block Move instruction is illustrated in Figure 2.7.

Figure 2.7 Block Move and Chained Block Move Instructions

Host Memory SCSI Bus

0x03 0x02 0x01 0x00

0x07 0x06 0x05 0x04

0x0B 0x0A 0x09 0x08

0x0F 0x0E 0x0D 0x0C

0x13 0x12 0x11 0x10

32 Bits 16 Bits

0x00

0x04

0x08

0x0C

0x10

0x04 0x03

0x06 0x05

0x09 0x07

0x0B 0x0A

0x0D 0x0C

CHMOV 5, 3 when Data-Out

Moves ﬁve bytes from address 0x03 in the host memory to the SCSI bus. Bytes 0x03, 0x04, 0x05, and 0x06 are moved, and byte 0x07 remains in the SCSI core (in the lower byte of the SODL register for asynchronous transfers, in the chain byte holding register for synchronous transfers). The stored byte is combined with the ﬁrst byte of the following CHMOVE instruction.

CHMOVE 0x5, 0x9 when Data-In

Moves ﬁve bytes from address 0x09 in the host memory to the SCSI bus. The data in address 0x09 is married with the stored data (0x07) and transferred to the SCSI bus.

SCSI Functional Description 2-55

2.2.18.1 Wide SCSI Send Bit

The WSS bit is set following a wide SCSI send operation (Data-Out for initiator mode or Data-In for target mode) when the SCSI core is holding a byte of chain data. The SCSI core holds the byte when the controller detects a partial transfer at the end of a Chained Block Move SCRIPTS instruction. This ﬂag is not set if a normal Block Move instruction is used. Under this condition, the SCSI controller does not send the low-order byte of the last partial memory transfer across the SCSI bus. Instead, the low-order byte is temporarily stored in the lower byte of the

SCSI Output Data Latch (SODL) register for asynchronous transfers or

in the chain byte holding register for synchronous transfers, and the WSS ﬂag is set.

The hardware uses the WSS bit to determine what behavior must occur at the start of the next data send transfer. If the WSS bit is set at the start of the next transfer, the ﬁrst byte (the high-order byte) of the next data send transfer is “married” with the byte of chain data. The two bytes are sent out across the bus regardless of the type of Block Move instruction (normal or chained). The WSS bit is automatically cleared when the “married” word is sent. Performing either a SCSI receive operation or any narrow transfer also clears the bit. In addition, SCRIPTS and the microprocessor can clear the WSS bit as well as use it for error detection and recovery purposes.

2.2.18.2 Wide SCSI Receive Bit

The WSR bit is set following a wide SCSI receive operation (Data-In for initiator mode or Data-Out for target mode) when the SCSI core is holding a byte of chain data. The SCSI core holds the byte when the controller detects a partial transfer at the end of a Chained Block Move instruction. Under this condition the high-order byte is not transferred out the DMA channel to memory. Instead, it is stored in the

SCSI Wide Residue (SWIDE) register and the WSR ﬂag is set.

The hardware uses the WSR bit to determine what behavior must occur at the start of the next data receive transfer. If set, the stored high-order byte may be residual data, valid data for a subsequent data transfer, or overrun data. The byte may be read as normal by starting a data receive transfer. The WSR bit is automatically cleared at the start of the next data receive

2-56 Functional Description

transfer. Performing either a SCSI send operation or any narrow transfer also clears the bit. In addition, SCRIPTS and the microprocessor can clear the WSR bit as well as use it for error detection and recovery purposes.

2.2.18.3 SWIDE Register

For wide asynchronous receive data transfers, the

SCSI Wide Residue (SWIDE) register holds the high-order byte of a

partial SCSI transfer which has not yet been transferred to memory. This stored data may be a residue byte (and therefore ignored) or it may be valid data that is transferred to memory at the beginning of the next data receive Block Move instruction.

2.2.18.4 SODL Register

For wide asynchronous send data transfers, the low-order byte of the

SCSI Output Data Latch (SODL) register holds the low-order byte of a

partial memory transfer which has not yet been transferred across the SCSI bus. This stored data is usually “married” with the ﬁrst byte of the next data send transfer, and both bytes are sent across the SCSI bus at the start of the next data send Block Move instruction.

2.2.18.5 Chained Block Move SCRIPTS Instruction

A Chained Block Move SCRIPTS instruction primarily transfers consecutive data send or data receive blocks. Using the Chained Block Move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. The behavior of the Chained Block Move instruction varies slightly for sending and receiving data.

For receive data (Data-In for the initiator or Data-Out for the target), a Chained Block Move instruction indicates that if a partial transfer occurred at the end of the instruction the WSR flag is set. The high order byte of the last SCSI transfer is stored in the SCSI Wide Residue (SWIDE) register rather than transferred to memory. The stored byte should be the first byte transferred to memory at the start of the Chained Block Move or regular Block Move data stream. Because the byte count always represents data transfers to/from memory (as opposed to/from the SCSI bus), the stored byte transferred out is one of the bytes in the count. If the WSR bit is cleared when a receive data Chained Block Move instruction is

SCSI Functional Description 2-57

executed, the data transfer occurs similar to that of the regular Block Move instruction. It is recommended that all Block Move instructions be Chained Block Moves.

For send data (Data-Out for the initiator or Data-In for the target), a Chained Block Move instruction indicates that if a partial transfer terminates, the Chained Block Move the WSS flag is set. The low-order byte should be stored in the lower byte of the SCSI Output Data Latch (SODL) register for asynchronous transfers or in the chain byte holding register for synchronous transfers and not sent across the SCSI bus. Without the Chained Block Move instruction, the last low-order byte would be sent across the SCSI bus. The starting byte count represents data bytes transferred from memory but not to the SCSI bus when a partial transfer exists. For example, if the instruction is an initiator Chained Block Move Data Out of five bytes (and WSS is not previously set), five bytes are transferred out of memory to the SCSI controller. Four bytes are transferred from the SCSI controller across the SCSI bus and one byte is temporarily stored as described, waiting to be “married” with the first byte of the next Block Move instruction. If the WSS bit is set at the start of a data send command, the first byte of the transfer is assumed to be the high-order byte and is “married” with the stored byte (low-order byte) before the two bytes are sent across the SCSI bus. It is recommended that all Block Move instructions be Chained Block Moves.

2-58 Functional Description

2.3 Parallel ROM Interface

The LSI53C1010R supports up to 1 Mbyte of external memory in binary increments from 16 Kbytes to allow the use of expansion ROM for add-in PCI cards. Both functions of the device share the ROM interface. This interface is designed for low speed operations such as downloading instruction code from ROM; it is not intended for dynamic activities such as executing instructions.

System requirements include the LSI53C1010R, two or three external 8-bit address holding registers (HCT273 or HCT374), and the appropriate memory device. The 4.7 kΩ pull-up resistors on the MAD bus require HC or HCT external components to be used. Pull-up resistors on the 8-bit bidirectional memory bus at power-up determine the memory size and speed. The LSI53C1010R senses this bus shortly after the release of the Reset signal and conﬁgures the Expansion ROM Base Address register and the memory cycle state machines for the appropriate conditions.

The LSI53C1010R supports a variety of sizes and speeds of expansion ROM. An example set of interface drawings is in

Appendix B, “External Memory Interface Diagram Examples.” The

encoding of pins MAD[3:1] allows the user to deﬁne how much external memory is available to the LSI53C1010R. Table 2.7 shows the memory space associated with the possible values of MAD[3:1]. The MAD[3:1] pins are fully described in Chapter 3, “Signal Descriptions.”

Table 2.7 Parallel ROM Support

MAD[3:1] Available Memory Space

000 16 Kbytes 001 32 Kbytes 010 64 Kbytes 011 128 Kbytes 100 256 Kbytes 101 512 Kbytes 110 1024 Kbytes 111 No external memory present, ROM interface disabled

Parallel ROM Interface 2-59

To use one of these conﬁgurations in a host adapter board design, put

4.7 kΩ pull-up resistors on the MAD pins corresponding to the available

memory space. Each MAD pin has an internal static pull-down; therefore, no external pull-down resistors are needed. For example, to connect to a 64 Kbyte external ROM, use a pull-up on MAD[2]. If the external memory interface is not used, MAD[3:1] should be pulled HIGH.

The LSI53C1010R allows the system to determine the size of the available external memory using the Expansion ROM Base Address register in the PCI conﬁguration space. For more information on how this works, refer to the PCI speciﬁcation or the Expansion ROM Base Address register description in Chapter 4, “Registers.”

MAD[0] is the slow ROM pin. When pulled up, it enables two extra clock cycles of data access time to allow use of slower memory devices. The external memory interface also supports updates to ﬂash memory.

2.4 Serial EEPROM Interface

For each SCSI function, the LSI53C1010R implements an interface permitting attachment of a serial EEPROM device to the GPIO[0] and GPIO[1] pins. There are two modes of operation relating to the serial EEPROM, the Subsystem ID register, and the Subsystem Vendor ID register for each SCSI function. These modes are programmable through the MAD[7] pin, which is sampled at power-up.

2.4.1 Default Download Mode

In this mode, MAD[7] is pulled down internally, GPIO[0] is the serial data signal (SDA) and GPIO[1] is the serial clock signal (SCL). Certain data in the serial EEPROM is automatically loaded into chip registers at power-up.

The format of the serial EEPROM data is deﬁned in Table 2.8. If the download is enabled and an EEPROM is not present or the checksum fails, the Subsystem ID and Subsystem Vendor ID registers read back all zeros. At power-up ﬁve bytes are loaded into the chip from locations 0xFB through 0xFF.

The Subsystem ID and Subsystem Vendor ID registers are read only in accordance with the PCI speciﬁcation, with a default value of all zeros if the download fails.

Note: The speed of the serial EEPROM must be 400 Kbits/s.

2-60 Functional Description

Table 2.8 Default Download Mode Serial EEPROM Data Format

Byte Name Description

0xFB SVID(0) Subsystem Vendor ID (SVID), LSB. This byte is loaded

0xFC SVID(1) Subsystem Vendor ID (SVID), MSB. This byte is loaded

0xFD SID(0) Subsystem ID (SID), LSB. This byte is loaded into the

0xFE SID(1) Subsystem ID (SID), MSB. This byte is loaded into the

0xFF CKSUM Checksum (CKSUM). This 8-bit checksum is formed by

2.4.2 No Download Mode

When MAD[7] is pulled up through an external resistor, the automatic download is disabled and data is not automatically loaded into chip registers at power-up. The Subsystem ID and Subsystem Vendor ID registers are read only, according to the PCI speciﬁcation, with a default value of 0x1000 and 0x1000, respectively.

into the least signiﬁcant byte of the Subsystem Vendor ID register in the appropriate PCI conﬁguration space at chip power-up.

into the most signiﬁcant byte of the Subsystem Vendor ID register in the appropriate PCI conﬁguration space at chip power-up.

least signiﬁcant byte of the Subsystem ID register in the appropriate PCI conﬁguration space at chip power-up.

most signiﬁcant byte of the Subsystem ID register in the appropriate PCI conﬁguration space at chip power-up.

adding, bytewise, each byte contained in locations 0xFB–0xFE to the seed value (0x55) and then taking the twos complement of the result.

2.5 Power Management

The LSI53C1010R complies with the PCI Bus Power Management Interface Speciﬁcation, Revision 1.1, in which the D0, D1, D2, and D3 are deﬁned.

D0 is the maximum powered state, and D3 is the minimum powered state. Power state D3 is further categorized as D3hot or D3cold. A function that is powered off is in the D3cold power state.

Power Management 2-61

The LSI53C1010R power states are independently controlled through two power state bits that are located in the PCI Conﬁguration Space

Power Management Control/Status (PMCSR) register, 0x44–0x45. The

power state bit settings are provided in Table 2.9.

Table 2.9 Power States

Conﬁguration Register

(0x44), Bits [1:0] Power State Function

00 D0 Maximum Power 01 D1 Disables SCSI clock 10 D2 Coma Mode 11 D3 Minimum Power

Although the PCI Bus Power Management Interface Speciﬁcation does not allow power state transitions D2 to D1, D3 to D2, or D3 to D1, the LSI53C1010R hardware places no restriction on transitions between power states.

As the device transitions from one power level to a lower one, the attributes that occur from the higher power state level are carried over into the lower power state level. For example,D1 disables the SCSI CLK. Therefore, D2 includes this attribute as well as the attributes deﬁned in the Power State D2 section. The PCI Function Power States – D0, D1, D2, and D3 – are described as follows in conjunction with each SCSI function. Power state actions are separate for each function.

2.5.1 Power State D0

Power state D0 is the maximum power state and is the power-up default state for each function. The LSI53C1010R is fully functional in this state.

2.5.2 Power State D1

Power state D1 is a lower power state than D0. A function in this state places the LSI53C1010R core in snooze mode and disables the SCSI CLK. In snooze mode, a SCSI reset does not generate an IRQ/ signal.

2-62 Functional Description

2.5.3 Power State D2

Power state D2 is a lower power state than D1. A function in this state places the LSI53C1010R core in the coma mode. The following PCI Conﬁguration Space Command register enable bits are suppressed:

• I/O Space Enable

• Memory Space Enable

• Bus Mastering Enable

• SERR/Enable

• Enable Parity Error Response

Thus, the function's memory and I/O spaces cannot be accessed, and the function cannot be a PCI bus master. Furthermore, SCSI and DMA interrupts are disabled when the function is in power state D2. If the function is changed from power state D2 to power state D1 or D0, the previous values of the PCI Command register are restored. Also, any pending interrupts before the function entered power state D2 are asserted.

2.5.4 Power State D3

Power state D3, the minimum power state, includes settings called D3hot and D3cold. D3hot allows the device to transition to D0 using software. The LSI53C1010R is considered to be in power state D3cold when power is removed from the device. D3cold can transition to D0 by applying VCCand resetting the device.

Power state D3 is a lower power level than power state D2. A function in this state places the LSI53C1010R core in the coma mode. Furthermore, the function's soft reset is continually asserted while in power state D3, which clears all pending interrupts and 3-states the SCSI bus. In addition, the function's PCI Command register is cleared. If both of the LSI53C1010R functions are placed in power state D3, the Clock Quadrupler is disabled, which results in additional power savings.

Power Management 2-63

2-64 Functional Description

Chapter 3 Signal Descriptions

This chapter describes the input and output signals of the LSI53C1010R. The chapter consists of the following sections:

• Section 3.1, “Signal Organization”

• Section 3.2, “Internal Pull-ups and Pull-downs on LSI53C1010R

Signals”

• Section 3.3, “PCI Bus Interface Signals”

• Section 3.4, “SCSI Bus Interface Signals”

• Section 3.5, “General Purpose I/O (GPIO) Signals”

• Section 3.6, “Flash ROM and Memory Interface Signals”

• Section 3.7, “Test Interface Signals”

• Section 3.8, “Power and Ground Signals”

• Section 3.9, “MAD Bus Programming”

3.1 Signal Organization

The LSI53C1010R has ﬁve major interfaces:

• PCI Interface

• SCSI Bus Interface

• GPIO

• Memory Interface

• Test Interface

Figure 3.1 illustrates the signals, their grouping, and their I/O direction. A

slash (/) at the end of a signal name indicates that it is an active LOW signal. When the slash is absent, the signal is active at a HIGH voltage.

LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller 3-1

The PCI Interface contains many functional groups of signals. The SCSI Bus Interface contains two functional groups of signals.

There are ﬁve signal type deﬁnitions:

I Input, a standard input-only signal. O Output, a standard output driver (typically a Totem Pole output). I/O Input and output (bidirectional). T/S 3-state, a bidirectional, 3-state input/output signal. S/T/S Sustained 3-state, an active LOW 3-state signal owned and driven by

one and only one agent at a time.

Figure 3.1 illustrates the signal groupings. Pinout information and package

drawings are available in Section 6.6, “Package Drawings,” on page 6-67.

3-2 Signal Descriptions

Figure 3.1 LSI53C1010R Functional Signal Grouping

PCI Bus

Interface

System

Address

and

Data

Interface

Control

Arbitration

Error

Reporting

Interrupt

SCSI

Function

GPIO

CLK ENABLE66 M66EN RST/

AD[63:0] C_BE[7:0]/ PAR PAR64

ACK64/ REQ64/ FRAME/ TRDY/ IRDY/ STOP/ DEVSEL/ IDSEL

REQ/ GNT/

PERR/ SERR/

INTA/ INTB/ ALT_INTA/ ALT_INTB/

A_GPIO0 A_GPIO1

A_GPIO2 A_GPIO3 A_GPIO4

LSI53C1010R

A_SCTRL/

B_SCTRL/

SCLK

A_SD[15:0]±

A_SDP[1:0]±

A_DIFFSENS

A_SCD±

A_SIO±

A_SMSG±

A_SREQ±

A_SACK± A_SBSY±

A_SATN±

A_SRST±

A_SSEL±

B_SD[15:0]±

B_SDP[1:0]±

B_DIFFSENS

B_SCD±

B_SIO±

B_SMSG±

B_SREQ±

B_SACK± B_SBSY±

B_SATN±

B_SRST±

B_SSEL±

SCSI Function A

SCSI Bus Interface

SCSI Function B

SCSI

Function

GPIO

Flash

ROM

and

Memory

Interface

B_GPIO0 B_GPIO1

B_GPIO2 B_GPIO3 B_GPIO4

MWE/ MCE/ MOE/ MAS0/ MAS1/ MAD[7:0]

SCAN_MODE

SCANEN

IDDTN

TEST_HSC

TEST_RST/

TCK_ CHIP

TMS_CHIP

TDI_CHIP

TDO_CHIP

Test Interface

Signal Organization 3-3

3.2 Internal Pull-ups and Pull-downs on LSI53C1010R Signals

Several LSI53C1010R signals use internal pull-ups and pull-downs.

Table 3.1 describes the conditions that enable these pull-ups and

pull-downs.

Table 3.1 LSI53C1010R Internal Pull-ups and Pull-downs

Pin Name

INTA/,INTB/,ALT_INTA/, ALT_INTB/

ENABLE66, M66EN, TCK_CHIP, TDI_CHIP, TEST_RST/, TMS_CHIP

AD[63:32], C_BE[7:4]/, PAR64

GPIO[4:0] 25 Pulled down internally. MAD[7:0] 25 Pulled down internally. SCAN_MODE,

TEST_HSC SCANEN, IDDTN 25 Pulled down internally.

1. When bit 3 of the DMA Control (DCNTL) register is set, the pad becomes a totem pole output pad and drives both HIGH and LOW.

Pull-up

Current (µA) Conditions for Pull-up

25 Pull-up enabled when the “AND-tree” mode is enabled by

25 Pulled up internally.

25 Pulled down internally.

driving TEST_RST/ LOW or when the IRQ mode bit (bit 3 of DCNTL, 0X3B) is cleared.

3-4 Signal Descriptions

3.3 PCI Bus Interface Signals

The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: System Signals; Address and Data Signals; Interface Control Signals; Arbitration Signals; Error Reporting Signals; Interrupt Signals.

3.3.1 System Signals

Table 3.2 describes the System Signals group.

Table 3.2 System Signals

Name Bump Type Strength Description

CLK AC9 I N/A Clock provides timing for all transactions on the PCI bus

ENABLE66 AC2 I N/A Enable66 enable the 66 MHz PCI operation. It sets the bit

M66EN AC5 I N/A M66EN enables the 66 MHz PCI mode. This pin is

RST/ AB10 I N/A Reset forces the PCI sequencer of each device to a known

and is an input to every PCI device and all other PCI signals are sampled on the rising edge of CLK and other timing parameters are deﬁned with respect to this edge.

in the PCI Conﬁguration Space indicating this device is 66 MHz capable. This pin has a static pull-up.

connected to the M66EN PCI signal on the PCI bus. If this signal is pulled HIGH, the 66 MHz PCI operation is enabled. This pin has a static pull-up. Note: Pulling this signal LOW does not affect the setting of the 66 MHz capable bit in the PCI Conﬁguration Space.

state. All T/S and S/T/S signals are forced to a HIGH impedance state and all internal logic is reset. The RST/ input is synchronized internally to the rising edge of CLK. To reset the device properly, the CLK input must be active while RST/ is active.

PCI Bus Interface Signals 3-5

3.3.2 Address and Data Signals

Table 3.3 describes the Address and Data Signals group.

Table 3.3 Address and Data Signals

Name Bump Type Strength Description

AD[63:0] W22, AB25, AC26,

AA25, W23, Y25, Y26, V22, U22, V24, V23, U24, V25, W26, U23, U25, T22, T23, T25, R25, R22, P22, P23, R23, P24, P25, T26, R26, M26, L26, N25, N24, AE9, AF8,AE10, AB11, AC11, AE11, AE12, AB12, AC12, AD13, AE13, AF11, AF16, AE14, AC15, AC14, AD17, AE19, AC18, AB17, AB18, AF20, AE20, AC19, AF23, AE22, AB19, AD21, AF24, AC20, AE23, AC21

C_BE[7:0]/ AA23, AC25, Y23,

AD26, AB13, AB14, AE18, AE21

T/S 8 mA PCI Physical longword Address and Data are

multiplexed on the same PCI pins. A bus transaction consists of an address phase followedby one or more data phases. During the ﬁrst clock of a transaction, AD[63:0] contain a 64-bit physical byte address. If the command is a DAC, implying a 64-bit address, AD[31:0] contain the upper 32 bits of the address during the second clock of the transaction. During subsequent clocks, AD[63:0] contain data. PCI supports both read and write bursts. AD[7:0] deﬁne the least signiﬁcant byte, and AD[63:56] deﬁne the most signiﬁcant byte.

T/S 8 mA PCI Bus Command and Byte Enables are

multiplexed on the same PCI pins. During the address phase of a transaction, C_BE[3:0]/ deﬁne the bus command. If the transaction is a DAC, C_BE[3:0]/ contain the DAC command and C_BE[7:4]/ deﬁne the bus command. C_BE[3:0]/ deﬁne the bus command during the second clock of the transaction. During the data phase, C_BE[7:0]/ are used as byte enables. The byte enables determine which byte lanes carry meaningful data: C_BE[0]/ applies to byte 0, and C_BE[7]/ to byte 7.

PAR AF19 T/S 8 mA PCI Parity is the even parity bit that protects the

3-6 Signal Descriptions

AD[31:0] and C_BE[3:0]/ lines. During the address phase, both the address and command bits are covered. During the data phase, both the data and byte enables are covered.

Avago Technologies LSI53C1010R User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 General Description

1.6.1 SCSI Performance

1.6.2 PCI Performance

1.6.3 Integration

1.6.4 Ease of Use

1.6.5 Flexibility

1.6.6 Reliability

1.6.7 Testability

2.1 PCI Functional Description

2.1.1 PCI Addressing

2.1.2 PCI Bus Commands and Functions Supported

2.1.3 Internal Arbiter

2.1.4 PCI Cache Mode

2.2 SCSI Functional Description

2.2.1 SCRIPTS Processor

2.2.2 Internal SCRIPTS RAM

2.2.4 Hardware Control of SCSI Activity LED

2.2.5 Designing an Ultra160 SCSI System

Table 2.3 New Phases on SCSI Bus

2.2.6 Prefetching SCRIPTS Instructions

2.2.7 Opcode Fetch Burst Capability

2.2.8 Load and Store Instructions

2.2.9 JTAG Boundary Scan Testing

2.2.10 Parity/CRC/AIP Options

Table 2.5 SCSI Parity Errors and Interrupts

2.2.11 DMA FIFO

2.2.12 SCSI Data Paths

2.2.13 SCSI Bus Interface

2.2.14 Select/Reselect during Selection/Reselection

2.2.15 Synchronous Operation

Table 2.6 SCF Divisor Values

2.2.16 Interrupt Handling

2.2.17 Interrupt Routing

2.2.18 Chained Block Moves

2.3 Parallel ROM Interface

Table 2.7 Parallel ROM Support

2.4 Serial EEPROM Interface

2.4.1 Default Download Mode

Table 2.8 Default Download Mode Serial EEPROM Data Format

2.4.2 No Download Mode

2.5 Power Management

Table 2.9 Power States

2.5.1 Power State D0

2.5.2 Power State D1

2.5.3 Power State D2

2.5.4 Power State D3

3.1 Signal Organization

3.2 Internal Pull-ups and Pull-downs on LSI53C1010R Signals

Table 3.1 LSI53C1010R Internal Pull-ups and Pull-downs

3.3 PCI Bus Interface Signals

3.3.1 System Signals

Table 3.2 System Signals

3.3.2 Address and Data Signals