Avago Technologies LSI53C1010 User Manual
PROGRAMMING
GUIDE
SCSI SCRIPTS™
Processors
Version 2.3
October 2000
®
S14044.A
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
DB15-000159-01, Second Edition (October 2000)
This document describes the LSI Logic Corporation SCSI SCRIPTS
™
Processors and will remain the official reference source for all revisions/releases
of this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 1995–2000 by LSI Logic Corporation. All rights reserved.
Ultra SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-20 SCSI, as documented in the SCSI-3 Fast-20 Parallel Interface standard,
X3.277-199X.
Ultra2 SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-40 SCSI, as documented in the SCSI Parallel Interface-2 standard, (SPI-2)
X3710-1142D.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, NASM, SCRIPTS, LVD Link, and TolerANT are
trademarks or registered trademarks of LSI Logic Corporation. All other brand
and product names may be trademarks of their respective companies.
ii
Audience
Preface
This book is the primary reference and programming guide for the
LSI Logic PCI to SCSI I/O Processors. It contains a complete functional
description for the LSI Logic PCI to SCSI I/O Processors and includes
complete physical and electrical specifications for the LSI Logic PCI to
SCSI I/O Processors.
This manual is written for users who are familiar with the SCSI and PCI
specifications, and have a working knowledge of computer architectures
and programming. It is specifically designed for use with programming
the LSI Logic SCSI SCRIPTS™ processor in the following chip families:
• LSI53C7XX
Organization
• LSI53C8XX
• LSI53C10XX (up to the LSI53C1010 and LSI53C1010R)
This document has the following chapters and appendixes:
• Chapter 1, Using the Programming Guide, introduces the
SCRIPTS processor features and functions, and the parts of the PCI
to SCSI system that are involved in operating the chip.
• Chapter 2, Programming with SCRIPTS, describes the SCRIPTS
processor and programming language in depth, including how
SCRIPTS programs are integrated with “C” code to execute SCSI
commands.
• Chapter 3, The SCSI SCRIPTS Processor Instruction Set,
describes the SCRIPTS processor instruction set, along with detailed
Preface iii
functional descriptions and usage guidelines for all of the instructions
supported.
• Chapter 4, Using the LSI Logic Assembler NASM™, describes
use and operation of the LSI Logic Assembler (NASM).
• Chapter 5, The NASM Output File, describes the LSI Logic
Assembler (NASM) output file.
• Chapter 6, Using the Registers to Control Chip Operations,
contains functional and address information on the
LSI53C7XX/8XX/10XX family chips register set.
• Chapter 7, Integrating SCRIPTS Programs into “C” Language
Drivers, illustrates the relationship between the SCRIPTS program
and the “C” language device driver.
• Chapter 8, Writing Device Drivers with SCRIPTS, addresses
specific kinds of driver applications, with code samples for all
applications discussed.
• Chapter 9, SCRIPTS Programming Topics, addresses specific
kinds of driver applications, with code samples for all applications
discussed.
• Chapter 10, Multithreaded I/O, contains guidelines for writing
SCRIPTS for multithreaded applications.
• Chapter 11, Using the SCRIPTS Processor in Target
Applications, provides guidelines that are specific to using the
SCRIPTS processor in a target device.
• Chapter 12, Debugging the SCRIPTS Processor, provides
information on debugging SCRIPTS programs.
• Chapter 13, New SCRIPTS Processor Features,provides
information on the new 64-bit features of the latest version of this
chip family.
• Appendix A, NASM Error Messages,providesalistofNASMerror
messages.
• Appendix B, Multithreaded SCRIPTS Example,providesexample
SCRIPTS code.
• Appendix C, Glossary of Terms and Abbreviations, provides
definitions of terms and abbreviations.
iv Preface
Related Publications
LSI53C770 SCSI I/O Processor with Ultra SCSI Data Manual,
Version 2.0, LSI Logic Corporation, Order Number T18962I
LSI53C810A PCI-SCSI I/O Processor Data Manual, Version 2.0,
LSI Logic Corporation, Order Number T07962I
LSI53C815 PCI-SCSI I/O Processor with Local ROM Interface
Data Manual, Version 2.0, LSI Logic Corporation, Order Number T10962I
LSI53C825A/825AE PCI-SCSI I/O Processor Data Manual, Version 3.0,
LSI Logic Corporation, Order Number T40937I
LSI53C860 PCI-Ultra SCSI I/O Processor Data Manual, Version 2.0,
LSI Logic Corporation, Order Number T09962I
LSI53C875/875E PCI-Ultra SCSI I/O Processor Data Manual,
Version 4.0, LSI Logic Corporation, Order Number T42984I
LSI53C895 PCI to Ultra2 SCSI I/O Processor with LVD Link™ Universal
Transceivers Technical Manual, Version 3.1, LSI Logic Corporation,
Order Number S14030
LSI53C895A PCI to Ultra2 SCSI Controller Technical Manual,
Version 2.2, LSI Logic Corporation, Order Number S14028.B
LSI53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller
Technical Manual, Version 3.1, LSI Logic Corporation,
Order Number S14015.B
LSI53C1000 PCI to Ultra3 SCSI Controller Technical Manual,
Version 2.0, LSI Logic Corporation, Order Number S14050
LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual,
Version 1.0, LSI Logic Corporation, Order Number S14052
LSI53C1010-33 PCI to Dual Channel Ultra3 SCSI Multifunction
Controller Technical Manual, Version 3.1, LSI Logic Corporation,
Order Number S14025.C
LSI53C1010-66 PCI to Dual Channel Ultra3 SCSI Multifunction
Controller Technical Manual, Version 2.0, LSI Logic Corporation,
Order Number S14049
Preface v
LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction
Controller Technical Manual, Version 1.0, LSI Logic Corporation,
Order Number S14053
Conventions Used in This Manual
The following is a list of notational conventions used throughout
this programming guide:
Notation Example Meaning and Use
square braces
[]
courier font
All Caps
Curly braces
{}
{} “...”
|
\
CALL [REL] Addre ss,
[{IF | WHEN} [NOT] CARRY]
program.exe
JUMP [REL] Addre ss,
[{IF | WHEN} [NOT] CARRY]
SELECT [ATN] {FROM Address |
ID}, [REL] Addre ss
SET {ACK|ATN|TAR GET|CARRY }
[and {ACK|ATN|TA RGET|CARR Y}...]
INTFLY int_value ,
[{IF | WHEN} [NOT] CARRY]
RELATIVE baselab el \
Optional items in instruction examples.
Used for code samples, file names,
command line information, prompts,etc.
that appear in body text.
Keywords.
Choosebetweenitems enclosed in curly
braces.
The character enclosed in the curly
braces can be repeated as often as
desired.
OR, select one item from a list.
Line continuation.
vi Preface
Revision Record
Revision Date Remarks
2.0 8/96 Initial release.
2.1 6/97 Added chapter on programming multifunction controllers.
2.2 6/00 Miscellaneous updates/format changes.
2.3 10/00 All product names changed from SYM to LSI.
Preface vii
viii Preface
Contents
Chapter 1 Using the Programming Guide
1.1 Product Overview 1-1
1.2 Benefits of Ultra, Ultra2, and Ultra3 SCSI 1-7
1.3 System Overview 1-8
Chapter 2 Programming with SCRIPTS
2.1 The SCSI SCRIPTS Processor 2-1
2.2 SCRIPTS and the SCSI Bus Phases 2-2
2.3 Assembling SCSI SCRIPTS 2-3
2.4 Using SCSI SCRIPTS 2-6
2.4.1 SCRIPTS Data Sizes 2-6
2.4.2 SCSI SCRIPTS Language Elements 2-6
2.4.3 SCSI SCRIPTS Expressions 2-7
2.4.4 SCSI SCRIPTS Keywords 2-7
2.5 Big and Little Endian Byte Addressing 2-8
2.5.1 SCRIPTS Instruction Sequence 2-8
2.5.2 Operating Register Access from Firmware 2-9
2.5.3 Operating Register Access from SCRIPTS
Routines 2-9
2.5.4 User Data Byte Ordering 2-9
Chapter 3 The SCSI SCRIPTS Processor Instruction Set
3.1 Overview of SCRIPTS Instructions 3-1
3.1.1 I/O Instructions 3-1
3.1.2 Memory Move Instructions 3-2
3.1.3 Transfer Control Instructions 3-2
3.1.4 Read/Write Instructions 3-3
3.1.5 Block Move Instructions 3-3
3.1.6 Load and Store Instructions 3-3
Contents ix
3.2 Instruction Descriptions 3-4
3.2.1 CALL 3-5
3.2.2 CHMOV 3-10
3.2.3 CLEAR 3-14
3.2.4 DISCONNECT 3-16
3.2.5 INT 3-17
3.2.6 INTFLY 3-21
3.2.7 JUMP 3-27
3.2.8 JUMP 64 3-32
3.2.9 LOAD 3-37
3.2.10 LOAD64 3-40
3.2.11 MOVE 3-42
3.2.12 MOVE MEMORY 3-46
3.2.13 MOVE REGISTER 3-48
3.2.14 NOP 3-53
3.2.15 RESELECT 3-54
3.2.16 RETURN 3-58
3.2.17 SELECT 3-62
3.2.18 SET 3-64
3.2.19 STORE 3-66
3.2.20 WAIT DISCONNECT 3-68
3.2.21 WAIT SELECT 3-69
3.2.22 WAIT RESELECT 3-71
3.3 Instruction Examples 3-73
3.3.1 I/O Instruction Example 3-74
3.3.2 Memory Move Instruction Example 3-74
3.3.3 Transfer Control Instruction Example 3-76
3.3.4 Read/Write Instruction Example 3-77
3.3.5 Block Move Instruction Example 3-78
3.3.6 Load/Store Instruction Example 3-79
Chapter 4 Using the LSI Logic Assembler NASM™
4.1 Overview 4-1
4.2 Using NASM 4-2
4.3 Command Line Options 4-3
4.3.1 Architecture 4-3
4.3.2 Binary Cross Reference Values 4-4
xContents
4.3.3 Error Listing File 4-4
4.3.4 Listing File 4-4
4.3.5 Output File 4-4
4.3.6 Partial “C” Source 4-4
4.3.7 .BIN Output 4-5
4.3.8 Omit Termination Record 4-5
4.3.9 Verbose Messages 4-5
4.3.10 Patch Offsets 4-6
4.4 Example Assembler Command Lines 4-6
4.5 How NASM Parses SCRIPTS Files 4-6
4.6 Assembler Declarative Keywords 4-7
4.6.1 ABSOLUTE 4-8
4.6.2 ARCH 4-8
4.6.3 ENTRY 4-9
4.6.4 EXTERN 4-9
4.6.5 PASS 4-10
4.6.6 PROC 4-10
4.6.7 RELATIVE 4-11
4.6.8 TABLE 4-12
4.7 Conditional Keywords 4-14
4.7.1 IF 4-14
4.7.2 WHEN 4-14
4.8 Logical Keywords 4-14
4.8.1 NOT 4-15
4.8.2 AND 4-15
4.8.3 OR 4-15
4.9 Flag Fields 4-15
4.9.1 ACK 4-15
4.9.2 ATN 4-15
4.9.3 TARGET 4-16
4.9.4 CARRY 4-16
4.10 Qualifier Keywords 4-16
4.10.1 DSAREL 4-16
4.10.2 FROM 4-16
4.10.3 MASK 4-16
4.10.4 MEMORY 4-17
4.10.5 PTR 4-17
4.10.6 REG 4-17
Contents xi
4.10.7 REL 4-17
4.10.8 TO 4-17
4.10.9 WITH 4-17
4.10.10 NOFLUSH 4-17
4.11 Other Keywords 4-18
4.11.1 Action Keywords 4-18
4.11.2 SCSI Phases 4-18
4.11.3 Register Names 4-18
Chapter 5 The NASM Output File
5.1 NASM Output Overview 5-1
5.2 NASM Output File Examples 5-2
5.2.1 SCRIPTS Array 5-3
5.2.2 External 5-5
5.2.3 Relative 5-7
5.2.4 Entry 5-9
5.2.5 Label Patches 5-9
5.2.6 Absolute 5-10
5.2.7 Termination Record 5-11
Chapter 6 Using the Registers to Control Chip Operations
6.1 Overview 6-1
6.2 SCSI Registers 6-2
6.3 DMA Registers 6-4
6.4 SCRIPTS Registers 6-5
6.5 64-Bit SCRIPTS Selector Registers 6-6
6.6 Interrupt Registers 6-7
6.7 Phase Mismatch Registers 6-8
6.8 Test and Miscellaneous Registers 6-9
6.9 General Purpose Registers 6-11
6.10 Register Initialization 6-11
Chapter 7 Integrating SCRIPTS Programs into “C” Language Drivers
7.1 Initializing the SCRIPTS Processor 7-1
7.1.1 Reset 7-3
7.1.2 Table Indirect Operations 7-3
7.2 Patching 7-7
xii Contents
7.2.1 EXTERN Buffers 7-8
7.2.2 RELATIVE Buffers 7-8
7.2.3 ABSOLUTE Values 7-9
7.2.4 Buffer Addresses 7-9
7.2.5 Byte Counts 7-9
7.2.6 Absolute JUMP/CALL Addresses 7-10
7.2.7 Entry Locations 7-10
7.2.8 Self-Modifying SCRIPTS Code 7-11
7.3 Running a SCRIPTS Program 7-12
Chapter 8 Writing Device Drivers with SCRIPTS
8.1 Device Driver Overview 8-1
8.2 Command Block 8-4
8.3 Power Up Example 8-4
8.4 I/O Request Process 8-5
8.5 How to Write a Device Driver with SCRIPTS 8-6
8.6 Table Indirect Addressing 8-7
8.6.1 Block Move Instructions 8-8
8.6.2 Select/Reselect Instructions 8-9
8.6.3 Defining a Table 8-10
8.7 Relative Addressing 8-11
Chapter 9 SCRIPTS Programming Topics
9.1 Scatter/Gather Operations 9-1
9.2 Loopback Mode 9-4
9.2.1 Loopback Example – Selection 9-5
9.3 Byte Recovery on Target Disconnect 9-9
9.3.1 Saving the Processor State 9-10
9.3.2 Updating the SCRIPTS Program 9-13
9.3.3 Cleaning Up 9-13
9.3.4 Example Byte Recovery Code 9-13
9.4 Synchronous Negotiation and Transf er 9-18
9.5 Interrupt Handling 9-19
9.5.1 Polling and Hardware Interrupts 9-19
9.5.2 Registers 9-20
9.5.3 Fatal vs. Nonfatal Interrupts 9-22
9.5.4 Masking 9-23
Contents xiii
9.5.5 Stacked Interrupts 9-24
9.5.6 Halting in an Orderly Fashion 9-24
9.5.7 Sample Interrupt Service Routine 9-25
9.6 Migrating Existing Software to Ultra, Ultra2, and
Ultra3 SCSI 9-26
9.6.1 Clock Divider Bits 9-27
9.6.2 Ultra Enable Bit 9-28
9.6.3 Loading the New Register Values 9-28
9.6.4 Negotiating Synchronous Transfers 9-28
9.6.5 Using the SCSI Clock Doubler 9-29
9.6.6 Using the SCSI Clock Quadrupler 9-29
9.7 Using the SCRIPTS RAM 9-30
9.7.1 Loading SCRIPTS RAM 9-30
9.7.2 Programming Techniques when Using
SCRIPTS RAM 9-31
9.7.3 Patching Internal and External SCRIPTS
Programs 9-37
Chapter 10 Multithreaded I/O
10.1 Overview 10-1
10.2 Multithreaded Operations Flow 10-2
10.3 SCRIPTS Areas 10-4
10.4 Multithreaded SCRIPTS Example 10-4
10.5 Using the SIGP Bit to Abort an Instruction 10-10
10.6 I/O Completion 10-12
Chapter 11 Using the SCRIPTS Processor in Target Applications
11.1 SCSI and Target SCRIPTS Protocol 11-1
11.2 Registers Used for Target Operation 11-3
11.3 Using SCRIPTS for Target Operation 11-3
11.3.1 Sample Target Operation SCRIPTS Program 11-4
11.4 Synchronous Negotiation by a Target Device 11-16
Chapter 12 Debugging the SCRIPTS Processor
12.1 Chip Debugging Guidelines 12-1
12.2 Register Used for Debugging 12-3
xiv Contents
Chapter 13 New SCRIPTS Processor Features
13.1 Improved FIFO Flushing 13-1
13.2 Larger FIFO 13-2
13.3 New ISTAT Registers 13-2
13.4 New Scratch Registers 13-2
13.5 New Load/Store Feature 13-2
13.6 Phase Mismatch Handling 13-3
13.6.1 Control Bits 13-3
13.6.2 Registers 13-4
13.6.3 SCRIPTS Example 13-5
13.7 64-Bit SCRIPTS Addressing 13-6
13.7.1 Control Bits 13-6
13.7.2 Block Move 13-7
13.7.3 Direct Block Move 13-7
13.7.4 Mode 0 Table Indirect Block Move 13-7
13.7.5 Mode 1 Table Indirect Block Move 13-8
13.7.6 Table Indirect Block Move Summary 13-10
13.7.7 LSI53C1010/LSI53C1010R 13-10
Appendix A NASM Error Messages
Appendix B Multithreaded SCRIPTS Example
Appendix C Glossary of Terms and Abbreviations
Index
Customer Feedback
Figures
1.1 Single Channel Block Diagram 1-6
1.2 Dual Channel Block Diagram 1-6
1.3 Typical SCRIPTS Operation 1-9
2.1 Overview of Assembling SCSI SCRIPTS 2-5
Contents xv
3.1 CALL Format 3-6
3.2 Use of the Mask Keyword 3-9
3.3 CHMOV Format 3-11
3.4 CLEAR Format 3-15
3.5 DISCONNECT Format 3-16
3.6 INT Format 3-18
3.7 INTFLY Format 3-23
3.8 JUMP Format 3-28
3.9 JUMP 64 Format 3-34
3.10 LOAD Format 3-38
3.11 MOVE Format 3-43
3.12 MOVE MEMORY Format 3-47
3.13 MOVE REGISTER Format 3-50
3.14 NOP Format 3-54
3.15 RESELECT Format 3-55
3.16 Reselection Instruction 3-57
3.17 RETURN Format 3-59
3.18 SELECT Format 3-63
3.19 SET Format 3-65
3.20 STORE Format 3-67
3.21 WAIT DISCONNECT Format 3-69
3.22 WAIT SELECT Format 3-70
3.23 WAIT RESELECT Format 3-71
3.24 WAIT RESELECT and the SIGP Bit 3-73
3.25 I/O Instruction Type 3-74
3.26 Memory Move Instruction Part 1 3-75
3.27 Memory Move Instruction Part 2 3-76
3.28 Transfer Control Instruction 3-77
3.29 Read/Write Instruction Example 3-78
3.30 Block Move Instruction 3-79
3.31 Load/Store Instruction 3-80
5.1 Sample SCRIPTS Program 5-2
7.1 Accessing I/O Mapped Registers 7-1
7.2 Resetting the SCRIPTS Processor 7-3
7.3 SCRIPTS Table Declaration 7-4
7.4 Creating Table Indirect Entry Offsets 7-4
7.5 Data Structure and Type Definition 7-5
7.6 Data Structure and Type Definition 7-6
xvi Contents
7.7 Creating Buffers 7-7
7.8 Self-Modifying Code 7-11
7.9 General.ss SCRIPTS Source File 7-12
7.10 General.out NASM Output File 7-16
8.1 The Role of the SCSI Device Drivers 8-2
8.2 SCSI Device Driver Layers 8-3
8.3 Power Up Examples 8-5
8.4 I/O Operation 8-6
8.5 Table Indirect Addressing 8-10
8.6 Table Definitions 8-11
9.1 Scatter/Gather Operation 9-2
9.2 Alternate Scatter/Gather Operation 9-4
9.3 Loopback Mode 9-6
9.4 Target Operation 9-7
9.5 Byte Transfer 9-8
9.6 Loopback Mode Selection Procedure 9-9
9.7 SCRIPTS Sequence to Move Data 9-14
9.8 Example Function for Handling DATA IN Phase
Mismatch Interrupts 9-15
9.9 Example Function for Handling DATA OUT Phase
Mismatch Interrupts 9-16
9.10 SELECT FROM Example Code 9-19
9.11 Storing Data Structures in SCRIPTS RAM 9-31
9.12 External Script (SCRIPTS.LIS file) 9-33
9.13 External Script (SCRIPTS.OUT file) 9-34
9.14 Internal Script (SCRIPTS.LIS file) 9-34
9.15 Internal SCRIPTS Program (SCRIPTS.OUT file) 9-36
9.16 Patching Routine 9-38
10.1 Multithreaded System Operation 10-2
10.2 Multithreaded SCRIPTS Operational Flow 10-3
10.3 Multithreaded SCRIPTS Example Step 1 10-5
10.4 Multithreaded SCRIPTS Example Step 2 10-6
10.5 Multithreaded SCRIPTS Example Step 3 10-7
10.6 Multithreaded SCRIPTS Example Step 6 10-7
10.7 Multithreaded SCRIPTS Example Step 10 10-9
10.8 Multithreaded SCRIPTS Example Step 11 10-9
10.9 Multithreaded SCRIPTS Example Step 13 10-10
10.10 Sample SIGP Code 10-10
Contents xvii
11.1 SCRIPTS Source Code–Comments 11-4
11.2 SCRIPTS Source Code–ABSOLUTE Declarations 11-5
11.3 SCRIPTS Source Code–EXTERN Variables 11-5
11.4 SCRIPTS Source Code–TABLE 11-6
11.5 SCRIPTS Source Code–ENTRY Declarations 11-7
11.6 SCRIPTS Source Code–wait_select Label 11-7
11.7 SCRIPTS Source Code–CDB Functions 11-8
11.8 SCRIPTS Source Code–Message Out Phase 11-8
11.9 SCRIPTS Source Code–Extended Message 11-9
11.10 SCRIPTS Source Code–Synchronous Negotiation 11-9
11.11 SCRIPTS Source Code–Wide Negotiation 11-9
11.12 SCRIPTS Source Code–Return Negotiation 11-9
11.13 SCRIPTS Source Code–Recovery Message 11-10
11.14 SCRIPTS Source Code–Test Unit Ready 11-10
11.15 SCRIPTS Source Code–stopped_busy_tur Command 11-10
11.16 SCRIPTS Source Code–Request Sense 11-11
11.17 SCRIPTS Source Code–Read Label 11-12
11.18 SCRIPTS Source Code–read_disconnect Label 11-12
11.19 SCRIPTS Source Code–read_reconnect Label 11-13
11.20 SCRIPTS Source Code–Write 11-13
11.21 SCRIPTS Source Code–write_disconnect Label 11-13
11.22 SCRIPTS Source Code–write_reconnect Label 11-14
11.23 SCRIPTS Source Code–reserve_unit Label 11-14
11.24 SCRIPTS Source Code–release_unit Command 11-14
11.25 SCRIPTS Source Code–abort Label 11-15
11.26 SCRIPTS Source Code–stopped_busy_wait_select
Command 11-15
13.1 64-Bit Direct Block Move Format 13-7
13.2 Index Mode 1 Table Entry Format 13-9
Tables
1.1 Features and Functions of LSI53C7XX/8XX/10XX
1.2 Features and Functions of LSI53C7XX/8XX/10XX
2.1 SCSI Protocol and SCRIPTS Instructions 2-2
2.2 Data Sizes 2-6
2.3 SCSI SCRIPTS Language Elements 2-6
xviii Contents
Family Chips (part 1) 1-2
Family Chips (part 2) 1-3
2.4 Arithmetic Operators 2-7
2.5 Bitwise Operators 2-7
2.6 Big and Little Endian Byte Addressing 2-8
3.1 Opcode Bit Options 3-2
3.2 Read/Write Instructions 3-3
3.3 SCRIPTS Instructions Set 3-4
3.4 SCSI Phase Bit V alues (CALL Format) 3-7
3.5 SCSI Phase Bit Values (CHMO V Format) 3-12
3.6 SCSI Phase Bit Values (INT Format) 3-18
3.7 SCSI Phase Bit Values (INTFLY Format) 3-23
3.8 SCSI Phase Bit Values (JUMP Format) 3-29
3.9 SCSI Phase Bit Values (JUMP 64 Format) 3-35
3.10 Register Address Field Definitions (LOAD Format) 3-39
3.11 LOAD64 Format 3-41
3.12 Register Address Field Definitions (LOAD64 Format) 3-42
3.13 SCSI Phase Bit Values (MOVE Format) 3-44
3.14 SCSI Phase Bit Values (RETURN Format) 3-59
3.15 Low Order Bit Options 3-68
4.1 Keywords 4-7
5.1 Relationship Between Entry and PROC Statements
and Output File 5-5
6.1 SCSI Registers 6-2
6.2 DMA Registers 6-5
6.3 SCRIPTS Registers 6-6
6.4 64-Bit Selector Registers 6-6
6.5 Interrupt Registers 6-7
6.6 Phase Mismatch Registers 6-9
6.7 Test and Miscellaneous Registers 6-10
6.8 General Purpose Registers 6-11
6.9 LSI53C815/810A/860 Startup Bits 6-12
6.10 LSI53C825A/875/876/885/895/895A/896/10XX
Startup Bits 6-14
8.1 Data Structure 8-9
8.2 I/O Data Structure 8-9
11.1 SCSI Protocol and Target SCRIPTS Instructions 11-2
11.2 Register Bits Used for Target Operation 11-3
13.1 ISTAT1 Register 13-2
13.2 Index Mapping 13-8
Contents xix
13.3 Table Indirect BMOV Upper 32-Bit Address Locations 13-10
A.1 NASM Error Messages A-1
A.2 Fatal Errors A-13
A.3 Warnings A-14
xx Contents
Chapter 1
Using the
Programming Guide
This chapter provides an overview of the LSI Logic SCSI SCRIPTS
processor. It also provides brief descriptions for some of the chips
containing the processor and their features. The chapter contains the
following sections:
• Section 1.1, “Product Overview”, page 1-1
• Section 1.2, “Benefits of Ultra, Ultra2, and Ultra3 SCSI”, page 1-7
• Section 1.3, “System Overview”, page 1-8
1.1 Product Overview
The LSI Logic SCSI SCRIPTS processor is based on the LSI53C7XX
SCSI I/O Processor family architecture, with a host interface to the
Peripheral Component Interconnect (PCI) bus. The SCRIPTS processor
connects to the PCI bus without glue logic.
Several LSI Logic product families contain the SCRIPTS processor.
• LSI53C7XX
• LSI53C8XX
• LSI53C10XX (up to the LSI53C1010 and LSI53C1010R)
Tables 1.1 and 1.2 list currently available chips using the SCRIPTS
processor and their basic specifications. More detailed information is
available in the respective chip technical manuals, listed in Related
Publications on page v.
SCSI SCRIPTS Processors 1-1
Table 1.1 Features and Functions of LSI53C7XX/8XX/10XX Family Chips (part 1)
LSI53C770 LSI53C810A LSI53C860 LSI53C815
Maximum Transfer
Rate
DMA FIFO Size
(bytes)
Synchronous
Offset (levels)
SCRIPTS RAM 4 Kbytes None None None 4 Kbytes
Differential SCSI No No No No HVD
Wide SCSI Yes No No No Yes
External Memory
Interface
Instruction Prefetch Yes Yes Yes No Y es
Load/Store
Instructions
20 Mbytes/s
synchronous
(with Wide
SCSI)
96 80 80 64 88 or 536
16 8 8 8 16
No No No Yes Yes
No Yes Y es No Yes
5Mbytes/s
asynchronous
10 Mbytes/s
synchronous
5Mbytes/s
asynchronous
20 Mbytes/s
synchronous
(with Ultra
SCSI)
5Mbytes/s
asynchronous
10 Mbytes/s
synchronous
LSI53C825A
LSI53C825AJ
10 Mbytes/s
asynchronous
20 Mbytes/s
synchronous
Enhanced Move
Register Capability
SCSI Selected As
ID Bits
Number of 32-bit
SCRATCH
Registers
PCI Caching No Yes Yes No Yes
Selectable IRQ
Disable
Big/Little Endian
Support
PCI Data Bus N/A 32-Bit 32-Bit 32-Bit 32-Bit
1-2 Using the Programming Guide
No No No No Yes
No Yes Y es No Yes
12 2 2 10
No Yes Y es No Yes
Big or Little
Endian
Little Endian Little Endian Big or Little
Endian
Big or Little
Endian (except
LSI53C825AJ)
Table 1.1 Features and Functions of LSI53C7XX/8XX/10XX Family Chips (part 1) (Cont.)
LSI53C770 LSI53C810A LSI53C860 LSI53C815
PCI Addressing N/A 32-Bit 32-Bit 32-Bit 32-Bit
Package 208 PQFP 100 PQFP 100 PQFP 128 PQFP 160 PQFP
Table 1.2 Features and Functions of LSI53C7XX/8XX/10XX Family Chips (part 2)
LSI53C875
LSI53C875A
LSI53C875J
Maximum
Transfer Rate
DMA FIFO
Size (bytes)
LSI53C875JB
LSI53C875N
10 Mbytes/s
asynchronous
40 Mbytes/s
synchronous
(with Ultra
SCSI)
88 or 536 112 or 816
LSI53C895
LSI53C895A LSI53C896
10 Mbytes/s
asynchronous
80 Mbytes/s
synchronous
(with Ultra2
SCSI)
(LSI53C895)
112 or 944
(LSI53C895A)
10 Mbytes/s
asynchronous
80 Mbytes/s
synchronous
per channel
for
160 Mbytes/s
112 or 944 896 to 920 896 to 920
LSI53C1000
LSI53C1000R
10 Mbytes/s
asynchronous
160 Mbytes/s
synchronous
(with Ultra2
SCSI)
LSI53C825A
LSI53C825AJ
LSI53C1010
LSI53C1010R
10 Mbytes/s
asynchronous
160 Mbytes/s
synchronous
per channel
for
320 Mbytes/s
Synchronous
Offset (levels)
SCRIPTS RAM 4 Kbytes 4 Kbytes
Differential
SCSI
Wide SCSI Yes Yes Yes
External
Memory
Interface
16 31 31 62 62
(LSI53C895)
8Kbytes
(LSI53C895A)
High Voltage
Differential
(HVD)
Yes Yes Yes Yes Y es
Product Overview 1-3
Low Voltage
Differential
(LVD) and HVD
8Kbytes 8Kbytes 8Kbytes
LVD and HVD LVD and HVD LVD and HVD
Dual Channel
Yes Yes
Dual Channel
Table 1.2 Features and Functions of LSI53C7XX/8XX/10XX Family Chips (part 2) (Cont.)
LSI53C875
LSI53C875A
LSI53C875J
LSI53C875JB
LSI53C875N
LSI53C895
LSI53C895A LSI53C896
LSI53C1000
LSI53C1000R
LSI53C1010
LSI53C1010R
Instruction
Prefetch
Load/Store
Instructions
Enhanced
Move Register
Capability
SCSI Selected
As ID Bits
Number of
32-bit
SCRATCH
Register
PCI Caching Yes Yes Yes Yes Yes
SelectableIRQ
Disable
Big/Little
Endian Support
PCI Data Bus 32-Bit 32-Bit 64-Bit 64-Bit 64-Bit
Yes Yes Yes Yes Y es
Yes Yes Yes Yes Y es
Yes Yes Yes Yes Y es
Yes Yes Yes Yes Y es
10 10 (LSI53C895)
Yes Yes Yes Yes Y es
Big or Little
Endian (except
LSI53C875J,
LSI53C875JB)
18
(LSI53C895A)
LSI53C895 Big
or Little Endian
LSI53C895A
Little Endian
18 18 18
Little Endian Little Endian Little Endian
PCI Addressing 32-Bit 32-Bit
(LSI53C895)
64-Bit
(LSI53C895A)
Package 160 PQFP,
169 BGA,
208 PQFP
208 PQFP 329 BGA 329 BGA 329 BGA
The LSI Logic SCSI SCRIPTS processors are the first products to
concentrate the functions of an intelligent SCSI adapter board onto a
single chip. These products integrate a high-performance SCSI core, a
PCI bus master DMA core, and the SCSI SCRIPTS processor to meet
1-4 Using the Programming Guide
64-Bit 64-Bit 64-Bit
the flexibility requirements of SCSI-3 and future SCSI standards. It
executes multithreaded I/O algorithms with minimum host processor
intervention, reducing the protocol overhead required for SCSI operations
to as little as one interrupt per SCSI I/O. The SCRIPTS language, a high
level instruction set, provides complete programmability of I/O operations
and supports the flexibility needed for multithreaded I/O algorithms.
SCRIPTS provides:
• Phase sequencing without processor intervention
• Automatic bus arbitration
• Data or phase comparison for independent SCSI algorithm decisions
• DMA interface control
All LSI53C7XX/8XX/10XX family chips are also supported by LSI Logic
software for connecting SCSI devices. This includes BIOS support for
LSI Logic SCSI processors and drivers for most types of SCSI
peripherals under the major operating systems. These chips also feature:
• On-chip Single-Ended (SE) drivers
• Synchronous and asynchronous transfer capabilities
• LSI Logic T olerANT
®
driver and receiver technology
• Bus mastering
• Automatic selection/reselection time-outs
• 32-bit memory addressing
• 32-bit data bus
• PCI bursting
Newer chips, including the LSI53C895, LSI53C895A, LSI53C896,
LSI53C1000, LSI53C1010, LSI53C1010R, and LSI53C1000R also have
these features:
• On-chip LVD
• 64-bit memory addressing
• 64-bit data bus
Note:
Product Overview 1-5
For specific information on the features and functions of the
various chips supporting SCRIPTS, refer to their respective
technical manuals. You must have the appropriate technical
manual in order to effectively program SCRIPTS for each
chip.
Figures 1.1 and 1.2 are block diagrams of the single and dual channel
LSI Logic chips that support SCRIPTS, with a map of SCSI data and
control paths through the chips.
Figure 1.1 Single Channel Block Diagram
VDD
PCI Bus
Channel Chip
External Memory
(When Supported)
External Oscillator
or Optimal Internal
Connection to
PCI Bus Clock
CPU baseboard
VSS
Single
SCLK
CPU Box
Figure 1 .2 Dual Channel Block Diagram
VDD
PCI Bus
Channel Chip
External Memory
(When Supported)
External Oscillator
or Optimal Internal
Connection to
PCI Bus Clock
CPU baseboard
VSS
Dual
SCLK
SCSI Term ConnectionSCSI Connection
SCSI Bus
Peripheral
Bulkhead
SCSI Term ConnectionSCSI Connection
SCSI Bus
Peripheral
SCSI Term ConnectionSCSI Connection
SCSI Bus
Peripheral
Bulkhead
CPU Box
1-6 Using the Programming Guide
1.2 Benefits of Ultra, Ultra2, and Ultra3 SCSI
Ultra SCSI is an extension of the SCSI-3 standard that expands the
bandwidth of the SCSI bus and allows faster synchronous SCSI transfer
rates. When enabled, Ultra SCSI performs 20 megatransfers per second,
which results in approximately doubling the synchronous transfer rates of
Fast SCSI-2. The LSI53C860 and LSI53C875 can perform 8-bit or
16-bit Ultra SCSI synchronous transfers as fast as 20 Mbytes/s or
40 Mbytes/s.
Ultra2 SCSI extends SCSI performance beyond Ultra SCSI rates, up to
40 megatransfers per second. It also defines a new physical interface,
LVD SCSI, that retains the reliability of HVD SCSI while allowing a longer
cable and more devices on the bus than Ultra SCSI. The LSI53C895 can
perform 16-bit, Ultra2 SCSI synchronous transfers as fast as
80 Mbytes/s.
Ultra3 SCSI delivers data up to two times faster than Ultra2 SCSI.
Ultra3 SCSI is an extension of the SPI-3 draft standard. When enabled,
Ultra3 SCSI performs 80 megatransfers per second. Ultra3 data transfer
speed is accomplished using Double Transition (DT) clocking. Data is
clocked on both rising and falling edges of the request and acknowledge
signals, doubling data transfer speeds without increasing the clock rate.
The advantages of Ultra/Ultra2/Ultra3 SCSI are most noticeable in
heavily loaded systems, or large block size applications such as video on
demand and image processing. Not only does it significantly improve
SCSI bandwidth, it also preserves existing hardware and software
investments. LSI Logic Ultra/Ultra2/Ultra3 SCSI chips are all compatible
with Fast SCSI software; the only changes required are to enable the
chip to negotiate for the faster synchronous transfer rates.
Some changes to existing cabling or system designs may be needed to
maintain signal integrity at Ultra SCSI synchronous transfer rates. These
design issues are discussed in the chip technical manuals.
Benefits of Ultra, Ultra2, and Ultra3 SCSI 1-7
1.3 System Overview
To execute SCSI SCRIPTS programs, only a SCSI SCRIPTS starting
address is required. All subsequent instructions are fetched from external
memory or internal SCRIPTS RAM (when supported). Depending on the
chip, up to eight Dwords at a time are fetched across the DMA interface
and loaded into the internal chip registers. When the chip is operating at
its highest frequency, instruction fetching and decoding take as little as
500 ns. The chip fetches instructions until a SCRIPTS interrupt occurs or
until an external, unexpected event (such as a hardware error) causes
an interrupt. The full set of SCSI features in the instruction set allows
re-entry to the algorithm at any point. This high level interface can be
used for both normal operation and exception conditions.
A typical SCRIPTS operation is illustrated in Figure 1.3. Before SCRIPTS
operation begins, the host processor writes the Data Structure Address
register value to initialize the pointer for table indirect operations. To
begin SCRIPTS operation, the host processor writes the starting address
of the SCRIPTS instructions into the chip’s DMA SCRIPTS Pointer
Register. Once it receives this address, the chip becomes a bus master
and fetches the first SCRIPTS instruction. The chip executes all steps of
the instruction, moving through the appropriate bus phases, interrupting
only on completion of SCRIPTS operation or when service from the
external processor is required. This leaves the host processor free for
other tasks.
Software developers can create SCSI SCRIPTS source code in any text
editor. The LSI Logic Assembler, NASM, is discussed in Chapter 4,
“Using the LSI Logic Assembler NASM™.” NASM assembles SCRIPTS
code into an array of assembled SCRIPTS instructions that can be
included in the main “C” language program and linked together to create
an executable driver. When compiled, these programs control chip
operation.
1-8 Using the Programming Guide
Figure 1.3 Typical SCRIPTS Operation
Host System
Processor
System Memor y
Write DSP
Interrupt when done
Fetch instructions from
internal or external
System Bus
memory
(Expanded View)
Data Structure
Message Buffer
Command Buffer
Data Buffer
Status Buffer
LSI53C7XX/8XX/10XX
Operating
Registers
SCRIPTS
Processor
SCSI Bus
SCRIPTS RAM
(when supported)
System Overview 1-9
1-10 Using the Programming Guide
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