The HDSP-253x is ideal for applications where displaying
eight or more characters of dot matrix information in an
aesthetically pleasing manner is required. These devices
are eight-digit, 5 x 7 dot matrix, alphanumeric displays.
The 5.0 mm (0.2 inch) high characters are packaged in a
0.300 inch (7.62 mm) 30 pin DIP. The on-board CMOS IC
has the ability to decode 128 ASCII characters, which are
permanently stored in ROM. In addition, 16 programmable
symbols may be stored in on-board RAM. Seven brightness
levels provide versatility in adjusting the display intensity
and power consumption. The HDSP-253x is designed for
standard microprocessor interface techniques. The display
and special features are accessed through a bidirectional
eight-bit data bus.
Features
• XY stackable
• 128 character ASCII decoder
• Programmable functions
• 16 user denable characters
• Multi-level dimming and blanking
• TTL compatible CMOS IC
• Wave solderable
Applications
• Avionics
• Computer peripherals
• Industrial instrumentation
• Medical equipment
• Portable data entry devices
• Telecommunications
• Test equipment
Device Selection Guide
AlGaAs Red HER Orange Yellow Green
HDSP-2534 HDSP-2532 HDSP-2530 HDSP-2531 HDSP-2533
ESD WARNING: Normal CMOS handling precautions should be observed to avoid static discharge.
Package Dimensions
PIN # 15
SYM.
TYP.
DATE CODE (YEAR, WEEK)
LUMINOUS INTENSITY CATEGORY
COLOR BIN (3)
3.81
(0.150)
PIN # 16
1.52
(0.060)
5.31
(0.209)
2.29
(0.090)
4.57
(0.180)
[4]
4.01
(0.158)
SYM.
5.08
(0.200)
10.16
(0.400)
TYP.
0.46 0.13
(0.018 0.005)
TYP.
PIN #1
PART NUMBER
2.54 0.13
(0.100 0.005)
(TOL. NON ACCUM.)
7.62
(0.300)
REF.
0.25
(0.010)
PIN #FUNCTIONPIN #FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RST
FL
A0
A1
A2
A3
NO PIN
NO PIN
NO PIN
A4
CLS
CLK
WR
CE
V
DD
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND (SUPPLY)
THERMAL TEST
GND (LOGIC)
RD
D0
D1
NO PIN
NO PIN
NO PIN
D2
D3
D4
D5
D6
D7
PIN FUNCTION ASSIGNMENT TABLE
34567
TYP.
SYM.
11.43
(0.450)
MAX.
TYP.
2.54
(0.100)
SYM.
2.68
(0.105)
42.93 (1.690) MAX.
TYP.
5.36
(0.211)
PIN #15
PIN #1 IDENTIFIER
HDSP-253x X Z
YYWW
210
Notes:
1. Dimensions are in mm (inches).
2. Unless otherwise specied, tolerance on dimensions is ±0.25 mm (0.010 inch).
3. For yellow and green displays only.
4. Marking is on side opposite pin 1.
Absolute Maximum Ratings
Supply Voltage, VDD to Ground
Operating Voltage, VDD to Ground
Input Voltage, Any Pin to Ground -0.3 V to VDD +0.3 V
Free Air Operating Temperature Range, T
Relative Humidity (Noncondensing) 85%
Storage Temperature Range, TS -55°C to 100°C
Soldering Temperature [1.59 mm (0.063 in.) Below Body]
Solder Dipping 260°C for 5 secs
Wave Soldering 250°C for 3 secs
ESD Protection @ 1.5 kΩ, 100 pF 4 kV (each pin)
Notes:
1. Maximum voltage is with no LEDs illuminated.
2. 20 dots ON in all locations at full brightness.
3. See Thermal Considerations section for information about operation in high temperature
ambients.
2
[1]
-0.3 V to 7.0 V
[2]
5.5 V
A
[3 ]
-40°C to + 85°C
ASCII Character Set
D7
D6
D5
D4
BIT
S
D3D0D2 D1
ROW
COLUMN
00000
00011
00102
00113
01004
01015
01106
01117
10008
10019
1010A
1011B
1100C
1101D
1110E
1111F
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
X
X
X
8–F
16
U
S
E
R
D
E
F
I
N
E
D
C
H
A
R
A
C
T
E
R
S
Optical Characteristics at 25°C
VDD = 5.0 V at Full Brightness
Luminous Intensity Peak Dominant
Character Average (#) Wavelength Wavelength
IV (mcd) l
LED Color Part Number Min. Typ. Typ. Typ.
AlGaAs Red HDSP-2534 5.1 25 645 637
High Eciency Red HDSP-2532 2.5 7.5 635 626
Orange HDSP-2530 2.5 7.5 600 602
Yellow HDSP-2531 2.5 7.5 583 585
Green HDSP-2533 2.5 7.5 568 574
Notes:
1. Refers to the initial case temperature of the device immediately prior to measurement.
2. Dominant wavelength, ld, is derived from the CIE chromaticity diagram, and represents the single wavelength which denes the color of the device.
[1]
PEAK
(nm) ld (nm)
[2]
3
Recommended Operating Conditions
Parameter Symbol Minimum Nominal Maximum Units
Supply Voltage VDD 4.5 5.0 5.5 V
Electrical Characteristics over Operating Temperature Range
4.5 < VDD < 5.5 unless otherwise specied
25°C 25°C
Parameter Symbol Min. Typ.
Input Leakage II -1.0 1.0 mA VIN = 0 to VDD, Pins CLK,
(Input without Pull-up) D0-D7, A0-A
Input Current IIP -30 -11 -18 0 mA VIN = 0 to VDD, Pins CLS,
(Input with Pull-up) RST, WR, RD, CE, FL
Output Voltage High VOH 2.4 V VDD = 4.5 V, IOH = -40 µA
Output Voltage Low D0-D7 VOL 0.4 V VDD = 4.5 V, IOL = 1.6 mA
Output Voltage Low CLK VOL 0.4 V V
Thermal Resistance IC Rq
Junction-to-PIN
Notes:
1. VDD = 5.0 V.
2. See Thermal Considerations Section for information about operation in high temperature ambients.
3. Average IDD measured at full brightness. See Table 2 in Control Word Section for IDD at lower brightness levels. Peak IDD = 28/15 x IDD(#).
4. Maximum IDD occurs at -55°C.
[2,3,4]
IDD(V) 230 295 390 mA “V” On in All 8 Locations
[2,3,4]
IDD(#) 330 410 480 mA “#” On in All 8 Locations
[2,3,4]
IDD(V) 200 255 330 mA “V” On in All 8 Locations
[2,3,4]
IDD(#) 300 370 430 mA “#” On in All 8 Locations
16 °C/W Measured at Pin 17
J-PIN
[1]
Max.
[1]
Max. Units Test Conditions
DD
= 4.5 V, IOL = 40 µA
DD
4
4
AC Timing Characteristics over Temperature Range
VDD = 4.5 to 5.5 V unless otherwise specied.
Reference
Number Symbol Description Min.
1 t
Write 210
Read 230 ns
2 t
3 tCE Chip Enable Active Time
Write 140
Read 160 ns
4 t
5 t
6 t
Write 140
Read 160 ns
7 t
8 tW Write Active Time 100 ns
9 tWD Data Valid Prior to Rising Edge of Write Signal 50 ns
10 tDH Data Write Hold Time 20 ns
11 tR Chip Enable Active Prior to Valid Data 160 ns
12 tRD Read Active Prior to Valid Data 75 ns
13 tDF Read Data Float Delay 10 ns
tRC Reset Active Time
Notes:
1. Worst case values occur at an IC junction temperature of 125°C.
2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied
together.
3. Changing the logic levels of the Address lines when CE = “0” may cause erroneous data to be entered into the Character RAM, regardless of the
logic levels of the WR and RD lines.
4. The display must not be accessed until after 3 clock pulses (110 µs min. using the internal refresh clock) after the rising edge of the reset line.
Display Access Time
ACC
Address Setup Time to Chip Enable 10 ns
ACS
[2, 3]
Address Hold Time to Chip Enable 20 ns
ACH
Chip Enable Recovery Time 60 ns
CER
Chip Enable Active Prior to Rising Edge of
CES
Chip Enable Hold Time to Rising Edge of Read/Write Signal
CEH
[4]
300 ns
[2, 3]
[2,3]
0 ns
[1]
Units
Symbol Description 25°C Typical Minimum
F
Oscillator Frequency 57 28 kHz
OSC
[5]
F
Display Refresh Rate 256 128 Hz
RF
[6]
F
Character Flash Rate 2 1 Hz
FL
[7]
t
Self Test Cycle Time 4.6 9.2 sec
ST
Notes:
5. FRF = F
6. FFL = F
7. tST = 262,144/F
OSC
OSC
/224.
/28,672.
OSC
.
[1]
5
Units
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