AVAGO HCPL 0721 Datasheet

HCPL-0720, HCPL-7720, HCPL-0721 and HCPL-7721

40 ns Propagation Delay, CMOS Optocoupler

Data Sheet

Lead (Pb) Free

RoHS 6 fully
compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Description

Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-772X or HCPL-072X optocouplers
utilize the latest CMOS IC technology to achieve out­standing performance with very low power consump­tion. The HCPL-772X/072X require only two bypass ca­pacitors for complete CMOS compatability.

Basic building blocks of the HCPL-772X/072X are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver IC
which supplies current to the LED. The detector IC incor­porates an integrated photodiode, a high-speed tran­simpedance amplier, and a voltage comparator with an
output driver.

Functional Diagram

**V

DD1

GND

1

2

V

I

3

*

LED1

4

1

SHIELD

8

V

**

DD2

7

NC*

I

O

6

V

O

5

GND

2

Features

x +5 V CMOS compatibility

x 20 ns maximum prop. delay skew

x High speed: 25 MBd

x 40 ns max. prop. delay

x 10 kV/μs minimum common mode rejection

x –40 to 85°C temperature range

x Safety and regulatory approvals

UL recognized
– 3750 Vrms for 1 min. per UL 1577
– 5000 Vrms for 1 min. per UL 1577
(for HCPL-772X option 020)

CSA component acceptance notice #5

IEC/EN/DIN EN 60747-5-2
– V
– V

= 630 Vpeak for HCPL-772X option 060

IORM

= 560 Vpeak for HCPL-072X option 060

IORM

Applications

x Digital eldbus isolation: CC-Link, DeviceNet, Pro-

bus, SDS

x AC plasma display panel level shifting

x Multiplexed data transmission

x Computer peripheral interface

x Microprocessor system interface

* Pin 3 is the anode of the internal LED and must be leftunconnected

for guaranteed data sheet performance. Pin 7 is not connected
internally.

** A 0.1 μF bypass capacitor must be connected between pins 1 and

4, and 5 and 8.

TRUTH TABLE

POSITIVE LOGIC

V

I

H OFF H

L ON L

LED1 Vo OUTPUT

CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.

Selection Guide

8-Pin DIP Small Outline
(300 Mil) SO-8 Data Rate PWD

HCPL-7721 HCPL-0721 25 MB 6 ns

HCPL-7720 HCPL-0720 25 MB 8 ns

Ordering Information

HCPL-0720, HCPL-0721, HCPL-7720 and HCPL-7721 are UL Recognized with 3750 Vrms for 1 minute per UL1577.

Option

Part RoHS non RoHS Surface Gull Tape UL 5000 Vrms/ IEC/EN/DIN
Number Compliant Compliant Package Mount Wing & Reel 1 Minute rating EN 60747-5-2 Quantity

-000E no option 50 per tube

-300E #300 X X 50 per tube

-500E #500 X X X 1000 per reel

HCPL-7720

HCPL-7721

-520E -520 X X X X 1000 per reel

-060E #060 X 50 per tube

-360E #360 X X X 50 per tube

-560E #560 X X X X 1000 per reel

-000E no option X X 100 per tube

HCPL-0720

HCPL-0721

-560E #560 X X X X 1500 per reel

-020E -020 300 mil X 50 per tube

-320E -320 DIP-8 X X X 50 per tube

-500E #500 SO-8 X X X 1500 per reel

-060E #060 X X X 100 per tube

To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.

Example 1:

HCPL-7720-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with

IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant.

Example 2:

HCPL-0721 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’

2

Package Outline Drawing

HCPL-772X 8-Pin DIP Package

TYPE NUMBER

1.19 (0.047) MAX.

3.56 ± 0.13

(0.140 ± 0.005)

1.080 ± 0.320

(0.043 ± 0.013)

9.65 ± 0.25

(0.380 ± 0.010)

A XXXXV

YYWW

OPTION 060 CODE*

5678

DATE CODE

4321

1.78 (0.070) MAX.

4.70 (0.185) MAX.

0.51 (0.020) MIN.

2.92 (0.115) MIN.

0.65 (0.025) MAX.

2.54 ± 0.25

(0.100 ± 0.010)

7.62 ± 0.25

(0.300 ± 0.010)

6.35 ± 0.25

(0.250 ± 0.010)

+ 0.076

5° TYP.

DIMENSIONS IN MILLIMETERS AND (INCHES).

*OPTION 300 AND 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

0.254

(0.010

- 0.051

+ 0.003)

- 0.002)

3

Package Outline Drawing

HCPL-772X Package with Gull Wing Surface Mount Option 300

9.65 ± 0.25

(0.380 ± 0.010)

6

7

8

5

LAND PATTERN RECOMMENDATION

1.016 (0.040)

6.350 ± 0.25

(0.250 ± 0.010)

1.19

(0.047)

MAX.

1.080 ± 0.320

(0.043 ± 0.013)

1

2.54

(0.100)

BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

3

2

4

1.780

(0.070)

MAX.

3.56 ± 0.13

(0.140 ± 0.005)

Package Outline Drawing

HCPL-072X Outline Drawing (Small Outline SO-8 Package)

0.635 ± 0.130

(0.025 ± 0.005)

10.9 (0.430)

1.27 (0.050)

9.65 ± 0.25

(0.380 ± 0.010)

7.62 ± 0.25

(0.300 ± 0.010)

0.635 ± 0.25

(0.025 ± 0.010)

LAND PATTERN RECOMMENDATION

2.0 (0.080)

0.254

(0.010

12° NOM.

+ 0.076

- 0.051

+ 0.003)

- 0.002)

8765

3.937 ± 0.127

(0.155 ± 0.005)

PIN ONE

0.406 ± 0.076

(0.016 ± 0.003)

3.175 ± 0.127

(0.125 ± 0.005)

TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)

*

5.207 ± 0.254 (0.205 ± 0.010)

DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.

OPTION NUMBER 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

XXXV
YWW

*

5.080 ± 0.127

(0.200 ± 0.005)

(0.236 ± 0.008)

4321

1.270

(0.050)

5.994 ± 0.203

TYPE NUMBER
(LAST 3 DIGITS)

DATE CODE

BSC

1.524

(0.060)

0 ~ 7°

7°

0.305

(0.012)

45° X

0.203 ± 0.102

(0.008 ± 0.004)

MIN.

0.64 (0.025)

0.432

(0.017)

7.49 (0.295)

1.9 (0.075)

0.228 ± 0.025

(0.009 ± 0.001)

4

Solder Reow Thermal Prole

300

PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.

200

160°C
150°C
140°C

100

TEMPERATURE (°C)

ROOM

TEMPERATURE

0

0

Note: Non-halide ux should be used.

Pb-Free IR Prole

T

p

217 °C

T

L

3 °C/SEC. MAX.

150 - 200 °C

T

smax

T

smin

TEMPERATURE

PREHEAT

60 to 180 SEC.

PEAK
TEMP.
245°C

2.5°C ± 0.5°C/SEC.

30

SEC.

30

3°C + 1°C/–0.5°C

PREHEATING TIME
150°C, 90 + 30 SEC.

50 150100 200 250

TIME (SECONDS)

TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE

t

p

260 +0/-5 °C

20-40 SEC.

RAMP-UP

t

s

t

L

60 to 150 SEC.

SEC.

RAMP-DOWN
6 °C/SEC. MAX.

SOLDERING

TIME

200°C

50 SEC.

PEAK
TEMP.
240°C

PEAK

TEMP.

230°C

TIGHT
TYPICAL
LOOSE

25

t 25 °C to PEAK

TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
T

smax

= 200 °C, T

smin

= 150 °C

Note: Non-halide ux should be used.

Regulatory Information

The HCPL-772X/072X have been approved by the following organizations:

UL

Recognized under UL 1577, component recognition program, File E55361.

CSA

Approved under CSA Component Acceptance Notice #5, File CA88324.

IEC/EN/DIN EN 60747-5-2

Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884Teil 2):2003-01. (Option 060 only)

5

Insulation and Safety Related Specications

Value

Parameter Symbol 772X 072X Units Conditions

Minimum External Air L(I01) 7.1 4.9 mm Measured from input terminals to output

Gap (Clearance) terminals, shortest distance through air.

Minimum External L(I02) 7.4 4.8 mm Measured from input terminals to output
Tracking (Creepage) terminals, shortest distance path along body.

Minimum Internal Plastic 0.08 0.08 mm Insulation thickness between emitter and
Gap (Internal Clearance) detector; also known as distance through
insulation.

Tracking Resistance CTI ≥175 ≥175 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking
Index)

Isolation Group IIIa IIIa Material Group
(DIN VDE 0110, 1/89, Table 1)

All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimen sions are needed as a starting point for the equip­ment designer when determining the circuit insulation
requirements. However, once mounted on a printed
circuit board, minimum creepage and clearance require­ments must be met as specied for individual equipment
standards. For creepage, the shortest distance path along

the surface of a printed circuit board between the solder
llets of the input and output leads must be considered.
There are recommended techniques such as grooves
and ribs which may be used on a printed circuit board to
achieve desired creepage and clearances. Creepage and
clearance distances will also change depending on fac­tors such as pollution degree and insulation level.

6

IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)
HCPL-772X HCPL-072X

Description Symbol Option 060 Option 060 Units

Installation classication per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms I-IV I-IV
for rated mains voltage ≤300 V rms I-IV I-III
for rated mains voltage ≤450 V rms I-III

Climatic Classication 55/85/21 55/85/21

Pollution Degree (DIN VDE 0110/1.89) 2 2

Maximum Working Insulation Voltage V

Input to Output Test Voltage, Method b† V
V

x 1.875 = VPR, 100% Production

IORM

Test with t

= 1 sec, Partial Discharge < 5 pC

m

Input to Output Test Voltage, Method a† V
V

x 1.5 = VPR, Type and Sample Test,

IORM

t

= 60 sec, Partial Discharge < 5 pC

m

Highest Allowable Overvoltage† V
(Transient Overvoltage, t

= 10 sec)

ini

Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature T
Input Current I
Output Power P

Insulation Resistance at T

, V10 = 500 V RIO ≥10

S

630 560 V peak

IORM

1181 1050 V peak

PR

945 840 V peak

PR

6000 4000 V peak

IOTM

175 150 °C

S

230 150 mA

S,INPUT

600 600 mW

S,OUTPUT

9

≥109 Ω

† Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations

section IEC/EN/DIN EN 60747-5-2, for a detailed description.
Note:
These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured
by means of protective circuits.
The surface mount classication is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Figure

Storage Temperature TS –55 125 °C

[1]

Ambient Operating Temperature

T

Supply Voltages V

Input Voltage V

Output Voltage V

Average Output Current I

–40 +85 °C

A

, V

DD1

–0.5 V

I

O

O

0 6.0 Volts

DD2

+0.5 Volts

DD1

–0.5 V

+0.5 Volts

DD2

10 mA

Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane

Solder Reow Temperature Prole See Solder Reow Temperature Prole Section

Recommended Operating Conditions

Parameter Symbol Min. Max. Units Figure

Ambient Operating Temperature TA –40 +85 °C

, V

Supply Voltages V

Logic High Input Voltage V

Logic Low Input Voltage V

Input Signal Rise and Fall Times t

DD1

IH

IL

, tf 1.0 ms

r

4.5 5.5 V

DD2

2.0 V

V 1, 2

DD1

0.0 0.8 V

7

Electrical Specications

Test conditions that are not specied can be anywhere within the recommended operating range.
All typical specications are at T

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note

= +25°C, V

A

DD1

= V

DD2

= +5 V.

DC Specications
Logic Low Input I

Supply Current
Logic High Input I

Supply Current
Output Supply Current I
I
Input Current I
Logic High Output V
Voltage 4.0 4.8 I
Logic Low Output VOL 0 0.1 V IO = 20 μA, VI = V

Voltage

0.5 1.0 IO = 4 mA, VI = V

6.0 10.0 mA VI = 0 V 2

DD1L

1.5 3.0 mA VI = V

DD1H

5.5 9.0 mA

DD2L

DD2H

–10 10 μA

I

4.4 5.0 V IO = -20 μA, VI = VIH 1, 2

OH

7.0 9.0

0.1 V

DD1

= -4 mA, VI = V

O

IO = 400 μA, VI = V

IH

IL

IL

IL

Switching Specications

Propagation Delay Time t
to Logic Low Output CMOS Signal Levels
Propagation Delay Time t
to Logic High Output
Pulse Width PW 40
Data Rate 25 MBd
Pulse Width Distortion PWD
|t

- t

|

PHL

PLH

Propagation Delay Skew t
Output Rise Time t
(10 - 90%)
Output Fall Time t
(90 - 10%)
Common Mode |CM
Transient Immunity at 0.8 V
Logic High Output V
Common Mode |CM
Transient Immunity at V
Logic Low Output
Input Dynamic Power C
Dissipation
Capacitance
Output Dynamic Power C
Dissipation
Capacitance

20 40 ns CL = 15 pF 3, 6 3

PHL

23 40

PLH

7721/0721
7720/0720

20 5

PSK

9 ns

R

8 ns

F

| 10 20 kV/μs VI = V

H

| 10 20 VI = 0 V, VO > 0.8 V,

L

60 pF 7

PD1

10

PD2

3 6 ns 7 4
3 8 ns

, VO > 6

DD1

,

DD1

= 1000 V

CM

= 1000 V

CM

8

Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note

Input-Output Momentary 072X V
Withstand Voltage 772X 3750 t = 1 min., 10
Option 020 5000 T
Resistance R
(Input-Output)
Capacitance C
(Input-Output)
Input Capacitance C
Input IC Junction-to-Case -772XT
Thermal Resistance -072X 160 located at center
Output IC Junction-to-Case -772X T
Thermal Resistance -072X 135

Package Power Dissipation P

Notes:

1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not

guarantee functionality.

2. The LED is ON when VI is low and OFF when VI is high.

3. t

propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal.

PHL

t

propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.

PLH

4. PWD is dened as |t

5. t

is equal to the magnitude of the worst case dierence in t

PSK

the recommended operating conditions.

6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 V

mode voltage slew rate that can be sustained while maintaining V
and falling common mode voltage edges.

7. Unloaded dynamic power dissipation is calculated as follows: CPD * V

8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.

9. In accordance with UL1577, each HCPL-072X is proof tested by applying an insulation test voltage ≥4500 V

current limit, I
current limit. I

10. The Input-Output Momentary With stand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous

voltage rating. For the continuous voltage rating refer to your equipment level safety specication or Avago Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.”

11. C

is the capacitance measured at pin 2 (VI).

I

- t

|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.

PHL

PLH

≤5 μA). Each HCPL-772X is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detection

I-O

≤ 5 μA.)

I-O

3750 Vrms RH ≤50%, 8, 9,

ISO

= 25°C

A

1012 Ω V

I-O

0.6 pF f = 1 MHz

I-O

3.0 11

I

jci

jco

150 mW

PD

145 °C/W Thermocouple

140 underside of package

and/or t

PHL

that will be seen between units at any given temperature within

PLH

< 0.8 V. The common mode voltage slew rates apply to both rising

O

* f + IDD * VDD, where f is switching frequency in MHz.

DD2

= 500 Vdc 8

I-O

. CML is the maximum common

DD2

for 1 second (leakage detection

RMS

5

0 °C
25 °C
85 °C

4123

(V)

O

V

4

3

2

1

0

0

VI (V)

Figure 1. Typical output voltage vs. input volt­age.

9

2.2

0 °C

2.1

2.0

(V)

1.9

ITH

V

1.8

1.7

5

1.6

4.5

25 °C
85 °C

V

(V)

DD1

Figure 2. Typical input voltage switching thresh­old vs. input supply voltage.

29

27

25

(ns)

23

PHL

, T

21

PLH

T

19

17

5.254.75 5

5.5

15

0

T

PLH

T

PHL

10 40 50 70

TA (C)

6020 30

80

Figure 3. Typical propagation delays vs. tem­perature.

4

11

7

3

(ns)

2

PWD

1

0

0

TA (C)

6020

40

Figure 4. Typical pulse width distortion vs.
temperature.

29

27

25

(ns)

PHL

, T

PLH

T

23

21

19

17

15

15

2520 35 45

30

CI (pF)

T

T

PHL

PLH

40

6

10

(ns)

R

T

9

80

8

0

40

TA (C)

80

6020

(ns)

F

T

5

4

3

2

0

40

TA (C)

80

6020

Figure 5. Typical rise time vs. temperature. Figure 6. Typical fall time vs. temperature.

6

5

4

(ns)

3

PWD

2

1

0

50

15

30

2520 35 45

CI (pF)

40

50

Figure 7. Typical propagation delays vs. output
load capacitance.

S

STANDARD 8 PIN DIP PRODUCT

800

700

600

500

, INPUT CURRENT – I

400

S

300

(230)

200

100

0

0

OUTPUT POWER – P

TA – CASE TEMPERATURE – °C

P

S

I

S

(mW)

(mA)

12525 75 100 150

175

Figure 8. Typical pulse width distortion vs.
output load capacitance.

S

SURFACE MOUNT SO8 PRODUCT

800

700

600

500

, INPUT CURRENT – I

400

S

300

200

(150)

100

0

20050

0

OUTPUT POWER – P

T

– CASE TEMPERATURE – °C

A

P

S

I

S

(mW)

(mA)

12525 75 100 150

175

Figure 9. Thermal derating curve, dependence of safety limiting value with case temperature per
IEC/EN/DIN EN 60747-5-2.

20050

10

Application Information

Bypassing and PC Board Layout

The HCPL-772X/072X optocouplers are extremely easy
to use. No external interface circuitry is required because
the HCPL-772X/072X use high-speed CMOS IC technol­ogy allowing CMOS logic to be connected directly to the
inputs and outputs.

As shown in Figure 10, the only external components

required for proper operation are two bypass capaci­tors. Capacitor values should be between 0.01 μF and

0.1 μF. For each capacitor, the total lead length between
both ends of the capacitor and the power-supply pins
should not exceed 20 mm. Figure 11 illustrates the rec­ommended printed circuit board layout for the HPCL­772X/072X.

V

DD1

C1 C2

V

I

GND

1

2

3

NC

4

1

C1, C2 = 0.01 μF TO 0.1 μF

YWW

72X

8

7

6

5

Figure 10. Recommended printed circuit board layout.

V

DD1

V

I

C1 C2

GND

1

NC

GND

YWW

2

72X

V

V

DD2

O

V

DD2

V

O

GND

C1, C2 = 0.01 μF TO 0.1 μF

2

Figure 11. Recommended printed circuit board layout.

Propagation Delay, Pulse-Width Distortion and Propagation Delay
Skew

Propagation Delay is a gure of merit which describes
how quickly a logic signal propagates through a sys­tem. The propaga tion delay from low to high (t

PLH

) is the
amount of time required for an input signal to propa­gate to the output, causing the output to change from

INPUT

OUTPUT

Figure 12.

11

V

I

t

PLH

V

10%

O

t

PHL

50%

90%90%

10%

5 V CMOS

0 V

V

OH

2.5 V CMOS
V

OL

low to high. Similarly, the propagation delay from high
to low (t

) is the amount of time required for the input

PHL

signal to propagate to the output, causing the output to
change from high to low. See Figure 12.

Pulse-width distortion (PWD) is the dierence between
t

PHL

and t

and often determines the maxi mum data

PLH

rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being trans mitted. Typical­ly, PWD on the order of 20 - 30% of the minimum pulse
width is tolerable.

Propagation delay skew, t

, is an important parameter

PSK

to con sider in parallel data applications where synchro­nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of opto­couplers, dierences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at dier­ent times. If this dierence in propagation delay is large
enough it will determine the maximum rate at which
parallel data can be sent through the optocouplers.

Propagation delay skew is dened as the dierence be­tween the minimum and maximum propa gation delays,
either t

PLH

or t

, for any given group of optocoup lers

PHL

which are operating under the same conditions (i.e., the
same drive current, supply volt age, output load, and op­erating temperature). As illustrated in Figure 13, if the in­puts of a group of optocouplers are switched either ON
or OFF at the same time, t
the shortest propagation delay, either t
the longest propagation delay, either t

As mentioned earlier, t

is the dierence between

PSK

or t

PLH

PLH

can determine the maximum

PSK

or t

PHL

PHL

.

, and

parallel data transmission rate. Figure 14 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the opto­couplers. The gure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked o of the rising edge of
the clock.

V

I

V

O

V

I

V

O

50%

CMOS

50%

2.5 V,

t

PSK

2.5 V,
CMOS

Figure 13. Propagation delay skew waveform.

Propagation delay skew repre sents the uncertainty of
where an edge might be after being sent through an op­tocoupler. Figure 14 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these consider­ations, the absolute minimum pulse width that can be sent
through optocouplers in a parallel application is twice t

PSK

DATA

INPUTS

CLOCK

DATA

OUTPUTS

CLOCK

t

PSK

t

PSK

Figure 14. Parallel data transmission example.

A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.

The HCPL-772X/072X optocouplers oer the advantage
of guaranteed specications for propagation delays,
pulse-width distortion, and propagation delay skew
over the recommended temperature and power supply
ranges.

.

12

Digital Field Bus Communication Networks

To date, despite its many draw backs, the 4 - 20 mA ana­log current loop has been the most widely accepted
standard for implementing process control systems. In
today’s manufacturing environment, however, automat­ed systems are expected to help manage the process,
not merely monitor it. With the advent of digital eld bus
communication networks such as CC-Link, DeviceNet,
PROFIBUS, and Smart Distributed Systems (SDS), gone
are the days of constrained information. Controllers can

CONTROLLER

BUS

INTERFACE

OPTICAL

ISOLATION

TRANSCEIVER

FIELD BUS

now receive multiple readings from eld devices (sen­sors, actuators, etc.) in addition to diagnostic informa­tion.

The physical model for each of these digital eld bus
communica tion networks is very similar as shown in
Figure 15. Each includes one or more buses, an interface
unit, optical isolation, transceiver, and sensing and/or ac­tuating devices.

TRANSCEIVER

OPTICAL

ISOLATION

BUS

INTERFACE

DEVICE

CONFIGURATION

TRANSCEIVER

OPTICAL

ISOLATION

BUS

INTERFACE

MOTOR

STARTER

Figure 15. Typical eld bus communication physical model.

TRANSCEIVER

OPTICAL

ISOLATION

BUS

INTERFACE

XXXXXX

YYY

MOTOR

CONTROLLER

TRANSCEIVER

OPTICAL

ISOLATION

BUS

INTERFACE

SENSOR

13

Optical Isolation for Field Bus Networks

To recognize the full benets of these networks, each
recom mends providing galvanic isolation using Avago
optocouplers. Since network communication is bi-direc­tional (involving receiving data from and transmitting
data onto the network), two Avago optocouplers are
needed. By providing galvanic isolation, data integrity is
retained via noise reduction and the elimination of false
signals. In addition, the network receives maximum pro­tection from power system faults and ground loops.

Within an isolated node, such as the DeviceNet Node
shown in Figure 16, some of the node’s components are
referenced to a ground other than V- of the network.

AC LINE

These components could include such things as devices
with serial ports, parallel ports, RS232 and RS485 type
ports. As shown in Figure 16, power from the network is
used only for the transceiver and input (network) side of
the optocouplers.

Isolation of nodes connected to any of the three types of
digital eld bus networks is best achieved by using the
HCPL-772X/072X optocouplers. For each network, the
HCPL-772X/072X satisify the critical propagation delay
and pulse width distortion require ments over the tem­perature range of 0°C to +85°C, and power supply volt­age range of 4.5 V to 5.5 V.

NODE/APP SPECIFIC

HCPL

772x/072x

TRANSCEIVER

DRAIN/SHIELD

SIGNAL

POWER

NETWORK

POWER
SUPPLY

Figure 16. Typical DeviceNet Node.

uP/CAN

HCPL

772x/072x

LOCAL

NODE

SUPPLY

5 V REG.

GALVANIC
ISOLATION
BOUNDARY

V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)

14

Implementing CC-Link with the HCPL-772X/072X

CC-Link (Control and Communication Link) is developed
to merge control and information in the low-level net­work (eld network) by PCs, thereby making the mul­tivendor environment a reality. It has data control and
message-exchange function, as well as bit control func­tion, and operates at the speed up to 10 Mbps.

Power Supplies and Bypassing

The recommended CC-Link circuit is shown in Figure

17. Since the HCPL-772X/072X are fully compatible with
CMOS logic level signals, the optocoupler is connected
directly to the transceiver. Two bypass capacitors (with
values between 0.01 μF and 0.1 μF) are required and
should be located as close as possible to the input and
output power supply pins of the HCPL-772X/072X. For
each capacitor, the total lead length between both ends
of capacitor and the power supply pins should not ex­ceed 20 mm. The bypass capacitors are required be­cause of the high speed digital nature of the signals in­side the optocoupler.

DA

DB

DG

SLD

FG

FIL

SN75ALS181NS

V

CC

V

CC

A

B

Y

Z

RE

DE

GND
GND

R

D

10 K

10 K

1 K

HC14

1 K

HC14

0.1 μ

0.1 μ

0.1 μ

0.1 μ

V

DD2

(5 V)

GND

HCPL-7720#500

V

DD1

V

I

GND

1

2

HCPL-7720#500

V

DD2

V

O

GND

HCPL-2611#560

V

OE

V

DD

V

O

GND

HCPL-2611#560

V

OE

V

DD

V

O

GND

V

DD2

GND

V

DD1

GND

V

NC

NC

NC

NC

V

DD1

(5 V)

10 K

1

RD1

SD

MPU
BOARD
OUTPUT

SDGATEON

O

V

+

–

+

–

0.1 μ

GND

I

0.1 μ

390

HC14

390

HC14

Figure 17. Recommended CC-Link application circuit.

15

Implementing DeviceNet and SDS with the HCPL-772X/072X

With transmission rates up to 1 Mbit/s, both DeviceNet
and SDS are based upon the same broadcast-oriented,
communica tions protocol — the Controller Area Network
(CAN). Three types of isolated nodes are recommended
for use on these networks: Isolated Node Powered by
the Network (Figure 18), Isolated Node with Transceiver
Powered by the Network (Figure 19), and Isolated Node
Providing Power to the Network (Figure 20).

NODE/APP SPECIFIC

uP/CAN

Isolated Node Powered by the Network

This type of node is very exible and as can be seen in
Figure 18, is regarded as “isolated” because not all of its
components have the same ground reference. Yet, all
compo nents are still powered by the network. This node
contains two regulators: one is isolated and powers the
CAN controller, node-specic application and isolated
(node) side of the two optocoup lers while the other is
non-isolated. The non-isolated regulator supplies the
transceiver and the non-isolated (network) half of the
two optocouplers.

DRAIN/SHIELD

SIGNAL

POWER

NETWORK

POWER

SUPPLY

HCPL

772x/072x

TRANSCEIVER

HCPL

772x/072x

REG.

Figure 18. Isolated node powered by the network.

Isolated Node with Transceiver Powered by the Network

Figure 19 shows a node powered by both the network
and another source. In this case, the trans ceiver and iso­lated (network) side of the two optocouplers are pow­ered by the network. The rest of the node is powered by
the AC line which is very benecial when an application
requires a signicant amount of power. This method is
also desirable as it does not heavily load the network.

More importantly, the unique “dual-inverting” design of
the HCPL-772X/072X ensure the network will not “lock­up” if either AC line power to the node is lost or the node
powered-o. Specically, when input power (V

DD1

) to the
HCPL-772X/072X located in the transmit path is eliminat­ed, a RECESSIVE bus state is ensured as the HCPL-772X/
072X output voltage (V

) go HIGH.

O

ISOLATED

SWITCHING

POWER

SUPPLY

GALVANIC
ISOLATION
BOUNDARY

V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)

*Bus V+ Sensing

It is suggested that the Bus V+ sense block shown in Fig­ure 19 be implemented. A locally powered node with an
un-powered isolated Physical Layer will accumulate er­rors and become bus-o if it attempts to transmit. The
Bus V+ sense signal would be used to change the BOI at­tribute of the DeviceNet Object to the “auto-reset” (01)
value. Refer to Volume 1, Section 5.5.3. This would cause
the node to continually reset until bus power was detect­ed. Once power was detected, the BOI attribute would
be returned to the “hold in bus-o” (00) value. The BOI
attribute should not be left in the “auto-reset” (01) value
since this defeats the jabber protection capability of the
CAN error connement. Any inexpensive low frequency
optical isolator can be used to implement this feature.

16

AC LINE

NON ISO

5 V

*HCPL

772x/072x

REG.

DRAIN/SHIELD

SIGNAL

POWER

NETWORK

POWER

SUPPLY

NODE/APP SPECIFIC

uP/CAN

HCPL

772x/072x

TRANSCEIVER

* OPTIONAL FOR BUS V + SENSE

HCPL

772x/072x

Figure 19. Isolated node with transceiver powered by the network.

Isolated Node Providing Power to the Network

Figure 20 shows a node providing power to the network.
The AC line powers a regulator which provides ve (5)
volts locally. The AC line also powers a 24 volt isolated
supply, which powers the network, and another ve-volt
regulator, which, in turn, powers the transceiver and iso­lated (network) side of the two optocouplers. This meth­od is recommended when there are a limited number of
devices on the network that don’t require much power,
thus eliminating the need for separate power supplies.

GALVANIC
ISOLATION
BOUNDARY

V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)

More importantly, the unique “dual-inverting” design of
the HCPL-772X/072X ensure the network will not “lock­up” if either AC line power to the node is lost or the node
powered-o. Specically, when input power (V

DD1

) to the
HCPL-772X/072X located in the transmit path is eliminat­ed, a RECESSIVE bus state is ensured as the HCPL-772X/
072X output voltage (V

) go HIGH.

O

DEVICENET NODE

NODE/APP SPECIFIC

uP/CAN

DRAIN/SHIELD

SIGNAL

POWER

HCPL

772x/072x

TRANSCEIVER

HCPL

772x/072x

Figure 20. Isolated node providing power to the network.

17

5 V REG.

5 V REG.

ISOLATED

SWITCHING

POWER
SUPPLY

AC LINE

GALVANIC
ISOLATION
BOUNDARY

V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)

Power Supplies and Bypassing

The recommended DeviceNet application circuit is
shown in Figure 21. Since the HCPL-772X/072X are fully
compatible with CMOS logic level signals, the optocoup­ler is connected directly to the CAN transceiver. Two by­pass capacitors (with values between 0.01 and 0.1 μF)
are required and should be located as close as possible

GALVANIC
ISOLATION

V

1

V

2

3

GND

4

GND

5

V

6

7

BOUNDARY

DD1

IN

HCPL-772x
HCPL-072x

1

2

O

HCPL-772x
HCPL-072x

V

DD2

GND

GND

8

0.01

7

μF

C4

0.01 μF

TxD

Rs

V

6

O

5

2

4

1

3

V

2

IN

0.01
μF

+

ISO 5 V

TX0

0.01 μF

GND

RX0

0.01 μF

to the input and output power-supply pins of the HCPL­772X/072X. For each capacitor, the total lead length be­tween both ends of the capacitor and the power supply
pins should not exceed 20 mm. The bypass capac itors
are required because of the high-speed digital nature of
the signals inside the optocoupler.

5 V

LINEAR OR

SWITCHING

REGULATOR

++

V

CC

82C250

GND

CANH

CANL

REF

RXD

VREF

D1

30 V

0.01 μF

C1

500 V

5 V+

4 CAN+

3 SHIELD

2 CAN–

1 V–

R1
1 M

ISO 5 V

V

8

DD2

V

1

DD1

5 V

Figure 21. Recommended DeviceNet application circuit.

Implementing PROFIBUS with the HCPL-772X/072X

An acronym for Process Fieldbus, PROFIBUS is essentially
a twisted-pair serial link very similar to RS-485 capable
of achieving high-speed communi cation up to 12 MBd.
As shown in Figure 22, a PROFIBUS Control ler (PBC) es­tablishes the connec tion of a eld automation unit (con­trol or central processing station) or a eld device to
the transmission medium. The PBC consists of the line
transceiver, optical isolation, frame character transmit­ter/receiver (UART), and the FDL/APP processor with the
interface to the PROFIBUS user.

PBC

MEDIUM

PROFIBUS USER:

CONTROL STATION

(CENTRAL PROCESSING)

OR FIELD DEVICE

USER INTERFACE

FDL/APP

PROCESSOR

UART

OPTICAL ISOLATION

TRANSCEIVER

18

Figure 22. PROFIBUS Controller (PBC).

Power Supplies and Bypassing

The recommended PROFIBUS application circuit is
shown in Figure 23. Since the HCPL-772X/072X are fully
compatible with CMOS logic level signals, the optocoup­ler is connected directly to the transceiver. Two bypass
capacitors (with values between 0.01 and 0.1 μF) are
required and should be located as close as possible to
the input and output power-supply pins of the HCPL­772X/072X. For each capacitor, the total lead length be­tween both ends of the capacitor and the power supply
pins should not exceed 20 mm. The bypass capac itors
are required because of the high-speed digital nature of
the signals inside the optocoupler.

GALVANIC

ISOLATION

8

7

6

5

1

2

3

BOUNDARY

V

DD2

HCPL-772x

V

HCPL-072x

O

GND

2

V

DD1

V

IN

HCPL-772x
HCPL-072x

V

DD1

GND

V

DD2

1

V

2

IN

0.01

3

μF

4

1

ISO 5 V

8

0.01

7

μF

V

6

O

0.01
μF

5 V ISO 5 V

0.01 μF

Rx

5 V

Tx

0.01 μF

Being very similar to multi-station RS485 systems, the
HCPL-061N optocoupler provides a transmit disable
function which is necessary to make the bus free after
each master/slave transmission cycle. Specically, the
HCPL-061N disables the transmitter of the line driver by
putting it into a high state mode. In addition, the HCPL­061N switches the RX/TX driver IC into the listen mode.
The HCPL-061N oers HCMOS compatibility and the
high CMR performance (1 kV/μs at V

= 1000 V) es-

CM

sential in industrial communication interfaces.

ISO 5 V

8

V

R

D

DE

RE

CC

SN75176B

GND

5

6

A

RT

7

B

0.01 μF

+

SHIELD

–

1 M

1

4

3

2

Tx ENABLE

5 V

1, 0 kΩ

GND

4

1

2

3

4

ANODE

CATHODE

HCPL-061N

GND

V

CC

V

V

GND

5

2

ISO 5 V

8

7

E

0.01
μF

6

O

5

680 Ω

1

Figure 23. Recommended PROFIBUS application circuit.

For product information and a complete list of distributors, please go to our website: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. Obsoletes AV01-0565EN
AV02-0876EN - March 15, 2011