AVAGO APDS-9303 DATA SHEET

APDS-9303

Miniature Ambient Light Photo Sensor
with Digital (SMBus) Output

Data Sheet

Description

The APDS-9303 is a low-voltage Digital Ambient Light
Photo Sensor that converts light intensity to digital signal
output capable of direct SMBus interface. Each device
consists of one broadband photodiode (visible plus
infrared) and one infrared photodiode. Two integrating
ADCs convert the photodiode currents to a digital output
that represents the irradiance measured on each channel.
This digital output can be input to a microprocessor where
illuminance (ambient light level) in lux is derived using
an empirical formula to approximate the human-eye
response.

Application Support Information

The Application Engineering Group is available to
assist you with the application design associated with
APDS-9303 ambient light photo sensor module. You can
contact them through your local sales representatives for
additional details.

Features

• Approximate the human-eye response

• Precise Illuminance measurement under diverse light-

ing conditions

• Programmable Interrupt Function with User-Defined

Upper and Lower Threshold Settings

• 16-Bit Digital Output with SMBus at 100 kHz

• Programmable Analog Gain and Integration Time

• Miniature ChipLED Package

– Height – 0.55mm
– Length – 2.60mm
– Width – 2.20mm

• 50/60-Hz Lighting Ripple Rejection

• Low Active Power (0.6 mW Typical) with Power Down

Mode

• RoHS Compliant

Applications

• Detection of ambient light to control display

backlighting
– Mobile devices – Cell phones, PDAs, PMP
– Computing devices – Notebooks, Tablet PC, Key

board

– Consumer devices – LCD Monitor, Flat-panel TVs,

Video Cameras, Digital Still Camera

• Automatic Residential and Commercial Lighting

Management

• Automotive instrumentation clusters.

• Electronic Signs and Signals

Ordering Information

Part Number Packaging Type Package Quantity

APDS-9303-020 Tape and Reel 6-pins Chipled package 2500

Functional Block Diagram

SMBus

Interrupt

ADC Register

Ch0 (Visible + IR)

Ch1 (IR)

V

DD

ADC

ADC

GND

SCL

INT

SDA

ADDR SEL

Command

Register

Address Select

I/O Pins Configuration Table

Pin Symbol Type Description

1 V

DD

2 GND Ground Power supply ground. All voltages are referenced to GND

3 ADDR SEL I SMBUS device select – three-state

4 SCL I SMBUS serial clock input terminal

5 SDA I/O SMBUS serial data I/O terminal

6 INT O Level interrupt – open drain

Supply Supply voltage

Absolute Maximum Ratings

Parameter Symbol Min Max Unit

Supply voltage V

DD

Digital output voltage range VO -0.5 3.8 V

Digital output current IO -1 20 mA

Storage temperature range T

stg

ESD tolerance human body model – 2000 V

– 3.8 V

-40 85 ºC

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit Condition

Supply Voltage V

Operating Temperature T

SCL, SDA input low voltage V

SCL, SDA input high voltage V

DD

a

IL

IH

2.7 3.3 3.6 V

-30 – 85 ºC

-0.5 – 0.8 V

2.1 – 3.6 V

Electrical Characteristics

Parameter Symbol Min Typ Max Unit Conditions

Supply current I

INT, SDA output low voltage V

Leakage current I

DD

OL

LEAK

2

– 0.24 0.6 mA Active

– 3.2 15

0 – 0.4 V 3 mA sink current

0 – 0.6 V 6 mA sink current

-5 – 5

μA

μA

Power down

Operating Characteristics, High Gain (16x), Ta = 25°C, (unless otherwise noted) (see Notes 2, 3, 4, 5)

Parameter Symbol Channel Min Typ Max Unit Conditions

Oscillator frequency fosc 690 735 780 kHz

Dark ADC count value Ch0 0 4 counts Ee = 0, Tint = 402 ms

Ch1 0 4

Full scale ADC count value
(Note 6)

ADC count value Ch0 750 1000 1250 counts

ADC count value ratio:
Ch1/Ch0

Irradiance responsivity Re Ch0 27.5 counts/

Illuminance responsivity Rv Ch0 36 counts/

ADC count value ratio:
Ch1/Ch0

Illuminance responsivity,
low gain mode (Note 7)

(Sensor Lux) /(actual Lux),
high gain mode (Note 8)

Rv Ch0 2.3 counts/

Ch0 65535 counts Tint > 178 ms

Ch1 65535

Ch0 37177 Tint = 101 ms

Ch1 37177

Ch0 5047 Tint = 13.7 ms

Ch1 5047

λp = 640 nm,
Tint = 101 ms

Ch1 200

Ch0 700 1000 1300

Ch1 820

0.15 0.2 0.25

0.69 0.82 0.95

Ch1 5.5

Ch0 8.4

Ch1 6.9

Ch1 4

Ch0 144 Incandescent light source:

Ch1 72

0.11 Fluorescent light source:

0.5 Incandescent light source:

Ch1 0.25

Ch0 9 Incandescent light source:

Ch1 4.5

0.65 1 1.35 Fluorescent light source:

0.60 1 1.40 Incandescent light source:

(μW/cm2)

lux

lux

Ee = 36.3 μW/cm

λp = 940 nm,
Tint = 101 ms

Ee = 119 μW/cm

λp = 640 nm,
Tint = 101 ms

λp = 940 nm,
Tint = 101 ms

λp = 640 nm,
Tint = 101 ms

λp = 940 nm,
Tint = 101 ms

Fluorescent light source:
Tint = 402 ms

Tint = 402 ms

Tint = 402 ms

Tint = 402 ms

Fluorescent light source:
Tint = 402 ms

Tint = 402 ms

Tint = 402 ms

Tint = 402 ms

2

2

3

NOTES:

2. Optical measurements are made using small–angle incident radiation from light–emitting diode optical sources. Visible 640 nm LEDs and infrared
940 nm LEDs are used for final product testing for compatibility with high–volume production.

3. The 640 nm irradiance Ee is supplied by an AlInGaP light–emitting diode with the following characteristics: peak wavelength λp = 640 nm and
spectral halfwidth Δλ½ = 17 nm.

4. The 940 nm irradiance Ee is supplied by a GaAs light–emitting diode with the following characteristics: peak wavelength λp = 940 nm and spectral
halfwidth Δλ½ = 40 nm.

5. Integration time T
the Register Set section. For nominal f
Field value 01: T
as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01), and 322/322 = 1 (field value 10).

6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also by a 2–count
offset. Full scale ADC count value = ((number of clock cycles)/2 - 2) Field value 00: Full scale ADC count value = ((11 x 918)/2 - 2) = 5047
value 01: Full scale ADC count value = ((81 x 918)/2 - 2) = 37177
register. This full scale ADC count value is reached for 131074 clock cycles, which occurs for T

7. Low gain mode has 16x lower gain than high gain mode: (1/16 = 0.0625).

8. For sensor Lux calculation, please refer to the empirical formula below. It is based on measured Ch0 and Ch1 ADC count values for the light source
specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual Lux) ratio is estimated based on the variation
of the 640 nm and 940 nm optical parameters. Devices are not 100% tested with fluorescent or incandescent light sources.

, is dependent on internal oscillator frequency (f

int

= (81 x 918)/f

int

= 735 kHz, nominal T

osc

= 101 ms Field value 10: T

osc

) and on the integration field value in the timing register as described in

osc

= (n umber of clock cy cles)/f

int

= (322 x 918)/f

int

Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit

= 402 msScaling between integration times vary proportionally

osc

Field value 00: T

osc

= 178 ms for nominal f

int

= (11 x 918)/f

int

= 735 kHz.

osc

osc

= 13.7 ms

Field

CH1/CH0 Sensor Lux Formula

0 ≤ CH1/CH0 ≤ 0.52 Sensor Lux = (0.0315 x CH0) – (0.0593 x CH0 x ((CH1/CH0)1.4))

0.52 ≤ CH1/CH0 ≤ 0.65 Sensor Lux = (0.0229 x CH0) – (0.0291 x CH1)

0.65 ≤ CH1/CH0 ≤ 0.80 Sensor Lux = (0.0157 x CH0) – (0.0180 x CH1)

0.80 ≤ CH1/CH0 ≤ 1.30 Sensor Lux = (0.00338 x CH0) – (0.00260 x CH1)

CH1/CH0 ≥ 1.30 Sensor Lux = 0

AC Electrical Characteristics (VDD = 3 V, Ta = 25°C)

PARAMETER

t

(CONV)

f

(SCL)

t

(BUF)

t

(HDSTA)

t

(SUSTA)

t

(SUSTO)

t

(HDDAT)

t

(SUDAT)

t

(LOW)

t

(HIGH)

t

F

t

R

C

j

† Specified by design and characterization; not production tested.

†

Conversion time 12 100 400 ms

Clock frequency – – 400 kHz

Bus free time between start and stop condition 1.3 – –

Hold time after (repeated) start condition. After this period,
the first clock is generated.

Repeated start condition setup time 0.6 – –

Stop condition setup time 0.6 – –

Data hold time 0 – 0.9

Data setup time 100 – – ns

SCL clock low period 1.3 – –

SCL clock high period 0.6 – –

Clock/data fall time – – 300 ns

Clock/data rise time – – 300 ns

Input pin capacitance – – 10 pF

MIN TYP MAX UNIT

μs

0.6 – –

μs

μs

μs

μs

μs

μs

4

Parameter Measurement Information

SDA

SCL

StopStart

SCL

ACK

t

(LOWMEXT)

t

(LOWMEXT)

t

(LOWSEXT)

SCL

ACK

t

(LOWMEXT)

P

t

(SUSTO)

t

(SUDAT)

t

(HDDAT)

t

(BUF)

V

IH

V

IL

t

(R)

t

(LOW)

t

(HIGH)

t

(F)

t

(HDSTA)

V

IH

V

IL

P

Stop

Condition

SS
Start
Condition

t

(SUSTA)

SDA

SCL

A0A1A2A3A4A5A6 D1D2D3D4D5D6D7 D0R/W

Start by
Master

ACK by

APDS-9303

Stop by
Master

ACK by

APDS-9303

SDA

Frame 1 I 2C Slave Address Byte Frame 2 Command Byte

SCL

1 9 1 9

A0A1A2A3A4A5A6 D1D2D3D4D5D6D7 D0R/W

Start by
Master

ACK by

APDS-9303

Stop by
Master

NACK by

Master

SDA

Frame 1 I 2C Slave Address Byte Frame 2 Data Byte From APDS-9303

SCL

1 9 1 9

Figure 1. Timing Diagrams

Figure 2. Example Timing Diagram for SMBus Send Byte Format

Figure 3. Example Timing Diagram for SMBus Receive Byte Format

5

Typical Characteristics

Spectral Responsivity

 - Wavelength - nm

0

400

0.2

0.4

0.6

0.8

1

500 600 700 800 900 1000 1100

Normalized Responsivity

300

Channel 1
Photodiode

Channel 0
Photodiode

Normalized Responsivity Vs.

Angular Displacement * Cl Package

 - Angular Displacement - 470 pF

Normalized Responsivity

0

0.2

0.4

0.6

0.8

1.0

-90 -60 -30 0 30 60

90

Optical Axis

Figure 4 Figure 5

PRINCIPLES OF OPERATION

Analog–to–Digital Converter

The APDS-9303 contains two integrating analog-to-digital
converters (ADC) that integrate the currents from the
channel 0 and channel 1 photodiodes. Integration of both
channels occurs simultaneously, and upon completion of
the conversion cycle the conversion result is transferred to
the channel 0 and channel 1 data registers, respectively.
The transfers are double buffered to ensure that invalid
data is not read during the transfer. After the transfer, the
device automatically begins the next integration cycle.

Digital Interface

Interface and control of the APDS-9303 is accomplished
through a two–wire serial interface to a set of registers
that provide access to device control functions and
output data. The serial interface is compatible to SMBUS
bus version 1.1 and 2.0. The APDS-9303 offers three slave
addresses that are selectable via an external pin (ADDR
SEL). The slave address options are shown in Table 1.

Table 1. Slave Address Selection

ADDR SEL
TERMINAL LEVEL

GND 0101001 0001100

Float 0111001 0001100

V

DD

NOTE: The Slave Addresses and SMB Alert Address are 7 bits. Please note
the SMBus protocol on the following contents. A read/write bit should
be appended to the slave address by the master device to properly
communicate with the APDS-9303 device.

SLAVE
ADDRESS

1001001 0001100

SMB ALERT
ADDRESS

SMBUS Protocol

Each Send and Write protocol is, essentially, a series of
bytes. A byte sent to the APDS-9303 with the most sig­nificant bit (MSB) equal to 1 will be interpreted as a
COMMAND byte. The lower four bits of the COMMAND
byte form the register select address (see Table 2), which is
used to select the destination for the subsequent byte(s)
received. The APDS-9303 responds to any Receive Byte
requests with the contents of the register specified by the
stored register select address.

The APDS-9303 implements the following protocols of
the SMBUS 2.0 specification:

• Send Byte protocol

• Receive Byte protocol

• Write Byte protocol

• Write Word protocol

• Read Word protocol

• Block Write protocol

• Block Read protocol

When an SMBus Block Write or Block Read is initiated (see
description of COMMAND Register), the byte following
the COMMAND byte is ignored but is a requirement of the
SMBus specification. This field contains the byte count (i.e.
the number of bytes to be transferred). The APDS-9303
device ignores this field and extracts this information by
counting the actual number of bytes transferred before
the Stop condition is detected.

6

For a complete description of SMBus protocols, please review the SMBus Specification at http://www.smbus.org/specs.

1 7 1 1 8 1 1

S Slave Address Wr A Data Byte A P

X X

A Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK)

P Stop Condition

Rd Read (bit value of 1)

S Start Condition

Sr Repeated Start Condition

Wr Write (bit value of 0)

X Shown under a field indicates that that field is required to have a value of X

... Continuation of protocol

Master-to-Slave

Slave-to-Master

Figure 6. SMBus Packet Protocol Element Key

1 7 1 1 8 1 1

S Slave Address Wr A Data Byte A P

Figure 7. SMBUS Send Protocols

1 7 1 1 8 1 1

S Slave Address Rd A Data Byte A P

Figure 8. SMBus Receive Byte Protocol

1 7 1 1 8 1 1 7 1 1 8 1 1

S Slave Address Wr A Command Code A S Slave Address Rd A Data Byte Low A P

Figure 9. SMBus Read Byte Protocol

1 7 1 1 8 1 8 1 8 1 1

S Slave Address Wr A Command Code A Data Byte Low A Data Byte High A P

Figure 10. SMBus Write Word Protocol

1

1 7 1 1 8 1 1 7 1 1 8 1

S Slave Address Wr A Command Code A S Slave Address Rd A Data Byte Low A ...

8 1 1

Data Byte Low A P

Figure 11. SMBus Read Word Protocol

1

7