Avago ACPL-C79B, ACPL-C79A, ACPL-C790 User Manual

ACPL-C79B, ACPL-C79A & ACPL-C790

Isolation Ampli er Evaluation Board User Manual

User Guide

Quick-Start Guide

Once visual inspection is done to ensure that the Evaluation Board is received in good condition, the Evaluation Board
can be powered up in just 3 simple steps according to Figure 1 as shown:

1. Select either one of the provided sensing resistors (10mΩ or 15mΩ), or user’s own sensing resistor and mount it
(through soldering) on pads provided for R1 on the Evaluation Board;

2. Connect the necessary power supplies and current source as shown:

a. Connect 1st isolated 5V DC supply (DC Supply 1) to connector CON1 as shown;

b. Connect a 3.3V DC supply (DC Supply 2, can be non-isolated) to connector CON2 as shown;

c. Connect, through soldering, the required input current source (for sensing) cables as shown;

3. Supply the input current (subject to a maximum signal level of 250mVpp, or ±125mVdc across resistor R1) through
the cables (as shown in 2c) and monitor the output through an oscilloscope.

2c

Current Source Cables
for sensing

2a

+5V

Gnd1

DC Supply 1

1

1

2b

+3.3V

DC Supply 2

Gnd2

Output to
Oscilloscope
for monitoring
/or MCU for
Readings

3

Figure 1. Default Test Setup of Evaluation Board

Schematics

Schematics of the Evaluation Board are as shown in Figure 2.

+V dd2

GND1

GND1

ACPL-C79X

1

C5

100nF

2

3

U1

VDD1

VDD2

Vin+

Vout+

Vin-

Vout-

Gnd14Gnd2

CON 1

Vdd1

Rsense+

Rsense-

CON 1X3

1

2

3

GND1

9V Batt+

Batt-/Gnd1

R1

GND1

GND1

C1

100nF

TP4

TP5

LM78L05ACM

8

236

GND1

U2

R2

10R, 1%

R3

10R, 1%

1

C2

7

100nF

GND1

C3

22nF

Figure 2. Schematics of ACPL-C79X Evaluation Board

J1

8

7

6

5

TP1

GND2

GND2

C6

100nF

GND2

J3

+V dd3

J2

R4
1K, 1%

R5

1K, 1%

GND2 GND2 GND2

GND2GND2

C13

10uF

-V dd3

Vref

J4

+V dd3

GND2

+V dd2

1
2
3
4
5
6

6PIN HEADER

CON 2

U3

L78L33ACD13T R

8

C7

100nF

GND2

GND2

TP2

10K, 1%

R6

10K, 1%

R8

TP3

C15

C9

68pF

NM

Vref

2

3

C14 NM

C10 68pF

R7

2

3

R9
10K, 1%

6

7

10K, 1%

7

+-U4

4

1

C8

100nF

GND2

0.1uF
C11

6

OPA2 37UA

C12

0.1uF

-V dd3

Board Description

The ACPL-C79X evaluation boards (shown in Figure 3),
can accommodate either a ACPL-C79B(0.5% tolerance),
ACPL-C79A(1% tolerance), or ACPL-C790(3% tolerance)
device on U1, to demonstrate the high linearity and low­o set capability of Avago’s Isolation Ampli er over a wide
range of input current conditions. It allows a designer to
easily test the performance of the high-precision isola­tion ampli er in an actual application under real-life op­erating conditions. Many of the circuit recommendations
discussed in Application Note 1078 are implemented on
the board. Operation requires merely the addition of a
5V Supply and a low-resistance shunt resistor on the in­put side of the isolation ampli er. The board has holes for
mounting a through-hole shunt, and pads for mounting
a surface-mount shunt. The board may also be used for
general voltage isolation without any shunt resistor.

As can be seen on the board, the isolation circuitry is easily
contained within a small area while maintaining adequate
spacing for good voltage isolation and easy assembly. The
overall size of the evaluation board has been enlarged to
allow mounting of feet for stand-alone use (using the 4
drilled holes at the corners of the board).

Using the Board

The evaluation board is easily prepared for use. Only mi­nor preparations (just by soldering of shunt resistor, wires
for power / sense current path and output signal) are re­quired. The evaluation board is having a default setup 1 as
shown in the tables when shipped to customer. Customer
is free to choose any one of the 6 setup con gurations as
shown in the tables by setting J1, J2, J3 and J4 as shown.

2

Figure 3. Top View of ACPL-C79X Evaluation Board

Table 1.

Recommended Vin
for better linearity

Default Setup 1 <230mVpp +5Vdc +3.3Vdc +3.3Vdc 0V

Setup 2 <500mVpp +5Vdc +3.3Vdc +3.3Vdc -3.3Vdc

Setup 3 <230mVpp +5Vdc +5Vdc +3.3Vdc 0V

Setup 4 <500mVpp +5Vdc +5Vdc +3.3Vdc -3.3Vdc

Setup 5 <440mVpp +5Vdc +5Vdc +5Vdc 0V

Setup 6 <550mVpp +5Vdc +5Vdc +5Vdc -5Vdc

Notes

1. Linear input range is limited by the post-amp output swing range. To avoid this limitation, directly measure the VOUT+, VOUT– of the isolation
ampli er.

[1]

Vdd1 Vdd2 Vdd3 -Vdd3

In order to satisfy the above Vdd1, Vdd2, Vdd3 and –Vdd3 voltages, J1, J2, J3 and J4 must be set according to the table
as shown below:

Table 2.

[1]

J1

Default
Setup 1

Setup 2 Always

Setup 3 Always

Setup 4 Always

Setup 5 Always

Setup 6 Always

Notes

1. To obtain +5Vdc at Vdd1, a 9V Battery can be connected across Pin-2 and 3 of CON1 connector or by connecting an external +5V DC supply directly
to Pin-1 and 3 of CON1 connector. J1 can be left shorted permanently unless U2 is non-functioning.

Always
shorted

shorted

shorted

shorted

shorted

shorted

J2 J3 J4 Remarks

Shorting Vdd2
& Vdd3 pins

Shorting Vdd2
& Vdd3 pins

Shorting Vdd3
& C8_2 pins

Shorting Vdd3
& C8_2 pins

Shorting Vdd2
& Vdd3 pins

Shorting Vdd2
& Vdd3 pins

Short Open Only 2 external supplies (+5V Vdd1 & isolated +3,3V for Vdd2) are

needed

Open Short 3 external supplies (+5V Vdd1, isolated +3,3V for Vdd2 and Vdd3,

while isolated -3,3V for –Vdd3) are needed.

Short Open Only 2 external supplies (+5V Vdd1 & isolated +5V for Vdd2) are

needed, Vdd3 is obtained thru converter U3.

Open Short 3 external supplies (+5V Vdd1 & isolated +5V for Vdd2, while

isolated -3,3V for –Vdd3) are needed, Vdd3 is obtained thru
converter U3.

Short Open Only 2 external supplies (+5V Vdd1 & isolated +5V for Vdd2 &

Vdd3) are needed.

Open Short 3 external supplies (+5V Vdd1, isolated +5V for Vdd2 & Vdd3,

while isolated -5V for –Vdd3) are needed.

The output signal is measured between the “Vout” and “GND2” terminals (at the output side of the board). With all con­nections made and power supplies turned on, the approximate relationship of output voltage to input current is:

V

= 8.2 x VIN, where

OUT

VIN= R

SENSE

x IIN;

With the shunt resistor in place, the maximum di erential input voltage swing for linear operation is ±200mV as speci­ ed in the datasheet. However, input voltage as high as ±300mV can be safely applied with minimal performance
degradation.

When 68pF capacitance is selected for both C9 and C10, the bandwidth will be limited to 150kHz. To obtain 200kHz
bandwidth, change both C9 & C10 to 47pF.

3

Output Measurement

A sample Vout against Vin waveforms are captured and shown in Figure 4 below.

(Orange and Green traces are the input and output voltages respectively).

= 100 mV, 50kHz.

V

IN+

Vout is taken at U4 Vout node, which is at pin-3 of Connector CON2.

Figure 4. Vout vs Vin Voltage Waveforms

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Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-2502EN - July 14, 2011