Features
•Serial Peripheral Interface (SPI) Compatible
•Supports SPI Modes 0 (0,0) and 3 (1,1)
•Low Voltage and Standard Voltage Operation
–5.0 (V CC = 4.5V to 5.5V)
–2.7 (V CC = 2.7V to 5.5V)
–1.8 (V CC = 1.8V to 3.6V)
•3 MHz Clock Rate
•64-Byte Page Mode and Byte Write Operation
•Block Write Protection
–Protect 1/4, 1/2, or Entire Array
•Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection
•Self-Timed Write Cycle (5 ms Typical)
•High Reliability
–Endurance: 100,000 Write Cycles
–Data Retention: >200 Years
–ESD Protection: >4000V
•Automotive Grade and Extended Temperature Devices Available
•8-Pin PDIP, 8-Pin EIAJ SOIC, 8-Pin and 16-Pin JEDEC SOIC, 14-Pin and 20-Pin TSSOP, and 8-Pin Leadless Array Packages
Description
The AT25128/256 provides 131,072/262,144 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The devices are available in
Pin Configurations
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Pin Name |
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Chip Select |
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CS |
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SCK |
Serial Data Clock |
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SI |
Serial Data Input |
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SO |
Serial Data Output |
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GND |
Ground |
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VCC |
Power Supply |
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Write Protect |
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WP |
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Suspends Serial Input |
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HOLD |
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NC |
No Connect |
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DC |
Don't Connect |
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14-Lead TSSOP
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CS |
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1 |
14 |
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VCC |
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SO |
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2 |
13 |
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HOLD |
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NC |
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3 |
12 |
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NC |
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NC |
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4 |
11 |
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NC |
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NC |
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5 |
10 |
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NC |
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6 |
9 |
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SCK |
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WP |
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GND |
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7 |
8 |
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SI |
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16-Pin SOIC
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CS |
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1 |
16 |
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VCC |
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SO |
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2 |
15 |
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HOLD |
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NC |
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3 |
14 |
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NC |
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NC |
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4 |
13 |
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NC |
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NC |
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5 |
12 |
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NC |
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NC |
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6 |
11 |
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NC |
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7 |
10 |
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SCK |
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WP |
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GND |
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8 |
9 |
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SI |
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(continued)
20-Lead TSSOP*
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NC |
1 |
20 |
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NC |
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2 |
19 |
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VCC |
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CS |
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SO |
3 |
18 |
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HOLD |
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SO |
4 |
17 |
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HOLD |
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NC |
5 |
16 |
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NC |
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NC |
6 |
15 |
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NC |
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7 |
14 |
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SCK |
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WP |
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GND |
8 |
13 |
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SI |
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DC |
9 |
12 |
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DC |
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NC |
10 |
11 |
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NC |
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8-Pin PDIP |
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8-Pin SOIC |
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8-Pin Leadless Array |
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VCC |
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CS |
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CS |
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1 |
8 |
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VCC |
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CS |
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1 |
8 |
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VCC |
8 |
1 |
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HOLD |
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SO |
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SO |
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2 |
7 |
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SO |
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2 |
7 |
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7 |
2 |
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HOLD |
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HOLD |
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SCK |
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WP |
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3 |
6 |
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SCK |
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3 |
6 |
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SCK |
6 |
3 |
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WP |
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WP |
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SI |
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GND |
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GND |
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4 |
5 |
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SI |
GND |
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4 |
5 |
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SI |
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5 |
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4 |
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Bottom View
*Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility.
SPI Serial |
EEPROMs |
128K (16,384 x 8) |
256K (32,768 x 8) |
AT25128 |
AT25256 |
Rev. 0872E–08/98 |
1 |
space saving 8-pin PDIP (AT25128/256), 8-pin EIAJ SOIC (AT25128/256), 8-pin and 16-pin JEDEC SOIC (AT25128), 14-pin TSSOP (AT25128), 20-pin TSSOP (AT25128/256), and 8-pin Leadless Array (AT25128/256) packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
The AT25128/256 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely selftimed, and no separate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status regis-
ter. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
Absolute Maximum Ratings*
Operating Temperature .................................. |
-55°C to +125°C |
Storage Temperature ..................................... |
-65°C to +150°C |
Voltage on Any Pin |
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with Respect to Ground .................................... |
-1.0V to +7.0V |
Maximum Operating Voltage........................................... |
6.25V |
DC Output Current ........................................................ |
5.0 mA |
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Block Diagram
16384/32768 x 8 |
2 AT25128/256
AT25128/256
Pin Capacitance
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
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Test Conditions |
Max |
Units |
Conditions |
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COUT |
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Output Capacitance (SO) |
8 |
pF |
VOUT = 0V |
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CIN |
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Input Capacitance |
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SCK, SI, |
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6 |
pF |
VIN = 0V |
(CS, |
WP, |
HOLD) |
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Note: |
1. This parameter is characterized and is not 100% tested. |
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DC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, V CC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V(unless otherwise noted).
Symbol |
Parameter |
Test Condition |
Min |
Typ |
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Max |
Units |
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VCC1 |
Supply Voltage |
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1.8 |
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3.6 |
V |
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VCC2 |
Supply Voltage |
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2.7 |
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5.5 |
V |
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VCC3 |
Supply Voltage |
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4.5 |
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5.5 |
V |
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ICC1 |
Supply Current |
VCC = 5.0V at 1 MHz, SO = Open, Read |
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2.0 |
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3.0 |
mA |
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ICC2 |
Supply Current |
VCC = 5.0V at 2 MHz, SO = Open, Read, Write |
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3.0 |
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5.0 |
mA |
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ISB1 |
Standby Current |
VCC = 1.8V, |
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= VCC |
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0.1 |
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2.0 |
μA |
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CS |
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ISB2 |
Standby Current |
VCC = 2.7V, |
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= VCC |
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0.2 |
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2.0 |
μA |
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CS |
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ISB3 |
Standby Current |
VCC = 5.0V, |
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= VCC |
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2.0 |
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5.0 |
μA |
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CS |
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IIL |
Input Leakage |
VIN = 0V to VCC |
-3.0 |
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3.0 |
μA |
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IOL |
Output Leakage |
VIN = 0V to VCC, TAC = 0°C to 70°C |
-3.0 |
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3.0 |
μA |
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V (1) |
Input Low Voltage |
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-1.0 |
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V |
CC |
x 0.3 |
V |
IL |
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VIH(1) |
Input High Voltage |
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VCC x 0.7 |
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VCC + 0.5 |
V |
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VOL1 |
Output Low Voltage |
4.5 ≤ VCC ≤ 5.5V |
IOL = 3.0 mA |
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0.4 |
V |
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VOH1 |
Output High Voltage |
IOH = -1.6 mA |
vCC - 0.8 |
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V |
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VOL2 |
Output Low Voltage |
1.8V≤ VCC ≤3.6V |
IOL = 0.15mA |
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0.2 |
V |
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VOH2 |
Output High Voltage |
IOH = -100μA |
VCC - 0.2 |
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V |
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Note: 1. |
VIL and VIH max are reference only and are not tested. |
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3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol |
Parameter |
Voltage |
Min |
Max |
Units |
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4.5 - 5.5 |
0 |
3.0 |
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fSCK |
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SCK Clock Frequency |
2.7 - 5.5 |
0 |
2.1 |
MHz |
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1.8 - 3.6 |
0 |
0.5 |
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4.5 - 5.5 |
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2 |
μs |
tRI |
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Input Rise Time |
2.7 - 5.5 |
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2 |
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1.8 - 3.6 |
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2 |
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4.5 - 5.5 |
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2 |
μs |
tFI |
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Input Fall Time |
2.7 - 5.5 |
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2 |
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1.8 - 3.6 |
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2 |
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4.5 - 5.5 |
150 |
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tWH |
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SCK High Time |
2.7 - 5.5 |
200 |
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1.8 - 3.6 |
800 |
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4.5 - 5.5 |
150 |
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tWL |
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SCK Low Time |
2.7 - 5.5 |
200 |
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1.8 - 3.6 |
800 |
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4.5 - 5.5 |
250 |
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tCS |
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CS |
High Time |
2.7 - 5.5 |
250 |
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1.8 - 3.6 |
1000 |
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4.5 - 5.5 |
100 |
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tCSS |
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CS |
Setup Time |
2.7 - 5.5 |
250 |
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1.8 - 3.6 |
1000 |
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4.5 - 5.5 |
150 |
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tCSH |
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CS |
Hold Time |
2.7 - 5.5 |
250 |
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1.8 - 3.6 |
1000 |
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4.5 - 5.5 |
30 |
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tSU |
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Data In Setup Time |
2.7 - 5.5 |
50 |
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1.8 - 3.6 |
100 |
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4.5 - 5.5 |
50 |
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tH |
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Data In Hold Time |
2.7 - 5.5 |
50 |
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1.8 - 3.6 |
100 |
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4.5 - 5.5 |
100 |
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tHD |
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Hold |
Setup Time |
2.7 - 5.5 |
100 |
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ns |
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1.8 - 3.6 |
400 |
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4.5 - 5.5 |
200 |
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tCD |
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Hold |
Hold Time |
2.7 - 5.5 |
300 |
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ns |
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1.8 - 3.6 |
400 |
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4.5 - 5.5 |
0 |
150 |
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tV |
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Output Valid |
2.7 - 5.5 |
0 |
200 |
ns |
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1.8 - 3.6 |
0 |
800 |
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4.5 - 5.5 |
0 |
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tHO |
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Output Hold Time |
2.7 - 5.5 |
0 |
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ns |
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1.8 - 3.6 |
0 |
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4 AT25128/256
AT25128/256
AC Characteristics (Continued)
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol |
Parameter |
Voltage |
Min |
Max |
Units |
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4.5 - 5.5 |
0 |
100 |
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tLZ |
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Hold |
to Output Low Z |
2.7 - 5.5 |
0 |
200 |
ns |
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1.8 - 3.6 |
0 |
300 |
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4.5 - 5.5 |
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100 |
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tHZ |
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Hold |
to Output High Z |
2.7 - 5.5 |
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200 |
ns |
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1.8 - 3.6 |
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300 |
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4.5 - 5.5 |
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200 |
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tDIS |
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Output Disable Time |
2.7 - 5.5 |
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250 |
ns |
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1.8 - 3.6 |
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1000 |
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4.5 - 5.5 |
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5 |
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tWC |
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Write Cycle Time |
2.7 - 5.5 |
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10 |
ms |
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1.8 - 3.6 |
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10 |
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Endurance(1) |
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5.0V, 25°C, Page Mode |
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100K |
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Write |
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Cycles |
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Note: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. |
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5
Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25128/256 always operates as a slave.
TRANSMITTER/RECEIVER: The AT25128/256 has separate pins designated for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128/256, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25128/256 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128/256. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the
WPEN bit in the status register is “0”. This will allow the user to install the AT25128/256 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”.
SPI Serial Interface
AT25128/256 |
6 AT25128/256