Features
•Low Voltage and Standard Voltage Operation
–5.0 (V CC = 4.5V to 5.5V)
–2.7 (V CC = 2.7V to 5.5V)
–1.8 (V CC = 1.8V to 3.6V)
•Internally Organized 16,384 x 8 and 32,768 x 8
•2-Wire Serial Interface
•Schmitt Trigger, Filtered Inputs for Noise Suppression
•Bidirectional Data Transfer Protocol
•1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
•Write Protect Pin for Hardware and Software Data Protection
•64-Byte Page Write Mode (Partial Page Writes Allowed)
•Self-Timed Write Cycle (5 ms typical)
•High Reliability
–Endurance: 100,000 Write Cycles
–Data Retention: 40 Years
–ESD Protection: > 4000V
•Automotive Grade and Extended Temperature Devices Available
•8-Pin JEDEC PDIP, 8-Pin JEDEC and EIAJ SOIC, 14-Pin TSSOP, and 8-Pin Leadless Array Packages
Description
The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device’s cascadable feature allows up to 4 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The devices are available in space-saving 8-pin JEDEC PDIP, 8-pin EIAJ, 8-pin JEDEC SOIC, 14-pin TSSOP, and 8-pin LAP packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
Pin Configurations |
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8-Pin PDIP |
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Pin Name |
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Function |
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A0 |
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1 |
8 |
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VCC |
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A0 to A1 |
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Address Inputs |
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A1 |
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2 |
7 |
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WP |
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SDA |
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Serial Data |
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NC |
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3 |
6 |
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SCL |
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GND |
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4 |
5 |
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SDA |
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SCL |
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Serial Clock Input |
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WP |
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Write Protect |
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8-Pin SOIC |
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NC |
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No Connect |
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A0 |
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1 |
8 |
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VCC |
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14-Pin TSSOP |
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A1 |
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2 |
7 |
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WP |
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NC |
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3 |
6 |
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SCL |
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A0 |
1 |
14 |
VCC |
GND |
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4 |
5 |
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SDA |
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A1 |
2 |
13 |
WP |
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NC |
3 |
12 |
NC |
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NC |
4 |
11 |
NC |
8-Pin Leadless Array |
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NC |
5 |
10 |
NC |
VCC |
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A0 |
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8 |
1 |
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NC |
6 |
9 |
SCL |
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WP |
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7 |
2 |
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A1 |
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GND |
7 |
8 |
SDA |
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SCL |
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6 |
3 |
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NC |
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SDA |
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5 |
4 |
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GND |
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Bottom View
2-Wire Serial |
EEPROMs |
128K (16,384 x 8) |
256K (32,768 x 8) |
AT24C128 |
AT24C256 |
Rev. 0670C–08/98 |
1 |
Absolute Maximum Ratings*
..................................Operating Temperature |
-55°C to +125°C |
*NOTICE: Stresses beyond those listed under “Absolute |
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Maximum Ratings” may cause permanent dam- |
Storage Temperature ..................................... |
-65°C to +150°C |
age to the device. This is a stress rating only and |
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functional operation of the device at these or any |
Voltage on Any Pin |
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other conditions beyond those indicated in the |
with Respect to Ground ..................................... |
-1.0V to +7.0V |
operational sections of this specification is not |
Maximum Operating Voltage |
6.25V |
implied. Exposure to absolute maximum rating |
conditions for extended periods may affect device |
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DC Output Current |
5.0 mA |
reliability. |
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Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with AT24C32/64. When the pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pins are not hardwired, the default A1 and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write operation creates a software write protect function.
Memory Organization
AT24C128/256, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as 256/512 pages of 64bytes each. Random word addressing requires a 14/15-bit data word address.
2 AT24C128/256
AT24C128/256
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol |
Test Condition |
Max |
Units |
Conditions |
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CI/O |
Input/Output Capacitance (SDA) |
8 |
pF |
VI/O = 0V |
CIN |
Input Capacitance (A0, A1, SCL) |
6 |
pF |
VIN = 0V |
Note: This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol |
Parameter |
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Test Condition |
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Min |
Typ |
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Max |
Units |
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VCC1 |
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Supply Voltage |
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1.8 |
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3.6 |
V |
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VCC2 |
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Supply Voltage |
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2.7 |
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5.5 |
V |
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VCC3 |
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Supply Voltage |
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4.5 |
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5.5 |
V |
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ICC1 |
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Supply Current |
VCC = 5.0V |
READ at 400 kHz |
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1.0 |
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2.0 |
mA |
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ICC2 |
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Supply Current |
VCC = 5.0V |
WRITE at 400 kHz |
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2.0 |
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3.0 |
mA |
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ISB1 |
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Standby Current |
VCC = 1.8V |
VIN = VCC or VSS |
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0.2 |
μA |
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(1.8V option) |
VCC = 3.6V |
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2.0 |
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ISB2 |
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Standby Current |
VCC = 2.7V |
VIN = VCC or VSS |
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0.5 |
μA |
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(2.7V option) |
VCC = 5.5V |
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6.0 |
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ISB3 |
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Standby Current |
VCC = 4.5 - 5.5V |
VIN = VCC or VSS |
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6.0 |
μA |
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(5.0V option) |
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ILI |
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Input Leakage Current |
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VIN = VCC or VSS |
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0.10 |
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3.0 |
μA |
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ILO |
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Output Leakage Current |
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VOUT = VCC or VSS |
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0.05 |
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3.0 |
μA |
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VIL |
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Input Low Level(Note:) |
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-0.6 |
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VCC x 0.3 |
V |
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V |
IH |
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Input High Level(Note:) |
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V |
CC |
x 0.7 |
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V |
+ 0.5 |
V |
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CC |
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VOL2 |
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Output Low Level |
VCC = 3.0V |
IOL = 2.1 mA |
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0.4 |
V |
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VOL1 |
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Output Low Level |
VCC = 1.8V |
IOL = 0.15 mA |
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0.2 |
V |
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Note: |
VIL min and VIH max are reference only and are not tested |
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3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.
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1.8-volt |
2.7-volt |
5.0-volt |
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Symbol |
Parameter |
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Units |
Min |
Max |
Min |
Max |
Min |
Max |
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fSCL |
Clock Frequency, SCL |
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100 |
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400 |
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1000 |
kHz |
tLOW |
Clock Pulse Width Low |
4.7 |
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1.3 |
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0.6 |
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μs |
tHIGH |
Clock Pulse Width High |
4.0 |
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1.0 |
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0.4 |
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μs |
tAA |
Clock Low to Data Out Valid |
0.1 |
4.5 |
0.05 |
0.9 |
0.05 |
0.55 |
μs |
tBUF |
Time the bus must be free before a new |
4.7 |
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1.3 |
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0.5 |
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μs |
transmission can start(1) |
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tHD.STA |
Start Hold Time |
4.0 |
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0.6 |
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0.25 |
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μs |
tSU.STA |
Start Set-up Time |
4.7 |
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0.6 |
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0.25 |
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μs |
tHD.DAT |
Data In Hold Time |
0 |
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0 |
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0 |
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μs |
tSU.DAT |
Data In Set-up Time |
200 |
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100 |
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100 |
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tR |
Inputs Rise Time(1) |
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1.0 |
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0.3 |
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0.3 |
μs |
tF |
Inputs Fall Time(1) |
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300 |
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300 |
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100 |
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tSU.STO |
Stop Set-up Time |
4.7 |
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0.6 |
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0.25 |
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μs |
tDH |
Data Out Hold Time |
100 |
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50 |
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50 |
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tWR |
Write Cycle Time |
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20 |
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10 |
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10 |
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Endurance(1) |
5.0V, 25°C, Page Mode |
100K |
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100K |
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100K |
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Write |
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Cycles |
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Notes: 1. This parameter is characterized and is not 100% tested.
2.AC measurement conditions:
RL (connects to VCC): 1.3KΩ (2.7V, 5V), 10KΩ (1.8V)
Input pulse voltages: 0.3VCC to 0.7VCC Input rise and fall times: ≤50ns
Input and output timing reference voltages: 0.5VCC
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The AT24C128/256 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.
4 AT24C128/256
AT24C128/256
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL |
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SDA |
8th BIT ACK |
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WORD n |
(1) |
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tWR |
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STOP |
START |
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CONDITION |
CONDITION |
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
5