ATMEL Corporation AT17C256-10PI, AT17C256-10PC, AT17C256-10JI, AT17C256-10JC, AT17C128-10SI, AT17C128-10SC, AT17C128-10PI, AT17LV256-10SI, AT17LV256-10SC, AT17LV256-10PI, AT17LV256-10PC, AT17LV256-10JI, AT17LV256-10JC, AT17LV128-10SI, AT17LV128-10SC, AT17LV128-10PI, AT17LV128-10PC, AT17LV128-10JI, AT17LV128-10JC, AT17C128-10JI, AT17C128-10JC, AT17C65-10SI, AT17C65-10SC, AT17C65-10PI, AT17C65-10PC, AT17C65-10JI, AT17C65-10JC, AT17C256-10SI, AT17C256-10SC, AT17LV65-10SI, AT17LV65-10SC, AT17LV65-10PI, AT17LV65-10PC, AT17LV65-10JI, AT17LV65-10JC, AT17C128-10PC Datasheet

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Features

E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories Designed To Store Configuration Programs For Programmable Gate Arrays

Simple Interface to SRAM FPGAs Requires Only One User I/O Pin

Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs, XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000

Cascadable To Support Additional Configurations or Future Higher-density Arrays (17C128 and 17C256 only)

Low-power CMOS EEPROM Process

Programmable Reset Polarity

Available In the Space-efficient Plastic DIP or Surface-mount PLCC and SOIC Packages

In-System Programmable Via 2-Wire Bus

Emulation of 24CXX Serial EPROMs

Available in 3.3V ± 10% LV Version

Description

The AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA Configuration EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-pin DIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a special feature of the AT17 Series, the user can select the polarity of the reset function by programming a special EEPROM bit.

The AT17 Series can be programmed with industry standard programmers.

Pin Configurations

20-pin PLCC

 

 

 

 

20-Pin SOIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-Pin DIP

AT17 Series

FPGA Configuration E2PROM

65K, 128K and 256K

AT17C65

AT17C128

AT17C256

0391E-A–5/97

1

ATMEL Corporation AT17C256-10PI, AT17C256-10PC, AT17C256-10JI, AT17C256-10JC, AT17C128-10SI, AT17C128-10SC, AT17C128-10PI, AT17LV256-10SI, AT17LV256-10SC, AT17LV256-10PI, AT17LV256-10PC, AT17LV256-10JI, AT17LV256-10JC, AT17LV128-10SI, AT17LV128-10SC, AT17LV128-10PI, AT17LV128-10PC, AT17LV128-10JI, AT17LV128-10JC, AT17C128-10JI, AT17C128-10JC, AT17C65-10SI, AT17C65-10SC, AT17C65-10PI, AT17C65-10PC, AT17C65-10JI, AT17C65-10JC, AT17C256-10SI, AT17C256-10SC, AT17LV65-10SI, AT17LV65-10SC, AT17LV65-10PI, AT17LV65-10PC, AT17LV65-10JI, AT17LV65-10JC, AT17C128-10PC Datasheet

Controlling The AT17 Series Serial EEPROMs

Most connections between the FPGA device and the Serial EEPROM are simple and self-explanatory.

The DATA output of the AT17 Series drives DIN of the FPGA devices.

The master FPGA CCLK output drives the CLK input of the AT17 Series.

The CEO output of any AT17C/LV128/256 drives the CE input of the next AT17C/LV128/256 in a cascade chain of PROMs.

SER_EN must be connected to VCC.

There are, however, two different ways to use the inputs CE and OE, as shown in the AC Characteristics waveforms.

Condition 1

The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel (Figure 1). Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configura-

tion cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17 Series does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle.

Condition 2

The FPGA D/P output drives only the CE input of the AT17 Series, while its OE input is driven by the inversion of the input to the FPGA RESET input pin. This connection works under all normal circumstances, even when the user aborts

a configuration before D/P has gone High. A High level on the RESET/OE input to the AT17C/LVxxx – during FPGA reset – clears the Configurator's internal address pointer, so that the reconfiguration starts at the beginning. The AT17 Series does not require an inverter since the RESET polarity is programmable.

Block Diagram

2

AT17 Series

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AT17 Series

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Configurations

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLCC/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SOIC

DIP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

Pin

 

Name

 

I/O

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

1

 

DATA

 

I/O

Three-state DATA output for reading. Input/Output pin for programming.

 

 

 

 

 

 

 

 

 

 

 

 

4

2

 

CLK

 

I

Clock input. Used to increment the internal address and bit counter for reading

 

 

and programming.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET/Output Enable input (when

 

 

 

 

 

is High). A Low level on both the

 

 

 

 

 

 

 

 

 

 

SER_EN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

inputs enables the data output driver. A High level on

6

3

 

 

 

 

 

 

 

 

CE

and RESET/OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET/OE

 

 

RESET/OE resets both the addresss and bit counters. A logic polarity of this

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

input is programmable as either RESET/OE

or RESET/OE. This document

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

describes the pin as RESET/OE.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

4

 

 

 

 

 

 

I

Chip Enable input. Used for device selection. A Low level on both

 

 

 

and

 

 

CE

CE

OE

 

 

 

 

 

 

 

 

 

 

enables the data output driver. A High level on

 

disables both the address

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

and bit counters and forces te device into a low power mode. Note this pin will

 

 

 

 

 

 

 

 

 

 

not enable/disable the device in 2-wire Serial mode (ie; when

SER_EN

is Low).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

5

 

GND

 

 

Ground Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

6

 

 

 

 

 

 

O

Chip Enable Out output. This signal is asserted Low on the clock cycle following

CEO

 

 

 

 

 

 

 

 

 

 

the last bit read from the memory. It will stay Low as long as CE and

 

are

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

both Low. It will then follow

 

until

 

goes High. Thereafter

 

will stay

 

 

 

 

 

 

 

 

 

 

CE

OE

CEO

 

 

 

 

 

 

 

 

 

 

High until the entire PROM is read again and senses the status of RESET

 

 

 

 

 

 

 

 

 

 

polarity.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A2

 

I

Device selection input, A2. This is used to enable (or select) the device during

 

 

 

 

 

 

 

 

 

 

programming and when

 

is Low (see Programming Guide for more

 

 

 

 

 

 

 

 

 

 

SER_EN

 

 

 

 

 

 

 

 

 

 

details).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial enable is normally high during FPGA loading operations. Bringing

17

7

 

SER_EN

 

I

 

 

SER_EN low, enables the 2-wire serial interface for programming.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

8

 

VCC

 

 

+3.3V/+5V power supply pin.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Absolute Maximum Ratings*

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*NOTICE:

Stresses beyond those listed under “Absolute

Operating Temperature.........................-55°C to +125°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Maximum Ratings” may cause permanent dam-

Storage Temperature............................-65°C to +150°C

 

 

 

 

 

 

 

age to the device. This is a stress rating only and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

functional operation of the device at these or any

Voltage on Any Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

other conditions beyond those indicated in the

with Respect to Ground.................... -0.1V to VCC + 0.5V

 

 

 

 

 

 

 

operational sections of this specification is not

 

 

 

 

 

 

 

implied. Exposure to absolute maximum rating

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Supply Voltage (Vcc) .............................. -0.5 V to +7.0V

 

 

 

 

 

 

 

conditions for extended periods may affect device

 

 

 

 

 

 

 

reliability.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Maximum Soldering Temp. (10 sec. @ 1/16 in.)... 260°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ESD (RZAP = 1.5K, CZAP = 100pF) ........................2000V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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