Atmel TSEV83102G0B User Manual

ADC 10-bit 2 Gsps Evaluation
Board - TSEV83102G0B

..............................................................................................

User Guide

Table of Contents

Section 1

Overview...............................................................................................1-1

1.1 Description................................................................................................1-1

1.2 TSEV83102G0B Evaluation Board...........................................................1-2

1.3 Board Mechanical Characteristics.............................................................1-3

1.4 Analog Input, Clock Input and De-embedding Fixture Accesses..............1-4

1.5 Digital Outputs Accesses ..........................................................................1-4

1.6 Power Supplies and Ground Access es.................. ...... ....... ...... ................1-4

1.7 ADC Function Setting Accesses...............................................................1-4

Section 2

Layout Information................................................................................2-1

2.1 Board ........................................................................................................2-1

2.2 AC Inputs/Digital Outputs................................ ....... ...... ....... ...... ....... ...... ...2-1

2.3 DC Function Settings ................................................................................2-1

2.4 Power Supplies.........................................................................................2-2

Section 3

Operating Procedur es and

Characteristics......................................................................................3-1

3.1 Introduction ...............................................................................................3-1

3.2 Operating Procedure (ECL Mode) ............................................................3-1

3.3 Use with DMUX Evaluation Board ............................................................3-2

3.4 Electrical Characteristics...........................................................................3-3

3.5 Operating Charcteristics............................................................................3-4

Section 4

Application Information.................................. .... ...................................4-1

4.1 Introduction ...............................................................................................4-1

4.2 Analog Inputs............................................................................................4-1

4.3 Clock Inputs ..............................................................................................4-1

4.4 Setting the Digital Output Data Format.....................................................4-1

4.5 ADC Gain Adjust.......................................................................................4-2

4.6 SMA Connectors and Microstrip Lines De-embedding Fixture .................4-2

4.7 Die Junction Temperature Monitoring.......................................................4-3

4.8 Decimation Function .................................................................................4-5

4.9 Pattern Generator Enable .........................................................................4-5

4.10 Data Ready Output Signal Reset..............................................................4-6

4.11 Sampling Delay Adjusting .........................................................................4-6

4.12 Test Bench Description.............................................................................4-7

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Table of Contents

Section 5

Package Description.............................................................................5-1

5.1 TS83102G0B Pinout.................... ...... ....... ...... ....... ...... ....... ...... ....... .........5-1

5.2 Thermal Characteristics............................................................................5-3

5.2.1 Thermal Resistance from Junction to Ambient: Rthja ........................5-3

5.2.2 Thermal Resistance from Junction to Case: Rthjc .............................5-4

5.2.3 Heatsink..............................................................................................5-4

5.3 Ordering Information.................................................................................5-5

Section 6

Schematics...........................................................................................6-1

6.1 TSEV83102G0B Electrical Schematic......................................................6-1

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Section 1
Overview

1.1 Description

The TSEV83102G0B Evaluati on Board (EB) is a p rototype board which has been
designed in order to facilitate the evaluation and the characterization of the
TS83102G0B device (in CBGA152) up to its 3 GHz full power bandwidth at up to 2 Gsps
in the extended temperature range.

The high speed of th e TS831 02G0 B requi res careful atten tion t o ci rcuit d esig n and lay­out to achieve optimal per formanc e. This four met al layer board w ith an inter nal groun d
plane has the function s that allow a quic k and simple ev aluation of the TS83102G0B
ADC performances over the temperature range.

The TS83102G0B Evaluation Board (EB) is very straightforward as it only implements
the TS83102G0B ADC device, SMA connectors for input/output accesses and a

2.54 mm pitch connec tor com patible with high speed ac qui siti on s y ste m hig h freq uen cy
probes.

The board has been desi gned to be fully co mpatible with Atme l’s DMUX evaluatio n
board (TSEV81102G0).

The board also implements a de-embedding fixture in order to facilitate the evaluation of
the high frequency insertion loss of the input microstrip lines.

The board is constructed l ike a sand wich of two dielec tric layers , featuring low inser tion
loss and enhanced thermal characteristics for operation in the high frequency domain
and extended temperature range.

The board dimensions are 120 mm x 150 mm.
The board set comes fully assembled and tested, with the TS83102G0B installed and

with a heatsink.

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Overview

1.2 TSEV83102G0B
Evaluation Board

Figure 1-1. TSEV83102G0B Block Diagram

CLK

Differential

Clock inputs

CLKB

VIN

Differential

analog inputs

VINB

TEST

GAIN

Z0 = 50Ω

Z0 = 50Ω

Z0 = 50Ω

Z0 = 50Ω

VEE

CLK

CLKB

TS83102G0B

VIN

VINB

GA

PGEB

DRRB

VCC

GND

VPLUSD

VEE

DR/DRB
D0/D0B

D7/D7B
PC/PCB

VCC = +5V

GND = 0V

VPLUSD = -0.8V (ECL)
VPLUSD = 1.6V (LVDS)

VEE = -5V

Z0 = 50Ω
Z0 = 50Ω

Z0 = 50Ω
Z0 = 50Ω

DRRB

CAL1
CAL2

VCC

VEE

GND

DVEE

SDA

OA

+5V

+5V

+5V

DVEE

SDA

SDAEN

L = 50 mm typ
LVIN/VINb = LCLK/CLKb = 43 mm typ
Loutputs = 58 mm typ

Short-circuit
possibility
here

DIODE

DVEE = -5V

J - diode

V - diode

VEE

B/BG

V-GND

I-GND

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Overview

1.3 Board
Mechanical
Characteristics

The board’s layer number, thickness, and functions are given below, from top to bottom.

Table 1-1. Board’s Layer Thickness Profile

Layer Characteristics

Layer 1
Copper layer

Layer 2
RO4003 dielectric layer

(Hydrocarbon/Wovenglass)

Layer 3
Copper layer

Layer 4
BT/Epoxy dielectric layer

Layer 5
Copper layer

Layer 6
BT/Epoxy dielectric layer

Layer 7
Copper layer

Copper thickness = 40 µm
AC signal traces = 50Ω microstrip lines
DC signal traces (B/GB, GAIN, DIODE, OA, TEST, SDA)

Layer thickness = 200 µm
Dielectric constant = 3.4 at 10 GHz

-0.044 dB/inch insertio n loss at 2.5 GHz

-0.318 dB/inch insertion loss at 18 GHz
Copper thickness = 39 µm

Ground plane = reference plane 50Ω microstrip return

Layer thickness = 330 µm

Copper thickness = 35 µm
Power and ground planes

Layer thickness = 330 µm

Copper thickness = 35 µm
Power and ground planes (identical to layer 5)

Layer 8
BT/Epoxy dielectric layer

Layer 9
Copper layer

Layer 10
BT/Epoxy dielectric layer

Layer 11
Copper layer

Layer thickness = 330 µm

Copper thickness = 35 µm
Ground planes (identical to layer 3)

Layer thickness = 200 µm

Copper thickness = 35 µm
Power and ground planes

The TSEV83102G0B is an ele ven la yer PC B made of s ix copper laye rs and five die lec­tric layers. The si x metal la yers corres pond respec tively from top to bottom to the A C
and DC signals layer (layer 1), two ground layers (layers 3 and 5), and one supply layer
(layer 7).

Considering the s evere mec hanica l constr aints due to the wide temperat ure rang e and
the high frequency domain in which the board is to operate, it is necessary to use a
sandwich of two different dielectric materials, with specific characteristics:

 A low insertion loss RO4003 Hydrocarbon/Wovenglass dielectric layer of 200 µm

thickness, chosen for its low loss (-0.318 dB/inch) and enhanced dielectric
consistency in the high frequency domain. The RO4003 dielectric layer is dedicated
to the routing of the 50Ω impedance signal traces (the RO4003 typical dielectric
constant is 3.4 at 10 GHz). The RO4003 dielectric layer characteristics are very close
to PTFE in terms of insertion loss characteristics.

 A BT/Epoxy dielectric layer of 0.9 mm total thickness which is sandwiched between

the upper ground plane and the back-side supply layer.

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Overview

The BT/Epoxy layer has been ch os en be ca us e of i ts e nhanced mechanical charac teri s­tics for elevated temperature operation. The typical dielectric constant is 4.5 at 1 MHz.

More precisely, the BT/E poxy diel ectric layer offe rs enha nced ch aracteris tics co mpare d
to FR4 Epoxy, namely:

 Higher operating temperature values: 170°C (125°C for FR4).
 Better withstanding of thermal shocks (-65°C up to 170°C).

The total board thi ckness is 1.6 mm. The prev iously desc ribed mechani cal and fre­quency characteristics makes the board particularly suitable for device evaluation and
characterization in the high frequency domain and in military temperature ranges.

1.4 Analog Input,
Clock Input and
De-embedding
Fixture Access es

1.5 Digital Outputs
Accesses

1.6 Power Supplies
and Ground
Accesses

1.7 ADC Function
Setting Accesse s

The differential active inputs (Analog, Clock, De-embedding fixture) are provided by
SMA connectors.

Reference: VITELEC 142-0701-851.
Connector mounting plates have been used for fastening the SMA connectors.

Access to the differential output data port is provided by a 2.54 mm pitch connector,
compatible with the high spee d digital acqui sition syst em. It enables acc ess to the con­verter output data, as well as proper 50Ω differential termination.

The power supply accesses are provided by five 2 mm section banana jacks respec­tively for DV

The power supply access is provided by one 4 mm section banana jack for V
The Ground accesses are provided by four 2 mm and one 4 mm banana jacks.

For ADC function setting accesses (B/GB, Die junction temp., Test), 2 mm section
banana jacks are provided.

Three potentiometers a re provided for ADC gain adj us t, S am pli ng de la y adj ust and O ff­set adjust.

EE

, V

EET

, VDD, V

PLUSD

and VCC.

EE

.

One sub-screw is provided for Asynchronous data ready reset.

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Section 2

Layout Information

2.1 Board

2.2 AC Inputs/Digital
Outputs

The TS83102G0B requires proper board layout for optimum full speed operation.
The following explains th e board l ayout recomm endations a nd demonstrates how the

Evaluation Board fulfills these implementation constraints.
A single low impedance ground plane is rec ommended, since it allows the user to lay

out signal traces and power planes without interrupting the ground plane.
Therefore a multi-layer board structure has been retained for the TSEV83102G0B.
Six copper metal layers are used, dedicated respectively (from top to bottom) to the sig-

nal traces, ground planes and power supplies.

The board uses 50Ω impedance micros trip line s for the diffe rentia l analog i nputs, cloc k
inputs, and differential digital outputs.

The input signals an d c lock si gna ls mus t b e r oute d on one l ay er on ly, without using any
through-hole vias. The line lengths are matched to within 2 mm.

The digital output lines are 50Ω differentially terminated.
The output data trace lengths are matched to within 0.25 inch (6 mm) to min imize the

data output delay skew.
For the TSEV83102G0B the propagation delay is approximately 6.1 ps/mm

(155 ps/inch). The RO4003 typical dielectric constant is 3.4 at 10 GHz.
For more informations about different output termination options refer to the specifica-

tion application notes.

2.3 DC Function
Settings

TSEV83102G0B - Evaluation Board User Guide 2-1

The DC signal traces are low impedance.
They have been routed with a 50Ω impeda nce near the devic e because of spac e

restriction.

Rev. 2166B–BDC–04/03

Layout Information

2.4 Power Supplies

The bottom metal layers 5 and 7 and 11 are dedicated to power supply traces (VEE,
DV

, V

EE

, VDD, V

EET

PLUSD

and VCC).

The supply traces are approximately 6 mm wide in order to present low impedance, and
are surrounded by a ground plane connected to the two inner ground planes.

The analog and digital negative power supply traces are independent, but the possibility
exists to short-circuit both supplies on the top metal layer).

No difference in ADC high speed performance is observed when connecting both nega­tive supply planes together. Obviously one single negative supply plane could be used
for the circuit.

Each power supply incoming is bypassed by a 1 µF Tantalum capacitor in parallel with
1 nF chip capacitor.

Each power supply access is decoupled very close to the device by 10 nF and 100 pF
surface mount chip capacitors in parallel.

Note: The decoupling capacitors are superposed. In this configuration, the 100 pF capacitors

must be mounted first.

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