ATMEL TS87C52X2 User Manual
BDTIC www.bdtic.com/ATMEL
Features
• 80C52 Compatible
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/Counters
– 256 Bytes Scratchpad RAM
• High-speed Architecture
• 40 MHz at 5V, 30 MHz at 3V
• X2 Speed Improvement Capability (6 Clocks/Machine Cycle)
– 30 MHz at 5V, 20 MHz at 3V (Equivalent to 60 MHz at 5V, 40 MHz at 3V)
• Dual Data Pointer
• On-chip ROM/EPROM (8Kbytes)
• Programmable Clock Out and Up/Down Timer/Counter 2
• Asynchronous Port Reset
• Interrupt Structure with
– 6 Interrupt Sources
– 4 Level Priority Interrupt System
• Full Duplex Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
• Low EMI (Inhibit ALE)
• Power Control Modes
– Idle Mode
– Power-down Mode
– Power-off Flag
• Once Mode (On-chip Emulation)
• Power Supply: 4.5 - 5.5V, 2.7 - 5.5V
• Temperature Ranges: Commercial (0 to 70
• Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 (13.9 footprint)
o
C) and Industrial (-40 to 85oC)
8-bit
Microcontroller
8 Kbytes
ROM/OTP,
ROMless
TS80C32X2
TS87C52X2
TS80C52X2
Description
TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions
of the 80C51 CMOS single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the 80C51 with extended ROM/EPROM
capacity (8 Kbytes), 256 bytes of internal RAM, a 6-source, 4-level interrupt system,
an on-chip oscilator and three timer/counters.
In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and an X2 speed improvement mechanism.
The fully static design of the TS80C52X2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The TS80C52X2 has 2 software-selectable modes of reduced activity for further
reduction in power consumption. In the idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
AT80C32X2
AT80C52X2
AT87C52X2
Rev. 4184I–8051–02/08
Block Diagram
Timer 0
INT
RAM
256x8
T0
T1
RxD
TxD
WR
RD
EA/VPP
PSEN
ALE/
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2) (2) (2)
Port 0P0Port 1
Port 2
Port 3
Parallel I/O Ports & Ext. Bus
P1
P2
P3
IB-bus
RESET
PROG
Vss
Vcc
(3)(3)
Timer2
T2EX
T2
(1) (1)
ROM
/EPROM
8Kx8
Table 1. Memory Size
ROM (bytes) EPROM (bytes) TOTAL RAM (bytes)
TS80C32X2 0 0 256
TS80C52X2 8k 0 256
TS87C52X2 0 8k 256
2
TS8xCx2X2
Notes: 1. Alternate function of Port 1
2. Alternate function of Port 3
4184I–8051–02/08
TS8xCx2X2
SFR Mapping
The Special Function Registers (SFRs) of the TS80C52X2 fall into the following
categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• Interrupt system registers: IE, IP, IPH
• Others: AUXR, CKCON
4184I–8051–02/08
3
Table 2. All SFRs with their address and their reset value
Bit
Addressable Non Bit Addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h FFh
F0h
E8h EFh
E0h
D8
h
D0
h
C8
h
C0
h
B8h
B0h
A8h
A0h
B
0000 0000
ACC
0000 0000
PSW
0000 0000
T2CON
0000 0000
IP
XX00 0000
P3
1111 1111
IE
0X00 0000
P2
1111 1111
T2MOD
XXXX XX00
SADEN
0000 0000
SADDR
0000 0000
RCAP2L
0000 0000
AUXR1
XXXX XXX0
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
IPH
XX00 0000
F7h
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
98h
90h
88h
80h
0000 0000
0000 0000
Reserved
4
SCON
P1
1111 1111
TCON
P0
1111 1111
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
SBUF
XXXX XXXX
TMOD
0000 0000
SP
0000 0111
TL0
0000 0000
DPL
0000 0000
TL1
0000 0000
DPH
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
XXXXXXX0
TS8xCx2X2
CKCON
XXXX XXX0
PCON
00X1 0000
4184I–8051–02/08
9Fh
97h
8Fh
87h
Pin Configuration
5 4 3 2 1 6
44 43 42 41 40
P1.4
P1.0/T2
P1.1/T2EX
P1.3
P1.2
VSS1/NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA/VPP
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
43 42 41 40 3944
38 37 36 35 34
P1.4
P1.0/T2
P1.1/T2EX
P1.3
P1.2
VSS1/NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA/VPP
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
NIC*
*NIC: No Internal Connection
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PLCC/CQPJ 44
33
32
31
30
29
28
27
26
25
24
23
PQFP44
1
2
3
4
5
6
7
8
9
10
11
18 19 20 21 22 23 24 25 26 27 28
12 13 14 15 16 17 18 19 20 21 22
VQFP44
P1.7
RST
P3.0/RxD
P3.1/TxD
P1.3
1
P1.5
P3.2/INT0
P3.3/INT1
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0 / A8
P2.1 / A9
P2.2 / A10
P2.3 / A11
P2.4 / A12
P0.4 / A4
P0.6 / A6
P0.5 / A5
P0.7 / A7
ALE/PROG
PSEN
EA/VPP
P2.7 / A15
P2.5 / A13
P2.6 / A14
P1.0 / T2
P1.1 / T2EX
VCC
P0.0 / A0
P0.1 / A1
P0.2 / A2
P0.3 / A3
PDIL/
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CDIL40
P1.6
P1.4
P1.2
P3.4/T0
TS8xCx2X2
4184I–8051–02/08
5
Mnemonic Pin Number Type Name and Function
VQFP
DIL LCC
1.4
V
SS
Vss1 1 39 I
V
CC
P0.0-P0.7
P1.0-P1.7 1-8 2-9 40-44
20 22 16 I Ground: 0V reference
40 44 38 I
39-3243-
1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout
2 3 41 I
36
37-30 I/O
1-3
Optional Ground: Contact the Sales Office for ground
connection.
Power Supply: This is the power supply voltage for normal,
idle and power-down operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0
pins that have 1s written to them float and can be used as
high impedance inputs.Port 0 pins must be polarized to Vcc
or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus
during access to external program and data memory. In this
application, it uses strong internal pull-up when emitting 1s.
Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program
verification during which P0 outputs the code bytes.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 1 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will source
current because of the internal pull-ups. Port 1 also receives
the low-order address byte during memory programming and
verification.
Alternate functions for Port 1 include:
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction
Control
P2.0-P2.7
P3.0-P3.7
6
TS8xCx2X2
21-2824-
10-1711,
10 11 5 I RXD (P3.0): Serial input port
11 13 7 O TXD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): External interrupt 0
31
13-
19
18-25 I/O
5,
7-13
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As
inputs, Port 2 pins that are externally pulled low will source
current because of the internal pull-ups. Port 2 emits the highorder address byte during fetches from external program
memory and during accesses to external data memory that
use 16-bit addresses (MOVX atDPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to
external data memory that use 8-bit addresses (MOVX atRi),
port 2 emits the contents of the P2 SFR. Some Port 2 pins
receive the high order address bits during EPROM
programming and verification: P2.0 to P2.4
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
I/O
pull-ups. Port 3 pins that have 1s written to them are pulled
high by the internal pull-ups and can be used as inputs. As
inputs, Port 3 pins that are externally pulled low will source
current because of the internal pull-ups. Port 3 also serves
the special features of the 80C51 family, as listed below.
4184I–8051–02/08
Mnemonic Pin Number Type Name and Function
VQFP
DIL LCC
13 15 9 I INT1 (P3.3): External interrupt 1
14 16 10 I T0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External data memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe
1.4
TS8xCx2X2
Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the
ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for
PSEN 29 32 26 O Program Store ENable: The read strobe to external program
EA/V
PP
31 35 29 I External Access Enable/Programming Supply Voltage:
oscillator is running, resets the device. An internal diffused
resistor to V
external capacitor to V
latching the low byte of the address during an access to
external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data
memory. This pin is also the program pulse input (PROG)
during EPROM programming. ALE can be disabled by setting
SFR’s AUXR.0 bit. With this bit set, ALE will be inactive
during internal fetches.
memory. When executing code from the external program
memory, PSEN is activated twice each machine cycle, except
that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches
from internal program memory.
EA must be externally held low to enable the device to fetch
code from external program memory locations 0000H and
3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is held
high, the device executes from internal program memory
unless the program counter contains an address greater than
3FFFH (RB) or 7FFFH (RC) EA must be held low for
ROMless devices. This pin also receives the 12.75V
programming supply voltage (VPP) during EPROM
programming. If security level 1 is programmed, EA will be
internally latched on Reset.
permits a power-on reset using only an
SS
CC.
4184I–8051–02/08
XTAL1 19 21 15 I
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier
Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.
7
XTAL1
2
CKCON reg
X2
state machine: 6 clock cycles.
CPU control
F
OSC
F
XTAL
0
1
XTAL1:2
TS80C52X2 Enhanced Features
X2 Feature
In comparison to the original 80C52, the TS80C52X2 implements some new features,
which are
:
• The X2 option
• The Dual Data Pointer
• The 4 level interrupt priority system
• The power-off flag
• The ONCE mode
• The ALE disabling
• Some enhanced features are also located in the UART and the Timer 2
The TS80C52X2 core needs only 6 clock periods per machine cycle. This feature called
”X2” provides the following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power
• Save power consumption while keeping same CPU power (oscillator power saving)
• Save power consumption by dividing dynamically operating frequency by 2 in
operating and idle modes
• Increase CPU power by 2 while keeping same crystal frequency
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. X2 bit is
validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD
mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock Generation Diagram
8
TS8xCx2X2
4184I–8051–02/08
Figure 2. Mode Switching Waveforms
XTAL1:2
XTAL1
CPU clock
X2 bit
X2 ModeSTD Mode STD Mode
The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles
per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated
(STD mode). Setting this bit activates the X2 feature (X2 mode).
Note: In order to prevent any incorrect operation while operating in X2 mode, user must be
Table 3. CKCON Register
CKCON - Clock Control Register (8Fh)
TS8xCx2X2
aware that all peripherals using clock frequency as time reference (UART, timers) will
have their time reference divided by two. For example a free running timer generating an
interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud
rate will have 9600 baud rate.
7 6 5 4 3 2 1 0
- - - - - - - X2
Bit
Number
7 -
6 -
5 -
4 -
3 -
2 -
1 -
0 X2
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, F
Set to select 6 clock periods per machine cycle (X2 mode, F
OSC=FXTAL
OSC=FXTAL
/
2).
).
Reset Value = XXXX XXX0b
Not bit addressable
For further details on the X2 feature, please refer to ANM072 available on the web
(http://www.atmel.com)
4184I–8051–02/08
9
External Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
Dual Data Pointer Register (Ddptr)
Figure 3. Use of Dual Pointer
The additional data pointer can be used to speed up code execution and reduce code
size in a number of ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them
(Refer to Figure 3).
Table 4. AUXR1: Auxiliary Register 1
7 6 5 4 3 2 1 0
- - - - GF3 0 - DPS
Bit
Number
7 -
6 -
5 -
4 -
3 GF3 This bit is a general purpose user flag
2 0
1 -
0 DPS
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
Always stuck at 0
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
10
TS8xCx2X2
Reset Value = XXXX XXX0
Not bit addressable
4184I–8051–02/08
TS8xCx2X2
Application
Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare, search ...) are well
served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,atDPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX atDPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
4184I–8051–02/08
11
Timer 2
Auto-reload Mode The Auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto-
The timer 2 in the
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2
and TL2, connected in cascade. It is controlled by T2CON register (See Table 5) and
T2MOD register (See Table 6). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2
selects F
clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as
described in the Atmel 8-bit Microcontroller Hardware description.
Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes.
In
TS80C52X2
• Auto-reload mode with up or down counter
• Programmable clock-output
matic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the
Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an
Up/down timer/counter as shown in Figure 4. In this mode the T2EX pin controls the
direction of count.
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
OSC
TS80C52X2
/12 (timer operation) or external pin T2 (counter operation) as the timer
Timer 2 includes the following enhancements:
is compatible with the timer 2 in the 80C52.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide
17-bit resolution.
12
TS8xCx2X2
4184I–8051–02/08
Figure 4. Auto-reload Mode Up/Down Counter (DCEN = 1)
(DOWN COUNTING RELOAD
C/T2
TF2
TR2
T2
EXF2
TH2
(8-bit)
TL2
(8-bit)
RCAP2H
(8-bit)
RCAP2L
(8-bit)
FFh
(8-bit)
FFh
(8-bit)
TOGGL
(UP COUNTING RELOAD VALUE)
TIMER 2
INTERRUPT
XTAL1
:12
F
OSC
F
XTAL
0
1
T2CONreg
T2CONreg
T2CONreg
T2CONreg
T2EX:
if DCEN=1, 1=UP
if DCEN=1, 0=DOWN
if DCEN = 0, up counting
(:6 in X2 mode)
Clo c k O utFreque n c y–
F
osc
4 65536 RCAP2H– RCAP2L⁄( )×
-----------------------------------------------------------------------------------------
=
TS8xCx2X2
Programmable Clock-output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock gen-
erator (See Figure 5) . The input clock increments TL2 at frequency F
/2. The timer
OSC
repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H
and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do
not generate interrupts. The formula gives the clock-out frequency as a function of the
system oscillator frequency and the value in the RCAP2H and RCAP2L registers :
For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz
(F
/2
OSC
Timer 2 is programmed for the clock-out mode as follows:
• Set T2OE bit in T2MOD register.
• Clear C/T2 bit in T2CON register.
16)
to 4 MHz (F
/4). The generated clock signal is brought out to T2 pin (P1.0).
OSC
• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
• To start the timer, set TR2 run control bit in T2CON register.
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
4184I–8051–02/08
13
:2
EXF2
TR2
OVERFLOW
T2EX
TH2
(8-bit)
TL2
(8-bit)
TIMER 2
RCAP2H
(8-bit)
RCAP2L
(8-bit)
T2OE
T2
XTAL1
T2CON reg
T2CON reg
T2CON reg
T2MOD reg
INTERRUPT
Q D
Toggle
EXEN2
(:1 in X2 mode)
Figure 5. Clock-Out Mode C/T2 = 0
14
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
Table 5. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7 6 5 4 3 2 1 0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number
Mnemonic Description
7 TF2
6 EXF2
5 RCLK
4 TCLK
3 EXEN2
2 TR2
1 C/T2#
0 CP/RL2#
Bit
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter
mode (DCEN = 1)
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0
for clock out mode.
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to Auto-reload on
timer 2 overflow.
Clear to Auto-reload on timer 2 overflows or negative transitions on T2EX pin if
EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
OSC
).
4184I–8051–02/08
Reset Value = 0000 0000b
Bit addressable
15
Table 6. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7 6 5 4 3 2 1 0
- - - - - - T2OE DCEN
Bit
Number
7 -
6 -
5 -
4 -
3 -
2 -
1 T2OE
0 DCEN
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 Output Enable bit
Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
Down Counter Enable bit
Clear to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down counter.
Reset Value = XXXX XX00b
Not bit addressable
16
TS8xCx2X2
4184I–8051–02/08
TS8xCx2X2
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART framing error control
SM0 to UART mode control (SMOD = 0)TS80C52X2
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD
D7D6D5D4D3D2D1D0
FE
SMOD0=1
TS80C52X2 Serial I/O Port
The serial I/O port in the TS80C52X2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as
an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates
Serial I/O port includes the following enhancements:
• Framing error detection
• Automatic address recognition
Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 6).
Figure 6. Framing Error Block Diagram
Figure 7. UART Timings in Mode 1
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 9.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 7. and Figure 8.).
4184I–8051–02/08
17
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