Atmel Wireless & Microcontrollers TS80C51Rx2 is high
performance CMOS ROM, OTP, EPROM and ROMless
versions of the 80C51 CMOS single chip 8-bit
microcontroller.
The TS80C51Rx2 retains all features of the 80C51 with
extended ROM/EPROM capacity (16/32/64Kbytes),256
bytes of internal RAM, a 7-source , 4-level interrupt
system, an on-chip oscilator and three timer/counters.
In addition, the TS80C51Rx2 has a Programmable
Counter Array, an XRAM of 256 or 768 bytes, a
Hardware Watchdog Timer, a more versatile serial
channel that facilitates multiprocessor communication
(EUART) and a X2 speed improvement mechanism.
The fully static design of the TS80C51Rx2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C51Rx2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
• Hardware Watchdog Timer (One-time enabled with
Reset-Out)
• 2 extra 8-bit I/O ports available on RD2 with high
Vss1139IOptional Ground: Contact the Sales Office for ground connection.
V
CC
P0.0-P0.739-32 43-3637-30I/OPort 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
P1.0-P1.71-82-940-44
P2.0-P2.721-28 24-3118-25I/OPort 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
P3.0-P3.710-1711,
202216IGround: 0V reference
404438I
1-3
1240I/OT2 (P1.0): Timer/Counter 2 external count input/Clockout
2341IT2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
3442IECI (P1.2): External Clock for the PCA
4543I/OCEX0 (P1.3): Capture/Compare External I/O for PCA module 0
5644I/OCEX1 (P1.4): Capture/Compare External I/O for PCA module 1
6745I/OCEX0 (P1.5): Capture/Compare External I/O for PCA module 2
7846I/OCEX0 (P1.6): Capture/Compare External I/O for PCA module 3
8947I/OCEX0 (P1.7): Capture/Compare External I/O for PCA module 4
5,
13-19
10115IRXD (P3.0): Serial input port
11137OTXD (P3.1): Serial output port
12148IINT0 (P3.2): External interrupt 0
13159IINT1 (P3.3): External interrupt 1
141610IT0 (P3.4): Timer 0 external input
151711IT1 (P3.5): Timer 1 external input
161812OWR (P3.6): External data memory write strobe
171913ORD (P3.7): External data memory read strobe
7-13
Power Supply: This is the power supply voltage for normal, idle and powerdown operation
written to them float and can be used as high impedance inputs. Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program verification during
which P0 outputs the code bytes.
I/OPort 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups. Port 1 also receives the low-order
address byte during memory programming and verification.
Alternate functions for Port 1 include:
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins (P2.0 to P2.5) receive the high order address bits during
EPROM programming and verification:
I/OPort 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Some Port 3 pins (P3.4 to P3.5)
receive the high order address bits during EPROM programming and verification.
Port 3 also serves the special features of the 80C51 family, as listed below.
Reset9104IReset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSSpermits a power-on reset
using only an external capacitor to V
time-out, the reset pin becomes an output during the time the internal reset is
activated.
ALE/PROG303327O (I)Address Latch Enable/Program Pulse: Output pulse for latching the low byte
PSEN293226OProgram Store ENable: The read strobe to external program memory. When
EA/V
PP
XTAL1192115I
XTAL2182014OCrystal 2: Output from the inverting oscillator amplifier
Pin NumberType
of the address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program
pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal
fetches.
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
313529IExternal Access Enable/Programming Supply Voltage: EA must be externally
held low to enable the device to fetch code from external program memory
locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is
held high, the device executes from internal program memory unless the program
counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must
be held low for ROMless devices. This pin also receives the 12.75V programming
supply voltage (VPP) during EPROM programming. If security level 1 is
programmed, EA will be internally latched on Reset.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
Port 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull-ups. Pins that have 1 written to them are pulled
high by the internal pull ups and can be used as inputs.
As inputs, pins that are externally pulled low will source current because of the internal pull-ups.
Refer to the previous pin description for other pins.
In comparison to the original 80C52, the TS80C51Rx2 implements some new features, which are:
• The X2 option.
• The Dual Data Pointer.
• The extended RAM.
• The Programmable Counter Array (PCA).
• The Watchdog.
• The 4 level interrupt priority system.
• The power-off flag.
• The ONCE mode.
• The ALE disabling.
• Some enhanced features are also located in the UART and the timer 2.
6.1. X2 Feature
The TS80C51Rx2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the
following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.
6.1.1. Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.
The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles per instruction to 6 clock
cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature
(X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals
using clock frequency as time reference (UART, timers, PCA...) will have their time reference divided by two.
For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms.
UART with 4800 baud rate will have 9600 baud rate.
The additional data pointer can be used to speed up code execution and reduce code size in a number of
ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 4.) that allows the program code to switch between them (Refer to Figure 3).
External Data Memory
07
DPS
AUXR1(A2H)
DPH(83H) DPL(82H)
DPTR1
DPTR0
Application
AUXR1
Address 0A2H
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
b. GF3 will not be available on first version of the RC devices.
Figure 3. Use of Dual Pointer
Table 4. AUXR1: Auxiliary Register 1
----GF3--DPS
Reset valueXXXX0XX0
Symbol
-Not implemented, reserved for future use.
DPSData Pointer Selection.
GF3This bit is a general purpose user flag
products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active
value will be 1. The value read from a reserved bit is indeterminate.
Function
DPSOperating Mode
0DPTR0 Selected
1DPTR1 Selected
a
b
.
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are wellserved by using one datapointer as a ’source’
pointer and the other one as a "destination" pointer.
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE; address of SOURCE
0003 05A2INC AUXR1; switch data pointers
0005 90A000MOV DPTR,#DEST; address of DEST
0008LOOP:
0008 05A2INC AUXR1; switch data pointers
000A E0MOVX A,@DPTR; get a byte from SOURCE
000B A3INC DPTR; increment SOURCE address
000C 05A2INC AUXR1; switch data pointers
000E F0MOVX @DPTR,A; write the byte to DEST
000F A3INC DPTR; increment DEST address
0010 70F6JNZ LOOP; check for 0 terminator
0012 05A2INC AUXR1; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However,
note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.
In simple routines, such as the block move example, only the factthat DPS is toggled in the proper sequence
matters, not its actual value.In other words, the block move routine worksthe same whether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the
opposite state.
The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space for increased data
parameter handling and high level language usage.
RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH in external data space;
RD2 devices have 768 bytes of expanded RAM, from 00H to 2FFH in external data space.
The TS80C51Rx2 has internal data memory that is mapped into four separate segments.
The four segments are:
•1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.
•2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.
•3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only.
•4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM
bit cleared in the AUXR register. (See Table 5.)
The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be
accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That
means they have the same address, but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is
to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.
• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data ,accesses the SFR
at location 0A0H (which is P2).
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0,
# data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
• The 256 or 768 XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX
instructions. This part of memory which is physically located on-chip, logically occupies the first 256 or 768
bytes of external data memory.
• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any
of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6
(WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations
higher than FFH (i.e. 0100H to FFFFH) (higher than 2FFH (i.e. 0300H to FFFFH for RD devices) will be
performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2
as data/address busses, and P3.6 and P3.7 as write and read timing signals. Refer to Figure . For RD devices,
accesses to expanded RAM from 100H to 2FFH can only be done thanks to the use of DPTR.
• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri
will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output
higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a
sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes
the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read
or write signals on P3.6 (WR) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal
data memory. The stack may not be located in the XRAM.
Figure 4. Internal and External Data Memory Address
Table 5. Auxiliary Register AUXR
AUXR
Address 08EH
Reset valueXXXXXX00
------
Special
Function
Register
FFFF
0000
External
Data
Memory
EXTRA
M
AO
SymbolFunction
-Not implemented, reserved for future use.
AODisable/Enable ALE
AOOperating Mode
0
1ALE is active only during a MOVX or MOVC instruction
EXTRAMInternal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR
EXTRAMOperating Mode
0Internal XRAM access using MOVX @ Ri/ @ DPTR
1External data memory access
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and
its active value will be 1. The value read from a reserved bit is indeterminate.
ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used)
The timer 2 in the TS80C51RX2 is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in
cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation
is similar to Timer 0 and Timer 1. C/T2 selects F
as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the
combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel Wireless & Microcontrollers 8bit Microcontroller Hardware description.
Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the description of
Capture and Baud Rate Generator Modes.
In TS80C51RX2 Timer 2 includes the following enhancements:
• Auto-reload mode with up or down counter
• Programmable clock-output
6.4.1. Auto-Reload Mode
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit
in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel Wireless & Microcontrollers 8-bit
Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in
Figure 5. In this mode the T2EX pin controls the direction of count.
/12 (timer operation) or external pin T2 (counter operation)
OSC
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates
an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded
into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and
TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh
into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2
does not generate any interrupt. This bit can be used to provide 17-bit resolution.
In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6) . The
input clock increments TL2 at frequency F
At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer
2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system
oscillator frequency and the value in the RCAP2H and RCAP2L registers :
/2. The timer repeatedly counts to overflow from a loaded value.
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration,
the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and
RCAP2L registers.
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to
clock the serial port.
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: F
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
OSC
).
0CP/RL2#
Reset Value = 0000 0000b
Bit addressable
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its
advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated
timer/counter which serves as the time base for an array of five compare/ capture modules. Its clock input
can be programmed to count any one of the following signals:
•Oscillator frequency
•Oscillator frequency
•Timer 0 overflow
•External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
•rising and/or falling edge capture,
•software timer,
•high-speed output, or
•pulse width modulator.
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 33).
When the compare/capture modules are programmed in the capture mode, software timer, or high speed
output mode, an interrupt can be generated when themodule executes its function. Allfive modules plus the
PCA timer overflow share one interrupt vector.
÷ 12 (÷ 6 in X2 mode)
÷ 4(÷ 2 in X2 mode)
The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed
below. If the port is not used for the PCA, it can still be used for standard I/O.
The PCA timer is a common time base for all five modules (
determined from the CPS1 and CPS0 bits in the CMOD SFR (See Table 8) and can be programmed to run
at:
See Figure 7). The timer count source is
• 1/12 the oscillator frequency. (Or 1/6 in X2 Mode)
• 1/4 the oscillator frequency. (Or 1/2 in X2 Mode)
-Not implemented, reserved for future use.
CPS1PCA Count Pulse Select bit 1.
CPS0PCA Count Pulse Select bit 0.
ECF
Function
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during
idle Mode. CIDL = 1 programs it to be gated off during idle.
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.
WDTE = 1 enables it.
CPS1 CPS0 Selected PCA input.
00Internal clock f
01Internal clock f
10Timer 0 Overflow
11External clock at ECI/P1.2 pin (max rate = f
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an
interrupt. ECF = 0 disables that function of CF.
CIDL WDTE---CPS1CPS0ECF
/12(Orf
osc
/4 ( Or f
osc
a
b
osc
CMOD
0xD9
CCON
0xD8
/6 in X2 Mode).
osc
/2 in X2 Mode).
osc
/8)
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
b. f
= oscillator frequency
osc
The CMOD SFR includes three additional bits associated with the PCA (See Figure 7 and Table 8).
• The CIDL bit which allows the PCA to stop during idle mode.
• The WDTE bit which enables or disables the watchdog function on module 4.
The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each
module (Refer to Table 9).
• Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit.
• Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set. The CF bit can only be cleared by software.
• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by
hardware when either a match or a capture occurs. These flags also can only be cleared by software.
Table 9. CCON: PCA Counter Control Register
CCON
Address 0D8H
Reset value00X00000
Symbol
CF
CR
-Not implemented, reserved for future use.
CCF4
CCF3
CCF2
CCF1
CCF0
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags
an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but
can only be cleared by software.
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared
by software to turn the PCA counter off.
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CFCR-CCF4CCF3CCF2CCF1CCF0
a
The watchdog timer function is implemented in module 4 (See Figure 10).
The PCA interrupt system is shown in Figure 8
PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:
•16-bit Capture, positive-edge triggered,
•16-bit Capture, negative-edge triggered,
•16-bit Capture, both positive and negative-edge triggered,
•16-bit Software Timer,
•16-bit High Speed Output,
•8-bit Pulse Width Modulator.
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCAhas a special function register associated with it.These registers are: CCAPM0 for
module 0, CCAPM1 for module 1, etc. (See Table 10). The registers contain the bits that control the mode
that each module will operate in.
• The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the
CCON SFR to generate an interrupt when a match or compare occurs in the associated module.
• PWM (CCAPMn.1) enables the pulse width modulation mode.
• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there
is a match between the PCA counter and the module's capture/compare register.
• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there
is a match between the PCA counter and the module's capture/compare register.
• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will
be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both
bits are set both edges will be enabled and a capture will occur for either transition.
• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
Table 11 shows the CCAPMn settings for the various PCA functions.
.
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
Function
a
Match. When MATn = 1, a match of the PCA counter with this module's compare/capture
register causes the CCFn bit in CCON to be set, flagging an interrupt.
Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture
register causes the CEXn pin to toggle.
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width
modulated output.
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate
an interrupt.
Table 11. PCA Module Modes (CCAPMn Registers)
ECOMn CAPPn CAPNn MATnTOGn PWMm ECCFnModule Function
There are two additional registers associated with each of the PCA modules. They are CCAPnH and
CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should
occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the
output (See Table 12 & Table 13)
28Rev. C - 06 March, 2001
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
Table 12. CCAPnH: PCA Modules Capture/Compare Registers High
To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP
for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition.
When a valid transition occurs the PCA hardware loads the valueof the PCAcounter registers (CHand CL)
into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON
SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 9).
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules
CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match
occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module
are both set (See Figure 10).
CCON
CFCCF2 CCF1 CCF0
CR
CCF4
CCF3
0xD8
Write to
CCAPnH
Write to
CCAPnL
10
Reset
CCAPnHCCAPnL
Enable
16 bit comparator
CHCL
PCA counter/timer
ECOMn
CIDLCPS1 CPS0ECF
WDTE
Match
CAPNn MATn TOGn PWMn ECCFnCAPPn
* Only for Module 4
Figure 10. PCA Compare Mode and PCA Watchdog Timer
PCA IT
RESET *
CCAPMn, n = 0 to 4
0xDA to 0xDE
CMOD
0xD9
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted
match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying
the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first,
and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.
In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match
occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT,
and ECOM bits in the module's CCAPMn SFR must be set (See Figure 11).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
CCON
0xD8
PCA IT
CEXn
CCAPMn, n = 0 to 4
0xDA to 0xDE
Write to
CCAPnH
Write to
CCAPnL
1
CFCR
Reset
CCAPnHCCAPnL
0
Enable
16 bit comparator
CHCL
PCA counter/timer
ECOMn
CCF4 CCF3 CCF2 CCF1 CCF0
Match
CAPNn MATn TOGn PWMn ECCFnCAPPn
Figure 11. PCA High Speed Output Mode
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted
match could happen.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying
the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first,
and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.
All of the PCA modules can be used as PWM outputs. Figure 12 shows the PWM function. The frequency of the
output depends on the source for the PCA timer. All of the modules will have the same frequency of output
because they all share the PCA timer. The duty cycle of each module is independently variable using the module's
capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn
SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from
FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The
PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.
Enable
ECOMn
6.5.5. PCA Watchdog Timer
CAPNn MATn TOGn PWMn ECCFnCAPPn
Overflow
CCAPnH
CCAPnL
8 bit comparator
CL
PCA counter/timer
Figure 12. PCA PWM Mode
“0”
<
≥
“1”
CCAPMn, n= 0 to 4
0xDA to 0xDE
CEXn
An on-board watchdog timer is available with the PCA to improve the reliability of the system without
increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches,
or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog.
However, this module can still be used for other modes if the watchdog is not needed. Figure 10 shows a
diagram of how the watchdog works. The user pre-loads a 16-bit value inthe compare registers. Just like the
other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur,
an internal reset will be generated. This will not cause the RST pin to be driven high.
In order to hold off the reset, the user has three options:
•1. periodically change the compare value so it will never match the PCA timer,
•2. periodically change the PCA timer value so it will never match the compare values, or
•3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it.
The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the
program counter ever goes astray, a match will eventually occur and cause an internal reset. The second
option is also not recommended if other PCA modulesare being used. Remember, thePCA timer is the time
base for all modules; changing the time base for other modules would not be a good idea. Thus, in most
applications the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
The serial I/O port in the TS80C51Rx2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates
Serial I/O port includes the following enhancements:
• Framing error detection
• Automatic address recognition
6.6.1. Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 13).
RITIRB8TB8RENSM2SM1SM0/FE
SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD = 0)
PCON (87h)
IDLPDGF0GF1POF-SMOD0SMOD1
To UART framing error control
Figure 13. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 16.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 14. and Figure 15.).
RXD
SMOD0=X
FE
SMOD0=1
SMOD0=0
SMOD0=1
SMOD0=1
RI
RXD
RI
RI
FE
Start
bit
Data byte
Figure 14. UART Timings in Mode 1
Start
bit
Data byteNinth
D7D6D5D4D3D2D1D0
Stop
bit
D8D7D6D5D4D3D2D1D0
Stop
bit
bit
Figure 15. UART Timings in Modes 2 and 3
6.6.2. Automatic Address Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled
(SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).
Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte
that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the
flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
Slave C:SADDR1111 0010b
SADEN1111 1001b
Given1111 0XX1b
SADEN1111 1101b
Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A
only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but
not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2
clear (e.g. 1111 0001b).
6.6.4. Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as
don’t-care bits, e.g.:
SADDR0101 0110b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a
broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1100b
SADEN1111 1010b
Broadcast 1111 1X11b,
Slave B:SADDR1111 0011b
Slave C:SADDR=1111 0010b
SADEN1111 1001b
Broadcast 1111 1X11B,
SADEN1111 1101b
Broadcast 1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the
master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send
and address FBh.
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX
XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards
compatible with the 80C51 microcontrollers that do not support automatic address recognition.
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
SM0SM1 ModeDescriptionBaud Rate
000Shift RegisterF
0118-bit UARTVariable
1029-bit UARTF
1139-bit UARTVariable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
/12 (/6 in X2 mode)
XTAL
/64orF
XTAL
/32(/32,/16 in X2 mode)
XTAL
2RB8
1TI
0RI
Reset Value = 0000 0000b
Bit addressable
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 14. and Figure 15. in the other modes.
The TS80C51Rx2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts
(timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in Figure 16.
WARNING: Note that in the first version of RC devices, the PCA interrupt is in the lowest priority. Thus the
order in INT0, TF0, INT1, TF1, RI or TI, TF2 or EXF2, PCA.
INT0
TF0
INT1
TF1
PCA IT
RI
TI
TF2
EXF2
IE0
IE1
IPH, IP
High priority
interrupt
3
0
3
0
3
0
3
0
3
0
3
0
3
0
Interrupt
polling
sequence, decreasing
from high to low priority
Individual Enable
Global Disable
Low priority
interrupt
Figure 16. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register (See Table 19.). This register also contains a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing
a bit in the Interrupt Priority register (See Table 20.) and in the Interrupt Priority High register (See Table 21.).
shows the bit values and priority levels associated with each combination.
The PCA interrupt vector is located at address 0033H. All other vector addresses are the same as standard C52 devices.
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 19. IE Register
IE - Interrupt Enable Register (A8h)
76543210
EAECET2ESET1EX1ET0EX0
Bit Number
7EA
6EC
5ET2
4ES
3ET1
2EX1
1ET0
Bit
Mnemonic
Description
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
enable bit.
PCA interrupt enable bit
Clear to disable . Set to enable.
Timer 2 overflow interrupt Enable bit
Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
External interrupt 0 Enable bit
0EX0
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode.
In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to
be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or
during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running,
the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
6.9. Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to Table 17., PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last
instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated.
VCCcan be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from
power-down. To properly terminate power-down, the reset or external interrupt should not be executed before V
is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled
and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 17.
When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power
down exit will be completed when the first input will be released. In this case the higher priority interrupt service
routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction
that put TS80C51Rx2 into power-down mode.
Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect
the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
NOTE:If idle mode isactivatedwith power-down mode (IDL andPDbits set), the exitsequenceis unchanged, when executionis vectored to interrupt,
PD and IDL bits are cleared and idle mode is not entered.
Table 22. The state of ports during idle and power-down mode
Mode
IdleInternal11Port Data*Port DataPort DataPort Data
IdleExternal11FloatingPort DataAddressPort Data
Power DownInternal00Port Data*Port DataPort DataPort Data
Power DownExternal00FloatingPort DataPort DataPort Data
* Port 0 can force a "zero" level. A "one" will leave port floating.
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The
WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default
disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST,
SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running
and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
6.10.1. Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When
WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.
The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled,
it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at
least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST
is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T
the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within
the time required to prevent a WDT reset.
To have a more powerful WDT, a 27counter has been added to extend the Time-out capability, ranking from
16ms to 2s @ F
= 12MHz. To manage this feature, refer to WDTPRG register description, Table 24. (SFR0A7h).
OSC
OSC
, where T
OSC
= 1/F
OSC
. To make
Table 23. WDTRST Register
WDTRST Address (0A6h)
7654321
Reset valueXXXXXXX
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the
user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset
or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power
Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C51Rx2
is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the
WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C51Rx2 while in
Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter
Idle mode.
The ONCE mode facilitates testing and debugging of systems using TS80C51Rx2 without removing the circuit
from the board. The ONCE mode is invoked by driving certain pins of the TS80C51Rx2; the following sequence
must be exercised:
• Pull ALE low while the device is in reset (RST high) and PSEN is high.
• Hold ALE low as RST is deactivated.
While the TS80C51Rx2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26.
shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset.
A cold start reset is the one induced by VCCswitch-on. A warm start reset occurs while VCCis still applied to
the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 26.). POF is set by hardware when VCCrises
from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type
of reset.
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will
return indeterminate value.
Table 26. PCON Register
PCON - Power Control Register (87h)
76543210
SMOD1SMOD0-POFGF1GF0PDIDL
Bit Number
7SMOD1
6SMOD0
5-
4POF
3GF1
2GF0
1PD
0IDL
Bit
Mnemonic
Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data
memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE
signal can be disabled by setting AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but
remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is
weakly pulled high.
Table 27. AUXR Register
AUXR - Auxiliary Register (8Eh)
76543210
------EXTRAMAO
Bit Number
7-
6-
5-
4-
3-
2-
1EXTRAM
0AO
Bit
Mnemonic
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EXTRAM bit
ALE Output bit
Reset Value = XXXX XX00b
Not bit addressable
Description
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
See Table 5.
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
The program Lock system, when programmed, protects the on-chip program against software piracy.
7.2.1. 7.2.1. Encryption Array
Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a
byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.
7.2.2. Program Lock Bits
The lock bits when programmed according to Table 28. will provide different level of protection for the on-chip
code and data.
Table 28. Program Lock bits
Program Lock Bits
Security
level
1UUU
2PUU
3UPU
U: unprogrammed
P: programmed
LB1LB2LB3
No program lock features enabled. Code verify will still be encrypted by the encryption
array if programmed.MOVCinstruction executedfrom external program memory returns
non encrypted data.
MOVC instruction executed from external program memory are disabled from fetching
code bytes from internal memory,
Same as level 1+ Verify disable.
This security level is only available for 51RDX2 devices.
Protection description
EA is sampled and latched on reset.
7.2.3. Signature bytes
The TS83C51RB2/RC2/RD2 contains 4 factory programmed signatures bytes. To read these bytes, perform the
process described in section 8.3.
The program Lock system, when programmed, protects the on-chip program against software piracy.
8.2.1. Encryption Array
Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time
a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.
8.2.2. Program Lock Bits
The three lock bits, when programmed according to Table 29.8.2.3. , will provide different level of protection for
the on-chip code and data.
Table 29. Program Lock bits
Program Lock Bits
Security levelLB1LB2LB3
1UUU
2PUU
3UPUSame as 2, also verify is disabled.
4UUPSame as 3, also external execution is disabled.
U: unprogrammed,
P: programmed
WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification.
Noprogramlock features enabled. Code verifywillstill be encrypted by the encryption
array if programmed. MOVC instruction executed from external program memory
returns non encrypted data.
MOVCinstruction executedfrom external programmemoryare disabled from fetching
code bytes from internal memory,
programming of the EPROM is disabled.
Protection description
EA is sampled and latched on reset, and further
8.2.3. Signature bytes
The TS87C51RB2/RC2/RD2 contains 4 factory programmed signatures bytes. To read these bytes, perform the
process described in section 8.3.
The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses
applied during byte programming from 25 to 1.
To program the TS87C51RB2/RC2/RD2 the following sequence must be exercised:
• Step 1: Activate the combination of control signals.
• Step 2: Input the valid address on the address lines.
• Step 3: Input the appropriate data on the data lines.
• Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).
• Step 5: Pulse ALE/PROG once.
• Step 6: Lower EA/VPP from VPP to VCC
Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is
reached (See Figure 19.).
8.3.4. Verify algorithm
Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify
of the programmed array will ensure reliable programming of the TS87C51RB2/RC2/RD2.
P 2.7 is used to enable data output.
To verify the TS87C51RB2/RC2/RD2 code the following sequence must be exercised:
• Step 1: Activate the combination of program and control signals.
• Step 2: Input the valid address on the address lines.
• Step 3: Read data on the data lines.
Repeat step 2 through 3 changing the address for the entire array verification (See Figure 19.)
The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the
Figure 19. Programming and Verification Signal’s Waveform
8.4. EPROM Erasure (Windowed Packages Only)
Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full
functionality.
Erasure leaves all the EPROM cells in a 1’s state (FF).
8.4.1. Erasure Characteristics
The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15
W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm2rating for 30 minutes, at a distance
of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers.
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately
4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources
over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause
inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque
label be placed over the window.
The TS83/87C51RB2/RC2/RD2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes
follow the procedure for EPROM verify but activate the control lines provided in Table 31. for Read Signature
Bytes. Table 31. shows the content of the signature byte for the TS87C51RB2/RC2/RD2.
Ambiant Temperature Under Bias:
C = commercial0°Cto70°C
I = industrial-40°Cto85°C
Storage Temperature-65°Cto+150°C
Voltage on VCCto V
Voltage on VPPto V
Voltage on Any Pin to V
Power Dissipation1 W
NOTES
1.
Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions may affect device reliability.
2.This value is based on the maximum allowable die temperature and the thermal resistance of the package.
SS
SS
SS
(1)
-0.5Vto+7V
-0.5Vto+13V
-0.5VtoVCC+ 0.5 V
(2)
10.2. Power consumption measurement
Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset,
which made sense for the designs were the CPU was running under reset. In Atmel Wireless & Microcontrollers
new devices, the CPU is no more active during reset, so the power consumption is very low but is not really
representative of what will happen in the customer system. That’s why, while keeping measurements under Reset,
Atmel Wireless & Microcontrollers presents a new way to measure the operating Icc:
Using an internal test ROM, the following code is executed:
Label:SJMP Label (80 FE)
Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1
is driven by the clock.
This is much more representative of the real operating Icc.
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used..
2.Idle ICCis measured with all output pins disconnected; XTAL1 driven with T
N.C; Port 0 = V
3.Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 23.).
4.Capacitance loading on Ports0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is
due to external bus capacitance discharginginto the Port0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi V
5.Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6.Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2, 3 and 4 and 5 when available: 15 mA
Maximum total I
7.For other values, please contact your sales office.
8.Operating I
VIH=VCC- 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICCwould be slightly
higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case.
Power Supply Current Maximum values, X1
(7)
mode:
under reset is measured with all output pins disconnected; XTAL1 driven with T
; EA = RST = VSS (see Figure 22.).
CC
for all output pins: 71 mA
OL
is measured with all output pins disconnected; XTAL1 driven with T
CC
CLCH,TCHCL
0.15 Freq
(MHz) + 0.2
@12MHz 2
mA
VCC = 3.3 V
@16MHz 2.6
, T
CLCH
= 5 ns (see Figure 24.), VIL = VSS + 0.5 V,
CHCL
= 5 ns, VIL=VSS+ 0.5 V,VIH=VCC- 0.5 V; XTAL2
peak 0.6V. A Schmitt Triggeruse is not necessary.
OL
, T
CLCH
= 5 ns (see Figure 24.), VIL = VSS + 0.5 V,
CHCL
(2)
V
CC
I
CC
V
CC
V
CC
P0
EA
SS
CLOCK
SIGNAL
(NC)
V
CC
RST
XTAL2
XTAL1
V
Figure 20. ICCTest Condition, under reset
All other pins are disconnected.
60Rev. C - 06 March, 2001
Reset = Vss after a high pulse
during at least 24 clock cycles
Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is
a list of all the characters and what they stand for.
Example:T
T
= Time for ALE Low to PSEN Low.
LLPL
TA =0to+70°C (commercial temperature range); VSS=0V;VCC=5V± 10%; -M and -V ranges.
TA = -40°Cto+85°C (industrial temperature range); VSS=0V; VCC=5V± 10%; -M and -V ranges.
TA =0to+70°C (commercial temperature range); VSS=0V;2.7V<V
TA = -40°Cto+85°C (industrial temperature range); VSS=0V;2.7V<V
Table 34. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals.
Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings
will then be degraded.
Port 0
Port 1, 2, 3
ALE / PSEN
Table 36., Table 39. and Table 42. give the description of each AC symbols.
Table 37., Table 40. and Table 43. give for each range the AC parameter.
= Time for Address Valid to ALE Low.
AVLL
Table 34. Load Capacitance versus speed range, in pF
-M-V-L
10050100
805080
10030100
5.5 V; -L range.
CC <
5.5 V; -L range.
CC <
Table 38., Table 41. and Table 44. give the frequency derating formula of the AC parameter. To calculate each
AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value
in the formula. Values of the frequency must be limited to the corresponding speed grade:
Table 35. Max frequency for derating formula regarding the speed grade
AC inputs during testing are driven at VCC- 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement
are made at VIHmin for a logic “1” and VILmax for a logic “0”.
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded VOH/VOLlevel occurs. IOL/IOH≥±20mA.
10.5.15. Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
INTERNAL
CLOCK
XTAL2
ALE
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
P2 (EXT)
READ CYCLE
RD
P0
P2
WRITE CYCLE
WR
P0
STATE4STATE5
P1P2P1P2
DAT A
SAMPLED
FLOATFLOAT
PCL OUT
INDICATES ADDRESS TRANSITIONS
DPL OR Rt OUT
DPL OR Rt OUT
STATE6
P1P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
STATE1STATE2STATE3STATE4
P1P2P1P2P1P2
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
DAT A
SAMPLED
PCL OUT
SAMPLED
FLOAT
FLOAT
STATE5
P1P2P1P2
DAT A
PCLOUT (EVEN IFPROGRAM
MEMORY IS INTERNAL)
PCL OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P2
PORT OPERATION
MOV DEST P0
MOV DEST PORT (P1, P2, P3)
(INCLUDES INT0, INT1, TO, T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
OLD DATA
P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLEDRXD SAMPLED
NEW DATA
P1, P2, P3 PINS SAMPLED
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0 PINS SAMPLED
Figure 33. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded)
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.
(*) Check with Atmel Wireless & Microcontrollers Sales Office for availability. Ceramic packages (J, K, N) are available for prot
typing, not for volume production. Ceramic packages are available for OTP only.