ATMEL TS68302 User Manual

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Features

• TS68000/TS68008 Microprocessor Core Supporting a 16- or 8-bit TS68000 Family

• System Integration Block Including:

– Independent Direct Memory Access (IDMA) Controller
– Interrupt Controller with Two Modes of Operation
– Parallel Input/output (I/O) Ports, some with Interrupt Capability
– On-chip Usable 1152 bytes of Dual-port Random-access Memory (RAM)
– Three Timers, including a Watchdog Timer
– Four Programmable Chip-select Lines with Wait-state Logic
– Programmable Address Mapping of Dual-port RAM and IMP Registers
– On-chip Clock Generator with an Output Clock Signal
–System Control:

System Control Register
Bus Arbitration Logic with Low Interrupt Latency Support
Hardware Watchdog for Monitoring Bus Activity
Low Power (Standby) Modes
Disable CPU Logic (TS68000)
Freeze Control for Debugging Selected On-chip Peripherals
DRAM Refresh Controller

• Communications Processor Including:

– Main Controller (RISC Processor)
– Three Full-duplex Serial Communication Controllers (SCCs)
– Six Serial Direct Memory Access (SDMA) Channels Dedicated to the Three SCCs
– Flexible Physical Interface Accessible by SCCs for Interchip Digital Link (IDL)

General Circuit Interface (GCI, see note), Pulse Code Modulation (PCM), and
Nonmultiplexed Serial Interface (NMSI) Operation

– Serial Communication Port (SCP) for Synchronous Communication, Clock Rate up

to 4.096 MHz

– Serial Management Controllers (SMCs) for IDL and GCI Channels

• Frequency of Operation: 16.67 MHz

• Power Supply: 5 V

± 10%

DC

Integrated
Multiprotocol
Processor (IMP)

TS68302

Description

The IMP is a very large-scale integration (VLSI) device incorporating the main building
blocks needed for the design of a wide variety of controllers. The device is especially
suitable to applications in the communications industry. The IMP is the first device to
offer the benefits of a closely coupled, industry-standard, TS68000/TS68008 micro­processor core and a flexible communications architecture. This multichannel
communications device may be configured to support a number of popular industry
interfaces, including those for the integrated services digital network (ISDN) basic rate
and terminal adapter applications. Through a combination of architectural and pro­grammable features, concurrent operation of different protocols is easily achieved
using the IMP. Data concentrators, line cards, bridges, and gateways are examples of
suitable applications for this versatile device.

The IMP is a high-density complementary metal-oxide semiconductor (HCMOS)
device consisting of a TS68000/TS68008 microprocessor core, a system integration
block (SIB), and a communications processor (CP). The TS68302 block diagram is
shown in Figure 1.

Note: GCI is sometimes referred to as IOM2.

Rev. 2117A–HIREL–11/02

1

Screening/Quality

This product is manufactured in full compliance with either:

• MIL-STD-883 (class B)

• DESC. Drawing 5962-93159

• Or according to Atmel standards

R suffix

PGA 132

(Ceramic Pin Grid Array)

(Ceramic Quad Flat Pack)

A suffix

CERQUAD 132

Introduction The TS68302 integrated multiprotocol processor (IMP) is a very large-scale integration

(VLSI) device incorporating the main building blocks needed for the design of a wide
variety of controllers. The device is especially suitable to applications in the communica­tions industry. The IMP is the first device to offer the benefits of a closely coupled,
industry-standard TS68000 microprocessor core and a flexible communications archi­tecture. The IMP may be configured to support a number of popular industry interfaces,
including those for the Integrated Services Digital Network (ISDN) basic rate and termi­nal adapter applications. Concurrent operation of different protocols is easily achieved
through a combination of architectural and programmable features. Data concentrators,
line cards, bridges, and gateways are examples of suitable applications for this device.

The IMP is a high-density complementary metal-oxide semiconductor (HCMOS) device
consisting of a TS68000 microprocessor core, a system integration block (SIB), and a
communications processor (CP).

Figure 1 is a block diagram of the TS68302. The processor can be divided into two main
sections: the bus controller and the micromachine. This division reflects the autonomy
with which the sections operate.

2

TS68302

2117A–HIREL–11/02

Figure 1. TS68302 Block Diagram

TS68000 BUS

TS68302

TS68000/TS68008 CORE

TS68000/TS68008 CORE

ON-CHIP PERIPHERALS BUS INTERFACE UNIT

INTERRUPT

CONTROLLER

(1 CHANNEL)

CONTROLLER

CONTROLLER

IDMA

DRAM

REFRESH

(6 CHANNELS)

MAIN

(RISC)

SDMA

BUS ARBITER

TIMERS (3)

PARALLEL I/O

PERIPHERAL BUS

SMC (2) SCC1 SCC2 SCC3 SCP

SERIAL CHANNELS PHYSICAL INTERFACE

1152 BYTES
DUAL-PORT

STATIC RAM

CHIP-SELECT

AND WAIT-

STATE LOGIC

SYSTEM INTEGRATION BLOCK

SYSTEM

CONTROL

CLOCK

GENERATOR

2117A–HIREL–11/02

COMMUNICATIONS PROCESSOR

I/O PORTS AND PIN ASSIGNEMENTS

3

Pin Assignments Figure 2. PGA Terminal Designation

N

M

L

K

J

H

G

F

E

D

C

B

A

PB10 TIN1

CS3 TOUT2

CS2

CS0

FC2

FC0

A1

GND

A6

A7

A10

A11

A14

PB11

RMC

CS1

VDD

A3

A4

A8

GND

A13

A18

A21

IACK1

TIN2

GND

IAC

GND

FC1

A2

A5

A9

A12

A17

A19

A22

GND

VDD

TOUT1

PB9

PB8

VDD

A15

GND

A20

GND

UDS

R/W VDDEXTAL

IACK7

AS CLK0

LDS

IACK6

WDOG

TS68302

BOTTOM VIEW

A16

D14

A23

D13

VDD

D12

D15

12345678910111213

Figure 3. CERQUAD Terminal Designation

GND

XTAL

D11

D10

GND

IPL1 IPL2 RESET HALTRCLK1

IPL0

VDD

D8

D9

BERR BR

AVEC

DTACK

RXD2

TXD2

CTS1

D4 D1

D5

D7

BGACK

NC1

BCLR CD3

VDD

TXD1 BUSW

BRG1

GND

FRZ

PA12

TXD3

CD2

TCLK2 VDD

CD1

D2

D6

GND

BG

RTS3

TCLK1

RTS1

DISCPUNC3

DACK

DONE

GND

DREQ

TCLK3RCLK3

RXD3SDS2

GND

RCLK2

RTS2

CTS3

D0

CTS2

RXD1

D3

VDD

A16
A17
A18
A19

GND

A20
A21
A22

A23
VDD
GND

D15

D14

D13

D12
GND

D11

D10

VDD

GND

CTS3

CD1

A15

A14

A13

A12

GND

A11

A10A9A8A7A6A5A4

17

D9
D8

D7
D6
D5
D4

D3
D2
D1
D0

50

GNDA3A2A1FC0

VDD

FC1

FC2

CS0

CS1

1

68302

CERQUAD132

(window frame down)

Top VIEW

GND

CS2

CS3

RMC

IAC

PB11

PB10

PB9

PB8

117

83

WDOG

GND
TOUT2
TIN2
TOUT1
VDD
TIN1
IACK1
IACK6
IACK7
GND
UDS
LDS
AS
R/W
GND
XTAL
EXTAL
VDD
CLK0
IPL0
IPL1
IPL2
BERR
AVEC
RESET
HALT
BR
NC1
BGACK
BG
BCLR
DTACK
GND

CD2

CTS2

RTS2

VDD

SDS2

TXD3

RXD3

TCLK3

RCLK3

GND

TXD2

RXD2

TCLK2

RCLK2

GND

CTS1

RXD1

4

TS68302

PA12

DACK

DREQ

FRZ

DONE

NC3

BUSW

DISCPU

CD3

BRG1

RTS3

RTS1

TXD1

TCLK1

RCLK1

VDD

2117A–HIREL–11/02

Figure 4. Functional Signal Groups

NMSI1/ISDN I/F

RXD1/L1RXD

TXD1/L1TXD

RCLK1/L1CLK

TCLK1/L1SY0/SDS1

CD1/L1SY1

CTS1/L1RG

RTS1/L1RQ/GCIDCL

BRG2/SDS2/PA7

BRG1

RXD2/PA0

TXD2/PA1

RCLK2/PA2

TCLK2/PA3

CTS2/PA4

RTS2/PA5

CD2/PA6

RXD3/PA8

TXD3/PA9

RCLK3/PA10

TCLK3/PA11

CTS3/SPRXD

RTS3/SPTXD

CD3/SPCLK

BRG3/PA12

DREQ/PA13

DACK/PA14

DONE/PA15

IACK7/PB0

IACK6/PB1

IACK1/PB2

TIN/PB3

TOUT1/PB4

TIN2/PB5

TOUT2/ PB6

WDOG/PB7

PBIO (INTERRUPT)

PB8

PB9

PB10

PB11

NMSI2/PIO

NMSI3/SCP/PIO

IDMA/PAIO

IACK/PBIO

TIMER/PBIO

TS68302

IMP

CLOCKS

ADDRESS BUS

DATA BUS

BUS CONTROL

BUS ARBITRATON

SYSTEM CONTROL

INTERRUPT CONTROL

CHIP SELECT

TESTING

EXTAL

XTAL

CLKO

A23-A1

D15-D0

AS

R/W

UDS/A0

LDS/DS

DTACK

RMC/IOUT1

IAC

BCLR

BR
BG

BGACK

RESET

HALT

BERR
BUSW
DISCPU

IPL0/IRQ1

IPL1/IRQ6

IPL2/IRQ7

FC0

FC1

FC2

AVEC

CS0/IOUT2

CS3-CS1

FRZ

NC(2)

GND(13)

VDD(8)

TS68302

/ IOUT0

2117A–HIREL–11/02

5

Signal Descriptions The input and output signals of the TS68302 are organized into functional groups as

shown in Table 1. Refer to TS68302 Integrated Multiprotocol Processor User’s Manual,
for detailed information on the TS68302 signals.

Table 1. Signal Definitions

Functional Group Signals Number

Clocks XTAL, EXTAL, CLKO 3

System Control RESET

Address Bus A23-A1 23

Data Bus D15-D0 16

Bus Control AS

Bus Control RMC

Bus Arbitration BR

Interrupt Control IPL2-IPL0, FC2-FC0, AVEC 7

NMSI1/ISDN I/F RXD, TXD, RCLK, TCLK, CD

NMSI2/PIO RXD, TXD, RCLK, TCLK, CD

NMSI3/SCP/PIO RXD, TXD, RCLK, TCLK, CD, CTS, RTS, PA12 8

IDMA/PAIO DREQ

IACK/PBIO IACK7

Timer/PBIO TIN2, TIN1, TOUT2, TOUT1, WDOG 5

PBIO PB11-PB8 4

Chip Select CS3

Te st i n g F RZ (2 Spare) 3

V

DD

GND Ground connection 13

, HALT, BERR, BUSW, DISCPU 5

, R/W, UDS/A0, LDS/DS, DTACK 5

, IAC, BCLR 3

, BG, BGACK 3

, CTS, RTS, BRG1 8

, CTS, RTS, SDS2 8

, DACK, DONE 3

, IACK6, IACK1 3

-CS0 4

Power supply 8

Scope This drawing describes the specific requirements for the processor TS68302, 16.67

MHz, in compliance either with MIL-STD-883 class B or with Atmel standards.

Applicable
Documents

MIL-STD-883 1. MIL-STD-883: test methods and procedures for electronics.

2. MIL-M-38535: general specifications for microcircuits.

3. Desc Drawing: 5962-93159 (planned).

Requirements

General The microcircuits are in accordance with the applicable document and as specified

herein.

6

TS68302

2117A–HIREL–11/02

TS68302

Design and Construction

Terminal Connections Depending on the package, the terminal connections shall be as shown in Figure 2 and

Figure 3.

Lead Material and Finish Lead material and finish shall be any option of MIL-M-38535.

Package The macrocircuits are packaged in hermetically sealed ceramic packages, which con-

form to case outlines of MIL-M-38535 appendix A (when defined):

• 132-pin Ceramic Pin Grid Array (PGA),

• 132-pin Ceramic Quad Flat Pack (CERQUAD).

The precise case outlines are described in Figure 2 and Figure 3.

Electrical Characteristics

Table 2. Absolute Maximum Ratings

Symbol Parameter Min Max Unit

P

P

LP

LP

LP

D

D

D

D

D

Power Dissipation (typical at 16.67 MHz)

Power Dissipation (typical at 8 MHz)

Low Power Mode Dissipation (typical at 16.67 MHz)

Lowest Power Mode Dissipation (typical at 16.67 MHz)

Lowest Power Mode Dissipation (typical at 50 MHz)

Notes: 1. The values shown are typical. The typical value varies as shown, based on how many IMP on-chip peripherals are enabled

and the rate at which they are clocked.

2. LPREC = 0. Divider = 2.

3. LPREC = 1. Divider = 1024.

4. The stated frequency must be externally applied to EXTAL only after the IMP has been placed in the lowest power mode
with LPREC = 1. The 68000 core is not specified to operate at this frequency, but the rest of the IMP is. In this configuration,
the user does not divide the clock internally using the LPCD4-LPCD0 bits in the system control register.

(1)

(1)

(2)

(3)

(4)

53 64 mA

26 31 mA

36 mA

32 mA

1mA

Unless otherwise stated, all voltages are referenced to the reference terminal (see Table 1).

Table 3. Recommended Condition of Use

Symbol Parameter Min Max Unit

V

CC

V

IL

V

IH

T

case

t

(c) Clock Rise Time - See Figure 5 5 ns

r

tf(c) Clock Fall Time Resistance - Figure 5 5 ns

f

c

t

cyc

2117A–HIREL–11/02

Supply Voltage 4.5 5.5 V

Low Level Input Voltage -0.3 +0.5 V

High Level Input Voltage 2.4 5.5 V

Operating Temperature -55 +125 °C

Clock Frequency - See Figure 5 8 16.67 MHz

Cycle Time - See Figure 5 60 125 ns

7

This device contains protective circuitry to protect the inputs against damage due to high
static voltages or electrical fields; however, it is advised that normal precautions be
taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to
an appropriate logic voltage level (e.g., either GND or V

DD

).

Figure 5. Clock Input Timing Diagram

t

cyc

2.0V

0.8V

tr (C) tf (C)

Note: Timing measurements are referenced to and from a low voltage of 0.8V and a voltage of 2.0V, unless otherwise noted. The volt-

age swing through this range should start outside, and pass through, the range such that the rise or fall will be linear between

0.8V and 2.0V.

Table 4. Thermal Characteristics at 25°C

Package Symbol Parameter Value Unit

PGA 132 θ

CERQUAD 132 θ

JA

θ

JC

JA

θ

JC

Thermal Resistance - Ceramic Junction To Ambient
Thermal Resistance - Ceramic Junction To Case

Thermal Resistance - Ceramic Junction To Ambient
Thermal Resistance - Ceramic Junction To Case

Power Considerations The average chip-junction temperature, T

= TA + (PD ⋅ θJA) (1)

T

J

T

= Ambient Temperature, °C

A

θ

= Package Thermal Resistance, Junction-to-Ambient, °C/W

JA

P

= P

D

P

INT

P

I/O

Note: For TA = 70°C and PD = 0.5 W at 12.5 MHz Tj = 88°C.

For most applications P

An approximate relationship between P

Solving equations (1) and (2) for K gives:

where K is a constant pertaining to the particular part. K can be determined from equa­tion (3) by measuring P
values of P
value of T

+ P

INT

I/O

= ICC ⋅ VCC, Watts - Chip Internal Power

= Power Dissipation on Input and Output pins - user determined

< 0,30 P

I/O

= K ÷ (TJ + 273) (2)

P

D

K = P

⋅ (TA + 273) + θJA ⋅ PD2 (3)

D

(at equilibrium) for a known TA. Using this value of K, the

and TJ can be obtained by solving equations (1) and (2) iteratively for any

D

.

A

D

and can be neglected.

INT

D

33

5

46

2

, in °C can be obtained from:

J

and TJ (if P

is neglected) is:

I/O

°C/W
°C/W

°C/W
°C/W

8

TS68302

2117A–HIREL–11/02

TS68302

The total thermal resistance of a package (θJA) can be separated into two components,

θ

and θCA, representing the barrier to heat flow from the semiconductor junction to the

JC

package (case), surface (
terms are related by the equation:

θ

= θJC + θCA (4)

JA

θ

is device-related and cannot be influenced by the user. However, θCA is user-depen-

JC

dent and can be minimized by such thermal management techniques as heat sinks,
ambient air cooling and thermal convection. Thus, good thermal management on the
part of the user can significantly reduce

θ

tution of
temperature.

for θJA in equation (1) will result in a lower semiconductor junction

JC

θ

) and from the case to the outside ambient (θCA). These

JC

θ

so that θJA approximately equals θJC. Substi-

CA

Mechanical and
Environment

The microcircuits shall meet all mechanical environmental requirements of either MIL­STD-883 for class B devices or Atmel standards.

Marking The document that defines the marking is identified in the related reference documents.

Each microcircuit is legible and permanently marked with the following information as
minimum:

• Atmel Logo

• Manufacturer’s part number

• Class B identification

• Date-code of inspection lot

• ESD identifier if available

• Country of manufacturing

Quality Conformance
Inspection

DESC/MIL-STD-883 Those quality levels are in accordance with MIL-M-38535 and method 5005 of MIL-

STD-883. Groups A and B inspections are performed on each production lot. Groups C
and D inspection are performed on a periodical basis.

Electrical
Characteristics

General Requirements All static and dynamic electrical characteristics specified. For inspection purposes, refer

to relevant specification:

• DESC see “DESC/MIL-STD-883” on page 9

Table 5 and Table 6: Static Electrical Characteristics for all electrical variants. Test
methods refer to IEC 748-2 method number, where existing.

Table 7 and Table 8: Dynamic Electrical Characteristics. Test methods refer to this
specification.

2117A–HIREL–11/02

9

Table 5. DC Electrical Characteristics

= 5.0 Vdc ± 10%; GND = 0 Vdc; Tc = -55°C/+125°C or -40°C/+85°C

V

CC

Symbol Parameter Min Max Unit

V

IH

V

IL

V

CIH

V

CIL

I

IN

C

IN

I

TSI

I

OD

V

OH

V

OL

Input High Voltage (except EXTAL) 2.0 V

DD

V

Input Low Voltage (except EXTAL) VSS - 0.3 0.8 V

Input High Voltage (EXTAL) 4.0 V

DD

V

Input Low Voltage (EXTAL) VSS - 0.3 0.6 V

Input Leakage Current 20 µA

Input Capacitance All Pins 15 pF

Three-state Leakage Current (2.4V/0.5V) 20 µA

Open Drain Leakage Current (2.4V) 20 µA

Output High Voltage (IOH = 400 µA) VDD - 1.0 V

Output Low Voltage

(IOL = 3.2 mA) A1-A23, PB0-PB11, FC0-FC3, CS0-CS3, IAC, AVEC, BG, RCLK1,

RCLK2, RCLK3, TCLK1, TCLK2, TCLK3, RTS1
SDS2, PA12, RXD2, RXD3, CTS2

(I

= 5.3 mA) AS, UDS, LDS, R/W, BERR, BGACK, BCLR, DTACK, DACK, RMC,

OL

, D0-D15, RESET

RMC

, CD2, CD3, DREQ

, RTS2, RTS3,

0.5 V

0.5 V

(IOL = 7.0 mA) TXD1, TXD2, TXD3 0.5 V

(IOL = 8.9 mA) BR, DONE, HALT, (BR as output) 0.5 V

(I

= 3.2 mA) CLKO 0.4 V

OL

O

CLK

O

GCI

O

ALL

Output Drive CLKO 50 pF

Output Drive ISDN I/F (GCI mode) 150 pF

Output Drive All Other Pins 130 pF

10

TS68302

2117A–HIREL–11/02

TS68302

Table 6. DC Electrical Characteristics - NMSI1 in IDL mode

Symbol Parameter Condition Min Nom Max Unit

V

V

Power 4.5 5.0 5.5 V

DD

Common 0 0 0 V

SS

T Temperature Operating range -55 25 +125 °C

Input Pin Characteristics: L1CLK, L1SY1, L1R x D, L1GR

V

V

I

IH

I

IH

Input Low Level Voltage (% of VDD) -10% +20% V

IL

Input High Level Voltage VDD - 20% VDD + 10% V

IH

Input Low Level Current Vin = V

Input High Level Current Vin = V

SS

DD

±10 µA

±10 µA

Output Pin Characteristics: L1T x D, SDS1-SDS2, L1RQ

V

OL

V

OH

Output Low Level Voltage IOL = 2.0 mA 0 0.50 V

Output High Level Voltage IOH = 2.0 mA VDD - 0.5 V

DD

V

2117A–HIREL–11/02

11

Dynamic (Switching)
Characteristics

Figure 6. Clock Timing Diagram

V

= 4V

CIH

EXTAL

V

= 0.6V

CIL

The limits and values given in this section apply over the full case temperature range ­55°C to +125°C or -40°C to +85°C depending on selection see “Ordering Information”
on page Reference 2 and VCC in the range 4.5V to 5.5V V

= 0.5V and VIH = 2.4V.

IL

The INTERVAL numbers (NUM) refer to the timing diagrams. See Figure 6 to Figure 25.

The AC specifications presented consist of output delays, input setup and hold times,
and signal skew times. All signals are specified relative to an appropriate edge of the
clock (CLKO pin) and possibly to one or more other signals.

1

2

3

5

4

5a

CLKO

5a

Table 7. AC Electrical Specifications - Clock Timing (see Figure 7)

Num. Symbol Parameter Min Max Unit

f Frequency of Operation 8 16.67 MHz

1t

2, 3 t

4, 5 t

5a t

Notes: 1. CLKO loading is 50 pF max.

2. CLKO skew from the rising and falling edges of EXTAL will not differ from each other more than 1 ns, if the EXTAL rise time

cyc

, t

CL

CH

, t

Cr

Cf

CD

equals the EXTAL fall time.

Clock Period (EXTAL) 60 125 ns

Clock Pulse Width (EXTAL) 25 62.5 ns

Clock Rise and Fall Times (EXTAL) 5 ns

EXTAL to CLKO delay

(1)(2)

211ns

12

TS68302

2117A–HIREL–11/02

TS68302

Table 8. AC Electrical Specifications

IMP Bus Master Cycles (see Figure 7, Figure 8 and Figure 9) f = 16.67 MHz

Num. Symbol Parameter Min Max Unit

6t

7t

8t

9t

11 t

12 t

13 t

14 t

14A t

15 t

16 t

17 t

18 t

20 t

20A t

21 t

22 t

23 t

25 t

26 t

27 t

28 t

29 t

30 t

31 t

32 t

33 t

34 t

35 t

36 t

37 t

37A t

38 t

39 t

CHFCADV

CHADZ

CHAFI

CHSL

AFCVSL

CLSH

SHAFI

SL

DSL

SH

CHCZ

SHRH

CHRH

CHRL

ASRV

AFCVRL

RLSL

CLDO

SHDOI

DOSL

DICL

SHDAH

SHDII

SHBEH

DALD I

, t

RHr

RHf

CHGL

CHGH

BRLGL

BRHGH

GALGH

GALBRH

GLZ

GH

Clock high to FC, address valid 45 ns

Clock high to address, data bus high impedance (maximum) 50 ns

Clock high to address, FC invalid (minimum) 0 ns

Clock high to AS, DS asserted

Address, FC valid to AS, DS asserted (read)/AS asserted

(2)

(write)

Clock low to AS, DS negated

AS, DS negated to address, FC invalid

AS (and DS read) width asserted

DS width asserted, write

AS, DS width negated

(2)

(1)

330ns

15 ns

(1)

(2)

(2)

(2)

15 ns

120 ns

60 ns

30 ns

60 ns

Clock high to control bus high impedance 50 ns

AS, DS negated to R/W invalid

Clock high to R/W high

Clock high to R/W low

(1)

(1)

AS asserted to R/W low (write)

Address FC valid to R/W low (write)

R/W low to DS asserted (write)

(2)

(2)(3)

(2)

15 ns

30 ns

30 ns

10 ns

(2)

15 ns

30 ns

Clock low to data-out valid 30 ns

AS, DS, negated to data-out invalid (write)

Data-out valid to DS asserted (write)

Data-in valid to clock low (Setup time on read)

AS, DS negated to DTACK negated (asynchronous hold)

(2)

(2)

(4)

(2)

15 ns

15 ns

7ns

0 110 ns

AS, DS negated to data-in invalid (hold time on read) 0 ns

AS, DS negated to BEER negated 0 ns

DTACK asserted to data-in valid (setup time)

(2)(4)

50 ns

HALT and RESET input transition time 150 ns

Clock high to BG asserted 30 ns

Clock high to BG negated 30 ns

BR asserted to BG asserted 2.5 4.5 clks

BR negated to BG negated

(5)

1.5 2.5 clks

BGACK asserted to BG negated 2.5 4.5 clks

BGACK asserted to BG negated

BG asserted to control, address, data bus high impedance

negated)

(AS

(6)

10 1.5 ns/clks

50 ns

BG width negated 1.5 clks

2117A–HIREL–11/02

13

Table 8. AC Electrical Specifications

IMP Bus Master Cycles (see Figure 7, Figure 8 and Figure 9) f = 16.67 MHz (Continued)

Num. Symbol Parameter Min Max Unit

44 t

46 t

47 t

48 t

53 t

55 t

56 t

57 t

57A t

58 f

58A t

60 t

61 t

62 t

63 t

64 t

SHVPH

GAL

ASI

BELDAL

CHDOI

RLDBD

HRPW

GASD

GAFD

RHSD

RHFD

CHBCL

CHBCH

CLRML

CHRMH

RMHGL

AS, DS negated to AVEC negated 0 50 ns

BGACK width low 1.5 clks

Asynchronous input setup time

BERR asserted to DTACK asserted

(4)

(2)(7)

10 ns

10 ns

Data-out hold from clock high 0 ns

R/W asserted to data bus impedance change 0 ns

HALT/RESET pulse width

(8)

10 clks

BGACK negated to AS, DS, R/W driven 1.5 clks

BGACK negated to FC 1 clks

BR negated to AS, DS, R/W driven

BR negated to FC

(5)

(5)

1.5 clks

1clks

Clock high to BCLR asserted 30 ns

Clock high to BCLR negated

(9)

30 ns

Clock low (S0 falling edge during read) to RMC asserted 30 ns

Clock high (S7 rising edge during write) to RMC negated 30 ns

RMC negated to BG asserted

(10)

30 ns

Notes: 1. For loading capacitance of less than or equal to 50 pF, subtract 4 ns from the value given in the maximum columns.

2. Actual value depends on clock period.

3. When AS and R/W are equally loaded (±20%), subtract 5 ns from the values given in these columns.

4. If the asynchronous input setup (#47) requirement is satisfied for DTACK

, the DTACK asserted to data setup time (#31)

requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.

5. The TS68302 will negate BG and begin driving the bus if external arbitration logic negates BR before asserting BGACK.

6. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.

7. If #47 is satisfied for both DTACK

and BERR, #48 may be ignored. In the absence of DTACK, BERR is a synchronous input

using the asynchronous input setup time (#47).

8. For power-up, the TS68302 must be held in the reset state for 100 ms to allow stabilization of on-chip circuit. After the sys­tem is powered up #56 refers to the minimum pulse width required to reset the processor.

9. Occurs on S0 of SDMA read/write access when the SDMA becomes bus master.

10. This specification is valid only when the RMCST bit is set in the SCR register.

14

TS68302

2117A–HIREL–11/02

Figure 7. Read Cycle Timing Diagram

CLKO

FC2-FC0

A23-A1

S0 S1 S2 S3 S4 S5 S6

8

6

TS68302

S7

AS

LDS-UDS

R/W

DTACK

DATA IN

BERR/BR

(Note 2)

HALT / RESET

7

13

15

9

11

17

18

48

47 47

32

32

14

47

27

31

47

12

28

29

30

56

ASYNCHRONOUS

INPUTS (Note 1)

47

Notes: 1. Setup time for asynchronous inputs IPL2-IPL0 guarantees their recognition at the next falling edge of the clock.

needs to fall at this time only to ensure being recognized at the end of the bus cycle.

2. BR

3. Timing measurements are reinforced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted.
The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear
between 0.8V and 2.0V.

2117A–HIREL–11/02

15

Figure 8. Write Cycle Timing Diagram

OUT

Notes: 1. Timing measurements are referenced to and from a low voltage of 0.8V and a high of 2.0V, unless otherwise noted. The

voltage swing through this range should start outside and pass through the range such that the rise and fall is linear between

0.8V and 2.0V.

2. Because of loading variations, R/W
tion #20A).

may be valid after AS even though both are initiated by the rising edge of S2 (specifica-

16

TS68302

2117A–HIREL–11/02

Figure 9. Bus Arbitration Timing Diagram

STROBES

AND R/W

BR

BGACK

35

BG

TS68302

37A

37

46

34

39

47

36

57

57A

58

58A

33

CLKO

38

Note: Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, and IPL2-IPL0 guarantees their recog-

nition at the next falling edge of the clock.

Table 9. AC Electrical Specifications - DMA (see Figure 10) f = 16.67 MHz

Num. Symbol Parameter Min Max Unit

80 t

REQASI

81 t

82 t

83 t

84 t

85 t

86 t

87 t

88 t

89 t

90 t

91 t

92 t

93 t

94 t

95 t

96 t

97 t

REQLBRL

CHBRL

CHBRZ

BKLBRZ

CHBKL

ABHBKL

BGLBKL

BRHBGH

CLBKLAL

CHBKH

CLBKZ

CHACKL

CLACKH

CHDNL

CLDNZ

DNLTCH

Notes: 1. DREQ

2. If #80 is satisfied for DREQ

3. BR

will not be asserted while AS, HALT, or BERR is asserted.

4. Specifications are for DISABLE CPU mode only.

DREQ asynchronous setup time

REQL

DREQ width low

DREQ low to BR low

Clock high to BR low

(2)

(3)(4)

(3)(4)

Clock high to BR high impedance

BGACK low to BR high impedance

Clock high to BGACK low 30 ns

AS and BGACK high (the latest one) to BGACK low (when
BG is asserted)

AS low to BGACK low (no other bus master)

BR high impedance to BG high

Clock on which BGACK low to clock on which AS low 2 2 clk

Clock high to BGACK high 30 ns

Clock low to BGACK high impedance 15 ns

Clock high to DACK low 30 ns

Clock high to DACK high 30 ns

Clock high to DONE low (output) 30 ns

Clock low to DONE high impedance 30 ns

DONE input low to clock high (asynchronous setup) 15 ns

is sampled on the falling edge of CLK in cycle steal and burst modes.

, #81 may be ignored.

(1)

(3)(4)

(3)(4)

(3)(4)

(3)(4)

15 ns

2clk

2clk

30 ns

30 ns

30 ns

1.5

2.5

+ 30

2.5

+ 30

clk

ns

clk

ns

0ns

2117A–HIREL–11/02

17

Figure 10. DMA Timing Diagram

Table 10. AC Electrical Specifications - External Master Internal Asynchronous Read/write Cycles

(2)

f = 16.67 MHz

Num. Symbol Parameter Min Max Unit

100 t

101 t

102 t

103 t

104 t

105 t

106 t

107 t

108 t

108A t

109 t

109A t

RWVDSL

DSLDIV

DKLDH

ASVDSL

DKLDSH

DSHDKH

DSIASI

DSHRWH

DSHDZ

DSHDH

DSHDOH

DOVDKL

R/W valid to DS low 0 ns

DS low to data in valid 30 ns

DTACK low to data in hold time 0 ns

AS valid to DS low 0 ns

DTACK low to DS high 0 ns

DS high to DTACK high 45 ns

DS inactive to AS inactive 0 ns

DS high to R/W high 0 ns

DS high to data high impedance 45 ns

DS high to data out hold time 0 ns

DS high to data in hold time

(1)

0ns

Data out valid to DTACK low 15 ns

Note: 1. If AS is negated before DS, the data bus could be three-stated (spec 126) before DS is negated.

2. See Figure 11 and Figure 12.

18

TS68302

2117A–HIREL–11/02

Figure 11. External Master Internal Asynchronous Read Cycle Timing Diagram

TS68302

2117A–HIREL–11/02

19

Figure 12. External Master Internal Asynchronous Write Cycle Timing Diagram

Table 11. AC Electrical Specifications

External Master Internal Synchronous Read/write Cycles

(2)

(1)

f = 16.67 MHz

Num. Symbol Parameter Min Max Unit

110 t

111 t

112 t

113 t

114 t

115 t

116 t

117 t

118 t

119 t

120 t

121 t

122 t

AVASL

ASLCH

CLASH

ASHAH

ASH

SLCH

CLSH

RWVCH

CHRWH

ASLIAH

ASHIAL

ASLDTL

CLDTL

Address valid to AS low 15 ns

AS low to clock high 30 ns

Clock low as to AS high 45 ns

AS high to address hold time on write 0 ns

AS inactive time 1 clk

UDS/LDS low to clock high 40 ns

Clock low to UDS/LDS high 45 ns

R/W valid to clock high 30 ns

Clock high to R/W high 45 ns

AS low to IAC high 40 ns

AS high to IAC low 40 ns

AS low to DTACK low (0 wait state) 45 ns

Clock low to DTACK low (1 wait state) 30 ns

20

TS68302

2117A–HIREL–11/02

TS68302

Table 11. AC Electrical Specifications

External Master Internal Synchronous Read/write Cycles

(2)

(1)

f = 16.67 MHz (Continued)

Num. Symbol Parameter Min Max Unit

123 t

124 t

ASHDTH

DTHDTZ

125 t

126 t

127 t

ASHDOI

128 t

129 t

130 t

131 t

CHDOV

ASHDZ

ASHAI

SH

CLDIV

CLDIH

AS high to DTACK high 45 ns

DTACK high to DTACK high impedance 15 ns

Clock high to data out valid 30 ns

AS high to data high impedance 45 ns

AS high to data out hold time 0 ns

AS high to address hold time on read 0 ns

UDS/LDS inactive time 1 clk

Data in valid to clock low 30 ns

Clock low to data in hold time 15 ns

Notes: 1. See Figure 13, Figure 14 and Figure 15.

2. Specifications are valid only when SAM = 1 in the SCR.

Figure 13. External Master Internal Synchronous Read Cycle Timing Diagram

2117A–HIREL–11/02

21

Figure 14. External Master Internal Synchronous Read Cycle Timing Diagram (One Wait State)

22

TS68302

2117A–HIREL–11/02

Figure 15. External Master Internal Synchronous Write Cycle Timing Diagram

TS68302

Table 12. AC Electrical Specifications - Internal Master Read/write Cycles

(1)

f = 16.67 MHz

Num. Symbol Parameter Min Max Unit

140 t

141 t

142 t

143 t

144 t

145 t

CHIAH

CLIAL

CHDTL

CLDTH

CHDOV

ASHDOH

Clock high to IAC high 40 ns

Clock low to IAC low 40 ns

Clock high to DTACK low (0 wait state) 45 ns

Clock low to DTACK high 40 ns

Clock high to data out valid 30 ns

AS high to data out hold time 0 ns

Note: 1. See Figure 16.

2117A–HIREL–11/02

23

Figure 16. Internal Master Internal Read Cycle Timing Diagram

S1 S2 S3 S4 S5 S6

CLKO

(OUTPUT)

A23-A1

(OUTPUT)

AS

(OUTPUT)

S0

S7

S0

140

IAC

(OUTPUT)

UDS

LDS

(OUTPUT)

R/W

(OUTPUT)

D15-D0

(OUTPUT)

142

DTACK

(OUTPUT)

Table 13. AC Electrical Specifications - Chip-select Timing Internal Master

144

(3)

f = 16.67 MHz

143

141

145

Num. Symbol Parameter Min Max Unit

150 t

151 t

CHCSIAKL

CLCSIAKH

152 t

153 t

154 t

155 t

156 t

157 t

158 t

DTKHDTKZ

171 t

172 t

173 t

174 t

175 t

CSH

CHDTKL

CLDTKL

CLDTKH

CHBERL

CLBERH

IDHCL

CSNDOI

AFVCSA

CSNAFI

CSLT

Clock high to CS, IACK low

Clock low to CS, IACK high

CS width negated 60 ns

Clock high to DTACK low (0 wait state) 45 ns

Clock low to DTACK low (1 - 6 wait states) 30 ns

Clock low to DTACK high 40 ns

Clock high to BERR low

Clock low to BERR high impedance

DTACK high to DTACK high impedance 15 ns

Input data hold time from S6 low 5 ns

CS negated to data out invalid (write)

Address, FC valid to CS asserted

CS negated to address, FC invalid

CS low time (0 wait states)

(1)

(1)

(2)

(2)

(4)

(4)

(4)

(4)

10 ns

15 ns

15 ns

120 ns

40 ns

40 ns

40 ns

40 ns

24

TS68302

2117A–HIREL–11/02

TS68302

Table 13. AC Electrical Specifications - Chip-select Timing Internal Master

(3)

f = 16.67 MHz (Continued)

Num. Symbol Parameter Min Max Unit

176 t

177 t

178 t

CSNRWI

CSARWL

CSNDII

CS negated to R/W invalid

CS asserted to R/W low (write)

CS negated to data in invalid (hold time on read)

(4)

(4)

(4)

10 ns

10 ns

0ns

Notes: 1. For loading capacitance less than or equal to 50 pF, subtract 4 ns from the maximum value given.

2. This specification is valid only when the ADCE or WPVE bits in the SCR are set.

3. See Figure 17.

4. Specs 172-178 do not have diagrams. However, similar diagrams for AS are shown as 25-11-13-14-17-20A and 29.

Figure 17. Internal Master Chip-select Timing Diagram

Sw Sw S5S4 S6 S7 S0S0 S1 S2 S3 S4 S5 S6 S7

154

CLKO

(OUTPUT)

CS0-CS3

IACK1,IACK6,

IACK7

(OUTPUT)

DTACK

(OUTPUT)

BERR

(OUTPUT)

150

153

156

S0

152

151

158

155

157

Table 14. AC Electrical Specifications - Chip-select Timing External Master

(4)

f = 16.67 MHz

Num. Symbol Parameter Min Max Unit

154 t

160 t

161 t

162 t

163 t

164 t

165 t

167 t

168 t

169 t

CLDTKL

ASLCSL

ASHCSH

AVASL

RWVASL

ASHAI

ASLDTKL

ASHDTKH

ASLBERL

ASHBERH

Clock low to DTACK low (1-6 wait states) 30 ns

AS low to CS low 30 ns

AS high to CS high 30 ns

Address valid to AS Low 15 ns

R/W valid to AS Low

(1)

15 ns

AS negated to Address hold time 0 ns

AS low to DTACK low (0 wait state) 45 ns

AS high to DTACK high 30 ns

AS low to BERR low

AS high to BERR high

(2)

(2)(3)

30 ns

30 ns

Notes: 1. The minimum value must be met to guarantee write protection operation.

2. This specification is valid when the DCE or WPVE bits in the SCR are set.

3. Also applies after a timeout of the hardware watchdog.

4. See Figure 18

2117A–HIREL–11/02

25

Figure 18. External Master Chip-select Timing Diagram

S0 S1 S2 S3 S4 S5 S6 S7

CLKO

A23-A1
(INPUT)

162

AS

(INPUT)

160

CS3-CS0

(OUTPUT)

R/W

(INPUT)

DTACK

(OUTPUT)

BERR

(OUTPUT)

163

165

168

S0

164

161

167

158

169

Table 15. AC Electrical Specifications - Parallel I/O

(1)

f = 16.67 MHz

Num. Symbol Parameter Min Max Unit

180 t

181 t

182 t

DSU

DH

CHDOV

Input Data Setup Time (to clock low) 20 ns

Input Data Hold Time (from clock low) 10 ns

Clock High to Data Out Valid (CPU writes data, control, or
direction) 35

35 ns

Note: 1. See Figure 19

Figure 19. Parallel I/O Data In/data Out Timing Diagram

CLKO

DATA IN

180

DATA OUT

181

182

CPU WRITE S6

26

TS68302

2117A–HIREL–11/02

TS68302

(2)

Table 16. AC Electrical Specifications - Interrupts

Num. Symbol Parameter Min Max Unit

f = 16.67 MHz

190 t

191 t

IPW

AEMT

Interrupt pulse width low IRQ (edge triggered mode) 50 ns

Minimum time between active edges 3 clk

Note: 1. Set up time for the asynchronous inputs IPL2-IPL0 and AVEC guarantees their recognition at the next falling edge of the

clock.

2. See Figure 20.

Figure 20. Interrupts Timing Diagram

IRQ

(INPUT)

190

191

Table 17. AC Electrical Specifications - Timers

Num. Symbol Parameter Min Max Unit

200 t

201 t

202 t

203 t

204 t

205 t

206 t

TPW

TICLT

TICHT

cyc

CHTOV

FRZSU

FRZHT

Note: 1. FRZ should be negated during total system reset.

2. See Figure 21.

Timer input capture pulse width 50 ns

TIN clock low pulse width 50 ns

TIN clock high pulse width 2 clk

TIN clock cycle time 3 clk

Clock high to TOUT valid 35 ns

FRZ input setup time (to clock high)

FRZ input hold time (from clock high) 10 ns

(2)

f = 16.67 MHz

(1)

20 ns

Figure 21. Timers Timing Diagram

CLKO

TOUT

(OUTPUT)

TIN

(INPUT)

FRZ

(INPUT)

2117A–HIREL–11/02

201

203

204

200

202

205

206

27

(2)

Table 18. AC Electrical Specifications - Serial Communication Port

f = 16.67 MHz

Num. Parameter Min Max Unit

250 SPCLK clock output period 4 64 clks

251 SPCLK clock output rise/fall time 15 ns

252 Delay from SPCLK to transmit

253 SCP receive setup time

254 SPC receive hold time

(1)

(1)

(1)

040ns

40 ns

10 ns

Note: 1. This also applies when SPCLK is inverted by CI in the SPMODE register. The enable signals for the slaves may be imple-

mented by the parallel I/O pins.

2. See Figure 22.

Figure 22. Serial Communication Port Timing Diagram

250

SPCLK

(OUTPUT)

SPTXD

(OUTPUT)

SPRXD

(INPUT)

123 4 567 8

12

Table 19. AC Electrical Specifications - Idle Timing

252

3

(3)

f = 16.67 MHz All timing measurements, unless otherwise specified,

251

253

45

254

6

78

are referenced to the L1CLK at 50% point of VDD

Num. Parameter Min Max Unit

260 L1CLK (IDL clock) frequency

261 L1CLK width low 55 ns

262 L1CLK width high 60 ns

263 L1T x D, L1RQ, SDS1-SDS2 rising/falling time 20 ns

(1)

6.66 MHz

264 L1SY1 (sync) setup time (to L1CLK falling edge) 30 ns

265 L1SY1 (sync) hold time (to L1CLK falling edge) 50 ns

266 L1SY1 (sync) inactive before 4th L1CLK 0 ns

267 L1T x D active delay (from L1CLK rising edge) 0 75 ns

268 L1T x D to high impedance (from L1CLK rising edge)

(2)

050ns

269 L1R x D setup time (to L1CLK falling edge) 50 ns

270 L1R x D hold time (from L1CLK falling edge) 50 ns

271 Time between successive IDL syncs 20 L1CLK

272 L1RQ valid before falling edge of L1SY1 1 L1CLK

273 L1GR setup time (to L1SY1 falling edge) 50 ns

28

TS68302

2117A–HIREL–11/02

TS68302

Table 19. AC Electrical Specifications - Idle Timing

(3)

f = 16.67 MHz All timing measurements, unless otherwise specified,

are referenced to the L1CLK at 50% point of VDD (Continued)

Num. Parameter Min Max Unit

274 L1GR hold time (from L1SY1 falling edge) 50 ns

275 SDS1-SDS2 active delay from L1CLK rising edge 10 75 ns

276 SDS1-SDS2 inactive delay from L1CLK falling edge 10 75 ns

Notes: 1. The ratio CLK/L1CLK must be greater than 2.5/1.

2. High impedance is measured at the 30% and 70% of VDD points, with the line at VDD/2 through 10K in parallel with 130 pF.

3. See Figure 23.

Figure 23. IDL Timing Diagram

271

L1SY1

(INPUT)

L1CLK

(INPUT)

L1TXD

(OUTPUT)

L1RXD

(INPUT)

265

264

262

12 345678910111213141516171819

267

B16

B17

270

269

B17 B15

B16

266

260

261

B15 B14 B12B13

263

B14

B13

B12

B11

B10B11

B10

D1

D1

AB27

268

A

B27

B26

B26

B25

B25

B24 B23

B24

B23

B22

B22

B21

B21

B20

B20 D2

D2

20

M

M

SDS1
SDS2

(OUTPUT)

L1RQ

(OUTPUT)

L1GR

(INPUT)

275

272

273

276

274

2117A–HIREL–11/02

29

Table 20. AC Electrical Specifications - GCI Timing

(5)

f = 16.67 MHz

GCI supports the NORMAL mode and the GCI channel 0 (GCN0) in MUX mode. Normal mode uses 512 kHz clock rate
(256K bit rate). MUX mode uses 256 x n - 3068K bits/sec (clock rate is data rate x 2). The ratio CLK/L1CLK must be greater
than 2.5/1.

Num. Parameter Min Max Unit

L1CLK GCI clock frequency (normal mode)

280 L1CLK clock period normal mode

(1)

281 L1CLK width low/high normal mode 840 1450 ns

282 L1CLK rise/fall time normal mode

(2)

L1CLK (GCI clock) period (MUX mode)

280 L1CLK clock period MUX mode

(1)

281 L1CLK width low/high MUX mode 55 ns

282 L1CLK rise/fall time MUX mode

(2)

283 L1SY1 sync setup time to L1CLK falling edge 30 ns

284 L1SY1 sync hold time from L1CLK falling edge 50 ns

285 L1T x D active delay (from L1CLK rising edge)

286 L1T x D active delay (from L1SY1 rising edge)

287 L1R x D setup time to L1CLK rising edge 20 ns

288 L1R x D hold time from L1CLK rising edge 50 ns

(1)

512 kHz

1800 2100 ns

--ns

(1)

6.668 MHz

150 ns

--ns

(3)

(3)

0 100 ns

0 100 ns

289 Time between successive L1SY1 in normal mode

SCIT mode

290 SDS1-SDS2 active delay from L1CLK riding edge

291 SDS1-SDS2 active delay from L1SY1 rising edge

(4)

(4)

64

192

10 90 ns

10 90 ns

292 SDS1-SDS2 inactive delay from L1CLK falling edge 10 90 ns

293 GCIDCL (GCI Data clock) active delay 0 50 ns

Notes: 1. The ratio CLK/L1CLK must be greater than 2.5/1.

2. Schmitt trigger used on input buffer.

3. Condition CL = 150 pF. L1T x D becomes valid after the L1CLK rising edge or L1SY1, whichever is later.

4. SDS1-SDS2 become valid after the L1CLK rising edge or L1SY1, whichever is later.

5. See Figure 24.

L1CLK
L1CLK

30

TS68302

2117A–HIREL–11/02

Figure 24. GSI Timing Diagram

TS68302

Table 21. AC Electrical Specifications - PCM Timing

(4)

f = 16.67 MHz

There are two sync types:
Short frame - Sync signals are one clock cycle prior to the data.
Long frame - Sync signals are N-bits that envelope the data, N > 0.

Num. Parameter Min Max Unit

300 L1CLK (PCM clock) frequency

301 L1CLK width low/high 55 ns

302 L1SY0-L1SY1 setup time to L1CLK falling edge 20 ns

303 L1SY0-L1SY1 hold time from L1CLK falling edge 40 ns

304 L1SY0-L1SY1 width low 1 L1CLK

305 Time between successive sync signals (short frame) 8 L1CLK

306 L1T x D data valid after L1CLK rising edge

307 L1T x D to high impedance (from L1CLK rising edge) 0 50 ns

308 L1R x D setup time (to L1CLK falling edge)

309 L1R x D hold time (from L1CLK falling edge)

310 L1T x D data valid after syncs rising edge (long)

311 L1T x D to high impedance (from L1SY0-L1SY1 falling edge) (long) 0 70 ns

Notes: 1. The ratio CLK/TCLK1 must be greater than 2.5/1.

2. L1T x D becomes valid after the L1CLK rising edge or the sync enable, whichever is later, if long frames are used.

3. Specification valid for both sync methods.

4. See Figure 25.

(1)

(2)

(3)

(3)

(2)

070ns

20 ns

50 ns

0 100 ns

6.66 MHz

2117A–HIREL–11/02

31

Table 22. AC Electrical Specifications - NMSI Timing

(4)

The NMSI mode uses two clocks, one for receive and one for transmit. Both clocks can be internal or external. When the
clock is internal, it is generated by the internal baud rate generator and it is output on L1R x D or L1T x D. All the timing is
related to the external clock pin. The timing is specified for NMSI1. It is also valid for NMS12 and NMS13.

Internal Clock External Clock

Num. Parameter

315 RCLK1 and TCLK1 frequency

(1)

5.12 6.668 MHz

UnitMin Max Min Max

316 RCLK1 and TCLK1 low/high 70 55 ns

317 RCLK1 and TCLK1 rise/fall time

(2)

————ns

318 T x D1 active delay TCLK1 falling edge 0 40 0 70 ns

319 RTS1 active/inactive delay from TCLK1 falling edge 0 40 0 100 ns

320 CTS1 setup time to TCLK1 rising edge 50 10 ns

321 R x D1 setup time to RCLK1 rising edge 50 10 ns

322 R x D1 hold time from RCLK1 rising edge

(3)

10 50 ns

323 CD1 setup time to RCLK1 rising edge 50 10 ns

Notes: 1. The ratio CLK/TCLK1 and CLK/RCLK1 must be greater than 2.5/1 for external clock. For internal clock the ratio must be

greater than 3/1 (the input clock to the baud rate generator may be either CLK or TIM1), in both cases the maximum fre­quency is limited to 16.67 MHz. In asynchronous mode (UART), the bit rate is 1/16 of the clock rate.

2. Schmitt triggers used on input buffers.

3. Also applies to CD

hold time when CD is used as an external sync in BISYNC or totally transparent mode.

4. See Figure 26.

Figure 25. PCM Timing Diagram

L1CLK

(INPUT)

302

L1SY0
L1SY1

(INPUT)

306

L1TXD

(OUTPUT)

L1RXD

(INTPUT)

L1SY0
L1SY1

(INPUT)

L1TXD

(OUTPUT)

1 2 3 4 5 6 7 8 91011

300

12345678

309

308

123456789

302

310

123456789

301

305

SYNC ENVELOPES DATAS

304

307

303

311

307

32

TS68302

2117A–HIREL–11/02

Figure 26. NMSI Timing Diagram

317

RCLK1

321

RXD1

(INPUT)

CD1

(INPUT)

TS68302

316

317

315

322

323

322

(SYNC INPUT)

CD1

TCLK1

TXD1

(OUTPUT)

RTS1

(OUTPUT)

CTS1

(INPUT)

317

317

316

319

315

318

319

320

2117A–HIREL–11/02

33

Functional
Description

The TS68302 uses a microprocessor architecture which has peripheral devices con­nected to the system bus through a dual-port memory. Various parameters, counters,
and all memory buffer descriptor tables reside in the dual-port RAM. The receive and
transmit data buffer may be located in this on-chip RAM or in the off-chip system RAM
(see Figure 29). Six DMA channels are dedicated to the six serial ports (receive and
transmit for each of the three SCC channels). If an SCC channel’s data is programmed
to be located in the external RAM, the CP main controller (RISC processor) will program
the corresponding DMA channel to perform the required accesses. If the data resides in
the on-chip dual-port RAM, then the CP main controller accesses the RAM with one
clock cycle access and no arbitration delays.

The buffer memory structure of the TS68302 can be configured by the software to
closely match I/O channel requirements. The interrupt structure is also programmable to
relieve the on-chip 68000/68008 core from bit manipulation functions for peripherals,
allowing the processor to perform application software or protocol processing.

In some cases, the interface to equipment or proprietary networks may require the use
of standard control and data signals. For these signals, the TS68302 can be pro­grammed to use the NMSI mode. This mode is available for one, two, or all three SCC
ports; remaining ports may then use one of the multiplexed interface modes: IDL, GCI,
or PCM.

Figure 27. Buffer Memory Structure

DUAL-PORT RAM (1152 BYTES)

EXTERNAL MEMORY

TX DATA BUFFER

SYSTEM RAM (576 BYTES)

SCC1 BUFFER

DESCRIPTORS

TABLE

SCC2 BUFFER

DESCRIPTORS

TABLE

SCC3 BUFFER

DESCRIPTORS

TABLE

PARAMETER RAM (576 BYTES)

SCP DESCRIPTOR

TX BUFFER DESCRIPTORS (8)

FRAME STATUS

DATA LENGTH

DATA POINTER

RX BUFFER DESCRIPTORS (8)

FRAME STATUS

DATA COUTDATA COUT

DATA POINTER

D

TX DATA BUFFER

RX DATA BUFFER

DATA

34

SMC1 DESCRIPTOR

SMC2 DESCRIPTOR

TS68302

E

R

TX DATA

RX DATA

2117A–HIREL–11/02

TS68302

68000/68008 Core
Overview

System Integration Block
(SIB)

IDMA Controller The TS68302 has one IDMA channel and six serial DMA channels which operate con-

The TS68302 allows operation either in the full 68000 mode with a 16-bit data bus or in
the 68008 mode with an 8-bit data bus.

The TS68302 has an SIB which simplifies the task of hardware and software design.
The IDMA controller eliminates the need for an external DMA controller on the system
board. In addition, there is an interrupt controller that can be used in a dedicated mode
to generate interrupt acknowledge signals without external logic. Similarly, the chip­select signals and wait-state logic eliminate the need to generate these signals
externally.

The SIB includes the IDMA controller, interrupt controller, parallel I/O ports, dual-port
RAM, three timers, chip-select logic, clock generator, and system control.

currently with other CPU operations. The IDMA can operate in different modes of data
transfer as programmed by the user. The six serial DMA channels for the three full­duplex SCC channels are transparent to the user, implementing bus-cycle-stealing data
transfers controlled by the TS68302’s internal RISC controller. These six channels have
priority over the separate IDMA channels.

The IDMA controller can transfer data between any combination of memory and I/O
devices. In addition, data may be transferred in either byte or word quantities, and the
source and destination addresses may be either odd or even. Every IDMA cycle
requires between two and four bus cycles, depending on the address boundary and
transfer size. If both the source and destination addresses are even, the IDMA fetches
one word of data and then immediately deposits it. If either the source or destination
block begins on an odd boundary, the transfer takes more bus cycles.

The IDMA features are as follows:

• memory-memory, memory-peripheral, or peripheral-memory data transfers,

• operation with data blocks located at even or odd addresses,

• packing and unpacking of operands,

• fast transfer rates: up to 4 MBps at 16 MHz with no wait states,

• full support of all bus exceptions: halt, bus error, and retry,

• flexible request generation

• two address pointer registers and one counter register,

• three I/O lines for externally requested data transfers,

• asynchronous bus structure with 24-bit address and 8- to 16-bit data bus.

Interrupt Controller The interrupt controller, which manages the priority of internal and external interrupt

requests, generates a vector number during the CPU interrupt acknowledge cycle.
Nested interrupts are fully supported.

The interrupt controller receives requests from internal sources (INRQ interrupts) such
as the timers, the IDMA, the serial controllers, and the parallel I/O pins (port B). The
interrupt controller allows the masking of each INRQ interrupt source. When multiple
events within a peripheral can cause the interrupt, each of these events is also
maskable.

2117A–HIREL–11/02

35

Figure 28. Interrupt Controller Block Diagram

TIMERS

SCP

SMCs

DMA

PB8-PB11

SCC1 EVENT

REGISTER

SCC1 MASK

REGISTER

SCC2 EVENT

REGISTER

SCC2 MASK

REGISTER

SCC3 EVENT

REGISTER

SCC3 MASK

REGISTER

3

1

2

2

4

1

1

1

INTERRUPT PENDING REGISTER (IPR)

INTERRUPT MASK REGISTER (IMR)

INTERRUPT IN-SERVICE REGISTER (ISR)

IRQ7/

IPL0

INTERRUPT

RESOLVER

GENERATION

IRQ6/

IPL1

PRIORITY

VECTOR

LOGIC

IRQ1/

IPL2

IPL2-IPL0 TO

TS68000 CORE

IACK1

IACK6

IACK7

TS68000 CORE

DATA BUS

The interrupt controller also receives external (EXRQ) requests. EXRQ interrupts are
received by the IMP according to the operational mode selected. In the normal opera­tional mode, EXRQ interrupts are encoded onto the IPL
operational mode, EXRQ interrupts are presented directly as IRQ

lines. In the dedicated

7, IRQ6, and IRQ1.

The interrupt controller block diagram is shown in Figure 28. The interrupt controller fea­tures are as follows:

• two operational modes: normal and dedicated,

• eighteen priority-organized interrupt sources (internal and external),

• fully nested interrupt environment,

• unique vector number for each internal/external source,

• three selectable interrupt request/interrupt acknowledge pairs.

Parallel I/O Ports Port A and port B are two general-purpose I/O ports. Each pin in the 16-bit port A may

be configured as a general-purpose I/O pin or as a dedicated peripheral interface pin.
Port B has 12 pins. Eight pins may be configured as general-purpose pins or as dedi­cated peripheral interface pins, and four are general-purpose pins, each with interrupt
capability.

36

TS68302

2117A–HIREL–11/02

TS68302

Dual-Port RAM The IMP has 1152 bytes of RAM configured as a dual-port memory. The RAM can be

accessed by the internal RISC controller or one of three bus masters: the 68000 core,
an external bus master, or the IDMA. All internal bus masters synchronously access the
RAM with no wait states. External bus masters can access the RAM and registers syn­chronously or asynchronously.

The RAM is divided into two parts. There are 576 bytes used as a parameter RAM,
which includes pointers, counters, and registers for the serial ports. The other 576 bytes
may be used for system RAM, which may include data buffers, or may be used for other
purposes such as a no-wait-state cache.

Timers There are three timer units. Two units are identical, general-purpose timers; the third

unit can be used to implement a watchdog timer function.

The two general-purpose timers are implemented with a timer mode register (TMR), a
timer capture register (TCR), a timer counter (TCN), a timer reference register (TRR),
and a timer event register (TER). The TMR contains the prescaler value programmed by
the user. The watchdog timer, which has a TRR and TCN, uses a fixed prescaler value.

The timer features are as follows:

• Two general-purpose timer units:

- maximum period of 16 seconds (at 16.67 MHz),

- 60-nanosecond resolution (at 16.67 MHz),

- programmable sources for the clock input,

- input capture capability,

- output compare with programmable mode for the output pin,

- free run and restart modes.

• One watchdog timer with a 16-bit counter and a reference register:

- maximum period of 16 seconds (16.67 MHz),

- 0.5-millisecond resolution (at 16 MHz),

- output signal (WDOG),

- interrupt capability.

External Chip-select
Signals and Wait-state
Logic

The TS68302 has a set of four programmable chip-select signals. Each chip select has
an identical structure. For each memory area, an internally generated cycle-termination
signal (DTACK
cycle-termination logic. The four signals may each support four different classes of
memory, such as high-speed static RAM, slower dynamic RAM, EPROM, and nonvola­tile RAM. The chip-select and wait-state generation logic is active for all potential bus
masters.

) may be defined with up to six wait states to avoid using board space for

Clock Generator The TS68302 has an on-chip clock generator which supplies internal and external high-

speed clocks (up to 16.67 MHz). The clock circuitry uses three dedicated pins: EXTAL,
XTAL, and CLKO.

37

2117A–HIREL–11/02

System Control The IMP system control consists of a system control register (SCR) containing bits for

the following system control functions:

• system status and control logic,

• bus arbitration logic with low interrupt latency,

• hardware watchdog,

• low power (standby) modes,

• disable CPU logic (68000),

• freeze control for debugging on-chip peripherals,

•AS

System Control Register The SCR is a 32-bit register that consists of system status and control bits, a bus arbiter

control bit, hardware watchdog control bits, low power control bits, and freeze select
bits. The eight most significant bits of the SCR report events recognized by the system
control logic and set the corresponding bit in the SCR.

The low power modes are used, when no processing is required from the 68000/68008
core, to reduce the system power consumption to its minimum value. The low power
modes may be exited by an interrupt from an on-chip peripheral.

Disable CPU Logic (68000) This control allows an external processor direct connection to the bus and to the IMP’s

peripherals while the on-chip 68000 core is disabled. Entered during a system reset
(RESET
als for use with other TS68032 units or other processors and is an effective
configuration for systems needing more than three SCCs.

control during read-modify-write cycles.

and HALT asserted together), this mode configures the IMP on-chip peripher-

Freeze Control This control is used to freeze the activity of selected peripherals and to debug systems.

The IMP freezes its activity with no new interrupt requests, no memory accesses (inter­nal or external), and no access of the serial channels. The IDMA controller completes
any bus cycle in progress and releases bus ownership. No further bus cycles will be
started as long as FRZ

remains asserted.

DRAM Refresh Controller The CP main (RISC) controller can optionally handle the dynamic RAM (DRAM) refresh

task without any intervention from the 68000 core. The refresh request can be gener­ated from a TS68302 timer, baud rate generator, or externally. The DRAM refresh
controller performs a standard 68000-type read cycle at programmable address
sequences, with user-provided RAS and CAS generation.

Communications
Processor

The CP in the TS68302 includes the main controller, six serial DMA channels, three
SCCs, an SCP, and two SMCs.

Host software configures each communications channel, as required by the application,
to include parameters, baud rates, physical channel interfaces desired, and interrupting
conditions. Buffer structures are set up for receive and transmit channels. Up to eight
frames may be received or transmitted without host software involvement. Selection of
the interrupt interface is also set by register bits in register space of the device.

Data is transmitted and received using the appropriate buffer descriptors and buffer data
space for a channel. The CP operates is a modified polling mode on each channel and
buffer descriptor to identify buffers awaiting transmission and channels requiring servic­ing. The user sets a bit in the buffer descriptor of a transmit frame; when the CP polls
and detects this bit, it will begin transmission. Generally, no other action is required to
accomplish transmission.

38

TS68302

2117A–HIREL–11/02

TS68302

Main Controller The main controller is a microcode RISC processor that services all the serial channels.

The main controller transfers data between the serial channels and internal/external
RAM, executes host commands, and generates interrupts to the interrupt controller.

Data is transferred from the serial channel to the dual-port RAM or to the external mem­ory through the peripheral bus. If data is transferred between the SCC channels and
external memory, the main controller uses up to six serial DMA channels for the trans­fer. The main controller also controls all character and address comparison and cyclic
redundancy check (CRD) generation and checking.

The execution unit includes the arithmetic logic unit (ALU), which performs arithmetic
and logic operations on the registers.

Serial Communication
Controllers

The TS68302 has three independent SCCs. Each SCC can be configured to implement
different protocols - for example, to perform a gateway function or to interface to an
ISDN basic rate channel. To simplify programming, each protocol implementation uses
identical data structures.

Five protocols are supported: high-level data link control (HDLC), binary synchronous
communication (BISYNC), synchronous/asynchronous digital data communications
message protocol (DDCMP), V.110, universal asynchronous receiver transmitter
(UART), and a fully transparent mode. To aid system diagnostics, each SCC may be
configured to operate in either an echo or loopback mode. In echo mode, the IMP
retransmits any signals received; in loopback mode, the IMP locally receives signals
originating from itself.

The clock pins (RCLK, TCLK) for each SCC can be programmed for either an external
or internal source, with user-programmable baud rates available for each SCC channel.

Each SCC also supports the standard modem control signals: request to send (RTS
clear to send (CTS
through the parallel I/O pins.

The SCC features are as follows:

• programmable baud rate generator driven by the internal or external clock,

• data may be clocked by the programmable baud rate generator or directly by an
external clock,

• provides modem signals RTS

• Full-duplex operation,

• Automatic echo mode,

• Local loopback mode,

• Baud rate generator outputs available externally.

), and carrier detect (CD). Other modem signals may be provided

, CTS, and CD,

),

2117A–HIREL–11/02

The SCC HDLC mode key features are as follows:

• flexible data buffers with multiple buffers per frame allowed,

• separate interrupts for frames and buffers (receive and transmit),

• four address comparison registers with mask,

• maintenance of five 16-bit counters,

• flag/abort/idle generation/detection,

• zero insertion/deletion,

• NRZ/NRZI data encoding,

• 16-bit or 32-bit CRC-CCITT generation/checking,

• detection of non-octet aligned frames,

39

• detection of frames that are too long,

• programmable 0 - 15 FLAGS between successive frames,

• automatic retransmission in case of collision.

The SCC BISYNC mode key features are as follows:

• flexible data buffers,

• eight control recognition registers,

• automatic SYNC1 and SYNC2 detection,

• SYNC/DLE stripping and insertion,

• CRC-16 and LRC generation/checking,

• parity (VRC) generation/checking,

• supports BISYNC transparent operation (use of DLE characters),

• supports promiscuous (totally transparent) reception and transmission,

• maintains parity error counter,

• external SYNC support,

• reverse data mode.

The SCC DDCMP mode key features are as follows:

• synchronous and asynchronous DDCMP links supported,

• flexible data buffers,

• four address comparison registers with mask,

• automatic frame synchronization,

• automatic message synchronization by searching for SOH, ENQ, or DLE,

• CRC-16 generation/checking,

• NRZ/NRZI data encoding,

• maintenance of four 16-bit error counters.

The SCC V.110 mode key features are as follows:

• provides synchronization and reception of 80-bit frames,

• automatic detection of framing errors,

• allows transmission of the 80-bit frame.

The SCC UART mode key features are as follows:

• flexible message-oriented data buffers,

• multidrop operation,

• receiver wakeup on idle line or address mode,

• eight control character comparison registers,

• two address comparison registers,

• four 16-bit error counters,

• programmable data length (7 - 8 bits),

• programmable 1 or 2 stop bits with fractional stop bits,

• even/odd/force/no parity generation,

• even/odd/no parity check,

• frame error, noise error, break, and idle detection,

• transmits idle and break sequences,

• freeze transmission option,

40

TS68302

2117A–HIREL–11/02

TS68302

• maintenance of four 16-bit error counters,

• provides asynchronous link over which DDCMP may be used,

• Flow control character transmission suppor ted.

Serial Communication Port The SCP is a full-duplex, synchronous, character-oriented channel which provides a

three-wire interface (TXD, RXD, and clock). The SCP consists of independent transmit­ter and receiver sections and a common SCP clock generator. The transmitter and
receiver section use the same clock, which is derived from the main clock by an on-chip
baud rate generator. The TS68302 is an SCP master, generating both the enable and
the clock signals. The enable signals may be generated by the general-purpose I/O
pins.

The SCP allows the TS68302 to communicate with a variety of serial devices for the
exchange of status and control information using a subset of the Motorola serial periph­eral interface (SPI). Such devices may include industry-standard CODECs and other
microcontrollers and peripherals.

The SCP can be configured to operate in a local loopback mode, which is useful for
diagnostic functions. The receiver and the transmitter operate normally in these modes.

The SCP features are as follows:

• three-wire interface (SPTXD, SPRXD, and SPCLK),

• full-duplex operation,

• clock rate up to 4.096 MHz,

• programmable baud rate generator,

• local loopback capability for testing purposes.

Serial Management
Controllers

Serial Channels Physical
Interface

The SMCs are two synchronous, full-duplex ports that may be configured to operate in
either IDL or GCI mode to handle the maintenance and control portions of these inter­faces. The SMC ports are not used in PCM or NMSI modes.

The SMC features are as follows:

• two modes of operation - IDL and GCI,

• local loopback capability for testing purposes,

• full-duplex operation,

• SMC1 in GCI mode detects collisions on the D channel.

The serial channels physical interface connects the physical layer serial lines and the
serial controllers (three SCCs and two SMCs). The interface implements both the rout­ing and the time-division multiplexing for the full ISDN bandwidth. It supports four buses:
IDL, GCI, PCM, and NMSI (a nonmultiplexed modem interface). The multiplexed modes
(IDL, GCI, and PCM) also allow multiple channels (e.g., ISDN B channels) or user­defined subchannels to be assigned to a given SCC. The serial interface also supports
two testing modes: echo and loopback.

For the IDL and GSI buses, support of management functions in the frame structure is
provided by the SCP or SMCs, respectively. Refer to Figure 29 for the serial channels
physical interface block diagram.

2117A–HIREL–11/02

41

Figure 29. Serial Channels Physical Interface Block Diagram

TS68000 DATA BUS

TO SMC1 TO SMC2 TO SCC1 TO SCC2 TO SCC3

PHYSICAL INTERFACE BUS

TXD

RXD

CTS

RTS

LAYER-1 BUS

INTERFACE

L1RQ

L1TXD

L1GR

L1RXD

ISDN INTERFACE OR SCC1

SIMASK

MASK REGISTER

CLOCKS

TIME-SLOT

ASSIGNER

L1SY1

SIMODE

MODE REGISTER

MUX MUX MUX

L1CLK

SCC2 SCC3

42

TS68302

2117A–HIREL–11/02

TS68302

Preparation For
Delivery

Packaging Microcircuits are prepared for delivery in accordance with MIL-STD-1835.

Certificate of Compliance Atmel offers a certificate of compliance with each shipment of parts, affirming the prod-

ucts are in compliance either with MIL-STD-883 or Atmel standards and guaranteeing
the parameters are tested at extreme temperatures for the entire temperature range.

Handling MOS devices must be handled with certain precautions to avoid damage due to accu-

mulation of static charge. Input protection devices have been designed in the chip to
minimize the effect of this static buildup. However, the following handling practices are
recommended:

a) Device should be handled on benches with conductive and grounded surfaces.

b) Ground test equipment, tool and operator.

c) Do not handle devices by the leads.

d) Store devices in conductive foam or carriers.

e) Avoid use of plastic, rubber, or silk in MOS areas.

f) Maintain relative humidity above 50%, if practical.

2117A–HIREL–11/02

43

Package Mechanical
Data

132-pin - Ceramic Pin
Grid Array (in millimeter)

TOP VIEW

34.544 ± 0.254

2.54 BSC

34.544 ± 0.254

1.27 ± 0.127

4.57 ± 0.025

1.27 ± 0.025

2.667 ± 0.254

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3.17 ± 0.635

2.54 BSC

2

3

BOTTOM VIEW

4

5

6

7

8

9

10

13

11

12

44

TS68302

2117A–HIREL–11/02

132-pin - Ceramic Quad
Flat Pack/CERQUAD

TS68302

pin one ident

VB

L

S

A

CERQUAD132

Top view

(window frame down)

M

D

G

J

H

0.1 (0.004)

D

SEATING PLANE

-T-

R

DIM MIN MAX MIN MAX

A
B
C
D
G
H

J

K

L
R
S
V

M

K

C

Millimeters

22.86

21.85

22.86

21.85

3.94

0.292

0.204

0.64

0.5

0.13

0.51

20.32

0.64

27.63

27.23

27.63

27.23
0°

4.52

BSC

1.0

0.20

0.76
REF

-

8°

Inches

0.86

0.86

0.155

0.008

0.025

0.019

0.005

0.020

0.800

0.025

1.072

1.072
0°

0.90

0.90

0.178

0.0115
BSC

0.039

0.008

0.030
REF

-

1.088

1.088

8°

Terminal
Connections

132-pin - Ceramic Pin
Grid Array

132-pin - Ceramic Quad
Flat Pack/CERQUAD

See Figure 2.

See Figure 3.

Ordering Information

HI-REL Product

Commercial Atmel
Part-Number Norms Package

TS68302MRB/C16 MIL-STD-883 PGA 132 -55/+125 16.67 -

TS68302MAB/C16 MIL-STD-883 CERQUAD 132 -55/+125 16.67 -

TS68302DESC01QXC DESC PGA 132

TS68302DESC01QYA DESC CERQUAD 132

Note: 1. Gullwing leads.

(1)

Temperature Range

-55/+125 16.67 5962-93159

(1)

-55/+125 16.67 5962-93159

Tc (°C)

Frequency

MHz

Drawing
Number

2117A–HIREL–11/02

45

Standard Product

Commercial Atmel
Part-Number Norms Package

TS68302VR16 Atmel Standard PGA 132 -40/+85 16.67 Internal

TS68302MR16 Atmel Standard PGA 132 -55/+125 16.67 Internal

TS68302VA16 Atmel Standard CERQUAD 132

TS68302MA16 Atmel Standard CERQUAD 132

Note: 1. Gullwing leads.

TS68302 M A B/C 16

Type

Temperature range: Tc
M: -55, +125°C
V: -40, +85°C
C: 0, +70°C

Package:
R: Pin Grid Array 132
A: CERQUAD 132
(Gullwing leads)

Temperature Range

(1)

(1)

-55/+125 16.67 Internal

Frequency

Tc (°C)

-40/+85 16.67 Internal

Speed (MHz)

Screening level:

---- : Standard
B/C: MIL-STD-883, class B
B/T: Class B Screening
according to MIL-STD-883

Hirel lead finish:

--: Gold for PGA or
Tinned for CERQUAD
1: Tinned for PGA

MHz

Drawing
Number

Note: For availability of the different versions, contact your local Atmel sales office.

46

TS68302

2117A–HIREL–11/02

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© Atmel Corporation 2002.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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Other terms and product names may be the trademarks of others.

Printed on recycled paper.

2117A–HIREL–11/02

0M