The Atmel®SAM4S-EK toolkit contains the following items:
Board:
– a SAM4S-EK board
– a universal input AC/DC power supply with US, Europe and UK plug adapters
Cables:
– one USB cable
– one serial RS232 cable
A Welcome Letter
Figure 2-1.Unpacked SAM4S-EK
Section 2
Kit Contents
Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit.
SAM4S-EK Development Board User Guide2-1
11139A–ATARM–29-Nov-11
Kit Contents
2.2Electrostatic Warning
The SAM4S-EK board is shipped in a protective anti-static package. The board must not be subjected to
high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the components or any other metallic element of the board.
2-2SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
3.1Power up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right
power plug adapter corresponding to that of your country, and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the
screen and enjoy the demo.
3.2Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can
downloadsamplecodeandgettechnicalsupportfromAtmelwebsite
This section introduces the Atmel SAM4S Evaluation Kit design. It introduces system-level concepts,
such as power distribution, memory, and interface assignments.
The SAM4S-EK board is based on the integration of an ARM®Cortex®-M3 processor with on-board
NAND Flash and a set of popular peripherals. It is designed to provide a high performance processor
evaluation solution with high flexibility for various kinds of applications.
Figure 4-1.SAM4S-EK Block Diagram
Section 4
Evaluation Kit Hardware
SAM4S-EK Development Board User Guide4-1
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.2Features List
Here is the list of the main board components and interfaces:
SAM4S16 chip LQFP100 package with optional socket footprint
12 MHz crystal
32.768 KHz crystal
Optional SMB connector for external system clock input
NAND Flash
2.8 inch TFT color LCD display with touch panel and backlight
UART port with level shifter circuit
USART port with level shifter circuit multiplexed with RS485 port with level shifter circuit
Microphone input and mono/stereo headphone jack output
SD/MMC interface
Reset button: NRST
User buttons: Left and Right
QTouch
Full Speed USB device port
JTAG/ICE port
On-board power regulation
Two user LEDs
Power LED
BNC connector for ADC input
BNC connector for DAC output
User potentiometer connected to the ADC input
ZigBEE connector
2x32 bit PIO connection interfaces (PIOA, PIOC) and 1x16 bit PIO connection interface (PIOB)
®
buttons: Up, Down, Left, Right, Valid and Slider
4.3Function Blocks
4.3.1Processor
The SAM4S-EK is equipped with a SAM4S16 device in LQFP100 package.
4.3.2Memory
The SAM4S16 chip embeds:
1024 Kbytes of embedded Flash
128 Kbytes of embedded SRAM
16 Kbytes of ROM with embedded BootLoader routines (UART, USB) and In-Application Programming
functions (IAP) routines.
4-2SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
The SAM4S features an External Bus Interface (EBI) that permits interfacing to a broad range of external
memories and virtually to any parallel peripheral. The SAM4S-EK board is equipped with a memory
device connected to the SAM4 EBI:
One NAND Flash MT29F2G08ABAEA.
Figure 4-2.NAND Flash
+3V3
+3V3
PC17
PC16
PC9
PC10
JP9
JP9
Header2
Header2
PC14
PC18
R190RR190R
R2147KR2147K
R15
R15
47K
47K
DGND
+3V3
R22
R22
0R nm
0R nm
R16
R16
47K
47K
NAND FLASH
MN3MN3
MT29F2G08ABAEA
16
CLE
17
ALE
8
RE
18
WE
9
CE
7
R/B
19
WP
1
N.C1
2
N.C2
3
N.C3
4
N.C4
5
N.C5
6
N.C6
10
N.C7
11
N.C8
14
N.C9
15
N.C10
20
N.C11
21
N.C12
22
N.C13
23
N.C14
24
N.C15
25
N.C16
26
N.C17
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
N.C28
N.C27
N.C26
N.C25
N.C24
N.C23
PRE
N.C22
N.C21
N.C20
N.C19
N.C18
VCC
VCC
VSS
VSS
29
30
31
32
41
42
43
44
48
47
46
45
40
39
38
35
34
33
28
27
37
12
36
13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
C27
C27
100nF
100nF
C28
C28
100nF
100nF
+3V3
DGND
C29
C29
1uF
1uF
NCS0 chip select signal is used for NAND Flash chip selection. Furthermore, a dedicated jumper (JP9)
can disconnect it from the on-board memories, thereby letting NCS0 free for other custom purpose.
4.3.3Clock Circuitry
The clock generator of a SAM4S microcontroller is made up of:
A Low Power 32.768 Hz Slow Clock Oscillator with bypass mode.
A 3 to 20 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB).
A factory programmed fast internal RC Oscillator. 3 output frequencies can be selected: 4 (default
value), 8 or 12 MHz.
A 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller.
A 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and
to the peripherals. The input frequency of PLLA is from 7.5 and 20 MHz.
The SAM4S-EK board is equipped with one 12 MHz crystal, optional Piezoelectric Ceramic Resonator
12 Mhz (Murata ref. CSTCE12M0G15L99-R0), one 32.768 Hz crystal and an external clock input connector (optional, not populated by default).
Figure 4-3.External Clock Source
NOT POPULATE
23
J1J1
DGND
D
1
54
DGND
R2
49.9R 1%R249.9R 1%
R1DNPR1DNP
3
DGND
R
R
3DNP
3DNP
1
Y1Y1
D
NP
2
R
7DN
7DN
PR
P
DGND
C
C
120pF
120pF
C
C
220pF
220pF
212MHz
212MHz
Y
Y
R40RR40R
R50
R50
3
3
C
C
20pF
20pF
MN1
12BTRG
MN1
DGND
C4
20pFC420pF
49
8
4
R9DNPR9DNP
32
XIN
R10DNPR10DNP
XOUT32
XIN
PB9
R6DN
R6DN
R
R
PB8
XO
R8DN
R8DN
97
P
P
PB9_XIN
PB8_XOUT
SAM4S
PA7_RTS0_PWMH3
PA8_CTS0_AD
UT
96
P
P
R1
R1
1
1
0R
0R
R12
R12
0
0
XIN32
XOUT32
R
R
1
3
Y3
Y3
32.768KHz
32.768KHz
2
PA7
PA8
SAM4S-EK Development Board User Guide4-3
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
The SAM4S chip internally generates the following clocks:
SLCK, the Slow Clock, which is the only permanent clock of the system
MAINCK, the output of the Main Clock Oscillator selection: either a Crystal Oscillator or a 4/8/12 MHz
Fast RC Oscillator
PLLACK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLA)
PLLBCK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLB)
4.3.4Reset Circuitry
On-board NRST button BP1 provides an external reset control of the SAM4S.
The NRST pin is bidirectional. It is handled by the on-chip reset controller. It can be driven low to provide
a reset signal out to the external components. Conversely, it can be asserted low from the outside to
reset the microcontroller Core and the peripherals. The NRST pin integrates a permanent pull-up resistor
of about 100 kOhm to VDDIO.
On the SAM4S-EK board, the NRST signal is connected to the LCD module and JTAG port.
Note:At power-on, the NRST signal is asserted with a default duration of 2 clock cycles. That duration may not be
sufficient to correctly reset any other system or board devices connected to that signal. First, in your custom
application, you need to check for these devices' datasheets about reset duration requirements. Then, you
need to set an appropriate configuration in the NRST Manager. This is done through the ERSTL field in the
RSTC_MR register. The NRST duration is thereby configurable between 60 µs and 2 s, whether it is subsequently activated by a software reset or a user reset. Refer to the SAM4S datasheet for in depth
information.
4.3.5Power Supply and Management
The SAM4S-EK board is supplied with an external 5V DC block through input J9. It is protected by a
PolyZen diode MN9 and an LC combinatory filter MN10. The PolyZen is used in the event of an incorrect
power supply connection.
The adjustable LDO regulator MN12 is used for the 3.3V rail main supply. It powers all the 3.3V components on the board.
Figure 4-4.Power Block
The SAM4S product series has different types of power supply pins:
J9
J9
Power Jack 2.1mm
Power Jack 2.1mm
1
2
3
+5V
MN9
MN9
ZEN056V130A24LS
ZEN056V130A24LS
1
3
2
MN12
MN12
MIC29152WU
MIC29152WU
Micrel's 1.5A LDO, TO263-5
Micrel's 1.5A LDO, TO263-5
VIN2VOUT
1
SD
ADJ
GND1
GND2
3
6
DGND
MN10
MN10
BNX002-01
BNX002-01
1
SV
2
SG
C65
C65
22uF
22uF
R89
R89
169K 1%
169K 1%
R92
R92
102K 1%
102K 1%
CG1
CG2
CG3
+
+
C64
C64
100nF
100nF
4
5
3
CV
4
5
6
+
+
C75
C75
100uF-TAN-6.3V
100uF-TAN-6.3V
+3V3
C76
C76
100nF
100nF
+5V
DGND
+
+
+
+
C66
C66
C98
C98
22uF
22uF
220uF-ELE-16V
220uF-ELE-16V
VDDIN pin:
Power for the internal voltage regulator, ADC, DAC, and analog comparator power supplies.
The voltage ranges from 1.8V to 3.6V.
4-4SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
4.3.6UART
Evaluation Kit Hardware
VDDIO pins:
Power for the Peripherals I/O lines.
The voltage ranges from 1.62V to 3.6V.
VDDOUT pin:
Output of the internal voltage regulator.
VDDCORE pins:
Power for the core, including the processor, embedded memories and peripherals.
The voltage ranges from 1.62V to 1.95V.
VDDPLL pin:
Power for the PLL A, PLL B and 12 MHz oscillator.
The voltage ranges from 1.62V to 1.95V.
Note:VDDPLL should be decoupled and filtered from VDDCORE.
The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes. It offers an ideal channel for in-situ programming solutions. This UART
is associated with two PDC channels to reduce the processor time on packet handling.
4.3.7USART
This two-pin UART (TXD and RXD only) is buffered through an RS232 Transceiver MN6 and brought to
the DB9 male connector J7.
Figure 4-5.UART
MN6
MN6
MAX3232CSE
MAX3232CSE
16
9
9
VCC
2
V+
6
V-
5
1
GND
1
1
IN
T1
2
1
UT
R1O
0
1
IN
T2
9
UT
R2O
C1+
C1-
C2+
C2-
T1OUT
R1IN
T2OUT
R2I
1
C38
C38
100nF
100nF
3
4
C42
C42
100nF
100nF
5
1
4
1
3
7
8
N
DGND
1
6
2
7
3
8
4
9
5
FGND
J7J7
10
11
PA10
PA9
+
T
T
SMD
SMD
3V3
P5
P5
R
R
100K
100K
45
45
+3V3
R46
R46
100
100
R470
R470
R480
R480
+3V3
C3
C3
100nF
100nF
C40
C40
100nF
100nF
C41
C41
100nF
K
K
100nF
R
R
R
R
GND
D
TP6
TP6
SM
SM
D
D
The Universal Synchronous/Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous/asynchronous serial link. The data frame format is extensively configurable (data
length, parity, number of stop bits) to support a broad range of serial communication standards. The
USART is also associated with PDC channels for TX/RX data access.
Note:For design optimization purposes, both transmitters have been implemented on the same
PIO lines, that is PA21, 22, 23, 24 25.
To avoid any electrical conflict, the RS485 transceiver is isolated from the receiving line PA21.
Should you need to implement an RS485 channel in place of the RS232, follow the procedure below:
1.make sure your software will permanently set PA23 to a high level - this will permanently disable the
RS232 receiver.
2.solder a shunt resistor in place of R25 (a solder drop will do).
SAM4S-EK Development Board User Guide4-5
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.3.8RS232
SAM4S-EK connects the USART1 bus (including TXD, RXD, RTS, CTS handshake signal controls and
EN command) to the DB9 male connector J5 through the RS232 Transceiver MN5.
Figure 4-6.USART
TXD1
RXD1
RTS1
CTS1
PA23
PA22
PA21_232
PA24
PA25
+3V3
+3V3
+3V3
C31
C31
4.7uF
4.7uF
DGND
R32
R32
47K
47K
R310RR310R
R330RR330R
R340RR340R
R350RR350R
R360RR360R
R3747KR3747K
C32
C32
100nF
100nF
DGND
C33
C33
100nF
100nF
C36
C36
100nF
100nF
USART
MN5
MN5
ADM3312EARU
ADM3312EARU
3
VCC
1
V+
21
V-
23
GND
19
SD
5
EN
T1IN7T1OUT
10
R1OUT
T2IN8T2OUT
11
R2OUT
9
T3IN
12
R3OUT
R1IN
R2IN
T3OUT
R3IN
C1+
C1C2+
C2C3+
C3-
6
20
2
4
24
22
18
15
17
14
16
13
C34
C34
100nF
100nF
C35
C35
100nF
100nF
C37
C37
100nF
100nF
R380RR380R
PA21_485
PA21
PA21_232
DGND
3
2
JP31JP31
1
J5J5
1
6
2
7
3
8
4
9
5
10
11
FGND
4.3.9RS485
As noticed above, the USART1 is shared with the RS485 port, connected to the transceiver MN4, connected to the 3-point connector J4. The design includes selectable jumpers for RS485 bus termination
resistors selection (JP10, JP11, JP12).
Figure 4-7.RS485
4.3.10Display Interface
The SAM4S-EK carries a TFT Transmissive LCD module with touch panel, FTM280C34D. Its integrated
driver IC is ILI9325. The LCD display area is 2.8 inches diagonally measured, with a native resolution of
240 x 320 dots.
RXD1
CTS1
RTS1
TXD1
PA21_485
PA25
PA24
PA22
R250R nmR250R nm
R270RR270R
R280RR280R
+3V3+3V3
RS 485
R23
R23
10K
10K
MN4
MN4
ADM3485ARZ
JP28
JP28
Header2 nm
Header2 nm
ADM3485ARZ
1
RO
2
RE
3
DE
4
DI
VCC
GND
A
B
+3V3
8
5
6
7
DGND
C30
C30
100nF
100nFR260RR260R
R29
R29
120R
120R
JP11
JP11
Header2
Header2
DGND
R24
R24
0R nm
0R nm
JP10
JP10
Header2
Header2
JP12
JP12
Header2
Header2
R30
R30
0R nm
0R nm
FGND
J4J4
1
2
3
4.3.11LCD Module
The LCD module gets reset from the NRST signal. As explained, this NRST is shared with the JTAG port
and the push-button BP1. The LCD chip select signal is connected to NCS1; the jumper JP13 can disconnect it so that this PIO line is available for other custom usage.
The SAM4S communicates with the LCD through PIOC where an 8-bit parallel “8080-like” protocol data
bus has to be implemented by software.
The LCD backlight is made of four integrated white chip-LEDs arranged in parallel. These are driven by
an AAT3155 charge pump, MN8.The AAT3155 is controlled by the SAM4S through a single PIO line
PC13 interface; the 0 Ohm resistor R68 is mounted in series on this line, which permits to use it for other
custom purposes. In that case, the pull-up resistor R64 maintains the charge pump permanently enabled
by default.
On the anode drive line, a 0 Ohm resistor R59 is implemented in series for an optional current limitation.
Figure 4-9.Backlight Control
+3V3
PC13
R680RR68
0R
FB1
FB1
BN03K314S300R
BN03K314S300R
+3V3
R64
R64
47K
47K
DGND
MN8
MN8
AAT3155ITP-T1
AAT3155ITP-T1
10
C1+
C54
C54
1uF
1uF
9
C1-
11
EN/SET
5
IN
C57
C57
4.7uF
4.7uF
4
GND
LCD BACKLIGHT
C2+
OUTCP
7
C55
C55
1uF
6
C2-
8
3
D1
2
D2
1
D3
12
D4
1uF
LED_A
LED_K1
LED_K2
LED_K3
LED_K4
TP7TP7
DGND
C56
C56
1uF
1uF
SAM4S-EK Development Board User Guide4-7
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.3.13Touch Screen Interface
The LCD module integrates a 4-wire touch panel controlled by MN7 (ADS7843) which is a slave device
on the SAM4S SPI bus. The controller sends back the information about the X and Y positions, as well
as a measurement for the pressure applied to the touch panel. The touch panel can be used with either
a stylus or a finger.
The ADS7843 touch panel controller connects to the SPI0 interface via the NPCS0 control signal. Two
interrupt signals are connected and provide events information back to the microcontroller: PenIrq and
Busy.
Note:PenIrq (PA16) is shared with ZigBEE signal IRQ0.
Busy (PA17) is shared with ZigBEE signal IRQ1.
Therefore, if using a ZigBEE interface in concurrence with the TouchScreen controller, take
care not to have both drivers enabled at the same time on either PA16 or PA17.
For that purpose, 0 Ohm resistors have been implemented on these PIO lines in order to disconnect
either end driver from the other:
On the touch panel controller side, R67 and R69.
On ZigBEE side, R117 and R120.
for further information, refer to the “Schematics” section.
Touch ADC auxiliary inputs IN3/IN4 of the ADS7843 are connected to test point (TP8, TP9) for optional
function extension.
Figure 4-10. Touch Panel Control
4.3.14JTAG/ICE
A standard 20-pin JTAG/ICE connector is implemented on the SAM4S-EK for the connection of a compatible ARM JTAG emulator interface, such as the SAM-ICE from Segger.
+3V3
R62
PA14
PA13
PA12
R62
100K
100K
R660RR660R
R670RR670R
R700RR700R
C58
C58
100nF
100nF
C59
C59
100nF
100nF
PA11
PA17
C6
C6
100nF
100nF
+3V3
R65
R65
100K
100K
R
R
690R
690R
L2
L2
10uH/100
10uH/100
R71
R71
1
1
R
R
0
0
C61
C61
4.7uF
4.7uF
R740RR74
0R
PA16
+3V3
mA
mA
DGND
MN7
MN7
ADS7843
ADS7843
E
E
X_RIGHT
Y_UP
X_LEFT
Y_DO WN
TP8
TP8
SMD
SMD
R72
R72
100K
100K
AGND_TPAGND_TP
2
XP
3
YP
4
XM
5
R73
R73
100
100
YM
7
3
IN
8
4
IN
K
K
T
T
P9
P9
SM
SM
D
D
DOUT
BUSY
PENIR
DCLK
DIN
VR
VC
VC
GND
1
6
1
4
1
2
1
5
CS
13
11
Q
9
EF
1
C1
10
C2
6
Notes: 1.The NRST signal is connected to BP1 system button and is also used to reset the LCD
module. The 0 ohm resistor R44 may be removed in order to isolate the JTAG port from
this system reset signal.
2.The TDO pin is in input mode with the pull-up resistor disabled when the Cortex M3 is
not in debug mode. To avoid current consumption on VDDIO and/or VDDCORE due to
floating input, the internal pull-up resistor corresponding to this PIO line must be
enabled.
4-8SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Figure 4-11. JTAG Interface
4.3.15Audio Interface
The SAM4S-EK board supports both audio recording and playback.
The audio volume can be adjusted using the potentiometer RV1, and the microphone amplifier gain can
be adjusted via jumpers (fixed gain of 24 or 26 dB).
4.3.16Microphone Input
The embedded microphone is connected to an audio pre-amplifier using the TS922 operational amplifier
(MN11). The gain is set by using JP14 and JP15 jumpers; both must be set or removed at the same
time.
Evaluation Kit Hardware
+3V3
R39
R39
R40
R40
1
1
R4
100
100
R4
K
K
100
100
K
K
R440
R440
K
K
100
100
PB4
PB6
PB7
PB5
N
RST
R42
R42
100
100
R43
R43
100
100
K
K
K
K
R
R
1
1
1
1
19
1
3
5
7
9
1
3
5
7
6
J6J
ref
VT
n
TRST
TDI
M
T
TCK
RTC
TDO
SRST
n
DBGRQ
DBGACK
2
Vsupply
4
G
1
ND
6
GND
2
8
GND
3
S
K
GND
GND
GND
GND
GND
GND
0
1
4
2
1
5
4
1
6
6
1
7
8
1
8
0
2
9
DGND
By modifying the jumper positions, you can select each of the following gain values:
20 dB (default setting, both JP14 and JP15 are off)
26 dB (both JP14 and JP15 are on).
Note:
3.The TB1 series 0 Ohm resistor is a reservation for future impedance adaptation facility.
Under specific amplifier settings conditions, this enables the easy insertion of a capacitor or any other bipolar device on the audio path. On the other hand, R83 is a default
0 Ohm resistor that enables the disconnection of PB0 from the audio input path for custom usage.
4.The audio pre-amplifier MN11 is powered by a dedicated low dropout regulator
MIC5219-3.3 (MN14).
SAM4S-EK Development Board User Guide4-9
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
Figure 4-12. Microphone Input
AGND
AGND
C63
C63
22uF
22uF
C73
C73
22uF
22uF
AVDD
12
AGND
R77
R77
470R
470R
R781KR78
1K
MIC1
MIC1
SVB6050
SVB6050
R851KR85
1K
R88
R88
470R
470R
C67
C67
1uF
1uF
C68
C68
1uF
1uF
AUDIO IN
R7547KR7547K
R7647KR7647K
MN11
R87
R87
47K
47K
JP15
JP15
Header2
Header2
MN11
TS922
TS922
2
IN1-
3
IN1+
7
OUT2
6
IN2-
5
IN2+
R791KR79
1K
R821KR82
1K
AGND
C77
C77
4.7uF
4.7uF
C69
C69
1nF
1nF
AGND
AVDD
R801KR80
1K
R841KR84
1K
C72
C72
1nF
1nF
R90
R90
100K
100K
R93
R93
100K
100K
R86
R86
47K
47K
JP14 and JP15 should be set
or removed together
C62
C62
100pF
100pF
JP14Header2JP14Header2
1
OUT1
8
VCC
4
GND
R81
R81
100R
100R
AVDD
AGND
C74
C74
100nF
100nF
AGND
C71
C71
22nF
22nF
VCC33
FB2
FB2
BN03K314S300R
BN03K314S300R
R910RR91
0R
DGND
R830RR83
0R
PB0
4.3.16.1 Headphone Output
The SAM4S-EK evaluation kit supports mono/stereo audio playback driven by a TPA0223 audio amplifier connected to two DAC channels of the microcontroller.
The TPA0223 is a 2W mono Bridge-Tied-Load (BTL) amplifier designed to drive speakers with as low as
4 Ohm impedance. The amplifier can be reconfigured on the fly to drive two stereo Single-Ended (SE)
signals into head phones.
Figure 4-13. Headphone Output
+5V
VCC33
PB13
AUDIO_OUTL
1
JP29JP29
3
Test Pad SQ-40TH
Test Pad SQ-40TH
2
C84 0.47uFC84 0.47uF
TP12
C88 0.47uFC88 0.47uF
DGND
AGND
FB3
FB3
BN03K314S300R
BN03K314S300R
C79
C79
1uF
1uF
JP17Header2JP17Header2
C85 0.47uFC85 0.47uF
JP19Header2JP19Header2
AGND
AGND
+
+
C80
C80
10uF
10uF
R9833KR9833K
R9947KR9947K
R10033KR10033K
R10447KR10447K
R10533KR10533K
VDD_AMP
C82
C82
100nF
100nF
AUDIO OUT
MN13
MN13
TPA0223DGQ
TPA0223DGQ
3
VDD
5
RIN
1
MONO-IN
9
LIN
AGND
RO/MO+
LO/MO-
ST/MN
SHUTD0WN
BYPASS
PAD
11
GND
6
10
7
2
4
8
C81220uF-TAN-6.3V
C81220uF-TAN-6.3V
R951KR951K
R971KR971K
AGND
C83220uF-TAN-6.3V
C83220uF-TAN-6.3V
R101100KR101100K
R103100KR103100K
C86 0.47uFC86 0.47uF
J10J10
1
2
J11
J11
Phonejack Stereo 3.5
Phonejack Stereo 3.5
R102100KR102100KTP12
JP20
JP20
Header2
Header2
AGND
5
4
3
2
1
VDD_AMP
AGND
C87
C87
1uF
1uF
+
+
+
+
AGND
AGND
MN14
DGND
C91
C91
4.7uF
4.7uF
DGND
C93
C93
470pF
470pF
MN14
MIC5219-3.3YMM
MIC5219-3.3YMM
2
IN
1
EN
GND
GND
GND
4
BYP
GND
OUT
3
5
6
7
8
DGND
VCC33+5V
+
+
C92
C92
100uF-TAN-6.3V
100uF-TAN-6.3V
DGND
4-10SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Using a readily available 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no
plug is inserted. When closed, a 100-kOhm/1-kOhm divider pulls the ST/MN input low. When a jack plug
is inserted, the 1-kOhm resistor is disconnected and the ST/MN input is pulled high. The mono speaker
(J10 connector) is also physically disconnected from the RO/MO+ output so that no sound is heard from
the speaker while the headphones are inserted.
4.3.17USB Device
The SAM4S UDP port is compliant with the Universal Serial Bus (USB) rev 2.0 Full Speed device specification. J15 is a micro B-type receptacle for USB device.
Both 27-Ohm resistors R114 and R116 build up a 90-Ohm differential impedance together with the
(embedded) 6-Ohm output impedance of the SAM4S full speed channel drivers.
R110 and R112 build up a divider bridge from VBUS +5V to implement plug-in detection (5V level gets
lowered to a PIO compatible 3.3V level) through PC21.
Figure 4-14. USB
PC21
FGN
11047K
11047K
R
R
11268K
11268K
R
R
Evaluation Kit Hardware
J15
J15
USB Micro B
USB Micro B
5V D- D+ ID G
5V D- D+ ID G
8
9
D
R
R
V2
V2
V5.5MLA060
V5.5MLA060
C94
C94
10pF
10pF
DGND
3
3
123
6
475
RV1
RV1
V5.5MLA0603
V5.5MLA0603
DGNDFGND
4.3.18Analog Interface
4.3.18.1 Analog Reference
The 3V voltage reference is based on an LM4040 (Precision Micropower Shunt Voltage Reference).
This ADVREF level can be set as 3V or 3.3V via the jumper JP2.
Figure 4-15. Analog Vref
PB1
PB11
0
R11427RR11427R
R11627RR11627R
SAM4SSAM
ADVREF
33
VC
C
JP2JP2
MN2
MN2
LM4040-2.5
LM4040-2.5
+5V
DGND
R13
R13
2.2K
2.2K
1
DGND
C5
100nFC5100nF
2
3
1
ADVREF
SAM4S-EK Development Board User Guide4-11
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.3.18.2 Analog Input
The BNC connector CN1 is connected to the ADC port PB1 as an external analog input. An on-board 50Ohm resistor termination can be applied by closing jumper JP16. A low pass filter can be implemented
for the BNC connector CN1 by replacing R94 and C78 with custom resistor and capacitor values,
depending on your application requirements.
A 10-KOhm potentiometer (VR1) is also connected to this channel to implement an easy access to ADC
programming and debugging (or implement an analog user control like display brightness, volume, etc.).
Either of these two functions can be selected by jumper JP18.
Figure 4-16. ADC Input
4.3.18.3 Analog Output
The BNC connector CN2 is connected to the DAC port PB14 and provides an external analog output. An
on-board 50-Ohm resistor termination can be enabled by closing jumper JP21. A filter can be implemented on this output channel by replacing R106 and C90 with appropriate resistor and capacitor
values, depending on the application requirements.
Figure 4-17. DAC Output
CN2
CN2
BN
BN
C
C
DAC01
CN1
CN1
BNC
BNC
Potentiometer
5
1
2
3
4
VR1
VR1
10K VR
10K VR
DGND
DGND
VCC33
13
DGND
JP21JP21
9
9
R10
R10
49.9R 1%
49.9R 1%
JP16
JP16
Header2
Header2
R96
R96
49.9R
49.9R
2
R940RR94
0R
C89
C89
10nF
10nF
106
106
R
R
0R
0R
C90 2.2uFC90 2.2uF
D
AU
C78
C78
10nF
10nF
SO
R DROP 2 pins open.Normal
LDE
1
1
IO_OUT
L
DAC
JP18JP18
SD1SD
SD2SD2
3
1
ADC
2
1
2
AD5
2
PB1
PB1
4
4.3.19QTouch Elements
QTouch keys consist in a series of sensors formed by the association of a copper area and the capacitive effect of human fingers approaching it.
4.3.19.1 Keys
The SAM4S-EK implements five individual capacitive touch keys (UP, DOWN, RIGHT, LEFT and
VALID) using five pairs of PIO.
4-12SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.3.19.2 Slider
Figure 4-18. QST Keys
PC25
PC24
PC31
PC30
PC29
PC28
PC23
PC22
PC27
PC26
R511KR511K
C47
C47
22nF
22nF
R531KR531K
C49
C49
22nF
22nF
R551KR551K
C51
C51
22nF
22nF
R571KR571K
C52
C52
22nF
22nF
R601KR601K
C53
C53
22nF
22nF
K1
K1
QTouch Key
QTouch Key
QTOUCH
A group of channels forms a Slider. A Slider is composed of three channels for a QTouch acquisition
method using three pairs of PIO. Such a sensor is used to detect a linear finger displacement on a sensitive area. A typical implementation is volume control.
Figure 4-19. QT_Slider
4.3.20User Buttons
There are two mechanical user buttons on the SAM4S-EK, which are connected to PIO lines and defined
to be "left" and "right" buttons by default.
In addition, a mechanical button controls the system reset, signal NRST.
Figure 4-20. System Buttons
PA1
PA0
PA3
PA2
PA5
PA4
22nF use X7R
R501KR501K
C46
C46
22nF
22nF
R521KR521K
C48
C48
22nF
22nF
R541KR541K
C50
C50
22nF
22nF
BP1BP1
1
2
BP2BP2
1
2
BP3BP3
1
2
S1
S1
QTouch Slider
QTouch Slider
SR
SL
SM
SR
3
4
3
4
3
4
NRST
JP25JP25
PB3
JP26JP26
PC12
DGND
SAM4S-EK Development Board User Guide4-13
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.3.21LEDs
There are three LEDs on the SAM4S-EK board:
A blue LED (D2) and a green LED (D3), which are user defined and controlled by the GPIO.
A red LED (D4), which is a power LED indicating that the 3.3V power rail is active. It is also controlled
by the GPIO and can be treated as a user LED as well. The only difference with the two others is that
it is controlled through a MOS transistor. By default, the PIO line is disabled; a pull-up resistor controls
the MOS to light the LED when the power is ON).
Figure 4-21. LEDs
PA1
PA2
+
R111
R111
220R
9
0
220R
R113
R113
220
220
R
R
2Bl
2Bl
D
D3Green-ledD3Green-led
ue-ledD
ue-led
3V3
4.3.22SD/MMC Card
The SAM4S EK has a high-speed 4-bit multimedia MMC interface, which is connected to a 4-bit
SD/MMC micro card slot featuring a card detection switch.
Figure 4-22. SD Card
PA26
PA27
PA28
PA29
PA30
PA31
PA6
IRLML250
IRLML250
DGND
R
R
17
17
10K
10K
R200RR20
PC20
Q
Q
R
R
115100K
7
7
R
R
RA1
RA1
68KX4
68KX4
+3V3
+
+
C25
C25
10uF
10uF
115100K
4Red-le
4Red-le
D
C26
C26
100nF
100nF
dD
d
J
J
3
3
TF01A
TF01A
1
DAT2
2
DAT3
3
CMD
4
VCC
5
C
6
VSS
7
DAT0
8
DAT1
10
GND
9
CD
11
Sh1
LK
12
Sh2
13
Sh3
DGND
1
1
1
2
2
2
R18
R18
10K
10K
R11
R11
2
2
0
0
2
2
3
123
45
678
0R
DGND
4.3.23ZigBEE
SAM4S has a 10-pin male connector for the RZ600 ZigBEE module.
Note:0 Ohm resistors have been implemented in series with the PIO lines that are used else-
where in the design, thereby enabling their individual disconnection, should a conflict occur
in your application.
4-14SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Figure 4-23. ZigBEE Interface
4.3.24PIO Expansion
The SAM4S product features three PIO controllers, PIOA, PIOB and PIOC, which are multiplexed with
the I/O lines of the embedded peripherals. Each PIO Controller controls up to 32 lines (16 for PIOB).
Expansion ports J12, J13 and J14 provide PIO lines access for customer defined usage.
JP10RS485OPENMaintain differential impedance for RS485 interface
JP11RS485CLOSEMaintain impedance matching for RS485 interface
JP12RS485OPENMaintain differential impedance for RS485 interface
JP13CSCLOSENCS1 chip select LCD
JP14 - JP15MIC GAIN0
JP16ADC inputOPENClose for impedance matching on ADC BNC port
JP17 – JP19MIC Gain stage Close to mux RIN/LIN into MONO-IN path within audio PA
Not populated
(OPEN)
CLOSE (both) 20db
OPEN (both) 26db
Analog reference voltage selection between 3.3V (close 1-2) and
2.5V (close 2-3)
Close for manufacturing test or fast programming mode
Close both to lower gain stage on microphone input.
JP18 SELECT ADC INP
JP20MONO/STEREOCLOSEClose to fix in mono speaker, no matter the stereo plug state
JP21DAC outputOPENClose for impedance matching on DAC BNC port
JP22
JP23
JP24
JP25BP2CLOSEOpen to disconnect and free PB3 for custom usage
JP26BP3CLOSEOpen to disconnect and free PC12 for custom usage
JP27ZIGBEECLOSE
PIO expansion J12
voltage supply
PIO expansion J13
voltage supply
PIO expansion J14
voltage supply
1-2
2-3
2-3Set to 3.3V (position 1-2 sets to 5V)
2-3Set to 3.3V (position 1-2 sets to 5V)
2-3Set to 3.3V (position 1-2 sets to 5V)
ADC input potentiometer
ADC input BNC
Power supply connection/disconnection for the ZigBEE module
May also be used as a current measurement point
SAM4S-EK Development Board User Guide4-19
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
Table 4-5. Audio Input Configuration
JP17JP19MONO-STEREO INPUT
OFFOFFPIN test point (TP12)
OFFONLeft-in only
4.4.3Test Points
Some test points have been placed on the SAM4S-EK board for the verification of important signals.
Table 4-6. Test Points
DesignationPartDescription
TP1Ring HookGND
TP2Ring HookGND
TP3Ring HookGND
TP4Ring HookGND
ONOFFRight-in only
ONONSum of Left-in and Right-in
TP5PadUART TXD
TP6PadUART RXD
TP7Pad LCD Backlight driver anode
TP8PadAux ADC input for Touch Screen controller
TP9PadAux ADC input for Touch Screen controller
TP10Ring Hook+5V
TP11Ring Hook+3V3
TP12PadOptional Audio PA input
4.4.4Solder Drops
There are two solder drops designed on the SAM4S-EK for isolation.
Table 4-7. Solder Drops
DesignationDefault SettingFeature
SD1OPENIsolation of DAC output from shared channel (PB14)
SD2CLOSEConnects PB14 to the AUDIO_OUTL channel
4.4.5Assigned PIO Lines, Disconnection Possibility
As pointed out in some previous interface description, 0 Ohm resistors have been inserted on the path of
the receiver PIO lines of the SAM4S-EK. These are the PIO lines connected to an external driver on the
board. The 0 Ohm resistors allow disconnecting each of these for custom usage (through PIO expansion
connectors for example). This feature gives the user an added level of versatility for prototyping a system
of his own. See the table below.
4-20SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Table 4-8. Disconnecting Possibility
DesignationDefault AssignmentPIO
R190RPC18, RDY/BSY on NAND Flash
R200RPA29
R22DNPOptional write protection on NAND Flash
R250RPA21
R260RPA25
R270RPA24
R280RPA22
R310RPA23
R330RPA22
R340RPA21
R350RPA24
R360RPA25
R440RNRST
Evaluation Kit Hardware
R470RPA9
R480RR2OUT/MN5
R590RLCD backlight LED anode
R660RPA11
R670RPA5
R680RPC13
R690RPA4
R700RVref TSC
R1180RPA3 ZB_RSTN
R1190RPA5 IRQ1_ZBEE
R1200RPA4 IRQ0_ZBEE
R1210RPA6 SLP_TR
Table 4-9. Default Not Populated Parts
ReferenceFunction
J1, R1External clock resource input
Y1, R3, R7Backup 12 MHz crystal
R6, R8Isolation on 12 MHZ clock source and GPIO expansion
R9, R10Isolation on 32 KHz clock source and GPIO expansion
R22Optional write protection NAND Flash
R23Optional pull-up for open drain output or equivalent device
R24, R30Differential impedance matching for RS485 cable
SAM4S-EK Development Board User Guide4-21
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
Table 4-9. Default Not Populated Parts
ReferenceFunction
D1Optional ESD protection for LCD touch panel
R61, R63, RA2, RA3Optional data bus termination for LCD controller
JP4Test mode selection for the SAM chip
J2Optional QFP socket for the SAM4 chip
K1Virtual component for QTouch keys set - implemented as copper areas
S1Virtual component for QTouch slider set - implemented as copper areas
TPxxSurface-mounted test points (copper area)
4.5Connectors
4.5.1Power Supply Connector J9
The SAM4S-EK evaluation board can be powered from a 5VDC power supply connected to the external
power supply jack J9. The positive pole is the center pin.
Figure 4-25. Power Supply Connector J9
Table 4-10. Power Supply Connector J9 Signal Descriptions
PinMnemonicSignal Description
1Center+5vcc
2GndGround reference
4.5.2USART Connector J5 With RTS/CTS Handshake Support
Figure 4-26. Male RS232/USART Connector J5
4-22SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Table 4-11. Serial COM1 Connector J5 Signal Descriptions
PinMnemonicSignal Description
1, 4, 6, 9NCNO CONNECTION
2TXD TRANSMITTED DATARS232 serial data output signal
3RXD RECEIVED DATARS232 serial data input signal
5GNDGROUND
7RTS READY TO SENDActive-positive RS232 input signal
8CTS CLEAR TO SENDActive-positive RS232 output signal
4.5.3UART Connector J7
Male RS232/UART connector J7
Evaluation Kit Hardware
Table 4-12. Male RS232/UART Connector J7 Signal Descriptions
PinMnemonicSignal Description
1, 4, 6, 7, 8, 9NCNO CONNECTION
2TXD TRANSMITTED DATARS232 serial data output signal
3RXD RECEIVED DATARS232 serial data input signal
5GNDGROUND
4.5.4USB Device Connector J15
Figure 4-27. Micro-B USB Connector J15
Table 4-13. Micro-B USB Connector J15 Signal Descriptions
PinMnemonicSignal Description
1Vbus5v power
2DMData -
3DPData +
4GndGround
5ShieldShield
SAM4S-EK Development Board User Guide4-23
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.5.5TFT LCD Connector J8
One 39-pin connector is available on the board to connect the LCD module, backlight and touch screen.
Figure 4-28. LCD Connector J8
Table 4-14. LCD Connector J8 Signal Descriptions
PinMnemonicPinMnemonic
13V32LCD_DB17 (PC7)
3LCD_DB16 (PC6)4LCD_DB15 (PC5)
5LCD_DB14 (PC4)6LCD_DB13 (PC3)
7LCD_DB12 (PC2)8LCD_DB11 (PC1)
9LCD_DB10 (PC0)10LCD_DB09 (NC)
11LCD_DB08 (NC)12LCD_DB07
13LCD_DB06 (NC)14LCD_DB05 (NC)
15LCD_DB04 (NC)16LCD_DB03 (NC)
17LCD_DB02 (NC)18LCD_DB01 (NC)
19LCD_DB00 (NC)203V3
21RD (PC11)22WR (PC8)
23RS (PC19)24CS (PC15)
25RESET26IM0
27IM128GND
29LED-A30LED-K1
31LED-K232LED-K3
33LED-K434Y UP
35Y DOWN36X RIGHT
37X LEFT38NC
39GND
4-24SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
4.5.6JTAG Debugging Connector J6
This JTAG connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm
male) that mates with IDC sockets mounted on a ribbon cable. Its signal assignment is compatible with
the SAM-ICE or any similar third-party interface.
Figure 4-29. JTAG/ICE Connector J6
Table 4-15. JTAG/ICE Connector J13 Signal Descriptions
PinMnemonicDescription
This is the target reference voltage. It is used to check if the target has power, to
1VTref. 3.3V power
create the logic-level reference for the input comparators and to control the output
logic levels to the target. It is normally fed from Vdd on the target board and must
not have a series resistor.
Evaluation Kit Hardware
2Vsupply. 3.3V power
nTRST TARGET RESET — Active-low
3
4GNDCommon ground
5
6GNDCommon ground
7TMS TEST MODE SELECT –
8GND Common ground
9
10GNDCommon ground
11
output signal that resets the target
TDI TEST DATA INPUT — Serial data
output line, sampled on the rising edge
of the TCK signal
TCK TEST CLOCK — Output timing
signal, for synchronizing test logic and
control register access
RTCK
Input Return test clock signal from the
target
This pin is not connected in SAM-ICE. It is reserved for compatibility with other
equipment. Connect to Vdd or leave open in target system.
JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port.
Typically connected to nTRST on the target CPU. This pin is normally pulled
HIGH on the target to avoid unintentional resets when there is no connection.
JTAG data input of target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TDI on target CPU.
JTAG mode set input of target CPU. This pin should be pulled up on the target.
Typically connected to TMS on target CPU. Output signal that sequences the
target’s JTAG state machine, sampled on the rising edge of the TCK signal.
JTAG clock signal to target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TCK on target CPU.
Some targets must synchronize the JTAG inputs to internal clocks. To assist in
meeting this requirement, a returned and retimed TCK can be used to
dynamically control the TCK rate. SAM-ICE supports adaptive clocking which
waits for TCK changes to be echoed correctly before making further changes.
Connect to RTCK if available, otherwise to GND.
12GNDCommon ground
13
14GNDCommon ground
SAM4S-EK Development Board User Guide4-25
TDO JTAG TEST DATA OUTPUT —
Serial data input from the target
JTAG data output from target CPU. Typically connected to TDO on target CPU.
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
Table 4-15. JTAG/ICE Connector J13 Signal Descriptions (Continued)
PinMnemonicDescription
15nSRST RESET — Active-low reset signal. Target CPU reset signal
16GNDCommon ground
17RFUThis pin is not connected in SAM-ICE.
18GNDCommon ground
19RFUThis pin is not connected in SAM-ICE.
20GNDCommon ground
4.5.7SD/MMC - MCI Connector J3
Figure 4-30. SD/MMC Connector J3
Table 4-16. SD/MMC Connector J3 Signal Descriptions
PinMnemonicPinMnemonic
1RSV/DAT32CDA
3GND4VCC
5CLK6GND
7DAT08DAT1
9DAT210Card Detect
11GND12
4-26SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
4.5.8Analog Connector CN1 & CN2
Figure 4-31. Analog Input Connector CN1 and Analog Output CN2, Bottom View
Table 4-17. Analog Input, Output Connector CN1, CN2 Signal Descriptions
PinMnemonic
1, 2, 3, 4 GND
5Analog input PB1 for CN1 and analog output PB13 for CN2 respectively
4.5.9RS485 Connector J14
Evaluation Kit Hardware
Figure 4-32. RS485 Connector J14
Table 4-18. RS485 J14 Signal Descriptions
PinMnemonic
1A - non-inverted RS485 signal A
2Frame ground
3B - non-inverted RS485 signal B
SAM4S-EK Development Board User Guide4-27
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.5.10Headphone Connector J11
Figure 4-33. Headphone J11
Table 4-19. Headphone J11 Signal Descriptions
PinMnemonic
1AGND
2Out left
3
4
5Out Right
4.5.11ZigBEE Connector J16
Figure 4-34. ZigBee Connector J16
Table 4-20. Connector J16 Signal Descriptions
Signal
Function
Reset/RST12Misc.
Interrupt
Request
NamePortPinPinPort
IRQ34SLP_TRSLP_TR
Signal
NameFunction
Option on Misc. Port Set by
Zero Ohm Resistor or Solder Shunts
EEPROM for MAC address, CAP array
settings and serial number
TST: test mode activation
CLKM: RF chip clock output
SPI chip
select
SPI MISOMISO78SCLKSPI CLK
Power
Supply
4-28SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
/SEL56MOSISPI MOSI
GNDGND910VCCVCCVCC
Voltage range: 1.8v to 5.5v, typically
regulated to 3.3v
4.5.12PIO Expansion Port C Connector J12
Figure 4-35. PIO Expansion Connector J12
Table 4-21. Connector J12 Signal Descriptions
PinMnemonicPinMnemonic
1+5V or +3v32+5V or +3v3
3GND4GND
5PC06PC16
7PC18PC17
9PC210PC18
Evaluation Kit Hardware
11PC312PC19
13PC414PC20
15PC516PC21
17PC618NC
19PC720NC
21PC822NC
23PC924NC
25PC1026NC
27PC1128NC
29PC1230NC
31PC1332NC
33PC1434NC
35PC1536NC
37GND38GND
393V3403V3
SAM4S-EK Development Board User Guide4-29
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.5.13PIO Expansion Port A Connector J13
Figure 4-36. PIO Expansion Connector J13
Table 4-22. Connector J13 Signal Descriptions
PinMnemonicPinMnemonic
1+5V or +3v32+5V or +3v3
3GND4GND
5NC6PA16
7NC8PA17
9NC10PA18
11NC12PA19
13NC14PA20
15NC16PA21
17PA618PA22
19PA720PA23
21PA822PA24
23PA924PA25
25PA1026PA26
27PA1128PA27
29PA1230PA28
31PA1332PA29
33PA1434PA30
35PA1536PA31
37GND38GND
393V3403V3
4-30SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
5.1Schematics
This section contains the following schematics:
Block diagram
General information
Microcontroller
NAND Flash, serial interface
TFT LCD & Touch
Audio & Power Supply
USB, LEDs, push-buttons & ZigBEE
Section 5
Schematics
SAM4S-EK Development Board User Guide5-1
11139A–ATARM–29-Nov-11
5
DD
4
3
2
1
5 V Input
POWER SUPPLY
(3.3V)
AUDIO In (ADC)
MIC
AUDIO Out (DAC)
PHONE
JACK
CC
POT
ADC/ DAC
Sheet 6
POWER
PIO A, B, C
ATMEL
Cortex-M4 ARM Processor
SAM4S (LQFP100)
PIO A, B, C
NAND FLASH
HSMCI
UART0
USART1
USART1
Micro SD
RS232
ICE
QTOUCH
Sheet 4
HE 10 RS485
LCD INTERFACE
2.8"
240x320
TFT
TOUCH SCREEN
Sheet 5
BB
Board Configuration
Sheet
Sheet 2
Sheet 3
FS
DEVICE
ZIGBEE
INTERFACE
LEDs, Buttons
PIO A, B, C
Extension
Sheet 7
USB
HE 10
HE 14
AA
INIT EDIT
INIT EDIT
INIT EDIT
A
A
A
REV
REV
REV
SCALE
SCALE
SAM4S-EK
SAM4S-EK
SAM4S-EK
Block Diagram
Block Diagram
Block Diagram
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This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SCALE
1/1
1/1
1/1
08-Mar-11
08-Mar-11
08-Mar-11
DES.
DATE
DES.
DATE
DES.
DATE
1
XX-XXX-XXJHXXX
XX-XXX-XXJHXXX
XX-XXX-XXJHXXX
DATEMODIF.
VER.
DATEMODIF.
VER.
DATEMODIF.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
1
1
1
A
A
A
7
7
7
5
4
3
2
1
REVISION HISTORY
REVDATA
DD
A
2011.03ORIGINAL RELEASED
NOTE
SCHEMATICS CONVENTIONS
(1) Resistance Unit: "K" is "Kohm", "R" is "Ohm?
(2) "nm" means the component is not populated
by default
TP7LCD backlight driver anode
TP8, TP9Aux ADC input for TSC
6
TP12Optional audio PA input
JUMPER and SOLDERDROP
PAGEREFERENCEFUNCTION
3JP1Close to select JTAG boundary scan
JP2Analog reference voltage selection between 3.3V and 3.0V
JP3Close to reinitialize the Flash contents and some of its NVM bits
JP4Close for manufacturing test or fast programming mode
JP5, JP6, JP7, JP8Access for current measurement on each power rail
JP14, JP15Sync close to degrade gain stage on microphone input
6
JP17, JP19Close to mux RIN/LIN into MONO-IN path within audio PA
JP16, JP21Close for impedance matching on AD/DA BNC port
JP18ADC input selection between BNC port and potentiometer
JP20Close to fix in mono speaker mode, no matter stereo plug state
JP291-2AUDIO Amplifier power select between +5V and VCC33
JP30DAC output between AUDIO left channel and BNC connector
7JP22, JP23, JP24DC voltage selection between 3.3V and 5V on PIO expansion ports
JP25Button BP2 disable
JP26
JP27Power consumption measure for ZigBEE module
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SCALE
1/1
1/1
1/1
08-Mar-11
08-Mar-11
08-Mar-11
DES.
DATE
DES.
DATE
DES.
DATE
1
XX-XXX-XXJHXXX
XX-XXX-XXJHXXX
XX-XXX-XXJHXXX
DATEMODIF.
VER.
DATEMODIF.
VER.
DATEMODIF.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
7
7
7
A
A
A
7
7
7
6.1Board Recovery
Closing JP3 and powering the board will assert ERASE and clear GPNVM bit 1, and thereby selects the
boot from the ROM by default. The MCU will boot from the internal ROM to enable a SAM-BA connection
through the UART. Connect the SAM4S-EK UART port (J3) to a PC COM port through an RS232 crossover cable.
You can then run the SAM-BA application from that PC to program the internal Flash of the MCU as well
as the GPNVM bit 1.
Section 6
Troubleshooting
SAM4S-EK Development Board User Guide6-1
11139A–ATARM–29-Nov-11
7.1Revision History
Table 7-1.
DocumentComments
11139AInitial version.
Section 7
Revision History
Change Request
Ref.
SAM4S-EK Development Board User Guide7-1
11139A–ATARM–29-Nov-11
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