SAM4S-EK Development Board
....................................................................................................................
User Guide
11139A–ATARM–29-Nov-11
1-2 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Section 1
Introduction.................................................................................................................1-1
1.1 SAM4S Evaluation Kit ........................................................................................................ 1-1
1.2 User Guide ......................................................................................................................... 1-1
1.3 References and Applicable Documents ............................................................................. 1-1
Section 2
Kit Contents ................................................................................................................2-1
2.1 Deliverables ....................................................................................................................... 2-1
2.2 Electrostatic Warning ......................................................................................................... 2-2
Section 3
Power Up....................................................................................................................3-1
3.1 Power up the Board ........................................................................................................... 3-1
3.2 Sample Code and Technical Support ................................................................................ 3-1
Section 4
Evaluation Kit Hardware .............................................................................................4-1
4.1 Board Overview.................................................................................................................. 4-1
4.2 Features List ...................................................................................................................... 4-2
4.3 Function Blocks.................................................................................................................. 4-2
4.3.1 Processor............................................................................................................. 4-2
4.3.2 Memory ................................................................................................................ 4-2
4.3.3 Clock Circuitry ...................................................................................................... 4-3
4.3.4 Reset Circuitry ..................................................................................................... 4-4
4.3.5 Power Supply and Management .......................................................................... 4-4
4.3.6 UART ................................................................................................................... 4-5
4.3.7 USART................................................................................................................. 4-5
4.3.8 RS232 .................................................................................................................. 4-6
4.3.9 RS485 .................................................................................................................. 4-6
4.3.10 Display Interface .................................................................................................. 4-6
4.3.11 LCD Module ........................................................................................................ 4-6
4.3.12 Backlight Control.................................................................................................. 4-7
4.3.13 Touch Screen Interface ....................................................................................... 4-8
4.3.14 JTAG/ICE............................................................................................................. 4-8
4.3.15 Audio Interface..................................................................................................... 4-9
4.3.16 Microphone Input ................................................................................................. 4-9
4.3.17 USB Device ....................................................................................................... 4-11
4.3.18 Analog Interface ................................................................................................ 4-11
4.3.19 QTouch Elements .............................................................................................. 4-12
4.3.20 User Buttons ...................................................................................................... 4-13
SAM4S-EK Development Board User Guide 1-1
11139A–ATARM–29-Nov-11
4.3.21 LEDs .................................................................................................................. 4-14
4.3.22 SD/MMC Card.................................................................................................... 4-14
4.3.23 ZigBEE............................................................................................................... 4-14
4.3.24 PIO Expansion................................................................................................... 4-15
4.4 Configuration.................................................................................................................... 4-16
4.4.1 PIO Usage ......................................................................................................... 4-16
4.4.2 Jumpers ............................................................................................................. 4-19
4.4.3 Test Points ......................................................................................................... 4-20
4.4.4 Solder Drops ...................................................................................................... 4-20
4.4.5 Assigned PIO Lines, Disconnection Possibility .................................................. 4-20
4.5 Connectors....................................................................................................................... 4-22
4.5.1 Power Supply Connector J9 .............................................................................. 4-22
4.5.2 USART Connector J5 With RTS/CTS Handshake Support ............................... 4-22
4.5.3 UART Connector J7 .......................................................................................... 4-23
4.5.4 USB Device Connector J15 ............................................................................... 4-23
4.5.5 TFT LCD Connector J8 ...................................................................................... 4-24
4.5.6 JTAG Debugging Connector J6 ......................................................................... 4-25
4.5.7 SD/MMC - MCI Connector J3 ............................................................................ 4-26
4.5.8 Analog Connector CN1 & CN2 .......................................................................... 4-27
4.5.9 RS485 Connector J14 ....................................................................................... 4-27
4.5.10 Headphone Connector J11................................................................................ 4-28
4.5.11 ZigBEE Connector J16 ...................................................................................... 4-28
4.5.12 PIO Expansion Port C Connector J12 ............................................................... 4-29
4.5.13 PIO Expansion Port A Connector J13 .............................................................. 4-30
4.5.14 PIO Expansion Port B Connector J14 ............................................................... 4-31
Section 5
Schematics .................................................................................................................5-1
5.1 Schematics......................................................................................................................... 5-1
Section 6
Troubleshooting..........................................................................................................6-1
6.1 Board Recovery ................................................................................................................. 6-1
Section 7
Revision History..........................................................................................................7-1
7.1 Revision History ................................................................................................................. 7-1
1-2 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
1.1 SAM4S Evaluation Kit
The SAM4S Evaluation Kit (SAM4S-EK) enables evaluation capabilities and code development of applications running on a SAM4S16 device.
1.2 User Guide
This guide focuses on the SAM4S-EK board as an evaluation platform. It is made up of 6 sections:
Section 1 includes references, applicable documents, acronyms and abbreviations.
Section 2 describes the kit contents, its main features and specifications.
Section 3 provides board specifications.
Section 4 describes the development environment.
Section 5 provides instructions to power up the SAM4S-EK and describes how to use it.
Section 6 describes the hardware resources, default jumper and switch settings, and connectors.
Section 7 provides schematics.
Section 8 describes the troubleshooting.
Introduction
Section 1
Introduction
1.3 References and Applicable Documents
Table 1-1. References and Applicable Documents
Title Comment
SAM4S Datasheet
http://www.atmel.com/dyn/resources/prod_documents/11100.pdf
SAM4S-EK Development Board User Guide 1-1
11139A–ATARM–29-Nov-11
2.1 Deliverables
The Atmel®SAM4S-EK toolkit contains the following items:
Board:
– a SAM4S-EK board
– a universal input AC/DC power supply with US, Europe and UK plug adapters
Cables:
– one USB cable
– one serial RS232 cable
A Welcome Letter
Figure 2-1. Unpacked SAM4S-EK
Section 2
Kit Contents
Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit.
SAM4S-EK Development Board User Guide 2-1
11139A–ATARM–29-Nov-11
Kit Contents
2.2 Electrostatic Warning
The SAM4S-EK board is shipped in a protective anti-static package. The board must not be subjected to
high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the components or any other metallic element of the board.
2-2 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
3.1 Power up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right
power plug adapter corresponding to that of your country, and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the
screen and enjoy the demo.
3.2 Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can
download sample code and get technical support from Atmel website
http://www.atmel.com/dyn/products/tools.asp?category_id=163&family_id=605&subfamily_id=2404
Figure 3-1. Atmel Website for AT91SAM Products
Section 3
Power Up
SAM4S-EK Development Board User Guide 3-1
11139A–ATARM–29-Nov-11
4.1 Board Overview
This section introduces the Atmel SAM4S Evaluation Kit design. It introduces system-level concepts,
such as power distribution, memory, and interface assignments.
The SAM4S-EK board is based on the integration of an ARM®Cortex®-M3 processor with on-board
NAND Flash and a set of popular peripherals. It is designed to provide a high performance processor
evaluation solution with high flexibility for various kinds of applications.
Figure 4-1. SAM4S-EK Block Diagram
Section 4
Evaluation Kit Hardware
SAM4S-EK Development Board User Guide 4-1
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.2 Features List
Here is the list of the main board components and interfaces:
SAM4S16 chip LQFP100 package with optional socket footprint
12 MHz crystal
32.768 KHz crystal
Optional SMB connector for external system clock input
NAND Flash
2.8 inch TFT color LCD display with touch panel and backlight
UART port with level shifter circuit
USART port with level shifter circuit multiplexed with RS485 port with level shifter circuit
Microphone input and mono/stereo headphone jack output
SD/MMC interface
Reset button: NRST
User buttons: Left and Right
QTouch
Full Speed USB device port
JTAG/ICE port
On-board power regulation
Two user LEDs
Power LED
BNC connector for ADC input
BNC connector for DAC output
User potentiometer connected to the ADC input
ZigBEE connector
2x32 bit PIO connection interfaces (PIOA, PIOC) and 1x16 bit PIO connection interface (PIOB)
®
buttons: Up, Down, Left, Right, Valid and Slider
4.3 Function Blocks
4.3.1 Processor
The SAM4S-EK is equipped with a SAM4S16 device in LQFP100 package.
4.3.2 Memory
The SAM4S16 chip embeds:
1024 Kbytes of embedded Flash
128 Kbytes of embedded SRAM
16 Kbytes of ROM with embedded BootLoader routines (UART, USB) and In-Application Programming
functions (IAP) routines.
4-2 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
The SAM4S features an External Bus Interface (EBI) that permits interfacing to a broad range of external
memories and virtually to any parallel peripheral. The SAM4S-EK board is equipped with a memory
device connected to the SAM4 EBI:
One NAND Flash MT29F2G08ABAEA.
Figure 4-2. NAND Flash
+3V3
+3V3
PC17
PC16
PC9
PC10
JP9
JP9
Header2
Header2
PC14
PC18
R19 0RR19 0R
R21 47KR21 47K
R15
R15
47K
47K
DGND
+3V3
R22
R22
0R nm
0R nm
R16
R16
47K
47K
NAND FLASH
MN3MN3
MT29F2G08ABAEA
16
CLE
17
ALE
8
RE
18
WE
9
CE
7
R/B
19
WP
1
N.C1
2
N.C2
3
N.C3
4
N.C4
5
N.C5
6
N.C6
10
N.C7
11
N.C8
14
N.C9
15
N.C10
20
N.C11
21
N.C12
22
N.C13
23
N.C14
24
N.C15
25
N.C16
26
N.C17
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
N.C28
N.C27
N.C26
N.C25
N.C24
N.C23
PRE
N.C22
N.C21
N.C20
N.C19
N.C18
VCC
VCC
VSS
VSS
29
30
31
32
41
42
43
44
48
47
46
45
40
39
38
35
34
33
28
27
37
12
36
13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
C27
C27
100nF
100nF
C28
C28
100nF
100nF
+3V3
DGND
C29
C29
1uF
1uF
NCS0 chip select signal is used for NAND Flash chip selection. Furthermore, a dedicated jumper (JP9)
can disconnect it from the on-board memories, thereby letting NCS0 free for other custom purpose.
4.3.3 Clock Circuitry
The clock generator of a SAM4S microcontroller is made up of:
A Low Power 32.768 Hz Slow Clock Oscillator with bypass mode.
A 3 to 20 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB).
A factory programmed fast internal RC Oscillator. 3 output frequencies can be selected: 4 (default
value), 8 or 12 MHz.
A 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller.
A 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and
to the peripherals. The input frequency of PLLA is from 7.5 and 20 MHz.
The SAM4S-EK board is equipped with one 12 MHz crystal, optional Piezoelectric Ceramic Resonator
12 Mhz (Murata ref. CSTCE12M0G15L99-R0), one 32.768 Hz crystal and an external clock input connector (optional, not populated by default).
Figure 4-3. External Clock Source
NOT POPULATE
2 3
J1J1
DGND
D
1
54
DGND
R2
49.9R 1%R249.9R 1%
R1 DNPR1 DNP
3
DGND
R
R
3DNP
3DNP
1
Y1Y1
D
NP
2
R
7DN
7DN
PR
P
DGND
C
C
1 20pF
1 20pF
C
C
2 20pF
2 20pF
212MHz
212MHz
Y
Y
R40RR40R
R50
R50
3
3
C
C
20pF
20pF
MN1
12BTRG
MN1
DGND
C4
20pFC420pF
49
8
4
R9 DNPR9 DNP
32
XIN
R10DNPR10DNP
XOUT32
XIN
PB9
R6 DN
R6 DN
R
R
PB8
XO
R8 DN
R8 DN
97
P
P
PB9_XIN
PB8_XOUT
SAM4S
PA7_RTS0_PWMH3
PA8_CTS0_AD
UT
96
P
P
R1
R1
1
1
0R
0R
R12
R12
0
0
XIN32
XOUT32
R
R
1
3
Y3
Y3
32.768KHz
32.768KHz
2
PA7
PA8
SAM4S-EK Development Board User Guide 4-3
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
The SAM4S chip internally generates the following clocks:
SLCK, the Slow Clock, which is the only permanent clock of the system
MAINCK, the output of the Main Clock Oscillator selection: either a Crystal Oscillator or a 4/8/12 MHz
Fast RC Oscillator
PLLACK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLA)
PLLBCK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLB)
4.3.4 Reset Circuitry
On-board NRST button BP1 provides an external reset control of the SAM4S.
The NRST pin is bidirectional. It is handled by the on-chip reset controller. It can be driven low to provide
a reset signal out to the external components. Conversely, it can be asserted low from the outside to
reset the microcontroller Core and the peripherals. The NRST pin integrates a permanent pull-up resistor
of about 100 kOhm to VDDIO.
On the SAM4S-EK board, the NRST signal is connected to the LCD module and JTAG port.
Note: At power-on, the NRST signal is asserted with a default duration of 2 clock cycles. That duration may not be
sufficient to correctly reset any other system or board devices connected to that signal. First, in your custom
application, you need to check for these devices' datasheets about reset duration requirements. Then, you
need to set an appropriate configuration in the NRST Manager. This is done through the ERSTL field in the
RSTC_MR register. The NRST duration is thereby configurable between 60 µs and 2 s, whether it is subsequently activated by a software reset or a user reset. Refer to the SAM4S datasheet for in depth
information.
4.3.5 Power Supply and Management
The SAM4S-EK board is supplied with an external 5V DC block through input J9. It is protected by a
PolyZen diode MN9 and an LC combinatory filter MN10. The PolyZen is used in the event of an incorrect
power supply connection.
The adjustable LDO regulator MN12 is used for the 3.3V rail main supply. It powers all the 3.3V components on the board.
Figure 4-4. Power Block
The SAM4S product series has different types of power supply pins:
J9
J9
Power Jack 2.1mm
Power Jack 2.1mm
1
2
3
+5V
MN9
MN9
ZEN056V130A24LS
ZEN056V130A24LS
1
3
2
MN12
MN12
MIC29152WU
MIC29152WU
Micrel's 1.5A LDO, TO263-5
Micrel's 1.5A LDO, TO263-5
VIN2VOUT
1
SD
ADJ
GND1
GND2
3
6
DGND
MN10
MN10
BNX002-01
BNX002-01
1
SV
2
SG
C65
C65
22uF
22uF
R89
R89
169K 1%
169K 1%
R92
R92
102K 1%
102K 1%
CG1
CG2
CG3
+
+
C64
C64
100nF
100nF
4
5
3
CV
4
5
6
+
+
C75
C75
100uF-TAN-6.3V
100uF-TAN-6.3V
+3V3
C76
C76
100nF
100nF
+5V
DGND
+
+
+
+
C66
C66
C98
C98
22uF
22uF
220uF-ELE-16V
220uF-ELE-16V
VDDIN pin:
Power for the internal voltage regulator, ADC, DAC, and analog comparator power supplies.
The voltage ranges from 1.8V to 3.6V.
4-4 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
4.3.6 UART
Evaluation Kit Hardware
VDDIO pins:
Power for the Peripherals I/O lines.
The voltage ranges from 1.62V to 3.6V.
VDDOUT pin:
Output of the internal voltage regulator.
VDDCORE pins:
Power for the core, including the processor, embedded memories and peripherals.
The voltage ranges from 1.62V to 1.95V.
VDDPLL pin:
Power for the PLL A, PLL B and 12 MHz oscillator.
The voltage ranges from 1.62V to 1.95V.
Note: VDDPLL should be decoupled and filtered from VDDCORE.
The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes. It offers an ideal channel for in-situ programming solutions. This UART
is associated with two PDC channels to reduce the processor time on packet handling.
4.3.7 USART
This two-pin UART (TXD and RXD only) is buffered through an RS232 Transceiver MN6 and brought to
the DB9 male connector J7.
Figure 4-5. UART
MN6
MN6
MAX3232CSE
MAX3232CSE
16
9
9
VCC
2
V+
6
V-
5
1
GND
1
1
IN
T1
2
1
UT
R1O
0
1
IN
T2
9
UT
R2O
C1+
C1-
C2+
C2-
T1OUT
R1IN
T2OUT
R2I
1
C38
C38
100nF
100nF
3
4
C42
C42
100nF
100nF
5
1
4
1
3
7
8
N
DGND
1
6
2
7
3
8
4
9
5
FGND
J7J7
10
11
PA10
PA9
+
T
T
SMD
SMD
3V3
P5
P5
R
R
100K
100K
45
45
+3V3
R46
R46
100
100
R470
R470
R480
R480
+3V3
C3
C3
100nF
100nF
C40
C40
100nF
100nF
C41
C41
100nF
K
K
100nF
R
R
R
R
GND
D
TP6
TP6
SM
SM
D
D
The Universal Synchronous/Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous/asynchronous serial link. The data frame format is extensively configurable (data
length, parity, number of stop bits) to support a broad range of serial communication standards. The
USART is also associated with PDC channels for TX/RX data access.
Note: For design optimization purposes, both transmitters have been implemented on the same
PIO lines, that is PA21, 22, 23, 24 25.
To avoid any electrical conflict, the RS485 transceiver is isolated from the receiving line PA21.
Should you need to implement an RS485 channel in place of the RS232, follow the procedure below:
1. make sure your software will permanently set PA23 to a high level - this will permanently disable the
RS232 receiver.
2. solder a shunt resistor in place of R25 (a solder drop will do).
SAM4S-EK Development Board User Guide 4-5
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.3.8 RS232
SAM4S-EK connects the USART1 bus (including TXD, RXD, RTS, CTS handshake signal controls and
EN command) to the DB9 male connector J5 through the RS232 Transceiver MN5.
Figure 4-6. USART
TXD1
RXD1
RTS1
CTS1
PA23
PA22
PA21_232
PA24
PA25
+3V3
+3V3
+3V3
C31
C31
4.7uF
4.7uF
DGND
R32
R32
47K
47K
R31 0RR31 0R
R33 0RR33 0R
R34 0RR34 0R
R35 0RR35 0R
R36 0RR36 0R
R37 47KR37 47K
C32
C32
100nF
100nF
DGND
C33
C33
100nF
100nF
C36
C36
100nF
100nF
USART
MN5
MN5
ADM3312EARU
ADM3312EARU
3
VCC
1
V+
21
V-
23
GND
19
SD
5
EN
T1IN7T1OUT
10
R1OUT
T2IN8T2OUT
11
R2OUT
9
T3IN
12
R3OUT
R1IN
R2IN
T3OUT
R3IN
C1+
C1C2+
C2C3+
C3-
6
20
2
4
24
22
18
15
17
14
16
13
C34
C34
100nF
100nF
C35
C35
100nF
100nF
C37
C37
100nF
100nF
R38 0RR38 0R
PA21_485
PA21
PA21_232
DGND
3
2
JP31JP31
1
J5J5
1
6
2
7
3
8
4
9
5
10
11
FGND
4.3.9 RS485
As noticed above, the USART1 is shared with the RS485 port, connected to the transceiver MN4, connected to the 3-point connector J4. The design includes selectable jumpers for RS485 bus termination
resistors selection (JP10, JP11, JP12).
Figure 4-7. RS485
4.3.10 Display Interface
The SAM4S-EK carries a TFT Transmissive LCD module with touch panel, FTM280C34D. Its integrated
driver IC is ILI9325. The LCD display area is 2.8 inches diagonally measured, with a native resolution of
240 x 320 dots.
RXD1
CTS1
RTS1
TXD1
PA21_485
PA25
PA24
PA22
R25 0R nmR25 0R nm
R27 0RR27 0R
R28 0RR28 0R
+3V3 +3V3
RS 485
R23
R23
10K
10K
MN4
MN4
ADM3485ARZ
JP28
JP28
Header2 nm
Header2 nm
ADM3485ARZ
1
RO
2
RE
3
DE
4
DI
VCC
GND
A
B
+3V3
8
5
6
7
DGND
C30
C30
100nF
100nFR26 0RR26 0R
R29
R29
120R
120R
JP11
JP11
Header2
Header2
DGND
R24
R24
0R nm
0R nm
JP10
JP10
Header2
Header2
JP12
JP12
Header2
Header2
R30
R30
0R nm
0R nm
FGND
J4J4
1
2
3
4.3.11 LCD Module
The LCD module gets reset from the NRST signal. As explained, this NRST is shared with the JTAG port
and the push-button BP1. The LCD chip select signal is connected to NCS1; the jumper JP13 can disconnect it so that this PIO line is available for other custom usage.
The SAM4S communicates with the LCD through PIOC where an 8-bit parallel “8080-like” protocol data
bus has to be implemented by software.
4-6 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Figure 4-8. LCD Block
PC[0..31]
PC13
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
+3V3
R56
R56
10K
10K
R58
R58
4.7K
4.7K
DGND
3
4
5
2
NOT POPULATED
DGND
NRST
The part is placed as
close as possible to J8
D1
D1
PACDN044Y5R nm
PACDN044Y5R nm
TVS, SOT23-5
TVS, SOT23-5
NRST
X_RIGHT
Y_UP
X_LEFT
Y_DOWN
1
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PC11
PC8
PC19
PC15
+
+
C43
C43
10uF
10uF
LED_A
+3V3
C44
C44
100nF
100nF
DGND
JP13 Header2JP13 Header2
R59 0RR59 0R
C45
C45
100nF
100nF
LCD_DB17
LCD_DB16
LCD_DB15
LCD_DB14
LCD_DB13
LCD_DB12
LCD_DB11
LCD_DB10
LCD_DB9
LCD_DB8
LCD_DB7
LCD_DB6
LCD_DB5
LCD_DB4
LCD_DB3
LCD_DB2
LCD_DB1
LCD_DB0
LED_K1
LED_K2
LED_K3
LED_K4
Y_UP
Y_DOWN
X_RIGHT
X_LEFT
R49
R49
47K
47K
DGND
J8
J8
FH26-39S-0.3SHW
FH26-39S-0.3SHW
1
VDD
2
DB17
3
DB16
4
DB15
5
DB14
6
DB13
7
DB12
8
DB11
9
DB10
10
DB9
11
DB8
12
DB7
13
DB6
14
DB5
15
DB4
16
DB3
17
DB2
18
DB1
19
DB0
20
VDD
21
RD
22
WR
23
RS
24
CS
25
RESET
26
IM0
27
IM1
28
GND
29
LED-A
30
LEDK1
31
LEDK2
32
LEDK3
33
LEDK4
34
Y+
35
Y-
36
X+
37
X-
38
NC
39
GND
LCD
Evaluation Kit Hardware
DGND
PIN 39
PIN 39
PINs
PINs
on
on
BOT
BOT
PIN 1
PIN 1
DGND DGND
Six slots on PCB for LCD shield
LCD_DB0
LCD_DB4
LCD_DB2
LCD_DB3
LCD_DB1
LCD_DB8
LCD_DB6
LCD_DB7
LCD_DB5
LCD_DB9
FTM280C34D
FTM280C34D
R61 4.7K nmR61 4.7K nm
1
2
3
4
1
2
3
4 5
R63 4.7K nmR63 4.7K nm
8
7
RA2
RA2
6
4.7Kx4 nm
4.7Kx4 nm
5
8
7
RA3
RA3
6
4.7Kx4 nm
4.7Kx4 nm
DGNDDGND
Z7
Z7
DGND
DGND
4.3.12 Backlight Control
The LCD backlight is made of four integrated white chip-LEDs arranged in parallel. These are driven by
an AAT3155 charge pump, MN8.The AAT3155 is controlled by the SAM4S through a single PIO line
PC13 interface; the 0 Ohm resistor R68 is mounted in series on this line, which permits to use it for other
custom purposes. In that case, the pull-up resistor R64 maintains the charge pump permanently enabled
by default.
On the anode drive line, a 0 Ohm resistor R59 is implemented in series for an optional current limitation.
Figure 4-9. Backlight Control
+3V3
PC13
R680RR68
0R
FB1
FB1
BN03K314S300R
BN03K314S300R
+3V3
R64
R64
47K
47K
DGND
MN8
MN8
AAT3155ITP-T1
AAT3155ITP-T1
10
C1+
C54
C54
1uF
1uF
9
C1-
11
EN/SET
5
IN
C57
C57
4.7uF
4.7uF
4
GND
LCD BACKLIGHT
C2+
OUTCP
7
C55
C55
1uF
6
C2-
8
3
D1
2
D2
1
D3
12
D4
1uF
LED_A
LED_K1
LED_K2
LED_K3
LED_K4
TP7TP7
DGND
C56
C56
1uF
1uF
SAM4S-EK Development Board User Guide 4-7
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.3.13 Touch Screen Interface
The LCD module integrates a 4-wire touch panel controlled by MN7 (ADS7843) which is a slave device
on the SAM4S SPI bus. The controller sends back the information about the X and Y positions, as well
as a measurement for the pressure applied to the touch panel. The touch panel can be used with either
a stylus or a finger.
The ADS7843 touch panel controller connects to the SPI0 interface via the NPCS0 control signal. Two
interrupt signals are connected and provide events information back to the microcontroller: PenIrq and
Busy.
Note: PenIrq (PA16) is shared with ZigBEE signal IRQ0.
Busy (PA17) is shared with ZigBEE signal IRQ1.
Therefore, if using a ZigBEE interface in concurrence with the TouchScreen controller, take
care not to have both drivers enabled at the same time on either PA16 or PA17.
For that purpose, 0 Ohm resistors have been implemented on these PIO lines in order to disconnect
either end driver from the other:
On the touch panel controller side, R67 and R69.
On ZigBEE side, R117 and R120.
for further information, refer to the “Schematics” section.
Touch ADC auxiliary inputs IN3/IN4 of the ADS7843 are connected to test point (TP8, TP9) for optional
function extension.
Figure 4-10. Touch Panel Control
4.3.14 JTAG/ICE
A standard 20-pin JTAG/ICE connector is implemented on the SAM4S-EK for the connection of a compatible ARM JTAG emulator interface, such as the SAM-ICE from Segger.
+3V3
R62
PA14
PA13
PA12
R62
100K
100K
R66 0RR66 0R
R67 0RR67 0R
R70 0RR70 0R
C58
C58
100nF
100nF
C59
C59
100nF
100nF
PA11
PA17
C6
C6
100nF
100nF
+3V3
R65
R65
100K
100K
R
R
69 0R
69 0R
L2
L2
10uH/100
10uH/100
R71
R71
1
1
R
R
0
0
C61
C61
4.7uF
4.7uF
R740RR74
0R
PA16
+3V3
mA
mA
DGND
MN7
MN7
ADS7843
ADS7843
E
E
X_RIGHT
Y_UP
X_LEFT
Y_DO WN
TP8
TP8
SMD
SMD
R72
R72
100K
100K
AGND_TP AGND_TP
2
XP
3
YP
4
XM
5
R73
R73
100
100
YM
7
3
IN
8
4
IN
K
K
T
T
P9
P9
SM
SM
D
D
DOUT
BUSY
PENIR
DCLK
DIN
VR
VC
VC
GND
1
6
1
4
1
2
1
5
CS
13
11
Q
9
EF
1
C1
10
C2
6
Notes: 1. The NRST signal is connected to BP1 system button and is also used to reset the LCD
module. The 0 ohm resistor R44 may be removed in order to isolate the JTAG port from
this system reset signal.
2. The TDO pin is in input mode with the pull-up resistor disabled when the Cortex M3 is
not in debug mode. To avoid current consumption on VDDIO and/or VDDCORE due to
floating input, the internal pull-up resistor corresponding to this PIO line must be
enabled.
4-8 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Figure 4-11. JTAG Interface
4.3.15 Audio Interface
The SAM4S-EK board supports both audio recording and playback.
The audio volume can be adjusted using the potentiometer RV1, and the microphone amplifier gain can
be adjusted via jumpers (fixed gain of 24 or 26 dB).
4.3.16 Microphone Input
The embedded microphone is connected to an audio pre-amplifier using the TS922 operational amplifier
(MN11). The gain is set by using JP14 and JP15 jumpers; both must be set or removed at the same
time.
Evaluation Kit Hardware
+3V3
R39
R39
R40
R40
1
1
R4
100
100
R4
K
K
100
100
K
K
R440
R440
K
K
100
100
PB4
PB6
PB7
PB5
N
RST
R42
R42
100
100
R43
R43
100
100
K
K
K
K
R
R
1
1
1
1
19
1
3
5
7
9
1
3
5
7
6
J6J
ref
VT
n
TRST
TDI
M
T
TCK
RTC
TDO
SRST
n
DBGRQ
DBGACK
2
Vsupply
4
G
1
ND
6
GND
2
8
GND
3
S
K
GND
GND
GND
GND
GND
GND
0
1
4
2
1
5
4
1
6
6
1
7
8
1
8
0
2
9
DGND
By modifying the jumper positions, you can select each of the following gain values:
20 dB (default setting, both JP14 and JP15 are off)
26 dB (both JP14 and JP15 are on).
Note:
3. The TB1 series 0 Ohm resistor is a reservation for future impedance adaptation facility.
Under specific amplifier settings conditions, this enables the easy insertion of a capacitor or any other bipolar device on the audio path. On the other hand, R83 is a default
0 Ohm resistor that enables the disconnection of PB0 from the audio input path for custom usage.
4. The audio pre-amplifier MN11 is powered by a dedicated low dropout regulator
MIC5219-3.3 (MN14).
SAM4S-EK Development Board User Guide 4-9
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
Figure 4-12. Microphone Input
AGND
AGND
C63
C63
22uF
22uF
C73
C73
22uF
22uF
AVDD
12
AGND
R77
R77
470R
470R
R781KR78
1K
MIC1
MIC1
SVB6050
SVB6050
R851KR85
1K
R88
R88
470R
470R
C67
C67
1uF
1uF
C68
C68
1uF
1uF
AUDIO IN
R75 47KR75 47K
R76 47KR76 47K
MN11
R87
R87
47K
47K
JP15
JP15
Header2
Header2
MN11
TS922
TS922
2
IN1-
3
IN1+
7
OUT2
6
IN2-
5
IN2+
R791KR79
1K
R821KR82
1K
AGND
C77
C77
4.7uF
4.7uF
C69
C69
1nF
1nF
AGND
AVDD
R801KR80
1K
R841KR84
1K
C72
C72
1nF
1nF
R90
R90
100K
100K
R93
R93
100K
100K
R86
R86
47K
47K
JP14 and JP15 should be set
or removed together
C62
C62
100pF
100pF
JP14 Header2JP14 Header2
1
OUT1
8
VCC
4
GND
R81
R81
100R
100R
AVDD
AGND
C74
C74
100nF
100nF
AGND
C71
C71
22nF
22nF
VCC33
FB2
FB2
BN03K314S300R
BN03K314S300R
R910RR91
0R
DGND
R830RR83
0R
PB0
4.3.16.1 Headphone Output
The SAM4S-EK evaluation kit supports mono/stereo audio playback driven by a TPA0223 audio amplifier connected to two DAC channels of the microcontroller.
The TPA0223 is a 2W mono Bridge-Tied-Load (BTL) amplifier designed to drive speakers with as low as
4 Ohm impedance. The amplifier can be reconfigured on the fly to drive two stereo Single-Ended (SE)
signals into head phones.
Figure 4-13. Headphone Output
+5V
VCC33
PB13
AUDIO_OUTL
1
JP29JP29
3
Test Pad SQ-40TH
Test Pad SQ-40TH
2
C84 0.47uFC84 0.47uF
TP12
C88 0.47uFC88 0.47uF
DGND
AGND
FB3
FB3
BN03K314S300R
BN03K314S300R
C79
C79
1uF
1uF
JP17 Header2JP17 Header2
C85 0.47uFC85 0.47uF
JP19 Header2JP19 Header2
AGND
AGND
+
+
C80
C80
10uF
10uF
R98 33KR98 33K
R99 47KR99 47K
R100 33KR100 33K
R104 47KR104 47K
R105 33KR105 33K
VDD_AMP
C82
C82
100nF
100nF
AUDIO OUT
MN13
MN13
TPA0223DGQ
TPA0223DGQ
3
VDD
5
RIN
1
MONO-IN
9
LIN
AGND
RO/MO+
LO/MO-
ST/MN
SHUTD0WN
BYPASS
PAD
11
GND
6
10
7
2
4
8
C81 220uF-TAN-6.3V
C81 220uF-TAN-6.3V
R95 1KR95 1K
R97 1KR97 1K
AGND
C83 220uF-TAN-6.3V
C83 220uF-TAN-6.3V
R101 100KR101 100K
R103 100KR103 100K
C86 0.47uFC86 0.47uF
J10J10
1
2
J11
J11
Phonejack Stereo 3.5
Phonejack Stereo 3.5
R102 100KR102 100KTP12
JP20
JP20
Header2
Header2
AGND
5
4
3
2
1
VDD_AMP
AGND
C87
C87
1uF
1uF
+
+
+
+
AGND
AGND
MN14
DGND
C91
C91
4.7uF
4.7uF
DGND
C93
C93
470pF
470pF
MN14
MIC5219-3.3YMM
MIC5219-3.3YMM
2
IN
1
EN
GND
GND
GND
4
BYP
GND
OUT
3
5
6
7
8
DGND
VCC33+5V
+
+
C92
C92
100uF-TAN-6.3V
100uF-TAN-6.3V
DGND
4-10 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Using a readily available 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no
plug is inserted. When closed, a 100-kOhm/1-kOhm divider pulls the ST/MN input low. When a jack plug
is inserted, the 1-kOhm resistor is disconnected and the ST/MN input is pulled high. The mono speaker
(J10 connector) is also physically disconnected from the RO/MO+ output so that no sound is heard from
the speaker while the headphones are inserted.
4.3.17 USB Device
The SAM4S UDP port is compliant with the Universal Serial Bus (USB) rev 2.0 Full Speed device specification. J15 is a micro B-type receptacle for USB device.
Both 27-Ohm resistors R114 and R116 build up a 90-Ohm differential impedance together with the
(embedded) 6-Ohm output impedance of the SAM4S full speed channel drivers.
R110 and R112 build up a divider bridge from VBUS +5V to implement plug-in detection (5V level gets
lowered to a PIO compatible 3.3V level) through PC21.
Figure 4-14. USB
PC21
FGN
110 47K
110 47K
R
R
112 68K
112 68K
R
R
Evaluation Kit Hardware
J15
J15
USB Micro B
USB Micro B
5V D- D+ ID G
5V D- D+ ID G
8
9
D
R
R
V2
V2
V5.5MLA060
V5.5MLA060
C94
C94
10pF
10pF
DGND
3
3
123
6
475
RV1
RV1
V5.5MLA0603
V5.5MLA0603
DGND FGND
4.3.18 Analog Interface
4.3.18.1 Analog Reference
The 3V voltage reference is based on an LM4040 (Precision Micropower Shunt Voltage Reference).
This ADVREF level can be set as 3V or 3.3V via the jumper JP2.
Figure 4-15. Analog Vref
PB1
PB11
0
R11427RR11427R
R116 27RR116 27R
SAM4SSAM
ADVREF
33
VC
C
JP2JP2
MN2
MN2
LM4040-2.5
LM4040-2.5
+5V
DGND
R13
R13
2.2K
2.2K
1
DGND
C5
100nFC5100nF
2
3
1
ADVREF
SAM4S-EK Development Board User Guide 4-11
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.3.18.2 Analog Input
The BNC connector CN1 is connected to the ADC port PB1 as an external analog input. An on-board 50Ohm resistor termination can be applied by closing jumper JP16. A low pass filter can be implemented
for the BNC connector CN1 by replacing R94 and C78 with custom resistor and capacitor values,
depending on your application requirements.
A 10-KOhm potentiometer (VR1) is also connected to this channel to implement an easy access to ADC
programming and debugging (or implement an analog user control like display brightness, volume, etc.).
Either of these two functions can be selected by jumper JP18.
Figure 4-16. ADC Input
4.3.18.3 Analog Output
The BNC connector CN2 is connected to the DAC port PB14 and provides an external analog output. An
on-board 50-Ohm resistor termination can be enabled by closing jumper JP21. A filter can be implemented on this output channel by replacing R106 and C90 with appropriate resistor and capacitor
values, depending on the application requirements.
Figure 4-17. DAC Output
CN2
CN2
BN
BN
C
C
DAC01
CN1
CN1
BNC
BNC
Potentiometer
5
1
2
3
4
VR1
VR1
10K VR
10K VR
DGND
DGND
VCC33
13
DGND
JP21JP21
9
9
R10
R10
49.9R 1%
49.9R 1%
JP16
JP16
Header2
Header2
R96
R96
49.9R
49.9R
2
R940RR94
0R
C89
C89
10nF
10nF
106
106
R
R
0R
0R
C90 2.2uFC90 2.2uF
D
AU
C78
C78
10nF
10nF
SO
R DROP 2 pins open.Normal
LDE
1
1
IO_OUT
L
DAC
JP18JP18
SD1SD
SD2SD2
3
1
ADC
2
1
2
AD5
2
PB1
PB1
4
4.3.19 QTouch Elements
QTouch keys consist in a series of sensors formed by the association of a copper area and the capacitive effect of human fingers approaching it.
4.3.19.1 Keys
The SAM4S-EK implements five individual capacitive touch keys (UP, DOWN, RIGHT, LEFT and
VALID) using five pairs of PIO.
4-12 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.3.19.2 Slider
Figure 4-18. QST Keys
PC25
PC24
PC31
PC30
PC29
PC28
PC23
PC22
PC27
PC26
R51 1KR51 1K
C47
C47
22nF
22nF
R53 1KR53 1K
C49
C49
22nF
22nF
R55 1KR55 1K
C51
C51
22nF
22nF
R57 1KR57 1K
C52
C52
22nF
22nF
R60 1KR60 1K
C53
C53
22nF
22nF
K1
K1
QTouch Key
QTouch Key
QTOUCH
A group of channels forms a Slider. A Slider is composed of three channels for a QTouch acquisition
method using three pairs of PIO. Such a sensor is used to detect a linear finger displacement on a sensitive area. A typical implementation is volume control.
Figure 4-19. QT_Slider
4.3.20 User Buttons
There are two mechanical user buttons on the SAM4S-EK, which are connected to PIO lines and defined
to be "left" and "right" buttons by default.
In addition, a mechanical button controls the system reset, signal NRST.
Figure 4-20. System Buttons
PA1
PA0
PA3
PA2
PA5
PA4
22nF use X7R
R50 1KR50 1K
C46
C46
22nF
22nF
R52 1KR52 1K
C48
C48
22nF
22nF
R54 1KR54 1K
C50
C50
22nF
22nF
BP1BP1
1
2
BP2BP2
1
2
BP3BP3
1
2
S1
S1
QTouch Slider
QTouch Slider
SR
SL
SM
SR
3
4
3
4
3
4
NRST
JP25JP25
PB3
JP26JP26
PC12
DGND
SAM4S-EK Development Board User Guide 4-13
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.3.21 LEDs
There are three LEDs on the SAM4S-EK board:
A blue LED (D2) and a green LED (D3), which are user defined and controlled by the GPIO.
A red LED (D4), which is a power LED indicating that the 3.3V power rail is active. It is also controlled
by the GPIO and can be treated as a user LED as well. The only difference with the two others is that
it is controlled through a MOS transistor. By default, the PIO line is disabled; a pull-up resistor controls
the MOS to light the LED when the power is ON).
Figure 4-21. LEDs
PA1
PA2
+
R111
R111
220R
9
0
220R
R113
R113
220
220
R
R
2Bl
2Bl
D
D3 Green-ledD3 Green-led
ue-ledD
ue-led
3V3
4.3.22 SD/MMC Card
The SAM4S EK has a high-speed 4-bit multimedia MMC interface, which is connected to a 4-bit
SD/MMC micro card slot featuring a card detection switch.
Figure 4-22. SD Card
PA26
PA27
PA28
PA29
PA30
PA31
PA6
IRLML250
IRLML250
DGND
R
R
17
17
10K
10K
R200RR20
PC20
Q
Q
R
R
115 100K
7
7
R
R
RA1
RA1
68KX4
68KX4
+3V3
+
+
C25
C25
10uF
10uF
115 100K
4Red-le
4Red-le
D
C26
C26
100nF
100nF
dD
d
J
J
3
3
TF01A
TF01A
1
DAT2
2
DAT3
3
CMD
4
VCC
5
C
6
VSS
7
DAT0
8
DAT1
10
GND
9
CD
11
Sh1
LK
12
Sh2
13
Sh3
DGND
1
1
1
2
2
2
R18
R18
10K
10K
R11
R11
2
2
0
0
2
2
3
123
45
678
0R
DGND
4.3.23 ZigBEE
SAM4S has a 10-pin male connector for the RZ600 ZigBEE module.
Note: 0 Ohm resistors have been implemented in series with the PIO lines that are used else-
where in the design, thereby enabling their individual disconnection, should a conflict occur
in your application.
4-14 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Figure 4-23. ZigBEE Interface
4.3.24 PIO Expansion
The SAM4S product features three PIO controllers, PIOA, PIOB and PIOC, which are multiplexed with
the I/O lines of the embedded peripherals. Each PIO Controller controls up to 32 lines (16 for PIOB).
Expansion ports J12, J13 and J14 provide PIO lines access for customer defined usage.
Figure 4-24. PIO Expansion
PB[0..14]
]
PA[0..31
PC[0..31]
_RST
ZB
N
EE
IRQ1_ZB
SPIO_NPCS2#
SO
MI
J16J16
1
PA18
R118 0RR118 0R
PA17
R119 0RR119 0R
PB2
PA12 PA14
3
5
7
9 10
2
4
6
8
R
R
120 0R
120 0R
R121 0RR121 0R
C95
C95
18pF
18pF
C96
C96
2.2n
2.2n
PA16
PA15
PA1
F
F
DGND
Evaluation Kit Hardware
IRQ0_ZBE
E
LP_TR
S
M
OSI
3
C97
C97
2.2uF
2.2uF
JP27JP2
S
PCK
7
+3
V3
0
1
2
3
4
DGND
V
+5
1
J
P23JP23
2
J13J13
1
3
5
7
9 1
1
1
3
1
15 1
7
1
9
1
1
2
3
2
5
2
7
2
9
2
1
3
3
3
5
3
7
3
39 4
+3V3
3
2
4
6
8
1
1
18
20
22
24
26
28
30
32
3
3
3
JP24JP24
+5V
1
PA16
PA17
0
PA18
2
PA19
4
PA20
6
PA21
2
PA2
PA23
PA24
PA25
PA26
PA27
PA28
PA29
4
PA30
6
PA31
8
0
DGND
PB0
PB1
B2
P
PB3
PB4
PB5
PB6
PB7
+
3V3
DGND
2
J14J
14
1 2
3 4
5 6
7 8
9 1
11 1
13 1
15 1
17 18
19
21
23
+3V3
3
2
2
2
0
2
4
6
0
2
4
DGND
+3V3
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
+5
DGND
JP22JP22
V
1
J12J12
1
3
5
7
9
1
1
3
1
5
1
7
1
19
21
23
25 26
7
2
9
2
31 32
33 34
35 36
37 38
39
+3V3
3
2
2
4
6
PC16
8
PC17
0
1
PC18
2
1
PC19
14
PC20
6
1
PC21
8
1
0
2
2
2
4
2
28
30
0
4
+3V3 +3V3
DGND
PA6
PA7
PA8
PA9
PA1
PA1
PA1
PA1
PA1
PA15
+
3V3
Note: All PIO lines are available on these expansion connectors, except those that are used for
the QTouch elements.
PB8
PB9
PB10
PB11
PB12
PB13
PB14
+3V3
SAM4S-EK Development Board User Guide 4-15
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.4 Configuration
This section describes the PIO usage, the jumpers, the test points and the solder drops of a SAM4S-EK
board.
4.4.1 PIO Usage
Table 4-1. PIO Port A Pin Assignments and Signal Descriptions
I/O
No
Line
1 PA0 PWMH0 TIOA0 A17 WKUP0 QTouch slider (left) SNS
2 PA1 PWMH1 TIOB0 A18 WKUP1 QTouch slider (left) SNSK
3 PA2 PWMH2 SCK0 DATRG WKUP2 QTouch slider (middle) SNS
4 PA3 TWD0 NPCS3 QTouch slider (middle) SNSK
5 PA4 TWCK0 TCLK0 WKUP3 QTouch slider (right) SNS
6 PA5 RXD0 NPCS3 WKUP4 QTouch slider (right) SNSK
7 PA6 TXD0 PCK0 MCI card detection
8 PA7 RTS0 PWMH3 XIN32 CLK32KHz
9 PA8 CTS0
10 PA9 URXD0 NPCS1 PWMFI0 WKUP6 UART receive data
11 PA10 UTXD0 NPCS2 UART transmit data
12 PA11 NPCS0 PWMH0 WKUP7 NPCS0# (TSC)
13 PA12 MISO PWMH1 MISO_TSC ZigBEE MISO
14 PA13 MOSI PWMH2 MOSI_TSC ZigBEE MOSI
15 PA14 SPCK PWMH3 WKUP8 SPCK_TSC ZigBEE CLK
PeripheralAPeripheralBPeripheral
C Extra Function
AD12BTR
G
System
Function Comment
WKUP5 XOUT32 CLK32KHz
16 PA15 TF TIOA1 PWML3 WKUP14 / PIO_DCEN1 ZigBEE SLPTR
17 PA16 TK TIOB1 PWML2 WKUP15 / PIO_DCEN2 IRQ_TSC ZigBEE IRQ0
18 PA17 TD PCK1 PWMH3 AD0 BUSY_TSC ZigBEE IRQ1
19 PA18 RD PCK2 A14 AD1 ZigBEE RSTN
20 PA19 RK PWML0 A15 AD2/ WKUP9 Blue LED (UserLED1)
21 PA20 RF PWML1 A16 AD3/ WKUP10 Green LED (UserLED2)
22 PA21 RXD1 PCK1 AD8 USART RXD
23 PA22 TXD1 NPCS3 NCS2 AD9 USART TXD
24 PA23 SCK1 PWMH0 A19 POI_DCCLK USART transceiver enable
25 PA24 RTS1 PWMH1 A20 POI_DC0 USART RTS
26 PA25 CTS1 PWMH2 A23 POI_DC1 USART CTS
27 PA26 DCD1 TIOA2 MCDA2 POI_DC2 MCI data bit 2
28 PA27 DTR1 TIOB2 MCDA3 POI_DC3 MCI data bit 3
29 PA28 DSR1 TCLK1 MCCDA POI_DC4 MCI command
4-16 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Table 4-1. PIO Port A Pin Assignments and Signal Descriptions (Continued)
Evaluation Kit Hardware
I/O
No
Line
30 PA29 RI1 TCLK2 MCCK POI_DC5 MCI clock
31 PA30 PWML2 NPCS2 MCDA0 WKUP11 / POI_DC6 MCI data bit 0
32 PA31 NPCS1 PCK2 MCDA1 POI_DC7 MCI data bit 1
PeripheralAPeripheralBPeripheral
C Extra Function
System
Function Comment
Table 4-2. PIO Port B Pin Assignments and Signal Descriptions
I/O
No
Line
1 PB0 PWMH0 AD4 Microphone input
2 PB1 PWMH1 AD5 Analog input
3 PB2 URXD1 NPCS2 AD6 / WKUP12 ZigBee chip select
4 PB3 UTXD1 PCK2 AD7 User push-button 1
5 PB4 TWD1 PWMH2 TDI JTAG data in
6 PB5 TWCK1 PWML0 WKUP13
7 PB6 TMS/SWDIO JTAG test mode select
PeripheralAPeripheralBPeripheral
C Extra Function
System
Function Comment
TDO/
TRACESWO
JTAG data out
8 PB7 TCK/SWCLK JTAG clock
9 PB8 XOUT CLK12MHz
10 PB9 XIN CLK12MHz
11 PB10 DDM USB DM
12 PB11 DDP USB DP
13 PB12 PWML1 ERASE Flash erase selector
14 PB13 PWML2 PCK0 DAC0 Audio Output R
15 PB14 NPCS1 PWMH3 DAC1 Audio Output L
SAM4S-EK Development Board User Guide 4-17
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
Table 4-3. PIO Port C Pin Assignments and Signal Descriptions
PeripheralBPeripheral
No I/O Line Peripheral A
1 PC0 D0 PWML0 EBI D0
2 PC1 D1 PWML1 EBI D1
3 PC2 D2 PWML2 EBI D2
4 PC3 D3 PWML3 EBI D3
5 PC4 D4 NPCS1 EBI D4
6 PC5 D5 EBI D5
7 PC6 D6 EBI D6
8 PC7 D7 EBI D7
9 PC8 NWR0/NWE TFT LCD write enable
10 PC9 NANDOE NAND Flash output enable
11 PC10 NANDWE NAND Flash write enable
12 PC11 NRD TFT LCD read enable
13 PC12 NCS3 AD12 User push-button 2
14 PC13 NWAIT PWML0 AD10 LCD backlight control
15 PC14 NCS0 NAND Flash chip select
16 PC15 NCS1 PWML1 AD11 TFT LCD chip select
C
Extra
Function
System
Function Comments
17 PC16 A21/NANDALE NAND Flash ALE
18 PC17 A22/NANDCLE NAND Flash CLE
19 PC18 A0/NBS0 PWMH0 RDYBSY NAND Flash RDY/BSY
20 PC19 A1 PWMH1 TFT LCD RegSel
21 PC20 A2 PWMH2 Red LED (Power)
22 PC21 A3 PWMH3 USB Vbus detection
23 PC22 A4 PWML3 QTouch valid button SNS
24 PC23 A5 TIOA3 QTouch valid button SNSK
25 PC24 A6 TIOB3 QTouch up button SNS
26 PC25 A7 TCLK3 QTouch up button SNSK
27 PC26 A8 TIOA4 QTouch down button SNS
28 PC27 A9 TIOB4 QTouch down button SNSK
29 PC28 A10 TCLK4 AD13 QTouch left button SNS
30 PC29 A11 TIOA5 AD14 QTouch left button SNSK
31 PC30 A12 TIOB5 QTouch right button SNS
32 PC31 A13 TCLK5 QTouch right button SNSK
4-18 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
4.4.2 Jumpers
The SAM4S-EK board jumpers are essentially used for two main purposes: functional selection or current measurement. Details are given below.
Table 4-4. Jumpers Setting
Designation Label Default Setting Feature
JP1 JTAG OPEN Close to select the JTAG boundary scan of the SAM4S
Evaluation Kit Hardware
JP2 ADVREF 1-2
JP3 ERASE OPEN Close to reinitialize the Flash contents and some of its NVM bits.
JP4 TEST
JP5 VDDPLL CLOSE Access for current measurement on VDDPLL
JP6 VDDIO CLOSE Access for current measurement on VDDIO
JP7 VDDIN CLOSE Access for current measurement on VDDIN
JP8 VDDCORE CLOSE Access for current measurement on VDDCORE
JP9 CE FLASH CLOSE NCS0 enable NAND Flash chip select
JP10 RS485 OPEN Maintain differential impedance for RS485 interface
JP11 RS485 CLOSE Maintain impedance matching for RS485 interface
JP12 RS485 OPEN Maintain differential impedance for RS485 interface
JP13 CS CLOSE NCS1 chip select LCD
JP14 - JP15 MIC GAIN0
JP16 ADC input OPEN Close for impedance matching on ADC BNC port
JP17 – JP19 MIC Gain stage Close to mux RIN/LIN into MONO-IN path within audio PA
Not populated
(OPEN)
CLOSE (both) 20db
OPEN (both) 26db
Analog reference voltage selection between 3.3V (close 1-2) and
2.5V (close 2-3)
Close for manufacturing test or fast programming mode
Close both to lower gain stage on microphone input.
JP18 SELECT ADC INP
JP20 MONO/STEREO CLOSE Close to fix in mono speaker, no matter the stereo plug state
JP21 DAC output OPEN Close for impedance matching on DAC BNC port
JP22
JP23
JP24
JP25 BP2 CLOSE Open to disconnect and free PB3 for custom usage
JP26 BP3 CLOSE Open to disconnect and free PC12 for custom usage
JP27 ZIGBEE CLOSE
PIO expansion J12
voltage supply
PIO expansion J13
voltage supply
PIO expansion J14
voltage supply
1-2
2-3
2-3 Set to 3.3V (position 1-2 sets to 5V)
2-3 Set to 3.3V (position 1-2 sets to 5V)
2-3 Set to 3.3V (position 1-2 sets to 5V)
ADC input potentiometer
ADC input BNC
Power supply connection/disconnection for the ZigBEE module
May also be used as a current measurement point
SAM4S-EK Development Board User Guide 4-19
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
Table 4-5. Audio Input Configuration
JP17 JP19 MONO-STEREO INPUT
OFF OFF PIN test point (TP12)
OFF ON Left-in only
4.4.3 Test Points
Some test points have been placed on the SAM4S-EK board for the verification of important signals.
Table 4-6. Test Points
Designation Part Description
TP1 Ring Hook GND
TP2 Ring Hook GND
TP3 Ring Hook GND
TP4 Ring Hook GND
ON OFF Right-in only
ON ON Sum of Left-in and Right-in
TP5 Pad UART TXD
TP6 Pad UART RXD
TP7 Pad LCD Backlight driver anode
TP8 Pad Aux ADC input for Touch Screen controller
TP9 Pad Aux ADC input for Touch Screen controller
TP10 Ring Hook +5V
TP11 Ring Hook +3V3
TP12 Pad Optional Audio PA input
4.4.4 Solder Drops
There are two solder drops designed on the SAM4S-EK for isolation.
Table 4-7. Solder Drops
Designation Default Setting Feature
SD1 OPEN Isolation of DAC output from shared channel (PB14)
SD2 CLOSE Connects PB14 to the AUDIO_OUTL channel
4.4.5 Assigned PIO Lines, Disconnection Possibility
As pointed out in some previous interface description, 0 Ohm resistors have been inserted on the path of
the receiver PIO lines of the SAM4S-EK. These are the PIO lines connected to an external driver on the
board. The 0 Ohm resistors allow disconnecting each of these for custom usage (through PIO expansion
connectors for example). This feature gives the user an added level of versatility for prototyping a system
of his own. See the table below.
4-20 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Table 4-8. Disconnecting Possibility
Designation Default Assignment PIO
R19 0R PC18, RDY/BSY on NAND Flash
R20 0R PA29
R22 DNP Optional write protection on NAND Flash
R25 0R PA21
R26 0R PA25
R27 0R PA24
R28 0R PA22
R31 0R PA23
R33 0R PA22
R34 0R PA21
R35 0R PA24
R36 0R PA25
R44 0R NRST
Evaluation Kit Hardware
R47 0R PA9
R48 0R R2OUT/MN5
R59 0R LCD backlight LED anode
R66 0R PA11
R67 0R PA5
R68 0R PC13
R69 0R PA4
R70 0R Vref TSC
R118 0R PA3 ZB_RSTN
R119 0R PA5 IRQ1_ZBEE
R120 0R PA4 IRQ0_ZBEE
R121 0R PA6 SLP_TR
Table 4-9. Default Not Populated Parts
Reference Function
J1, R1 External clock resource input
Y1, R3, R7 Backup 12 MHz crystal
R6, R8 Isolation on 12 MHZ clock source and GPIO expansion
R9, R10 Isolation on 32 KHz clock source and GPIO expansion
R22 Optional write protection NAND Flash
R23 Optional pull-up for open drain output or equivalent device
R24, R30 Differential impedance matching for RS485 cable
SAM4S-EK Development Board User Guide 4-21
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
Table 4-9. Default Not Populated Parts
Reference Function
D1 Optional ESD protection for LCD touch panel
R61, R63, RA2, RA3 Optional data bus termination for LCD controller
JP4 Test mode selection for the SAM chip
J2 Optional QFP socket for the SAM4 chip
K1 Virtual component for QTouch keys set - implemented as copper areas
S1 Virtual component for QTouch slider set - implemented as copper areas
TPxx Surface-mounted test points (copper area)
4.5 Connectors
4.5.1 Power Supply Connector J9
The SAM4S-EK evaluation board can be powered from a 5VDC power supply connected to the external
power supply jack J9. The positive pole is the center pin.
Figure 4-25. Power Supply Connector J9
Table 4-10. Power Supply Connector J9 Signal Descriptions
Pin Mnemonic Signal Description
1 Center +5vcc
2 Gnd Ground reference
4.5.2 USART Connector J5 With RTS/CTS Handshake Support
Figure 4-26. Male RS232/USART Connector J5
4-22 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
Table 4-11. Serial COM1 Connector J5 Signal Descriptions
Pin Mnemonic Signal Description
1, 4, 6, 9 NC NO CONNECTION
2 TXD TRANSMITTED DATA RS232 serial data output signal
3 RXD RECEIVED DATA RS232 serial data input signal
5 GND GROUND
7 RTS READY TO SEND Active-positive RS232 input signal
8 CTS CLEAR TO SEND Active-positive RS232 output signal
4.5.3 UART Connector J7
Male RS232/UART connector J7
Evaluation Kit Hardware
Table 4-12. Male RS232/UART Connector J7 Signal Descriptions
Pin Mnemonic Signal Description
1, 4, 6, 7, 8, 9 NC NO CONNECTION
2 TXD TRANSMITTED DATA RS232 serial data output signal
3 RXD RECEIVED DATA RS232 serial data input signal
5 GND GROUND
4.5.4 USB Device Connector J15
Figure 4-27. Micro-B USB Connector J15
Table 4-13. Micro-B USB Connector J15 Signal Descriptions
Pin Mnemonic Signal Description
1 Vbus 5v power
2 DM Data -
3 DP Data +
4 Gnd Ground
5 Shield Shield
SAM4S-EK Development Board User Guide 4-23
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.5.5 TFT LCD Connector J8
One 39-pin connector is available on the board to connect the LCD module, backlight and touch screen.
Figure 4-28. LCD Connector J8
Table 4-14. LCD Connector J8 Signal Descriptions
Pin Mnemonic Pin Mnemonic
1 3V3 2 LCD_DB17 (PC7)
3 LCD_DB16 (PC6) 4 LCD_DB15 (PC5)
5 LCD_DB14 (PC4) 6 LCD_DB13 (PC3)
7 LCD_DB12 (PC2) 8 LCD_DB11 (PC1)
9 LCD_DB10 (PC0) 10 LCD_DB09 (NC)
11 LCD_DB08 (NC) 12 LCD_DB07
13 LCD_DB06 (NC) 14 LCD_DB05 (NC)
15 LCD_DB04 (NC) 16 LCD_DB03 (NC)
17 LCD_DB02 (NC) 18 LCD_DB01 (NC)
19 LCD_DB00 (NC) 20 3V3
21 RD (PC11) 22 WR (PC8)
23 RS (PC19) 24 CS (PC15)
25 RESET 26 IM0
27 IM1 28 GND
29 LED-A 30 LED-K1
31 LED-K2 32 LED-K3
33 LED-K4 34 Y UP
35 Y DOWN 36 X RIGHT
37 X LEFT 38 NC
39 GND
4-24 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
4.5.6 JTAG Debugging Connector J6
This JTAG connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm
male) that mates with IDC sockets mounted on a ribbon cable. Its signal assignment is compatible with
the SAM-ICE or any similar third-party interface.
Figure 4-29. JTAG/ICE Connector J6
Table 4-15. JTAG/ICE Connector J13 Signal Descriptions
Pin Mnemonic Description
This is the target reference voltage. It is used to check if the target has power, to
1 VTref. 3.3V power
create the logic-level reference for the input comparators and to control the output
logic levels to the target. It is normally fed from Vdd on the target board and must
not have a series resistor.
Evaluation Kit Hardware
2 Vsupply. 3.3V power
nTRST TARGET RESET — Active-low
3
4 GND Common ground
5
6 GND Common ground
7 TMS TEST MODE SELECT –
8 GND Common ground
9
10 GND Common ground
11
output signal that resets the target
TDI TEST DATA INPUT — Serial data
output line, sampled on the rising edge
of the TCK signal
TCK TEST CLOCK — Output timing
signal, for synchronizing test logic and
control register access
RTCK
Input Return test clock signal from the
target
This pin is not connected in SAM-ICE. It is reserved for compatibility with other
equipment. Connect to Vdd or leave open in target system.
JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port.
Typically connected to nTRST on the target CPU. This pin is normally pulled
HIGH on the target to avoid unintentional resets when there is no connection.
JTAG data input of target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TDI on target CPU.
JTAG mode set input of target CPU. This pin should be pulled up on the target.
Typically connected to TMS on target CPU. Output signal that sequences the
target’s JTAG state machine, sampled on the rising edge of the TCK signal.
JTAG clock signal to target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TCK on target CPU.
Some targets must synchronize the JTAG inputs to internal clocks. To assist in
meeting this requirement, a returned and retimed TCK can be used to
dynamically control the TCK rate. SAM-ICE supports adaptive clocking which
waits for TCK changes to be echoed correctly before making further changes.
Connect to RTCK if available, otherwise to GND.
12 GND Common ground
13
14 GND Common ground
SAM4S-EK Development Board User Guide 4-25
TDO JTAG TEST DATA OUTPUT —
Serial data input from the target
JTAG data output from target CPU. Typically connected to TDO on target CPU.
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
Table 4-15. JTAG/ICE Connector J13 Signal Descriptions (Continued)
Pin Mnemonic Description
15 nSRST RESET — Active-low reset signal. Target CPU reset signal
16 GND Common ground
17 RFU This pin is not connected in SAM-ICE.
18 GND Common ground
19 RFU This pin is not connected in SAM-ICE.
20 GND Common ground
4.5.7 SD/MMC - MCI Connector J3
Figure 4-30. SD/MMC Connector J3
Table 4-16. SD/MMC Connector J3 Signal Descriptions
Pin Mnemonic Pin Mnemonic
1 RSV/DAT3 2 CDA
3 GND 4 VCC
5 CLK 6 GND
7DAT08DAT1
9 DAT2 10 Card Detect
11 GND 12
4-26 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
4.5.8 Analog Connector CN1 & CN2
Figure 4-31. Analog Input Connector CN1 and Analog Output CN2, Bottom View
Table 4-17. Analog Input, Output Connector CN1, CN2 Signal Descriptions
Pin Mnemonic
1, 2, 3, 4 GND
5 Analog input PB1 for CN1 and analog output PB13 for CN2 respectively
4.5.9 RS485 Connector J14
Evaluation Kit Hardware
Figure 4-32. RS485 Connector J14
Table 4-18. RS485 J14 Signal Descriptions
Pin Mnemonic
1 A - non-inverted RS485 signal A
2 Frame ground
3 B - non-inverted RS485 signal B
SAM4S-EK Development Board User Guide 4-27
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.5.10 Headphone Connector J11
Figure 4-33. Headphone J11
Table 4-19. Headphone J11 Signal Descriptions
Pin Mnemonic
1 AGND
2 Out left
3
4
5 Out Right
4.5.11 ZigBEE Connector J16
Figure 4-34. ZigBee Connector J16
Table 4-20. Connector J16 Signal Descriptions
Signal
Function
Reset /RST 1 2 Misc.
Interrupt
Request
Name Port Pin Pin Port
IRQ 3 4 SLP_TR SLP_TR
Signal
Name Function
Option on Misc. Port Set by
Zero Ohm Resistor or Solder Shunts
EEPROM for MAC address, CAP array
settings and serial number
TST: test mode activation
CLKM: RF chip clock output
SPI chip
select
SPI MISO MISO 7 8 SCLK SPI CLK
Power
Supply
4-28 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
/SEL 5 6 MOSI SPI MOSI
GND GND 9 10 VCC VCC VCC
Voltage range: 1.8v to 5.5v, typically
regulated to 3.3v
4.5.12 PIO Expansion Port C Connector J12
Figure 4-35. PIO Expansion Connector J12
Table 4-21. Connector J12 Signal Descriptions
Pin Mnemonic Pin Mnemonic
1 +5V or +3v3 2 +5V or +3v3
3 GND 4 GND
5 PC0 6 PC16
7 PC1 8 PC17
9 PC2 10 PC18
Evaluation Kit Hardware
11 PC3 12 PC19
13 PC4 14 PC20
15 PC5 16 PC21
17 PC6 18 NC
19 PC7 20 NC
21 PC8 22 NC
23 PC9 24 NC
25 PC10 26 NC
27 PC11 28 NC
29 PC12 30 NC
31 PC13 32 NC
33 PC14 34 NC
35 PC15 36 NC
37 GND 38 GND
39 3V3 40 3V3
SAM4S-EK Development Board User Guide 4-29
11139A–ATARM–29-Nov-11
Evaluation Kit Hardware
4.5.13 PIO Expansion Port A Connector J13
Figure 4-36. PIO Expansion Connector J13
Table 4-22. Connector J13 Signal Descriptions
Pin Mnemonic Pin Mnemonic
1 +5V or +3v3 2 +5V or +3v3
3 GND 4 GND
5 NC 6 PA16
7 NC 8 PA17
9 NC 10 PA18
11 NC 12 PA19
13 NC 14 PA20
15 NC 16 PA21
17 PA6 18 PA22
19 PA7 20 PA23
21 PA8 22 PA24
23 PA9 24 PA25
25 PA10 26 PA26
27 PA11 28 PA27
29 PA12 30 PA28
31 PA13 32 PA29
33 PA14 34 PA30
35 PA15 36 PA31
37 GND 38 GND
39 3V3 40 3V3
4-30 SAM4S-EK Development Board User Guide
11139A–ATARM–29-Nov-11
5.1 Schematics
This section contains the following schematics:
Block diagram
General information
Microcontroller
NAND Flash, serial interface
TFT LCD & Touch
Audio & Power Supply
USB, LEDs, push-buttons & ZigBEE
Section 5
Schematics
SAM4S-EK Development Board User Guide 5-1
11139A–ATARM–29-Nov-11
5
D D
4
3
2
1
5 V Input
POWER SUPPLY
(3.3V)
AUDIO In (ADC)
MIC
AUDIO Out (DAC)
PHONE
JACK
C C
POT
ADC/ DAC
Sheet 6
POWER
PIO A, B, C
ATMEL
Cortex-M4 ARM Processor
SAM4S (LQFP100)
PIO A, B, C
NAND FLASH
HSMCI
UART0
USART1
USART1
Micro SD
RS232
ICE
QTOUCH
Sheet 4
HE 10 RS485
LCD INTERFACE
2.8"
240x320
TFT
TOUCH SCREEN
Sheet 5
B B
Board Configuration
Sheet
Sheet 2
Sheet 3
FS
DEVICE
ZIGBEE
INTERFACE
LEDs, Buttons
PIO A, B, C
Extension
Sheet 7
USB
HE 10
HE 14
A A
INIT EDIT
INIT EDIT
INIT EDIT
A
A
A
REV
REV
REV
SCALE
SCALE
SAM4S-EK
SAM4S-EK
SAM4S-EK
Block Diagram
Block Diagram
Block Diagram
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SCALE
1/1
1/1
1/1
08-Mar-11
08-Mar-11
08-Mar-11
DES.
DATE
DES.
DATE
DES.
DATE
1
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
DATEMODIF.
VER.
DATEMODIF.
VER.
DATEMODIF.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
1
1
1
A
A
A
7
7
7
5
4
3
2
1
REVISION HISTORY
REV DATA
D D
A
2011.03 ORIGINAL RELEASED
NOTE
SCHEMATICS CONVENTIONS
(1) Resistance Unit: "K" is "Kohm", "R" is "Ohm?
(2) "nm" means the component is not populated
by default
TABLE OF CONTENTS
PAGE
1
Block Diagram
Reference guide
2
Microcontroller
3
4
C C
NAND Flash, RS232, RS485, MCI, JTAG
LCD, Touch items
5
Audio, AD/DA, Power
6
7
IO Expansion, USB, ZigBEE, LED, Button
DESCRIPTION
TEST POINT
PAGE REFERENCE FUNCTION
3 TP1, TP2, TP3, TP4 GND
TP5 UART TXD
4
TP6 UART RXD
5
TP7 LCD backlight driver anode
TP8, TP9 Aux ADC input for TSC
6
TP12 Optional audio PA input
JUMPER and SOLDERDROP
PAGE REFERENCE FUNCTION
3 JP1 Close to select JTAG boundary scan
JP2 Analog reference voltage selection between 3.3V and 3.0V
JP3 Close to reinitialize the Flash contents and some of its NVM bits
JP4 Close for manufacturing test or fast programming mode
JP5, JP6, JP7, JP8 Access for current measurement on each power rail
JP9 Nand Flash chip select enable
4
JP11
JP10, JP12 OPEN RS485 pull resistor selectors
JP31
JP13
5 LCD chip select enable
JP14, JP15 Sync close to degrade gain stage on microphone input
6
JP17, JP19 Close to mux RIN/LIN into MONO-IN path within audio PA
JP16, JP21 Close for impedance matching on AD/DA BNC port
JP18 ADC input selection between BNC port and potentiometer
JP20 Close to fix in mono speaker mode, no matter stereo plug state
JP29 1-2 AUDIO Amplifier power select between +5V and VCC33
JP30 DAC output between AUDIO left channel and BNC connector
7 JP22, JP23, JP24 DC voltage selection between 3.3V and 5V on PIO expansion ports
JP25 Button BP2 disable
JP26
JP27 Power consumption measure for ZigBEE module
DEFAULT
OPEN
1-2
OPEN
OPEN
CLOSE
CLOSE
CLOSE
1-2
CLOSE
OPEN
OPEN
OPEN
1-2
OPEN
1-2
1-2
CLOSE
CLOSE
CLOSE
RS485 bus termination enable
RS232 USART and RS485 selection
Button BP3 disable
PIO MUXING
PIOA USAGE
PA0
TSLIDR_SL_SNS
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
TSLIDR_SL_SNSK
TSLIDR_SM_SNS
TSLIDR_SM_SNSK
TSLIDR_SR_SNS
TSLIDR_SR_SNSK
MCI_CD
CLK_32K
CLK_32K
RX_UART0
TX_UART0
TSC_CS
MISO
MOSI
SPCK
ZB_SLPTR
5
B B
A A
PIOA USAGE
TSC_IRQ/ZB_IRQ0
PA16
TSC_BUSY/ZB_IRQ1
PA17
ZB_RSTN
PA18
LED_BLUE
PA19
LED_GREEN
PA20
RXD1
PA21
TXD1
PA22
COM1EN
PA23
RTS1
PA24
CTS1
PA25
MCI
PA26
MCI
PA27
MCI
PA28
MCI
PA29
MCI
PA30
MCI
PA31
PIOB USAGE
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
MIC INPUT
ANA INPUT
ZB_NPCS2
USER_PB1
JTAG
JTAG
JTAG
JTAG
CLK_12M
CLK_12M
USB_DDM
USB_DDP
ERASE
AUDIO OUT R
AUDIO OUT L
4
PIOC USAGE
PC0
D0
PC1
D1
PC2
D2
PC3
D3
PC4
D4
PC5
D5
PC6
D6
PC7
D7
PC8
WR_LCD
PC9
NAND_OE
PC10
NAND_WE
PC11
RD_LCD
PC12
USER_PB2
PC13
EN_LCD
PC14
NAND_NCS0
PC15
NSC1_LCD
PIOC USAGE
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
NAND_ALE
NAND_CLE
NAND_RDYBSY
REGSEL_LCD
LED_RED(POWER)
USB_CNX
TVALID_SNS
TVALID_SNSK
TUP_SNS
TUP_SNSK
TDWN_SNS
TDWN_SNSK
TLEFT_SNS
TLEFT_SNSK
TRIGHT_SNS
TRIGHT_SNSK
3
DEFAULT NO POPULATE PARTS
PAGE REFERENCE FUNCTION
3 J1, R1 External clock resource input
Y1, R3, R7 Backup 12MHz crystal
R6, R8 Isolation between 12MHz clock source and GPIO line
R9, R10 Isolation between 32KHz clock source and GPIO line
4 R22 Optional write protection on NAND flash
R24, R30
R25 Disconnect RS485 Receive data from PA21
D1 Optional ESD protection for LCD touch panel
5
R61, R62, RA2, RA3 Optional databus termination for LCD controller
2
Differential impedance matching for RS485 cable
REV
REV
REV
SCALE
SCALE
SAM4S-EK
SAM4S-EK
SAM4S-EK
Board Configuration
Board Configuration
Board Configuration
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SCALE
A
A
A
INIT EDIT
INIT EDIT
INIT EDIT
1/1
1/1
1/1
08-Mar-11
08-Mar-11
08-Mar-11
DES.
DATE
DES.
DATE
DES.
DATE
1
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
DATEMODIF.
VER.
DATEMODIF.
VER.
DATEMODIF.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
2
2
2
A
A
A
7
7
7
5
4
3
2
1
VCC33
2
TP2TP2 TP4TP4
INIT EDIT
INIT EDIT
INIT EDIT
1/1
1/1
1/1
PC[0..31]
PA[0..31]
1
JP2JP2
3
MN2
MN2
LM4040AIM3X-3.0
LM4040AIM3X-3.0
PB[0..14]
TP3TP3
DGND
08-Mar-11
08-Mar-11
08-Mar-11
DES.
DATE
DES.
DATE
DES.
DATE
1
+5V
DGND
R13
R13
2.2K
2.2K
VER.
VER.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
A
A
A
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
DATEMODIF.
DATEMODIF.
DATEMODIF.
3
3
3
7
7
7
J1
SMA nmJ1SMA nm
1
2 3
54
D D
C C
B B
A A
VDDIO
VDDCORE
VDDIO
DGND
PA16
PC7
PA15
PA14
PC6
PA13
PA24
PC5
PC4
PA25
PA26
PC3
PA12
PA11
PC2
PA10
PA9
PC1
XOUT32
XIN32
NOT POPULATED
R1 0R nmR1 0R nm
R2
49.9R 1%R249.9R 1%
3
DGND
DGND
C3
20pFC320pF
DGND
C4
20pFC420pF
PC12
PC0
PA20
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51525354555657585960616263646566676869707172737475
PA5
PB4
PA6
5
R3 0R nmR3 0R nm
12
Y1Y1
DNP
R7 0R nmR7 0R nm
R110RR11
0R
12
3
Y3
Y3
32.768KHz
32.768KHz
XOUT32
R120RR12
0R
VDDCORE
PA23
PA19
PC15
PC13
PA22
PC27
PA21
PA18
PC26
PA17
SOCKET_THROUGHT_HOLE
LQFP100
PC28
PA4
PA27
PC8
NRST
PA28
PA30
PA29
TEST
PC9
VDDCORE VDDIO
XIN32
VDDOUT
VDDIN
PA3
PC10
DGND
PB3
PA2
PC31
PC11
C1 20pFC1 20pF
C2 20pFC2 20pF
PB2
PC30
PB1
PC14
PC29
PA1
PB0
PC16
ADVREF
12345678910111213141516171819202122232425
PA0
PC17
Y2 12MHzY2 12MHz
R4 0RR4 0R
R5 0RR5 0R
PB2
PB3
PB10
PB11
+3V3
PB4
PB6
PB7
PB5
NRST
PB0
PB1
+3V3
J2
J2
Socket-QFP100 nm
Socket-QFP100 nm
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
DGND
4
PB14
XIN
XOUT
PC25
PB13
PC24
PC23
PB11
PB10
PB12
PC22
PC21
PB7
PC20
PA31
PC19
PB6
PC18
JTAGSEL
PB5
PB9
PB8
JP1
JP1
Header2 nm
Header2 nm
JP3JP3
JP4
JP4
Header2 nm
Header2 nm
VDDPLL
VDDIO
VDDIO
VDDCORE
XIN
R6 0R nmR6 0R nm
XOUT
R8 0R nmR8 0R nm
PB2
PB3
PB10
PB11
JTAGSEL
PB4
PB6
PB7
PB5
NRST
PB0
PB1
PB12
TEST
97
PB9_XIN
96
PB8_XOUT
7
PB2_URXD1_NPCS2_AD12B6
9
PB3_UTXD1_PCK2_AD12B7
88
PB10_DDM
89
PB11_DDP
77
JTAGSEL
51
PB4_TWD1_PWMH2_TDI
79
PB6_TMS_SWDIO
83
PB7_TCK_SWCLK
76
PB5_TWCK1_PWML0_TDO
60
NRST
3
PB0_PWMH0_AD12B4
5
PB1_PWMH1_AD12B5
87
PB12_PWML1_ERASE
61
TEST
VDDINVDDOUT
VDDIN
10
C6 100nFC6 100nF
VDDPLL
VDDCORE
PC0
PC1
PC2
PC3
40
PC0_D0_PWML025PC1_D1_PWML147PC2_D2_PWML243PC3_D3_PWML3
VDDOUT
11
C7 100nFC7 100nF
DGND
JP5
JP5
Header2
Header2
JP8
JP8
Header2
Header2
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
75
21
62
29
68
37
58
PC5_D535PC6_D632PC7_D7
PC4_D4_NPCS1
PC8_NWR0_NWE
AT91SAM4S-LQFP100
AT91SAM4S-LQFP100
VDDCORE
16
C9 100nFC9 100nF
C8 2.2uFC8 2.2uF
C10 100nFC10 100nF
C22
C22
100nF
100nF
C70
C70
4.7uF
4.7uF
DGND
3
65
PC9_NANDOE
PC10_NANDWE
VDDCORE
36
C11 100nFC11 100nF
DGND
23
PC11_NRD
PC12_NCS3_AD12B12
VDDCORE
56
C12 100nFC12 100nF
DGND
R141RR14
1R
C23
C23
4.7uF
4.7uF
71
PC13_NWAIT_PWML0_AD12B10
VDDCORE
85
19
73
PC14_NCS0
PC16_A21_NANDALE
PC15_NCS1PWML1_AD12B11
C13 4.7uF nmC13 4.7uF nm
L1
L1
10uH-100mA
10uH-100mA
78
PC17_A22_NANDCLE
PC18_A0_NBS0_PWMH0
VDDPLL
100
C14 100nFC14 100nF
PC19_A1_PWMH180PC20_A2_PWMH282PC21_A3_PWMH3
PC21
84
PC22
86
PC22_A4_PWML3
GND
26
PC23
PC23_A5_TIOA390PC24_A6_TIOB3
DGND
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
94
92
17
8
6
54
PC26_A8_TIOA413PC27_A9_TIOB4
PC25_A7_TCLK3
PC28_A10_TCLK4
PC29_A11_TIOA5_AD12B134PC30_A12_TIOB5_AD12B14
PC31_A13_TCLK5_AD12B15
PA17_TD_PCK1_PWMH3_AD12B0
PA18_RD_PCK2_A14_AD12B1
PA19_RK_PWML0_A15_AD12B2
PA20_RF_PWML1_A16_AD12B3
PA22_TXD1_NPCS3_NCS2_AD12B9
PA30_PWML2_NPCS2_MCDA0
PB14_NPCS1_PWMH3_DACO1
GND45GND
GND
VDDIO27VDDIO69VDDIO
95
70
C15 100nFC15 100nF
VDDPLLVDDCORE
VDDOUT
MN1
MN1
AT91SAM4S-LQFP100
AT91SAM4S-LQFP100
PA0_PWMH0_TIOA0_A17
PA1_PWMH1_TIOB0_A18
PA2_PWMH2_SCK0_DATRG
PA3_TWD0_NPCS3
PA4_TWCK0_TCLK0
PA5_RXD0_NPCS3
PA6_TXD0_PCKO
PA7_RTS0_PWMH3
PA8_CTS0_AD12BTRG
PA9_URXD0_NPCS1
PA10_UTXD0_NPCS2
PA11_NPCS0_PWMH0
PA12_MISO_PWMH1
PA13_MOSI_PWMH2
PA14_SPCK_PWMH3
PA15_TF_TIOA1_PWML3
PA16_TK_TIOB1_PWML2
PA21_RXD1_PCK1_AD12B8
PA23_SCK1_PWMH0_A19
PA24_RTS1_PWMH1_A20
PA25_CTS1_PWMH2_A23
PA26_DCD1_TIOA2_MCDA2
PA27_DTR1_TIOB2_MCDA3
PA28_DSR1_TCLK1_MCCDA
PA29_RI1_TCLK2_MCCK
PA31_NPCS1_PCK2_MCDA1
ADVREF
PB13_PWML2_PCK0_DACO0
GNDANA
C17 100nFC17 100nF
91
C18 100nFC18 100nF
DGND
VDDIO
VDDIN
DGND
VDDIO
98
C21 4.7uFC21 4.7uF
C19 100nFC19 100nF
C20 4.7uFC20 4.7uF
JP6
JP6
Header2
Header2
JP7
JP7
Header2
Header2
+
+
C24
C24
10uF
10uF
2
VDDIO
50
C16 100nFC16 100nF
VDDIO
74
72
67
66
55
53
52
49
XIN32
48
46
44
42
41
33
31
30
28
12
14
18
24
15
20
22
34
38
39
57
59
63
64
81
1
93
99
2
R9 0R nmR9 0R nm
XOUT32
R10 0R nmR10 0R nm
ADVREF
PB13
PB14
R1070RR107
0R
+3V3
SAM4S-EK
SAM4S-EK
SAM4S-EK
Microcontroller
Microcontroller
Microcontroller
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
PB13
PB14
DGND
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
100nFC5100nF
C5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
DGND
A
A
A
REV
REV
REV
SCALE
SCALE
SCALE
TP1TP1
5
+3V3
+3V3
R15
R15
R16
R16
47K
47K
47K
C40
C40
100nF
100nF
TP6TP6
DGND
C32
C32
100nF
100nF
R22
R22
0R nm
0R nm
DGND
DGND
47K
C33
C33
100nF
100nF
C36
C36
100nF
100nF
C39
C39
100nF
100nF
C41
C41
100nF
100nF
PC[0..31]
D D
C C
B B
A A
PA[0..31]
UTXD0
URXD0
TXD1
RXD1
RTS1
CTS1
5
PA10
PA9
+3V3
+3V3
PA23
PA22
PA21_232
PA24
PA25
+3V3
+3V3 +3V3
R45
R45
100K
100K
TP5TP5
PC17
PC16
PC9
PC10
JP9
JP9
Header2
Header2
PC14
PC18
R19 0RR19 0R
R21 47KR21 47K
+3V3
C31
C31
4.7uF
4.7uF
DGND
R32
R32
47K
47K
R31 0RR31 0R
R33 0RR33 0R
R34 0RR34 0R
R35 0RR35 0R
R36 0RR36 0R
R37 47KR37 47K
+3V3
R46
R46
100K
100K
R47 0RR47 0R
R48 0RR48 0R
4
NAND FLASH
MN3MN3
MT29F2G08ABAEA
16
CLE
17
ALE
8
RE
18
WE
9
CE
7
R/B
19
WP
1
N.C1
2
N.C2
3
N.C3
4
N.C4
5
N.C5
6
N.C6
10
N.C7
11
N.C8
14
N.C9
15
N.C10
20
N.C11
21
N.C12
22
N.C13
23
N.C14
24
N.C15
25
N.C16
26
N.C17
USART
MN5
MN5
ADM3312EARU
ADM3312EARU
3
VCC
1
V+
21
V-
23
GND
19
SD
5
EN
T1IN7T1OUT
10
R1OUT
T2IN8T2OUT
11
R2OUT
T3IN9T3OUT
12
R3OUT
UART
MN6
MN6
MAX3232CSE
MAX3232CSE
16
VCC
2
V+
6
V-
15
GND
11
T1IN
12
R1OUT
10
T2IN
9
R2OUT
4
C1+
C2+
C3+
R1IN
R2IN
R3IN
C1+
C2+
T1OUT
R1IN
T2OUT
R2IN
3
29
I/O0
30
I/O1
31
I/O2
32
I/O3
41
I/O4
42
I/O5
43
I/O6
44
I/O7
48
N.C28
47
N.C27
46
N.C26
45
N.C25
40
N.C24
39
N.C23
38
PRE
35
N.C22
34
N.C21
33
N.C20
28
N.C19
27
N.C18
37
VCC
12
VCC
36
VSS
13
VSS
6
20
C1-
2
4
C2-
24
22
C3-
18
15
17
14
16
R38 0RR38 0R
13
1
3
C1-
4
5
C2-
14
13
7
8
C38
C38
100nF
100nF
C42
C42
100nF
100nF
C34
C34
100nF
100nF
C35
C35
100nF
100nF
C37
C37
100nF
100nF
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
C27
C27
100nF
100nF
C28
C28
100nF
100nF
PA21_485
PA21
PA21_232
+3V3
DGND
DGND
DGND
C29
C29
1uF
1uF
PA21_485
PA25
PA24
PA22
R25 0R nmR25 0R nm
R27 0RR27 0R
R28 0RR28 0R
PB4
PB6
PB7
PB5
NRST
3
2
JP31JP31
1
J5J5
1
6
2
7
3
8
4
9
5
10
11
FGND
J7J7
1
6
2
7
3
8
4
9
5
10
11
FGND
3
RXD1
CTS1
RTS1
TXD1
2
123
45
R18
R18
R17
R17
10K
10K
10K
10K
PA26
PA27
PA28
PA29
PA30
PA31
PA6
R20 0RR20 0R
+3V3 +3V3
678
RA1
RA1
68Kx4
68Kx4
+
+
C25
C25
10uF
10uF
RS 485
R23
R23
10K
10K
MN4
JP28
JP28
Header2 nm
Header2 nm
2
R39
R39
100K
100K
1
2
3
4
MN4
ADM3485ARZ
ADM3485ARZ
RO
VCC
RE
GND
DE
DI
R40
R40
100K
100K
A
B
+3V3
R41
R41
100K
100K
8
5
6
7
C30
C30
100nF
100nFR26 0RR26 0R
DGND
R29
R29
120R
120R
R43
R43
R42
R42
100K
100K
100K
100K
R44 0RR44 0R
SAM4S-EK
SAM4S-EK
SAM4S-EK
NAND Flash & Serial IF
NAND Flash & Serial IF
NAND Flash & Serial IF
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
+3V3
DGND
+3V3
10
C26
C26
100nF
100nF
R24
R24
0R nm
0R nm
JP10
JP10
Header2
Header2
JP11
JP11
JP12
JP12
Header2
Header2
Header2
Header2
R30
R30
0R nm
0R nm
DGND
ICE INTERFACE
J6
J6
HE10 20PTS
HE10 20PTS
VTref1Vsupply
nTRST3GND1
TDI5GND2
TMS7GND3
TCK9GND4
RTCK11GND5
TDO13GND6
nSRST15GND7
DBGRQ17GND8
DBGACK19GND9
REV
REV
REV
SCALE
SCALE
SCALE
SD CARD
J3
TF01AJ3TF01A
1
DAT2
2
DAT3
3
CMD
4
VCC
5
CLK
6
VSS
7
DAT0
8
DAT1
GND
9
CD
FGND
INIT EDIT
INIT EDIT
INIT EDIT
A
A
A
1/1
1/1
1/1
1
11
Sh1
12
Sh2
13
Sh3
DGND
J4J4
1
2
3
2
4
6
8
10
12
14
16
18
20
DGND
08-Mar-11
08-Mar-11
08-Mar-11
DES.
DATE
DES.
DATE
DES.
DATE
1
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
DATEMODIF.
VER.
DATEMODIF.
VER.
DATEMODIF.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
4
4
4
A
A
A
7
7
7
5
+3V3
+
+
C43
C43
10uF
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PC11
PC8
PC19
PC15
DGND
+3V3
R62
R62
100K
100K
R66 0RR66 0R
R67 0RR67 0R
R70 0RR70 0R
C58
C58
100nF
100nF
AGND_TP
C59
C59
100nF
100nF
10uF
LED_A
DGND
PA11
PA17
C60
C60
100nF
100nF
PC[0..31]PA[0..31]
D D
NRST
C C
LCD_DB0
LCD_DB4
LCD_DB2
LCD_DB3
LCD_DB1
LCD_DB8
LCD_DB6
LCD_DB7
LCD_DB5
LCD_DB9
B B
MN7
MN7
ADS7843E
ADS7843E
X_RIGHT
Y_UP
X_LEFT
Y_DOWN
R72
R72
100K
100K
A A
AGND_TP
2
XP
3
YP
4
XM
5
YM
PENIRQ
7
IN3
8
IN4
R73
R73
100K
100K
LCD TOUCH SCREEN
PC13
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
+3V3
R56
R56
10K
10K
R58
R58
4.7K
4.7K
DGND
R61 4.7K nmR61 4.7K nm
1
8
2
7
3
6
4 5
1
8
2
7
3
6
4 5
R63 4.7K nmR63 4.7K nm
16
DCLK
14
DIN
12
DOUT
15
CS
13
BUSY
11
9
VREF
1
VCC1
10
VCC2
6
GND
NRST
RA2
RA2
4.7Kx4 nm
4.7Kx4 nm
RA3
RA3
4.7Kx4 nm
4.7Kx4 nm
PA14
PA13
PA12
4
C44
C44
C45
C45
100nF
100nF
100nF
100nF
LCD_DB17
LCD_DB16
LCD_DB15
LCD_DB14
LCD_DB13
LCD_DB12
LCD_DB11
LCD_DB10
LCD_DB9
LCD_DB8
LCD_DB7
LCD_DB6
LCD_DB5
LCD_DB4
LCD_DB3
LCD_DB2
LCD_DB1
LCD_DB0
JP13 Header2JP13 Header2
R59 0RR59 0R
X_RIGHT
Y_UP
X_LEFT
Y_DOWN
+3V3
R65
R65
100K
100K
R69 0RR69 0RTP9TP9
L2
L2
10uH-100mA
10uH-100mA
R711RR71
1R
C61
C61
4.7uF
4.7uF
LED_K1
LED_K2
LED_K3
LED_K4
Y_UP
Y_DOWN
X_RIGHT
X_LEFT
1
R740RR74
0R
R49
R49
47K
47K
DGND
The part is placed as
close as possible to J8
3
4
5
2
NOT POPULATED
DGND
PA16
+3V3
DGND
J8
J8
FH26-39S-0.3SHW
FH26-39S-0.3SHW
1
VDD
2
DB17
3
DB16
4
DB15
5
DB14
6
DB13
7
DB12
8
DB11
9
DB10
10
DB9
11
DB8
12
DB7
13
DB6
14
DB5
15
DB4
16
DB3
17
DB2
18
DB1
19
DB0
20
VDD
21
RD
22
WR
23
RS
24
CS
25
RESET
26
IM0
27
IM1
28
GND
29
LED-A
30
LEDK1
31
LEDK2
32
LEDK3
33
LEDK4
34
Y+
35
Y-
36
X+
37
X-
38
NC
39
GND
LCD
D1
D1
PACDN044Y5R nm
PACDN044Y5R nm
TVS, SOT23-5
TVS, SOT23-5
+3V3
PC13
3
DGND
PIN 39
PIN 39
PINs
PINs
on
on
BOT
PIN 1
PIN 1
BOT
DGND DGND
FTM280C34D
FTM280C34D
Six slots on PCB for LCD shield
MN8
MN8
AAT3155ITP-T1
AAT3155ITP-T1
10
C1+
C54
C54
1uF
1uF
9
C1-
11
EN/SET
5
IN
C57
C57
4.7uF
4.7uF
4
GND
LCD BACKLIGHT
R680RR68
0R
FB1
FB1
BN03K314S300R
BN03K314S300R
+3V3
R64
R64
47K
47K
DGND
DGNDDGND
OUTCP
C2+
2
Z7
Z7
DGND
7
C55
C55
1uF
LED_A
LED_K1
LED_K2
LED_K3
LED_K4
1uF
6
C2-
8
3
D1
2
D2
1
D3
12
D4
TP7TP7TP8TP8
DGND
C56
C56
1uF
1uF
PC25
PC24
PC31
PC30
PC29
PC28
PC23
PC22
PC27
PC26
R51 1KR51 1K
C47
C47
22nF
22nF
R53 1KR53 1K
C49
C49
22nF
22nF
R55 1KR55 1K
C51
C51
22nF
22nF
R57 1KR57 1K
C52
C52
22nF
22nF
R60 1KR60 1K
C53
C53
22nF
22nF
PA1
PA0
PA3
PA2
PA5
PA4
22nF use X7R
R50 1KR50 1K
C46
C46
22nF
22nF
R52 1KR52 1K
C48
C48
22nF
22nF
R54 1KR54 1K
C50
C50
22nF
22nF
K1
K1
QTouch Key
QTouch Key
QTOUCH
S1
S1
QTouch Slider
QTouch Slider
SR
SL
SM
SR
1
INIT EDIT
INIT EDIT
INIT EDIT
A
A
A
REV
REV
REV
SCALE
SCALE
SAM4S-EK
SAM4S-EK
SAM4S-EK
TFT-LCD & QTouch
TFT-LCD & QTouch
TFT-LCD & QTouch
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SCALE
1/1
1/1
1/1
08-Mar-11
08-Mar-11
08-Mar-11
DES.
DATE
DES.
DATE
DES.
DATE
1
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
DATEMODIF.
VER.
DATEMODIF.
VER.
DATEMODIF.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
5
5
5
A
A
A
7
7
7
5
4
3
2
1
AUDIO IN
AVDD
R77
R77
470R
470R
D D
C C
C63
C63
22uF
22uF
12
AGND
C73
C73
22uF
22uF
AGND AGND
R781KR78
1K
MIC1
MIC1
SVB6050
SVB6050
R851KR85
1K
R88
R88
470R
470R
C67
C67
1uF
1uF
C68
C68
1uF
1uF
R791KR79
1K
R821KR82
1K
AGND
C69
C69
1nF
1nF
AGND AGND
AVDD
C77
C77
4.7uF
4.7uF
AGND
R801KR80
1K
R841KR84
1K
C72
C72
1nF
1nF
R90
R90
100K
100K
R93
R93
100K
100K
R86
R86
47K
47K
JP14 and JP15 should be set
or removed together
R87
R87
47K
47K
JP15
JP15
Header2
Header2
R75 47KR75 47K
R76 47KR76 47K
MN11
MN11
TS922
TS922
2
IN1-
3
IN1+
7
OUT2
6
IN2-
5
IN2+
AUDIO OUT
+5V
VCC33
PB13
B B
A A
JP29JP29
AUDIO_OUTL
1
2
3
C84 0.47uFC84 0.47uF
TP12
Test Pad SQ-40TH
Test Pad SQ-40TH
C88 0.47uFC88 0.47uF
DGND
FB3
FB3
BN03K314S300R
BN03K314S300R
C79
C79
1uF
1uF
JP17 Header2JP17 Header2
C85 0.47uFC85 0.47uF
JP19 Header2JP19 Header2
AGND
+
+
VDD_AMP
C80
C80
10uF
10uF
R98 33KR98 33K
R99 47KR99 47K
R100 33KR100 33K
R104 47KR104 47K
R105 33KR105 33K
C91
C91
4.7uF
4.7uF
DGND
C82
C82
100nF
100nF
DGND
C93
C93
470pF
470pF
MN13
MN13
TPA0223DGQ
TPA0223DGQ
3
VDD
5
RIN
1
MONO-IN
9
LIN
MN14
MN14
MIC5219-3.3YMM
MIC5219-3.3YMM
2
IN
1
EN
4
BYP
OUT
GND
GND
GND
GND
11
AGND
RO/MO+
LO/MO-
ST/MN
SHUTD0WN
BYPASS
GND
PAD
3
5
6
7
8
DGND
JP14 Header2JP14 Header2
OUT1
VCC
GND
6
AGND
10
7
2
4
8
C62
C62
100pF
100pF
R81
R81
100R
100R
1
AVDD
8
C74
C74
100nF
100nF
4
AGND
+
C81 220uF-TAN-6.3V
+
C81 220uF-TAN-6.3V
R95 1KR95 1K
R97 1KR97 1K
+
C83 220uF-TAN-6.3V
+
C83 220uF-TAN-6.3V
R101 100KR101 100K
R103 100KR103 100K
C86 0.47uFC86 0.47uF
AGND
VCC33+5V
+
+
C92
C92
100uF-TAN-6.3V
100uF-TAN-6.3V
DGND
C71
C71
22nF
22nF
AGND
FB2
FB2
BN03K314S300R
BN03K314S300R
R910RR91
0R
AGND
VCC33
DGND
R102 100KR102 100KTP12
JP20
JP20
Header2
Header2
AGND
R830RR83
0R
J10J10
1
2
J11
J11
Phonejack Stereo 3.5
Phonejack Stereo 3.5
5
4
3
2
1
VDD_AMP
AGND
C87
C87
1uF
1uF
PB0
J9
J9
Power Jack 2.1mm
Power Jack 2.1mm
1
2
3
+5V
CN1
CN1
BNC
BNC
Potentiometer
CN3
CN3
BNC
BNC
MN9
MN9
ZEN056V130A24LS
ZEN056V130A24LS
1
2
MN12
MN12
MIC29152WU
MIC29152WU
Micrel's 1.5A LDO, TO263-5
Micrel's 1.5A LDO, TO263-5
2
VIN
VOUT
1
SD
3
DGND
GND1
VR1
VR1
10K VR
10K VR
ADJ
GND2
6
DGND
VCC33
13
DGND
DGND
3
JP16
JP16
Header2
Header2
R96
R96
49.9R
49.9R
2
JP21
JP21
Header2
Header2
R109
R109
49.9R
49.9R
4
5
C64
C64
100nF
100nF
R940RR94
0R
+
+
C65
C65
22uF
22uF
C89
C89
10nF
10nF
R1060RR106
0R
C90 2.2uFC90 2.2uF
AUDIO_OUTL
R89
R89
169K 1%
169K 1%
R92
R92
102K 1%
102K 1%
C78
C78
10nF
10nF
MN10
MN10
BNX002-01
BNX002-01
1
SV
2
SG
CV
CG1
CG2
CG3
+
+
C75
C75
100uF-TAN-6.3V
100uF-TAN-6.3V
JP18JP18
ADC
JP30JP30
DAC
3
4
5
6
3
1
3
1
+5V
+
+3V3
DGND
C76
C76
100nF
100nF
+
C66
C66
22uF
22uF
+
+
C98
C98
220uF-ELE-16V
220uF-ELE-16V
AD5
2
PB1
DAC1
2
PB14
INIT EDIT
INIT EDIT
INIT EDIT
A
A
A
REV
REV
REV
SCALE
SCALE
SAM4S-EK
SAM4S-EK
SAM4S-EK
Audio & Power supply
Audio & Power supply
Audio & Power supply
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
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SCALE
1/1
1/1
1/1
08-Mar-11
08-Mar-11
08-Mar-11
DES.
DATE
DES.
DATE
DES.
DATE
1
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
DATEMODIF.
VER.
DATEMODIF.
VER.
DATEMODIF.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
6
6
6
A
A
A
7
7
7
5
PB[0..14]
D D
PA[0..31]
PC[0..31]
4
3
2
1
R122
R122
4.7K nm
4.7K nm
R123
R123
4.7K nm
4.7K nm
NRST
+3V3
DGND
1
JP23JP23
1
2
J13J13
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
PIO A
R111
R111
220R
220R
R113
R113
220R
220R
R117
R117
220R
220R
32
3
DGND
R115 100KR115 100K
LEDS
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
D2 LED BlueD2 LED Blue
D3 LED GreenD3 LED Green
D4 LED RedD4 LED Red
JP24JP24
1
3
2
J14J14
1 2
3 4
5 6
PB0
7 8
PB1
9 10
PB2
11 12
PB3
13 14
PB4
15 16
PB5
17 18
PB6
19 20
PB7
21 22
DGND
23 24
PIO B
DGND
DGND
+3V3 +3V3
+3V3
PB8
PB9
PB10
PB11
PB12
PB13
PB14
BP1BP1
1
BP2BP2
1
BP3BP3
1
BUTTONS
TWD1
TWCK1
3
42
JP25
3
42
3
42
+3V3 +5V
JP25
Header2
Header2
JP26
JP26
Header2
Header2
PB4
PB5
PB3
PC12
JP22JP22
+5V +3V3 +5V +5V+3V3 +3V3
1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
C C
FGND
B B
PC21 PC20
PB10
PB11
R110 47KR110 47K
R112 68KR112 68K Q1
R114 27RR114 27R
R116 27RR116 27R
DGND
RV2
RV2
V5.5MLA0603
V5.5MLA0603
C94
C94
10pF
10pF
PC15
+3V3 +3V3 +3V3+3V3
DGND DGND
J15
J15
USB Micro B
USB Micro B
5V D- D+ ID G
5V D- D+ ID G
8
9
123
475
3
2
J12J12
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
PIO C
6
RV1
RV1
V5.5MLA0603
V5.5MLA0603
DGND FGND
PC16
PC17
PC18
PC19
PC20
PC21
Q1
IRLML2502
IRLML2502
DGND
PA19
PA20
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
USB
DGND
J16
J16
HE10 5x2
ZB_RSTN
IRQ1_ZBEE
SPIO_NPCS2#
MISO
A A
Note:
Pin1 is not on the indentation side
PA18
R118 0RR118 0R
R119 0RR119 0R
PB2
PA12 PA14
HE10 5x2
1 2
3 4
5 6
7 8
9 10
R120 0RR120 0R
R121 0RR121 0R
C95
C95
18pF
18pF
C96
C96
2.2nF
2.2nF
Pin1
ZIGBEE
HE10
5
4
3
PA16
PA15PA17
PA13
DGND
C97
C97
2.2uF
2.2uF
IRQ0_ZBEE
SLP_TR
MOSI
SPCK
JP27
JP27
Header2
Header2
+3V3
PROTOTYPE AREA
Pitch = 2.54MM
INIT EDIT
INIT EDIT
INIT EDIT
A
A
A
REV
REV
REV
SCALE
SCALE
SAM4S-EK
SAM4S-EK
SAM4S-EK
User IF & ZigBee
User IF & ZigBee
User IF & ZigBee
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SCALE
1/1
1/1
1/1
08-Mar-11
08-Mar-11
08-Mar-11
DES.
DATE
DES.
DATE
DES.
DATE
1
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
XX-XXX-XXJH XXX
DATEMODIF.
VER.
DATEMODIF.
VER.
DATEMODIF.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
7
7
7
A
A
A
7
7
7
6.1 Board Recovery
Closing JP3 and powering the board will assert ERASE and clear GPNVM bit 1, and thereby selects the
boot from the ROM by default. The MCU will boot from the internal ROM to enable a SAM-BA connection
through the UART. Connect the SAM4S-EK UART port (J3) to a PC COM port through an RS232 crossover cable.
You can then run the SAM-BA application from that PC to program the internal Flash of the MCU as well
as the GPNVM bit 1.
Section 6
Troubleshooting
SAM4S-EK Development Board User Guide 6-1
11139A–ATARM–29-Nov-11
7.1 Revision History
Table 7-1.
Document Comments
11139A Initial version.
Section 7
Revision History
Change Request
Ref.
SAM4S-EK Development Board User Guide 7-1
11139A–ATARM–29-Nov-11
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