The Atmel® SAM3S-EK toolkit contains the following items:
Board:
– a SAM3S-EK board
– a universal input AC/DC power supply with US, Europe and UK plug adapters
Cables:
– one USB cable
– one serial RS232 cable
A Welcome Letter
Figure 2-1. Unpacked SAM3S-EK
Section 2
Kit Contents
Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit.
SAM3S-EK Development Board User Guide2-1
11031C–ATARM–30-Mar-11
Kit Contents
2.2Electrostatic Warning
The SAM3S-EK board is shipped in a protective anti-static package. The board must not be subjected to
high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the components or any other metallic element of the board.
2-2SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
3.1Power up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right
power plug adapter corresponding to that of your country, and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the
screen and enjoy the demo.
3.2DevStart
The on-board NAND Flash contains “SAM3S-EK DevStart”.
It is stored in the “SAM3S-EK DevStart” folder on the USB Flash disk available when the SAM3S-EK is
connected to a host computer and you click on the Flash Disk icon of the on-board demo.
Click the file “welcome.html” in this folder to launch SAM3S-EK DevStart.
Section 3
Power Up
SAM3S-EK DevStart guides you through installation processes of IAR™ EWARM, Keil MDK and GNU
toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and how
to program it into the SAM3S-EK. Optionally, if you have a SAM-ICE™, instructions are also given about
how to debug the code.
We recommend that you backup the “SAM3S-EK DevStart” folder on your computer before launching it.
3.3Recovery Procedure
The DevStart ends by giving step-by-step instructions on how to recover the SAM3S-EK to the state as it
was when shipped by Atmel.
Follow the instructions if you deleted the contents of the embedded Flash or the NAND Flash and want
to recover from this situation.
SAM3S-EK Development Board User Guide3-1
11031C–ATARM–30-Mar-11
Power Up
3.4Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can
download sample code and get technical support from Atmel website
This section introduces the Atmel SAM3S Evaluation Kit design. It introduces system-level concepts,
such as power distribution, memory, and interface assignments.
The SAM3S-EK board is based on the integration of an ARM
NAND Flash and a set of popular peripherals. It is designed to provide a high performance processor
evaluation solution with high flexibility for various kinds of applications.
Figure 4-1. SAM3S-EK Block Diagram
Section 4
Evaluation Kit Hardware
®
Cortex®-M3 processor with on-board
SAM3S-EK Development Board User Guide4-1
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
4.2Features List
Here is the list of the main board components and interfaces:
SAM3S4C chip LQFP100 package with optional socket footprint
12 MHz crystal
32.768 KHz crystal
Optional SMB connector for external system clock input
NAND Flash
2.8 inch TFT color LCD display with touch panel and backlight
UART port with level shifter circuit
USART port with level shifter circuit multiplexed with RS485 port with level shifter circuit
Microphone input and mono/stereo headphone jack output
SD/MMC interface
Reset button: NRST
User buttons: Left and Right
QTouch
Full Speed USB device port
JTAG/ICE port
On-board power regulation
Two user LEDs
Power LED
BNC connector for ADC input
BNC connector for DAC output
User potentiometer connected to the ADC input
ZigBEE connector
2x32 bit PIO connection interfaces (PIOA, PIOC) and 1x16 bit PIO connection interface (PIOB)
®
buttons: Up, Down, Left, Right, Valid and Slider
4.3Function Blocks
4.3.1Processor
The SAM3S-EK is equipped with a SAM3S4C device in LQFP100 package.
4.3.2Memory
The SAM3S4 chip embeds:
256 Kbytes of embedded Flash
48 Kbytes of embedded SRAM
16 Kbytes of ROM with embedded BootLoader routines (UART, USB) and In-Application Programming
functions (IAP) routines.
4-2SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
MT29F2G08AADWP
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PC10
PC9
PC16
PC17
PC1
8
PC1
4
+
3V3
DGND
+3V3
DGND
+3V3
+3
V3
PC[0..31
]{3,5,7
}
MN3MN3
W
E
18
N.C
6
6
VCC
37
CE
9
RE
8
N.C11
20
W
P
1
9
N.C
5
5
N.C1
1
N.C2
2
N.C3
3
N.C
4
4
N.C12
2
1
N.C
13
2
2
N.C14
23
N.C15
24
R
/B
7
N.C17
26
N
.C18
27
N
.C19
28
I/O0
29
N
.C21
34
N
.C22
35
VSS
3
6
PR
E
3
8
N.C2
3
3
9
VCC
12
VSS
1
3
AL
E
17
N.C
8
11
N.C
7
1
0
N.C9
14
N.C10
15
CLE
16
N.C16
25
N
.C20
33
I/O1
30
I/O3
32
I/O2
31
N.C2
7
47
N.C2
6
46
N.C2
5
4
5
I/O7
44
I/O6
4
3
I/O5
42
I/O4
41
N.C2
4
4
0
N
.C28
48
C2
7
100nF
C2
7
100nF
R15
47K
R15
47K
R2147KR2147K
R1
6
47K
R1
6
47K
C29
1uF
C29
1uF
R190
R
R190
R
R22
DN
P
R22
DN
P
JP9J
P9
C
28
100nF
C
28
100nF
NOT POPULATE
D
D
NP
XOUT32
XIN32
XIN
32
XOUT32
PA7
PA8
XIN
XO
UT
PB8
PB9
DGND
DG
ND
DGND
DGND
DGND
R
3DNP
R
3DNP
R6DN
P
R6DN
P
R
9D
NPR
9D
NP
R1DNPR1DNP
C
3
20pF
C
3
20pF
R40RR40R
C4
20pFC420pF
R2
49.9R 1%R249.9R 1%
Y1Y1
12
3
R8DN
P
R8DN
P
R
7DN
PR
7DN
P
AT91SAM3S
MN1
AT91SAM3S
MN1
PA7_RTS0_PWMH3
49
PA8_CTS0_AD
12BTRG
4
8
PB8_XO
U
T
96
PB9_XIN
97
R1
1
0R
R1
1
0R
Y
212MHz
Y
212MHz
C
120pF
C
120pF
R10DNPR10DNP
Y3
32.768KHz
Y3
32.768KHz
12
3
R50
R
R50
R
R12
0
R
R12
0
R
J1J1
1
23
54
C
220pF
C
220pF
The SAM3S features an External Bus Interface (EBI) that permits interfacing to a broad range of external
memories and virtually to any parallel peripheral. The SAM3S-EK board is equipped with a memory
device connected to the SAM3 EBI:
One NAND Flash MT29F2G08AADWP.
Figure 4-2. NAND Flash
NCS0 chip select signal is used for NAND Flash chip selection. Furthermore, a dedicated jumper can
disconnect it from the on-board memories, thereby letting NCS0 free for other custom purpose.
4.3.3Clock Circuitry
The clock generator of a SAM3S microcontroller is made up of:
A Low Power 32.768 Hz Slow Clock Oscillator with bypass mode.
A 3 to 20 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB).
A factory programmed fast internal RC Oscillator. 3 output frequencies can be selected: 4 (default
value), 8 or 12 MHz.
A 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller.
A 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and
to the peripherals. The input frequency of PLLA is from 7.5 and 20 MHz.
The SAM3S-EK board is equipped with one 12 MHz crystal, optional Piezoelectric Ceramic Resonator
12 Mhz (Murata ref. CSTCE12M0G15L99-R0), one 32.768 Hz crystal and an external clock input connector (optional, not populated by default).
Figure 4-3. External Clock Source
SAM3S-EK Development Board User Guide4-3
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
DGND
+
5V
+5V+3V3
C75
100uF
+
C75
100uF
C65
22uF
+
C65
22uF
C64
100nF
C64
100nF
MN10
BN
X002-01
MN10
BN
X002-01
SV
1
SG
2
C
V
3
CG
1
4
CG2
5
CG3
6
C76
100nF
C76
100nF
C66
22u
F
+
C66
22u
F
MN9
ZEN056V130A24LS
MN9
ZEN056V130A24LS
1
2
3
R92
102K
1%
R92
102K
1%
MN12
MIC29152WU
Mic
rel's 1.5A LDO, TO263-5
MN12
MIC29152WU
Mic
rel's 1.5A LDO, TO263-5
VI
N
2
VOUT
4
SD
1
GND1
3
ADJ
5
GND2
6
R89
169K 1%
R89
169K 1%
J9
MP179P 2.1mm
J9
MP179P 2.1mm
1
2
3
The SAM3S chip internally generates the following clocks:
SLCK, the Slow Clock, which is the only permanent clock of the system
MAINCK, the output of the Main Clock Oscillator selection: either a Crystal Oscillator or a 4/8/12 MHz
Fast RC Oscillator
PLLACK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLA)
PLLBCK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLB)
4.3.4Reset Circuitry
On-board NRST button BP1 provides an external reset control of the SAM3S.
The NRST pin is bidirectional. It is handled by the on-chip reset controller. It can be driven low to provide
a reset signal out to the external components. Conversely, it can be asserted low from the outside to
reset the microcontroller Core and the peripherals. The NRST pin integrates a permanent pull-up resistor
of about 100 kOhm to VDDIO.
On the SAM3S-EK board, the NRST signal is connected to the LCD module and JTAG port.
Note:At power-on, the NRST signal is asserted with a default duration of 2 clock cycles. That duration may not be
sufficient to correctly reset any other system or board devices connected to that signal. First, in your custom
application, you need to check for these devices' datasheets about reset duration requirements. Then, you
need to set an appropriate configuration in the NRST Manager. This is done through the ERSTL field in the
RSTC_MR register. The NRST duration is thereby configurable between 60 µs and 2 s, whether it is subsequently activated by a software reset or a user reset. Refer to the SAM3S datasheet for in depth
information.
4.3.5Power Supply and Management
The SAM3S-EK board is supplied with an external 5V DC block through input J9. It is protected by a
PolyZen diode MN9 and an LC combinatory filter MN10. The PolyZen is used in the event of an incorrect
power supply connection.
The adjustable LDO regulator MN12 is used for the 3.3V rail main supply. It powers all the 3.3V components on the board.
Figure 4-4. Power Block
The SAM3S4/2/1 product series has different types of power supply pins:
VDDIN pin:
Power for the internal voltage regulator, ADC, DAC, and analog comparator power supplies.
The voltage ranges from 1.8V to 3.6V.
4-4SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
4.3.6UART
+3V3
D
GND
DGND
+
3V3
+3V3
FGND
PA10
PA9
C3
9
100nF
C3
9
100nF
C40
100nF
C40
100nF
T
P5
SMD
T
P5
SMD
J7J7
5
4
3
2
1
9
8
7
6
10
11
R46
100
K
R46
100
K
C38
100nF
C38
100nF
TP6
SM
D
TP6
SM
D
C41
100nF
C41
100nF
R470
R
R470
R
R480
R
R480
R
C42
100nF
C42
100nF
MN6
MAX3232CSE
MN6
MAX3232CSE
T1
IN
1
1
T2
IN
1
0
R1O
UT
1
2
R2O
UT
9
T1OUT
1
4
T2OUT
7
R1IN
1
3
R2I
N
8
V+
2
C1+
1
C1-
3
C2+
4
C2-
5
V-
6
VCC
16
GND
1
5
R
45
100K
R
45
100K
Evaluation Kit Hardware
VDDIO pins:
Power for the Peripherals I/O lines.
The voltage ranges from 1.62V to 3.6V.
VDDOUT pin:
Output of the internal voltage regulator.
VDDCORE pins:
Power for the core, including the processor, embedded memories and peripherals.
The voltage ranges from 1.62V to 1.95V.
VDDPLL pin:
Power for the PLL A, PLL B and 12 MHz oscillator.
The voltage ranges from 1.62V to 1.95V.
Note:VDDPLL should be decoupled and filtered from VDDCORE.
The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes. It offers an ideal channel for in-situ programming solutions. This UART
is associated with two PDC channels to reduce the processor time on packet handling.
This two-pin UART (TXD and RXD only) is buffered through an RS232 Transceiver MN6 and brought to
the DB9 male connector J7.
4.3.7USART
Figure 4-5. UART
The Universal Synchronous/Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous/asynchronous serial link. The data frame format is extensively configurable (data
length, parity, number of stop bits) to support a broad range of serial communication standards. The
USART is also associated with PDC channels for TX/RX data access.
Note:For design optimization purposes, both transmitters have been implemented on the same
PIO lines, that is PA21, 22, 23, 24 25.
To avoid any electrical conflict, the RS485 transceiver is isolated from the receiving line PA21.
SAM3S-EK Development Board User Guide4-5
Should you need to implement an RS485 channel in place of the RS232, follow the procedure below:
1.make sure your software will permanently set PA23 to a high level - this will permanently disable the
2.solder a shunt resistor in place of R25 (a solder drop will do).
RS232 receiver.
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
PA2
5
PA2
4
PA2
1
PA2
2
PA23
F
GND
DGND
+3V3
DGND
+
3V3
+
3V3
DGND
R360
R
R360
R
C3
4
100nF
C3
4
100nF
C35
100nF
C35
100nF
C36
100nF
C36
100nF
R3
2
47K
R3
2
47K
MN5
ADM3312EAR
U
MN5
ADM3312EAR
U
C1+
6
C1-
2
0
C2+
2
C2-
4
C3
+
24
C3-
22
VC
C
3
V
+
1
V-
2
1
GND
23
SD
19
EN
5
T1I
N
7
T1OU
T
18
R1IN
15
R1OU
T
10
T2I
N
8
T
2OU
T
17
R2IN
14
R2OU
T
11
T3I
N
9
T
3OU
T
16
R3IN
13
R3O
UT
1
2
R380RR380R
C31
4
.7u
F
C31
4
.7u
F
C32
1
00nF
C32
1
00nF
R350
R
R350
R
C37
100nF
C37
100nF
C3
3
100nF
C3
3
100nF
J5J5
5
4
3
2
1
9
8
7
6
10
11
R340
R
R340
R
R330RR330R
R310RR310R
R3747KR3747K
PA2
2
PA2
4
PA2
5
PA2
1
PA2
3
DGND
+3V3
+3V3+3V3
DGND
FGND
MN4
ADM3485AR
Z
MN4
ADM3485AR
Z
R
O
1
R
E
2
D
E
3
D
I
4
VCC
8
G
ND
5
A
6
B
7
R28
0
R
R28
0
R
R3
0
DNP
R3
0
DNP
J4J4
1
2
3
R29
120
R
R29
120
R
C30
100nF
C30
100nF
R26
0
R
R26
0
R
JP11JP11JP12JP12
JP10JP1
0
R27
0
R
R27
0
R
R23
D
N
P
R23
D
N
P
R25
DN
P
R25
DN
P
R24
D
N
P
R24
D
N
P
4.3.7.1RS232
SAM3S-EK connects the USART1 bus (including TXD, RXD, RTS, CTS handshake signal controls and
EN command) to the DB9 male connector J5 through the RS232 Transceiver MN5.
Figure 4-6. USART
4.3.7.2RS485
As noticed above, the USART1 is shared with the RS485 port, connected to the transceiver MN4, connected to the 3-point connector J4. The design includes selectable jumpers for RS485 bus termination
resistors selection (JP10, JP11, JP12).
Figure 4-7. RS485
4.3.8Display Interface
The SAM3S-EK carries a TFT Transmissive LCD module with touch panel, FTM280C34D. Its integrated
driver IC is ILI9325. The LCD display area is 2.8 inches diagonally measured, with a native resolution of
240 x 320 dots.
The LCD module gets reset from the NRST signal. As explained, this NRST is shared with the JTAG port
and the push-button BP1. The LCD chip select signal is connected to NCS1; the jumper JP13 can disconnect it so that this PIO line is available for other custom usage.
The SAM3S communicates with the LCD through PIOC where an 8-bit parallel “8080-like” protocol data
bus has to be implemented by software.
The LCD backlight is made of four integrated white chip-LEDs arranged in parallel. These are driven by
an AAT3155 charge pump, MN8.The AAT3155 is controlled by the SAM3S through a single PIO line
PC13 interface; the 0 Ohm resistor R68 is mounted in series on this line, which permits to use it for other
custom purposes. In that case, the pull-up resistor R64 maintains the charge pump permanently enabled
by default.
On the anode drive line, a 0 Ohm resistor R59 is implemented in series for an optional current limitation.
Figure 4-9. Backlight Control
SAM3S-EK Development Board User Guide4-7
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
PA12
PA13
PA14
PA17
PA11
X_RIGHT
Y_UP
X_LEFT
Y_DO WN
PA16
DGND
+3V3
+3V3
+3V3
AGND_TPAGND_TP
R62
100K
R62
100K
R700RR700R
R670RR670R
R660RR660R
R65
100K
R65
100K
C6
0
100nF
C6
0
100nF
C58
100nF
C58
100nF
L2
10uH/100
mA
L2
10uH/100
mA
R72
100K
R72
100K
R
690R
R
690R
C61
4.7uF
C61
4.7uF
T
P9
SM
D
T
P9
SM
D
R71
1
R
R71
1
R
C59
100nF
C59
100nF
TP8SMD
TP8SMD
R740RR74
0R
R73
100
K
R73
100
K
MN7
ADS7843
E
MN7
ADS7843
E
XP
2
YP
3
XM
4
YM
5
DCLK
1
6
DIN
1
4
DOUT
1
2
CS
1
5
BUSY
13
PENIR
Q
11
VR
EF
9
VC
C1
1
VC
C2
10
GND
6
IN
3
7
IN
4
8
4.3.8.3Touch Screen Interface
The LCD module integrates a 4-wire touch panel controlled by MN7 (ADS7843) which is a slave device
on the SAM3S SPI bus. The controller sends back the information about the X and Y positions, as well
as a measurement for the pressure applied to the touch panel. The touch panel can be used with either
a stylus or a finger.
The ADS7843 touch panel controller connects to the SPI0 interface via the NPCS0 control signal. Two
interrupt signals are connected and provide events information back to the microcontroller: PenIrq and
Busy.
Note:PenIrq (PA16) is shared with ZigBEE signal IRQ0.
Busy (PA17) is shared with ZigBEE signal IRQ1.
Therefore, if using a ZigBEE interface in concurrence with the TouchScreen controller, take
care not to have both drivers enabled at the same time on either PA16 or PA17.
For that purpose, 0 Ohm resistors have been implemented on these PIO lines in order to disconnect
either end driver from the other:
On the touch panel controller side, R67 and R69.
On ZigBEE side, R117 and R120.
for further information, refer to the “Schematics” section.
Touch ADC auxiliary inputs IN3/IN4 of the ADS7843 are connected to test point (TP8, TP9) for optional
function extension.
Figure 4-10. Touch Panel Control
4.3.9JTAG/ICE
A standard 20-pin JTAG/ICE connector is implemented on the SAM3S-EK for the connection of a compatible ARM JTAG emulator interface, such as the SAM-ICE from Segger.
Notes: 1. The NRST signal is connected to BP1 system button and is also used to reset the LCD
module. The 0 ohm resistor R44 may be removed in order to isolate the JTAG port from
this system reset signal.
2. The TDO pin is in input mode with the pull-up resistor disabled when the Cortex M3 is
not in debug mode. To avoid current consumption on VDDIO and/or VDDCORE due to
floating input, the internal pull-up resistor corresponding to this PIO line must be
enabled.
4-8SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
Figure 4-11. JTAG Interface
+3V3
DGND
N
RST
PB5
PB7
PB6
PB4
R43
100
K
R43
100
K
R4
1
100
K
R4
1
100
K
R39
100
K
R39
100
K
J6J
6
VT
ref
1
Vsupply
2
nTRST
3
G
ND1
4
TDI
5
GND
2
6
T
M
S
7
GND
3
8
TCK
9
GND
4
1
0
RTC
K
1
1
GND
5
1
2
TDO
1
3
GND6
1
4
n
SRST
1
5
GND
7
1
6
DBGRQ
1
7
GND
8
1
8
DBGACK
19
GND
9
2
0
R42
100
K
R42
100
K
R40
100
K
R40
100
K
R440
R
R440
R
4.3.10Audio Interface
The SAM3S–EK board supports both audio recording and playback.
The audio volume can be adjusted using the potentiometer RV1, and the microphone amplifier gain can
be adjusted via jumpers (fixed gain of 24 or 26 dB).
4.3.10.1 Microphone Input
The embedded microphone is connected to an audio pre-amplifier using the TS922 operational amplifier
(MN11). The gain is set by using JP14 and JP15 jumpers; both must be set or removed at the same
time.
Evaluation Kit Hardware
By modifying the jumper positions, you can select each of the following gain values:
20 dB (default setting, both JP14 and JP15 are off)
26 dB (both JP14 and JP15 are on).
Note:
3. The TB1 series 0 Ohm resistor is a reservation for future impedance adaptation facility.
Under specific amplifier settings conditions, this enables the easy insertion of a capacitor or any other bipolar device on the audio path. On the other hand, R83 is a default
0 Ohm resistor that enables the disconnection of PB0 from the audio input path for custom usage.
4. The audio pre-amplifier MN11 is powered by a dedicated low dropout regulator
MIC5219-3.3 (MN14).
SAM3S-EK Development Board User Guide4-9
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
JP14 and JP15 should be set
or removed togethe
r
AG
ND
AGNDAGND
AVDD
AG
ND
AGN
D
AGND
AVDD
AG
ND
AGND
DGN
D
AVDD
AGND
VCC33
PB0
C72
1
nF
C72
1
nF
R80
1
K
R80
1
K
R90
100
K
R90
100
K
C67
1uF
C67
1uF
C74
100nF
C74
100nF
R84
1
K
R84
1
K
R87
47K
R87
47K
R79
1
K
R79
1
K
R781KR78
1K
R7
7
470R
R7
7
470R
B2 BN03K314S
300
RB2 BN03K314S
300
R
C71
2
2nF
C71
2
2nF
R830RR83
0R
R88
470R
R88
470R
T
B1
0R
T
B1
0R
C63
22uF
C63
22uF
C62
100pF
C62
100pF
C7
7
4.7u
F
C7
7
4.7u
F
R85
1
K
R85
1
K
C7
3
22u
F
C7
3
22u
F
R7547KR7547K
MN11
TS92
2
MN11
TS92
2
IN1
-
2
IN1+
3
OUT2
7
IN2-
6
IN2+
5
GND
4
VCC
8
O
UT1
1
JP14JP14
R7647KR7647K
R9
3
100
K
R9
3
100
K
R910RR91
0R
JP15JP15
C69
1nF
C69
1nF
R86
47K
R86
47K
R8
2
1K
R8
2
1K
C68
1uF
C68
1uF
MIC1
SVB6050
MIC1
SVB6050
12
R81
100R
R81
100R
Figure 4-12. Microphone Input
4.3.10.2 Headphone Output
The SAM3S-EK evaluation kit supports mono/stereo audio playback driven by a TPA0223 audio amplifier connected to two DAC channels of the microcontroller.
The TPA0223 is a 2W mono Bridge-Tied-Load (BTL) amplifier designed to drive speakers with as low as
4 Ohm impedance. The amplifier can be reconfigured on the fly to drive two stereo Single-Ended (SE)
signals into head phones.
Figure 4-13. Headphone Output
1
1
0
0
J
J
1
2
M
M
N13
3
5
1
9
2
2
N13
TPA02
TPA02
VDD
RIN
MONO-
LIN
2
Q
2
Q
3DG
3DG
IN
SH
PAD
11
ND
AG
RO/M
O/M
L
ST/M
UTD0WN
BYPASS
GND
PB14{
6
O+
AGN
10
O-
7
N
2
4
8
3,7}
C81
C81
R951KR95
971K
971K
R
R
D
C83220uF
C83220uF
1100
1100
R10
3100
3100
R10
C860.47uFC860.47uF
+
+
20uF
20uF
2
2
1K
+
+
AGN
R102100
R102100
KR10
K
KR10
K
0
JP20JP2
AGND
AGND
1
1
J1
J1
EARJACK
EARJACK
5
4
3
2
1
D
P
VDD_AM
K
K
C87
C87
uF
uF
1
1
AG
ND
+
V
3K314S30
3K314S30
BN0
BN0
C79
C79
1uF
1uF
ND
C840.
DIO_O
C840.
UTL
C880.47uFC 880.47uF
PB13
AU
4-10SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
G
F
F
7u
7u
4
4
2
2
TP1
TP1
D
D
SM
SM
JP17JP17
C850.47uFC850.47uF
9
9
P1
P1
J
J
( to DAC output
0R
0R
AGNDD
connector )
AUDIO_OUTL
VDD_AM
+
+
C8
C8
0
0
10uF
10uF
R9833
R9833
R9947
R9947
R10033
R10033
R10447
R10447
R10533
R10533
C82
C82
1
1
P
0n
0n
0
0
1
1
F
F
K
K
K
K
K
K
K
K
K
K
SD1SD1
SD2SD2
B3
B3
5
Using a readily available 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no
PC21
PB1
0
PB11
DGND
DGNDFGND
FGN
D
C94
10pF
C94
10pF
R
11047K
R
11047K
R11627RR11627R
5V D- D+ ID G
J15
USB Micro B
5V D- D+ ID G
J15
USB Micro B
123
475
6
8
9
RV1
V5.5MLA0603
RV1
V5.5MLA0603
R
V2
V5.5MLA060
3
R
V2
V5.5MLA060
3
R
11268K
R
11268K
R11427RR11427R
ADVREF
DGND
DGND
VC
C
33
+5V
JP2JP2
1
2
3
C5
100nFC5100nF
AT91SAM3SAT91SAM3S
ADVREF
1
R13
2.2K
R13
2.2K
MN2
LM
4040-2.
5
MN2
LM
4040-2.
5
plug is inserted. When closed, a 100-kOhm/1-kOhm divider pulls the ST/MN input low. When a jack plug
is inserted, the 1-kOhm resistor is disconnected and the ST/MN input is pulled high. The mono speaker
(J10 connector) is also physically disconnected from the RO/MO+ output so that no sound is heard from
the speaker while the headphones are inserted.
4.3.11USB Device
The SAM3S UDP port is compliant with the Universal Serial Bus (USB) rev 2.0 Full Speed device specification. J15 is a micro B-type receptacle for USB device.
Both 27-Ohm resistors R114 and R116 build up a 90-Ohm differential impedance together with the
(embedded) 6-Ohm output impedance of the SAM3S full speed channel drivers.
R110 and R112 build up a divider bridge from VBUS +5V to implement plug-in detection (5V level gets
lowered to a PIO compatible 3.3V level) through PC21.
Figure 4-14. USB
Evaluation Kit Hardware
4.3.12Analog Interface
4.3.12.1 Analog Reference
SAM3S-EK Development Board User Guide4-11
The 2V5 voltage reference is based on an LM4040 (Precision Micropower Shunt Voltage Reference).
This ADVREF level can be set as 2.5V or 3.3V via the jumper JP2.
Figure 4-15. Analog Vref
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
Potentiometer
AD12B5
ADC
DGND
DGND
VCC33
PB1
J
P18JP18
1
2
3
CN1
BN
C
CN1
BN
C
1
2
3
4
5
JP16JP16
VR1
10K
VR1
10K
13
2
R
96
49.9R
1%
R
96
49.9R
1%
C8
9
10nF
C8
9
10nF
R
94
0
R
R
94
0
R
C78
10
nF
C78
10
nF
SO
LDE
R DROP 2 pins open.Normal
DAC01
DAC
AU
D
IO_OUT
L
DGND
PB1
4
C90 2.2uFC90 2.2uF
JP21JP21
R10
9
49.9R 1%
R10
9
49.9R 1%
SD1SD
1
1
2
R
106
0R
R
106
0R
CN2
BN
C
CN2
BN
C
1
2
3
4
5
SD2SD2
1
2
4.3.12.2 Analog Input
The BNC connector CN1 is connected to the ADC port PB1 as an external analog input. An on-board 50Ohm resistor termination can be applied by closing jumper JP16. A low pass filter can be implemented
for the BNC connector CN1 by replacing R94 and C78 with custom resistor and capacitor values,
depending on your application requirements.
A 10-KOhm potentiometer (VR1) is also connected to this channel to implement an easy access to ADC
programming and debugging (or implement an analog user control like display brightness, volume, etc.).
Either of these two functions can be selected by jumper JP18.
Figure 4-16. ADC Input
4.3.12.3 Analog Output
The BNC connector CN2 is connected to the DAC port PB13 and provides an external analog output. An
on-board 50-Ohm resistor termination can be enabled by closing jumper JP21. A filter can be implemented on this output channel by replacing R106 and C90 with appropriate resistor and capacitor
values, depending on the application requirements.
Figure 4-17. DAC Output
4.3.13QTouch Elements
QTouch keys consist in a series of sensors formed by the association of a copper area and the capacitive effect of human fingers approaching it.
4.3.13.1 Keys
4-12SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
The SAM3S-EK implements five individual capacitive touch keys (UP, DOWN, RIGHT, LEFT and
VALID) using five pairs of PIO.
4.3.13.2 Slider
PC25
PC2
4
PC31
PC30
PC2
9
PC28
PC23
PC22
PC
27
PC
26
R
531K
R
531K
C
49
22nF
C
49
22nF
R601
K
R601
K
R511KR511K
R571KR571K
C
51
22nF
C
51
22nF
R
55
1KR
55
1K
C47
22nF
C47
22nF
K1
DNPK1DNP
C5
3
22nF
C5
3
22nF
C52
22nF
C52
22nF
PA1
PA0
PA
3
PA2
PA5
PA4
R541KR541K
R
501K
R
501K
C50
22nF
C50
22nF
C
46
22nF
C
46
22nF
S1
DNPS1DNP
SL
SM
SR
SR
R521KR521K
C
48
22nF
C
48
22nF
PB3
PC12
DGND
NRST
JP26JP26
BP1BP1
1
4
2
3
BP3BP3
1
4
2
3
JP25JP25
BP2BP2
1
4
2
3
Evaluation Kit Hardware
Figure 4-18. QST Keys
A group of channels forms a Slider. A Slider is composed of three channels for a QTouch acquisition
method using three pairs of PIO. Such a sensor is used to detect a linear finger displacement on a sensitive area. A typical implementation is volume control.
Figure 4-19. QT_Slider
4.3.14User Buttons
There are two mechanical user buttons on the SAM3S-EK, which are connected to PIO lines and defined
to be "left" and "right" buttons by default.
In addition, a mechanical button controls the system reset, signal NRST.
SAM3S-EK Development Board User Guide4-13
Figure 4-20. System Buttons
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
PA1
9
PA2
0
PC20
+
3V3
DGND
D
4Red-le
dD
4Red-le
d
R113
220
R
R113
220
R
Q
1
IRLML250
2
Q
1
IRLML250
2
1
3
2
R
115100K
R
115100K
D3Green-ledD3Green-led
R11
7
2
2
0
R
R11
7
2
2
0
R
R111
220R
R111
220R
D
2Bl
ue-ledD
2Bl
ue-led
PA2
8
PA29
PA6
PA26
PA27
PA30
PA31
DGND
+3V3
DGND
+
C25
10uF
+
C25
10uF
RA1
68KX4
RA1
68KX4
123
45
678
R18
10K
R18
10K
R
17
10K
R
17
10K
C26
100nF
C26
100nF
J
3
TF01A
J
3
TF01A
DAT2
1
DAT3
2
CMD
3
VCC
4
C
LK
5
VSS
6
DAT0
7
DAT1
8
GND
10
CD
9
Sh1
11
Sh2
12
Sh3
13
R200RR20
0R
4.3.15LEDs
There are three LEDs on the SAM3S-EK board:
A blue LED (D2) and a green LED (D3), which are user defined and controlled by the GPIO.
A red LED (D4), which is a power LED indicating that the 3.3V power rail is active. It is also controlled
by the GPIO and can be treated as a user LED as well. The only difference with the two others is that
it is controlled through a MOS transistor. By default, the PIO line is disabled; a pull-up resistor controls
the MOS to light the LED when the power is ON).
Figure 4-21. LEDs
4.3.16SD/MMC Card
The SAM3S EK has a high-speed 4-bit multimedia MMC interface, which is connected to a 4-bit
SD/MMC micro card slot featuring a card detection switch.
Figure 4-22. SD Card
4.3.17ZigBEE
SAM3S has a 10-pin male connector for the RZ600 ZigBEE module.
4-14SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
Note:0 Ohm resistors have been implemented in series with the PIO lines that are used else-
where in the design, thereby enabling their individual disconnection, should a conflict occur
in your application.
The SAM3S product features three PIO controllers, PIOA, PIOB and PIOC, which are multiplexed with
the I/O lines of the embedded peripherals. Each PIO Controller controls up to 32 lines (16 for PIOB).
Expansion ports J12, J13 and J14 provide PIO lines access for customer defined usage.
Figure 4-24. PIO Expansion
Evaluation Kit Hardware
Note:All PIO lines are available on these expansion connectors, except those that are used for
the QTouch elements.
11031C–ATARM–30-Mar-11
SAM3S-EK Development Board User Guide4-15
Evaluation Kit Hardware
4.4Configuration
This section describes the PIO usage, the jumpers, the test points and the solder drops of a SAM3S-EK
board.
4.4.1PIO Usage
Table 4-1. PIO Port A Pin Assignments and Signal Descriptions
JP10RS485OPENMaintain differential impedance for RS485 interface
JP11RS485CLOSEMaintain impedance matching for RS485 interface
JP12RS485OPENMaintain differential impedance for RS485 interface
JP13CSCLOSENCS1 chip select LCD
JP14 - JP15MIC GAIN0
JP16ADC inputOPENClose for impedance matching on ADC BNC port
JP17 – JP19MIC Gain stage Close to mux RIN/LIN into MONO-IN path within audio PA
JP18 SELECT ADC INP
JP20MONO/STEREOCLOSEClose to fix in mono speaker, no matter the stereo plug state
JP21DAC outputOPENClose for impedance matching on DAC BNC port
Not populated
(OPEN)
CLOSE (both) 20db
OPEN (both) 26db
1-2
2-3
Analog reference voltage selection between 3.3V (close 1-2) and
2.5V (close 2-3)
Close for manufacturing test or fast programming mode
Close both to lower gain stage on microphone input.
ADC input potentiometer
ADC input BNC
JP22
JP23
JP24
JP25BP2CLOSEOpen to disconnect and free PB3 for custom usage
JP26BP3CLOSEOpen to disconnect and free PC12 for custom usage
JP27ZIGBEECLOSE
SAM3S-EK Development Board User Guide4-19
PIO expansion J12
voltage supply
PIO expansion J13
voltage supply
PIO expansion J14
voltage supply
2-3Set to 3.3V (position 1-2 sets to 5V)
2-3Set to 3.3V (position 1-2 sets to 5V)
2-3Set to 3.3V (position 1-2 sets to 5V)
Power supply connection/disconnection for the ZigBEE module
May also be used as a current measurement point
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
Table 4-5. Audio Input Configuration
JP17JP19MONO-STEREO INPUT
OFFOFFPIN test point (TP12)
OFFONLeft-in only
4.4.3Test Points
Some test points have been placed on the SAM3S-EK board for the verification of important signals.
Table 4-6. Test Points
DesignationPartDescription
TP1Ring HookGND
TP2Ring HookGND
TP3Ring HookGND
TP4Ring HookGND
ONOFFRight-in only
ONONSum of Left-in and Right-in
TP5PadUART TXD
TP6PadUART RXD
TP7Pad LCD Backlight driver anode
TP8PadAux ADC input for Touch Screen controller
TP9PadAux ADC input for Touch Screen controller
TP10Ring Hook+5V
TP11Ring Hook+3V3
TP12PadOptional Audio PA input
4.4.4Solder Drops
There are two solder drops designed on the SAM3S-EK for isolation.
Table 4-7. Solder Drops
DesignationDefault SettingFeature
SD1OPENIsolation of DAC output from shared channel (PB14)
SD2CLOSEConnects PB14 to the AUDIO_OUTL channel
4.4.5Assigned PIO Lines, Disconnection Possibility
As pointed out in some previous interface description, 0 Ohm resistors have been inserted on the path of
the receiver PIO lines of the SAM3S-EK. These are the PIO lines connected to an external driver on the
board. The 0 Ohm resistors allow disconnecting each of these for custom usage (through PIO expansion
connectors for example). This feature gives the user an added level of versatility for prototyping a system
of his own. See the table below.
4-20SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
Table 4-8. Disconnecting Possibility
DesignationDefault Assignment PIO
R190RPC18, RDY/BSY on NAND Flash
R200RPA29
R22DNPOptional write protection on NAND Flash
R250RPA21
R260RPA25
R270RPA24
R280RPA22
R310RPA23
R330RPA22
R340RPA21
R350RPA24
R360RPA25
R440RNRST
R470RPA9
Evaluation Kit Hardware
R480RR2OUT/MN5
R590RLCD backlight LED anode
R660RPA11
R670RPA5
R680RPC13
R690RPA4
R700RVref TSC
R1180RPA3 ZB_RSTN
R1190RPA5 IRQ1_ZBEE
R1200RPA4 IRQ0_ZBEE
R1210RPA6 SLP_TR
Table 4-9. Default Not Populated Parts
ReferenceFunction
J1, R1External clock resource input
Y1, R3, R7Backup 12 MHz crystal
R6, R8Isolation on 12 MHZ clock source and GPIO expansion
R9, R10Isolation on 32 KHz clock source and GPIO expansion
R22Optional write protection NAND Flash
R23Optional pull-up for open drain output or equivalent device
R24, R30Differential impedance matching for RS485 cable
SAM3S-EK Development Board User Guide4-21
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
Table 4-9. Default Not Populated Parts
ReferenceFunction
D1Optional ESD protection for LCD touch panel
R61, R63, RA2, RA3Optional data bus termination for LCD controller
JP4Test mode selection for the SAM chip
J2Optional QFP socket for the SAM3 chip
K1Virtual component for QTouch keys set - implemented as copper areas
S1Virtual component for QTouch slider set - implemented as copper areas
TPxxSurface-mounted test points (copper area)
4.5Connectors
4.5.1Power Supply Connector J9
The SAM3S-EK evaluation board can be powered from a 5VDC power supply connected to the external
power supply jack J9. The positive pole is the center pin.
Figure 4-25. Power Supply Connector J9
Table 4-10. Power Supply Connector J9 Signal Descriptions
PinMnemonicSignal Description
1Center+5vcc
2GndGround reference
4.5.2USART Connector J5 With RTS/CTS Handshake Support
Figure 4-26. Male RS232/USART Connector J5
4-22SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
Table 4-11. Serial COM1 Connector J5 Signal Descriptions
PinMnemonicSignal Description
1, 4, 6, 9NCNO CONNECTION
2TXD TRANSMITTED DATARS232 serial data output signal
3RXD RECEIVED DATARS232 serial data input signal
5GNDGROUND
7RTS READY TO SENDActive-positive RS232 input signal
8CTS CLEAR TO SENDActive-positive RS232 output signal
4.5.3UART Connector J7
Male RS232/UART connector J7
Evaluation Kit Hardware
Table 4-12. Male RS232/UART Connector J7 Signal Descriptions
PinMnemonicSignal Description
1, 4, 6, 7, 8, 9NCNO CONNECTION
2TXD TRANSMITTED DATARS232 serial data output signal
3RXD RECEIVED DATARS232 serial data input signal
5GNDGROUND
4.5.4USB Device Connector J15
Figure 4-27. Micro-B USB Connector J15
Table 4-13. Micro-B USB Connector J15 Signal Descriptions
PinMnemonicSignal Description
1Vbus5v power
2DMData -
3DPData +
4GndGround
5ShieldShield
SAM3S-EK Development Board User Guide4-23
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
4.5.5TFT LCD Connector J8
One 39-pin connector is available on the board to connect the LCD module, backlight and touch screen.
Figure 4-28. LCD Connector J8
Table 4-14. LCD Connector J8 Signal Descriptions
PinMnemonicPinMnemonic
13V32LCD_DB17 (PC7)
3LCD_DB16 (PC6)4LCD_DB15 (PC5)
5LCD_DB14 (PC4)6LCD_DB13 (PC3)
7LCD_DB12 (PC2)8LCD_DB11 (PC1)
9LCD_DB10 (PC0)10LCD_DB09 (NC)
11LCD_DB08 (NC)12LCD_DB07
13LCD_DB06 (NC)14LCD_DB05 (NC)
15LCD_DB04 (NC)16LCD_DB03 (NC)
17LCD_DB02 (NC)18LCD_DB01 (NC)
19LCD_DB00 (NC)203V3
21RD (PC11)22WR (PC8)
23RS (PC19)24CS (PC15)
25RESET26IM0
27IM128GND
29LED-A30LED-K1
31LED-K232LED-K3
33LED-K434Y UP
35Y DOWN36X RIGHT
37X LEFT38NC
39GND
4-24SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
4.5.6JTAG Debugging Connector J6
This JTAG connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm
male) that mates with IDC sockets mounted on a ribbon cable. Its signal assignment is compatible with
the SAM-ICE or any similar third-party interface.
Figure 4-29. JTAG/ICE Connector J6
Table 4-15. JTAG/ICE Connector J13 Signal Descriptions
PinMnemonicDescription
This is the target reference voltage. It is used to check if the target has power, to
1VTref. 3.3V power
create the logic-level reference for the input comparators and to control the output
logic levels to the target. It is normally fed from Vdd on the target board and must
not have a series resistor.
Evaluation Kit Hardware
2Vsupply. 3.3V power
nTRST TARGET RESET — Active-low
3
4GNDCommon ground
5
6GNDCommon ground
7TMS TEST MODE SELECT –
8GND Common ground
9
10GNDCommon ground
11
12GNDCommon ground
output signal that resets the target
TDI TEST DATA INPUT — Serial data
output line, sampled on the rising edge
of the TCK signal
TCK TEST CLOCK — Output timing
signal, for synchronizing test logic and
control register access
RTCK
Input Return test clock signal from the
target
This pin is not connected in SAM-ICE. It is reserved for compatibility with other
equipment. Connect to Vdd or leave open in target system.
JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port.
Typically connected to nTRST on the target CPU. This pin is normally pulled
HIGH on the target to avoid unintentional resets when there is no connection.
JTAG data input of target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TDI on target CPU.
JTAG mode set input of target CPU. This pin should be pulled up on the target.
Typically connected to TMS on target CPU. Output signal that sequences the
target’s JTAG state machine, sampled on the rising edge of the TCK signal.
JTAG clock signal to target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TCK on target CPU.
Some targets must synchronize the JTAG inputs to internal clocks. To assist in
meeting this requirement, a returned and retimed TCK can be used to
dynamically control the TCK rate. SAM-ICE supports adaptive clocking which
waits for TCK changes to be echoed correctly before making further changes.
Connect to RTCK if available, otherwise to GND.
13
14GNDCommon ground
SAM3S-EK Development Board User Guide4-25
TDO JTAG TEST DATA OUTPUT —
Serial data input from the target
JTAG data output from target CPU. Typically connected to TDO on target CPU.
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
Table 4-15. JTAG/ICE Connector J13 Signal Descriptions (Continued)
PinMnemonicDescription
15nSRST RESET — Active-low reset signal. Target CPU reset signal
16GNDCommon ground
17RFUThis pin is not connected in SAM-ICE.
18GNDCommon ground
19RFUThis pin is not connected in SAM-ICE.
20GNDCommon ground
4.5.7SD/MMC - MCI Connector J3
Figure 4-30. SD/MMC Connector J3
Table 4-16. SD/MMC Connector J3 Signal Descriptions
PinMnemonicPinMnemonic
1RSV/DAT32CDA
3GND4VCC
5CLK6GND
7D AT 08DAT 1
9DAT210Card Detect
11GND12
4-26SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
4.5.8Analog Connector CN1 & CN2
Figure 4-31. Analog Input Connector CN1 and Analog Output CN2, Bottom View
Table 4-17. Analog Input, Output Connector CN1, CN2 Signal Descriptions
PinMnemonic
1, 2, 3, 4 GND
5Analog input PB1 for CN1 and analog output PB13 for CN2 respectively
4.5.9RS485 Connector J14
Evaluation Kit Hardware
Figure 4-32. RS485 Connector J14
Table 4-18. RS485 J14 Signal Descriptions
PinMnemonic
1A - non-inverted RS485 signal A
2Frame ground
3B - non-inverted RS485 signal B
SAM3S-EK Development Board User Guide4-27
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
4.5.10Headphone Connector J11
Figure 4-33. Headphone J11
Table 4-19. Headphone J11 Signal Descriptions
PinMnemonic
1AGND
2Out left
3
4
5Out Right
4.5.11ZigBEE Connector J16
Figure 4-34. ZigBee Connector J16
Table 4-20. Connector J16 Signal Descriptions
Signal
Function
Reset/RST12Misc.
Interrupt
Request
NamePortPinPinPort
IRQ34SLP_TRSLP_TR
Signal
NameFunction
Option on Misc. Port Set by
Zero Ohm Resistor or Solder Shunts
EEPROM for MAC address, CAP array
settings and serial number
TST: test mode activation
CLKM: RF chip clock output
SPI chip
select
SPI MISOMISO78SCLKSPI CLK
Power
Supply
4-28SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
/SEL56MOSISPI MOSI
GNDGND910VCCVCCVCC
Voltage range: 1.8v to 5.5v, typically
regulated to 3.3v
4.5.12PIO Expansion Port C Connector J12
Figure 4-35. PIO Expansion Connector J12
Table 4-21. Connector J12 Signal Descriptions
PinMnemonicPinMnemonic
1+5V or +3v32+5V or +3v3
3GND4GND
5PC06PC16
7PC18PC17
9PC210PC18
11PC312PC19
13PC414PC20
Evaluation Kit Hardware
15PC516PC21
17PC618NC
19PC720NC
21PC822NC
23PC924NC
25PC1026NC
27PC1128NC
29PC1230NC
31PC1332NC
33PC1434NC
35PC1536NC
37GND38GND
393V3403V3
SAM3S-EK Development Board User Guide4-29
11031C–ATARM–30-Mar-11
Evaluation Kit Hardware
4.5.13PIO Expansion Port A Connector J13
Figure 4-36. PIO Expansion Connector J13
Table 4-22. Connector J13 Signal Descriptions
PinMnemonicPinMnemonic
1+5V or +3v32+5V or +3v3
3GND4GND
5NC6PA16
7NC8PA17
9NC10PA18
11NC12PA19
13NC14PA20
15NC16PA21
17PA618PA22
19PA720PA23
21PA822PA24
23PA924PA25
25PA1026PA26
27PA1128PA27
29PA1230PA28
31PA1332PA29
33PA1434PA30
35PA1536PA31
37GND38GND
393V3403V3
4-30SAM3S-EK Development Board User Guide
11031C–ATARM–30-Mar-11
4.5.14PIO Expansion Port B Connector J14
Figure 4-37. PIO Expansion Connector J14
Table 4-23. Connector J14 Signal Descriptions
PinMnemonicPinMnemonic
1+5V or +3v32+5V or +3v3
3GND4GND
5PB06PB8
7PB18PB9
9PB210PB10
11PB312PB11
13PB414PB12
Evaluation Kit Hardware
15PB516PB13
17PB618PB14
19PB720NC
21GND22GND
233V3243V3
SAM3S-EK Development Board User Guide4-31
11031C–ATARM–30-Mar-11
5.1Schematics
This section contains the following schematics:
Block diagram
General information
Microcontroller
NAND Flash, serial interface
TFT LCD & Touch
Audio & Power Supply
USB, LEDs, push-buttons & ZigBEE
Section 5
Schematics
SAM3S-EK Development Board User Guide5-1
11031C–ATARM–30-Mar-11
5
4
3
2
1
SAM3S-EK RevB Block Diagram
DD
ATMEL Cortex M3 Processor SAM3S (LQFP100)
Reset,Debug Logic
CC
Audio PA
Microphone
USB FS Device
BB
RS232 & RS485
AD/DA
Power Manage
2.8 Inch TFT-LCD
MicroSD Card
Nand Flash
QTouch Input
ZIGBEE IF
AA
BPP26-NOV-09
BPP26-NOV-09
User Interface (PIO PortA,B,C)
SAM3S-EK
SAM3S-EK
SAM3S-EK
Block Diagram
Block Diagram
Block Diagram
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This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
2
BPP26-NOV-09
INIT EDIT
INIT EDIT
INIT EDIT
A
A
A
REV
REV
REV
SCALE
SCALE
SCALE
1/1
1/1
1/1
DES.
DES.
DES.
XX-XXX-XX
XX-XXX-XX
XX-XXX-XX
DATE
DATE
DATE
1
XX-XXX-XXNLXXX
XX-XXX-XXNLXXX
XX-XXX-XXNLXXX
DATEMODIF.
VER.
DATEMODIF.
VER.
DATEMODIF.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
1
1
1
B
B
B
7
7
7
5
4
3
2
1
REVISION HISTORY
REVDATA
DD
A
2009.07ORIGINAL RELEASED
B2009.11UPDATED
NOTE
SCHEMATICS CONVENTIONS
(1) Resistance Unit: "K" is "Kohm", "R" is "Ohm¸"
(2) "DNP" means the component is not populated
by default
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This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SCALE
1/1
1/1
1/1
26-NOV-09PPB
XX-XXX-XX
XX-XXX-XX
XX-XXX-XX
DES.
DATE
DES.
DATE
DES.
DATE
1
XX-XXX-XXNLXXX
XX-XXX-XXNLXXX
XX-XXX-XXNLXXX
DATEMODIF.
VER.
DATEMODIF.
VER.
DATEMODIF.
VER.
REV. SHEET
REV. SHEET
REV. SHEET
7
7
7
B
B
B
7
7
7
6.1Self-Test
A test package software is available to implement a functional test for each section of the board. Refer to
the SAM3S-EK page on www.atmel.com.
6.2Board Recovery
Closing JP3 and powering the board will assert ERASE and clear GPNVM bit 1, and thereby selects the
boot from the ROM by default. The MCU will boot from the internal ROM to enable a SAM-BA connection
through the UART. Connect the SAM3S-EK UART port (J3) to a PC COM port through an RS232 crossover cable.
You can then run the SAM-BA application from that PC to program the internal Flash of the MCU as well
as the GPNVM bit 1.
Section 6
Troubleshooting
SAM3S-EK Development Board User Guide6-1
11031C–ATARM–30-Mar-11
7.1Revision History
Table 7-1.
DocumentComments
Section 7
Revision History
Change Request
Ref.
11031CNote 2 added to
11031BA note added at the end of
11031AFirst issue.
Section 4.3.9 ”JTAG/ICE”7637
Section 4.3.4, ” Reset Circuitry”.7565
SAM3S-EK Development Board User Guide7-1
11031C–ATARM–30-Mar-11
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