Atmel SAM3S-EK User guide

SAM3S-EK Development Board

....................................................................................................................

User Guide

11031C–ATARM–30-Mar-11

Section 1

Introduction.................................................................................................................1-1

1.1 SAM3S Evaluation Kit ........................................................................................................ 1-1

1.2 User Guide ......................................................................................................................... 1-1

1.3 References and Applicable Documents ............................................................................. 1-1

Section 2

Kit Contents ................................................................................................................2-1

2.1 Deliverables ....................................................................................................................... 2-1

2.2 Electrostatic Warning ......................................................................................................... 2-2

Section 3

Power Up....................................................................................................................3-1

3.1 Power up the Board ...........................................................................................................3-1

3.2 DevStart ............................................................................................................................. 3-1

3.3 Recovery Procedure .......................................................................................................... 3-1

3.4 Sample Code and Technical Support ................................................................................ 3-1

Section 4

Evaluation Kit Hardware .............................................................................................4-1

4.1 Board Overview.................................................................................................................. 4-1

4.2 Features List ...................................................................................................................... 4-2

4.3 Function Blocks.................................................................................................................. 4-2

4.3.1 Processor............................................................................................................. 4-2

4.3.2 Memory................................................................................................................ 4-2

4.3.3 Clock Circuitry...................................................................................................... 4-3

4.3.4 Reset Circuitry ..................................................................................................... 4-4

4.3.5 Power Supply and Management.......................................................................... 4-4

4.3.6 UART ................................................................................................................... 4-5

4.3.7 USART................................................................................................................. 4-5

4.3.8 Display Interface .................................................................................................. 4-6

4.3.9 JTAG/ICE............................................................................................................. 4-8

4.3.10 Audio Interface..................................................................................................... 4-9

4.3.11 USB Device ....................................................................................................... 4-10

4.3.12 Analog Interface ................................................................................................ 4-11

4.3.13 QTouch Elements .............................................................................................. 4-12

4.3.14 User Buttons ...................................................................................................... 4-13

4.3.15 LEDs .................................................................................................................. 4-13

4.3.16 SD/MMC Card ................................................................................................... 4-14

4.3.17 ZigBEE............................................................................................................... 4-14

4.3.18 PIO Expansion ................................................................................................... 4-14

SAM3S-EK Development Board User Guide 1-1

11031C–ATARM–30-Mar-11

4.4 Configuration.................................................................................................................... 4-15

4.4.1 PIO Usage ......................................................................................................... 4-15

4.4.2 Jumpers ............................................................................................................. 4-19

4.4.3 Test Points ......................................................................................................... 4-20

4.4.4 Solder Drops ...................................................................................................... 4-20

4.4.5 Assigned PIO Lines, Disconnection Possibility.................................................. 4-20

4.5 Connectors....................................................................................................................... 4-22

4.5.1 Power Supply Connector J9 .............................................................................. 4-22

4.5.2 USART Connector J5 With RTS/CTS Handshake Support ............................... 4-22

4.5.3 UART Connector J7 .......................................................................................... 4-23

4.5.4 USB Device Connector J15 ............................................................................... 4-23

4.5.5 TFT LCD Connector J8...................................................................................... 4-24

4.5.6 JTAG Debugging Connector J6 ......................................................................... 4-24

4.5.7 SD/MMC - MCI Connector J3 ............................................................................ 4-27

4.5.8 Analog Connector CN1 & CN2 .......................................................................... 4-27

4.5.9 RS485 Connector J14 ....................................................................................... 4-28

4.5.10 Headphone Connector J11 ................................................................................ 4-28

4.5.11 ZigBEE Connector J16 ...................................................................................... 4-28

4.5.12 PIO Expansion Port C Connector J12 ............................................................... 4-29

4.5.13 PIO Expansion Port A Connector J13 .............................................................. 4-30

4.5.14 PIO Expansion Port B Connector J14 ............................................................... 4-31

Section 5

Schematics .................................................................................................................5-1

5.1 Schematics......................................................................................................................... 5-1

Section 6

Troubleshooting..........................................................................................................6-1

6.1 Self-Test............................................................................................................................. 6-1

6.2 Board Recovery ................................................................................................................. 6-1

Section 7

Revision History..........................................................................................................7-1

7.1 Revision History ................................................................................................................. 7-1

1-2 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

1.1 SAM3S Evaluation Kit

The SAM3S Evaluation Kit (SAM3S-EK) enables evaluation capabilities and code development of applications running on a SAM3S4C device.

1.2 User Guide

This guide focuses on the SAM3S-EK board as an evaluation platform. It is made up of 6 sections:

 Section 1 includes references, applicable documents, acronyms and abbreviations.

 Section 2 describes the kit contents, its main features and specifications.

 Section 3 provides board specifications.

 Section 4 describes the development environment.

 Section 5 provides instructions to power up the SAM3S-EK and describes how to use it.

 Section 6 describes the hardware resources, default jumper and switch settings, and connectors.

 Section 7 provides schematics.

 Section 8 describes the troubleshooting.

Section 1

Introduction

1.3 References and Applicable Documents

Table 1-1. References and Applicable Documents

Title Comment

SAM3S Datasheet

SAM3S-EK Development Board User Guide 1-1

http://www.atmel.com/dyn/products/datasheets.asp?family_id=605#2127

11031C–ATARM–30-Mar-11

2.1 Deliverables

The Atmel® SAM3S-EK toolkit contains the following items:

 Board:

– a SAM3S-EK board

– a universal input AC/DC power supply with US, Europe and UK plug adapters

 Cables:

– one USB cable

– one serial RS232 cable

 A Welcome Letter

Figure 2-1. Unpacked SAM3S-EK

Section 2

Kit Contents

Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit.

SAM3S-EK Development Board User Guide 2-1

11031C–ATARM–30-Mar-11

Kit Contents

2.2 Electrostatic Warning

The SAM3S-EK board is shipped in a protective anti-static package. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the components or any other metallic element of the board.

2-2 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

3.1 Power up the Board

Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country, and insert it in the power supply.

Connect the power supply DC connector to the board and plug the power supply to an AC power plug.

The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the screen and enjoy the demo.

3.2 DevStart

The on-board NAND Flash contains “SAM3S-EK DevStart”.

It is stored in the “SAM3S-EK DevStart” folder on the USB Flash disk available when the SAM3S-EK is connected to a host computer and you click on the Flash Disk icon of the on-board demo.

Click the file “welcome.html” in this folder to launch SAM3S-EK DevStart.

Section 3

Power Up

SAM3S-EK DevStart guides you through installation processes of IAR™ EWARM, Keil MDK and GNU toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and how to program it into the SAM3S-EK. Optionally, if you have a SAM-ICE™, instructions are also given about how to debug the code.

We recommend that you backup the “SAM3S-EK DevStart” folder on your computer before launching it.

3.3 Recovery Procedure

The DevStart ends by giving step-by-step instructions on how to recover the SAM3S-EK to the state as it was when shipped by Atmel.

Follow the instructions if you deleted the contents of the embedded Flash or the NAND Flash and want to recover from this situation.

SAM3S-EK Development Board User Guide 3-1

11031C–ATARM–30-Mar-11

Power Up

3.4 Sample Code and Technical Support

After boot up, you can run some sample code or your own application on the development kit. You can download sample code and get technical support from Atmel website

http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4678

Figure 3-1. Atmel Website for AT91SAM Products

3-2 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

4.1 Board Overview

This section introduces the Atmel SAM3S Evaluation Kit design. It introduces system-level concepts, such as power distribution, memory, and interface assignments.

The SAM3S-EK board is based on the integration of an ARM NAND Flash and a set of popular peripherals. It is designed to provide a high performance processor evaluation solution with high flexibility for various kinds of applications.

Figure 4-1. SAM3S-EK Block Diagram

Section 4

Evaluation Kit Hardware

®

Cortex®-M3 processor with on-board

SAM3S-EK Development Board User Guide 4-1

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

4.2 Features List

Here is the list of the main board components and interfaces:

 SAM3S4C chip LQFP100 package with optional socket footprint

 12 MHz crystal

 32.768 KHz crystal

 Optional SMB connector for external system clock input

 NAND Flash

 2.8 inch TFT color LCD display with touch panel and backlight

 UART port with level shifter circuit

 USART port with level shifter circuit multiplexed with RS485 port with level shifter circuit

 Microphone input and mono/stereo headphone jack output

 SD/MMC interface

 Reset button: NRST

 User buttons: Left and Right

 QTouch

 Full Speed USB device port

 JTAG/ICE port

 On-board power regulation

 Two user LEDs

 Power LED

 BNC connector for ADC input

 BNC connector for DAC output

 User potentiometer connected to the ADC input

 ZigBEE connector

 2x32 bit PIO connection interfaces (PIOA, PIOC) and 1x16 bit PIO connection interface (PIOB)

®

buttons: Up, Down, Left, Right, Valid and Slider

4.3 Function Blocks

4.3.1 Processor

The SAM3S-EK is equipped with a SAM3S4C device in LQFP100 package.

4.3.2 Memory

The SAM3S4 chip embeds:

 256 Kbytes of embedded Flash

 48 Kbytes of embedded SRAM

 16 Kbytes of ROM with embedded BootLoader routines (UART, USB) and In-Application Programming

functions (IAP) routines.

4-2 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

MT29F2G08AADWP

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PC10

PC9

PC16

PC17

PC1

8

PC1

4

+

3V3

DGND

+3V3

DGND

+3V3

+3

V3

PC[0..31

]{3,5,7

}

MN3MN3

W

E

18

N.C

6

VCC

37

CE

9

RE

8

N.C11

20

W

P

1

9

N.C

5

N.C1

1

N.C2

2

N.C3

3

N.C

4

N.C12

2

1

N.C

13

2

N.C14

23

N.C15

24

R

/B

7

N.C17

26

N

.C18

27

N

.C19

28

I/O0

29

N

.C21

34

N

.C22

35

VSS

3

6

PR

E

3

8

N.C2

3

9

VCC

12

VSS

1

3

AL

E

17

N.C

8

11

N.C

7

1

0

N.C9

14

N.C10

15

CLE

16

N.C16

25

N

.C20

33

I/O1

30

I/O3

32

I/O2

31

N.C2

7

47

N.C2

6

46

N.C2

5

4

5

I/O7

44

I/O6

4

3

I/O5

42

I/O4

41

N.C2

4

0

N

.C28

48

C2

7

100nF

C2

7

100nF

R15 47K

R2147KR2147K

R1

6

47K

R1

6

47K

C29 1uF

R190

R

R190

R

R22 DN

P

R22 DN

P

JP9J

P9

C

28

100nF

C

28

100nF

NOT POPULATE

D

NP

XOUT32

XIN32

XIN

32

XOUT32

PA7 PA8

XIN

XO

UT

PB8

PB9

DGND

DG

ND

DGND

R

3 DNP

R

3 DNP

R6 DN

P

R6 DN

P

R

9D

NPR

9D

NP

R1 DNPR1 DNP

C

3

20pF

C

3

20pF

R40RR40R

C4 20pFC420pF

R2

49.9R 1%R249.9R 1%

Y1Y1

12

3

R8 DN

P

R8 DN

P

R

7DN

PR

7DN

P

AT91SAM3S

MN1

AT91SAM3S

MN1

PA7_RTS0_PWMH3

49

PA8_CTS0_AD

12BTRG

4

8

PB8_XO

U

T

96

PB9_XIN

97

R1

1

0R

R1

1

0R

Y

212MHz

Y

212MHz

C

120pF

C

120pF

R10DNPR10DNP

Y3

32.768KHz

Y3

32.768KHz

12

3

R50

R

R50

R

R12 0

R

R12 0

R

J1J1

1

2 3

54

C

220pF

C

220pF

The SAM3S features an External Bus Interface (EBI) that permits interfacing to a broad range of external memories and virtually to any parallel peripheral. The SAM3S-EK board is equipped with a memory device connected to the SAM3 EBI:

 One NAND Flash MT29F2G08AADWP.

Figure 4-2. NAND Flash

NCS0 chip select signal is used for NAND Flash chip selection. Furthermore, a dedicated jumper can disconnect it from the on-board memories, thereby letting NCS0 free for other custom purpose.

4.3.3 Clock Circuitry

The clock generator of a SAM3S microcontroller is made up of:

 A Low Power 32.768 Hz Slow Clock Oscillator with bypass mode.

 A 3 to 20 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB).

 A factory programmed fast internal RC Oscillator. 3 output frequencies can be selected: 4 (default

value), 8 or 12 MHz.

 A 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller.

 A 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and

to the peripherals. The input frequency of PLLA is from 7.5 and 20 MHz.

The SAM3S-EK board is equipped with one 12 MHz crystal, optional Piezoelectric Ceramic Resonator 12 Mhz (Murata ref. CSTCE12M0G15L99-R0), one 32.768 Hz crystal and an external clock input connector (optional, not populated by default).

Figure 4-3. External Clock Source

SAM3S-EK Development Board User Guide 4-3

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

DGND

+

5V

+5V +3V3

C75 100uF

+

C75 100uF

C65 22uF

+

C65 22uF

C64 100nF

MN10 BN

X002-01

MN10 BN

X002-01

SV

1

SG

2

C

V

3

CG

1

4

CG2

5

CG3

6

C76 100nF

C66 22u

F

+

C66 22u

F

MN9 ZEN056V130A24LS

1

2

3

R92 102K

1%

R92 102K

1%

MN12 MIC29152WU

Mic

rel's 1.5A LDO, TO263-5

MN12 MIC29152WU

Mic

rel's 1.5A LDO, TO263-5

VI

N

2

VOUT

4

SD

1

GND1

3

ADJ

5

GND2

6

R89 169K 1%

J9

MP179P 2.1mm

J9

MP179P 2.1mm

1 2

3

The SAM3S chip internally generates the following clocks:

 SLCK, the Slow Clock, which is the only permanent clock of the system

 MAINCK, the output of the Main Clock Oscillator selection: either a Crystal Oscillator or a 4/8/12 MHz

Fast RC Oscillator

 PLLACK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLA)

 PLLBCK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLB)

4.3.4 Reset Circuitry

On-board NRST button BP1 provides an external reset control of the SAM3S.

The NRST pin is bidirectional. It is handled by the on-chip reset controller. It can be driven low to provide a reset signal out to the external components. Conversely, it can be asserted low from the outside to reset the microcontroller Core and the peripherals. The NRST pin integrates a permanent pull-up resistor of about 100 kOhm to VDDIO.

On the SAM3S-EK board, the NRST signal is connected to the LCD module and JTAG port.

Note: At power-on, the NRST signal is asserted with a default duration of 2 clock cycles. That duration may not be

sufficient to correctly reset any other system or board devices connected to that signal. First, in your custom application, you need to check for these devices' datasheets about reset duration requirements. Then, you need to set an appropriate configuration in the NRST Manager. This is done through the ERSTL field in the RSTC_MR register. The NRST duration is thereby configurable between 60 µs and 2 s, whether it is subsequently activated by a software reset or a user reset. Refer to the SAM3S datasheet for in depth information.

4.3.5 Power Supply and Management

The SAM3S-EK board is supplied with an external 5V DC block through input J9. It is protected by a PolyZen diode MN9 and an LC combinatory filter MN10. The PolyZen is used in the event of an incorrect power supply connection.

The adjustable LDO regulator MN12 is used for the 3.3V rail main supply. It powers all the 3.3V components on the board.

Figure 4-4. Power Block

The SAM3S4/2/1 product series has different types of power supply pins:

 VDDIN pin:

Power for the internal voltage regulator, ADC, DAC, and analog comparator power supplies. The voltage ranges from 1.8V to 3.6V.

4-4 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

4.3.6 UART

+3V3

D

GND

DGND

+

3V3

+3V3

FGND

PA10 PA9

C3

9

100nF

C3

9

100nF

C40 100nF

T

P5

SMD

T

P5

SMD

J7J7

5

4

3

2

1

9

8

7

6

10

11

R46 100

K

R46 100

K

C38 100nF

TP6 SM

D

TP6 SM

D

C41 100nF

R470

R

R470

R

R480

R

R480

R

C42 100nF

MN6 MAX3232CSE

T1

IN

1

T2

IN

1

0

R1O

UT

1

2

R2O

UT

9

T1OUT

1

4

T2OUT

7

R1IN

1

3

R2I

N

8

V+

2

C1+

1

C1-

3

C2+

4

C2-

5

V-

6

VCC

16

GND

1

5

R

45

100K

R

45

100K

Evaluation Kit Hardware

 VDDIO pins:

Power for the Peripherals I/O lines. The voltage ranges from 1.62V to 3.6V.

 VDDOUT pin:

Output of the internal voltage regulator.

 VDDCORE pins:

Power for the core, including the processor, embedded memories and peripherals. The voltage ranges from 1.62V to 1.95V.

 VDDPLL pin:

Power for the PLL A, PLL B and 12 MHz oscillator. The voltage ranges from 1.62V to 1.95V.

Note: VDDPLL should be decoupled and filtered from VDDCORE.

The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes. It offers an ideal channel for in-situ programming solutions. This UART is associated with two PDC channels to reduce the processor time on packet handling.

This two-pin UART (TXD and RXD only) is buffered through an RS232 Transceiver MN6 and brought to the DB9 male connector J7.

4.3.7 USART

Figure 4-5. UART

The Universal Synchronous/Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous/asynchronous serial link. The data frame format is extensively configurable (data length, parity, number of stop bits) to support a broad range of serial communication standards. The USART is also associated with PDC channels for TX/RX data access.

Note: For design optimization purposes, both transmitters have been implemented on the same

PIO lines, that is PA21, 22, 23, 24 25.

To avoid any electrical conflict, the RS485 transceiver is isolated from the receiving line PA21.

SAM3S-EK Development Board User Guide 4-5

Should you need to implement an RS485 channel in place of the RS232, follow the procedure below:

1. make sure your software will permanently set PA23 to a high level - this will permanently disable the

2. solder a shunt resistor in place of R25 (a solder drop will do).

RS232 receiver.

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

PA2

5

PA2

4

PA2

1

PA2

2

PA23

F

GND

DGND

+3V3

DGND

+

3V3

+

3V3

DGND

R360

R

R360

R

C3

4

100nF

C3

4

100nF

C35 100nF

C36 100nF

R3

2

47K

R3

2

47K

MN5 ADM3312EAR

U

MN5 ADM3312EAR

U

C1+

6

C1-

2

0

C2+

2

C2-

4

C3

+

24

C3-

22

VC

C

3

V

+

1

V-

2

1

GND

23

SD

19

EN

5

T1I

N

7

T1OU

T

18

R1IN

15

R1OU

T

10

T2I

N

8

T

2OU

T

17

R2IN

14

R2OU

T

11

T3I

N

9

T

3OU

T

16

R3IN

13

R3O

UT

1

2

R38 0RR38 0R

C31 4

.7u

F

C31 4

.7u

F

C32 1

00nF

C32 1

00nF

R350

R

R350

R

C37 100nF

C3

3

100nF

C3

3

100nF

J5J5

5

4

3

2

1

9

8

7

6

10

11

R340

R

R340

R

R33 0RR33 0R

R310RR310R

R3747KR3747K

PA2

2

PA2

4

PA2

5

PA2

1

PA2

3

DGND

+3V3

+3V3 +3V3

DGND

FGND

MN4 ADM3485AR

Z

MN4 ADM3485AR

Z

R

O

1

R

E

2

D

E

3

D

I

4

VCC

8

G

ND

5

A

6

B

7

R28

0

R

R28

0

R

R3

0

DNP

R3

0

DNP

J4J4

1

2

3

R29 120

R

R29 120

R

C30 100nF

R26

0

R

R26

0

R

JP11JP11JP12JP12

JP10JP1

0

R27

0

R

R27

0

R

R23 D

N

P

R23 D

N

P

R25

DN

P

R25

DN

P

R24 D

N

P

R24 D

N

P

4.3.7.1 RS232

SAM3S-EK connects the USART1 bus (including TXD, RXD, RTS, CTS handshake signal controls and EN command) to the DB9 male connector J5 through the RS232 Transceiver MN5.

Figure 4-6. USART

4.3.7.2 RS485

As noticed above, the USART1 is shared with the RS485 port, connected to the transceiver MN4, connected to the 3-point connector J4. The design includes selectable jumpers for RS485 bus termination resistors selection (JP10, JP11, JP12).

Figure 4-7. RS485

4.3.8 Display Interface

The SAM3S-EK carries a TFT Transmissive LCD module with touch panel, FTM280C34D. Its integrated driver IC is ILI9325. The LCD display area is 2.8 inches diagonally measured, with a native resolution of 240 x 320 dots.

The LCD module gets reset from the NRST signal. As explained, this NRST is shared with the JTAG port and the push-button BP1. The LCD chip select signal is connected to NCS1; the jumper JP13 can disconnect it so that this PIO line is available for other custom usage.

The SAM3S communicates with the LCD through PIOC where an 8-bit parallel “8080-like” protocol data bus has to be implemented by software.

4.3.8.1 LCD Module

4-6 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

Figure 4-8. LCD Block

LED_

A

LED_

K1

LED_

K2

LED_K

3

LED_

K4

PC13

+

3

V3

+3V3

DG

N

D

DGND

R6

8

0

R

R6

8

0

R

C

5

7

4.7uF

C

5

7

4.7uF

C55 1uF

MN8 AAT3155ITP-T1

C1+

1

0

C1-

9

EN/

SET

1

C2+

7

C2-

6

O

UTC

P

8

I

N

5

GND

4

D

1

3

D

2

D3

1

D

4

1

2

R

64

47

K

R

64

47

K

B1 BN03K314S300

R

B1 BN03K314S300

R

C5

6

1uF

C5

6

1uF

C5

4

1uF

C5

4

1uF

T

P7

SM

D

T

P7

SM

D

PC[0..31]

Evaluation Kit Hardware

V3

+3

+

C

C43

C43 10uF

10uF

C 100nF

100nF

5

44

C4

49

R

100nF

47K

NRST

X_RIGHT Y_UP X_L

EFT

Y_DOW

+3V3

DGND

N

R5

R5 10K

10K

R5

4.7K

1

PC13 PC22 PC23 PC24 PC2 PC2 PC2 PC2 PC2 PC3 PC31

5 6 7

8

9 0

6

RST

N

8

5

2

DGND

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PC11

8

PC PC1

PC1

3

4

D

1

PACDN044Y5R

TVS, SOT23-5

NOT POPULAT

DGND

7

LCD_DB1

6

LCD_DB1

5

LCD_DB1

4

LCD_DB1

3 LCD_DB12 LCD_DB11 LCD_DB10

LCD_DB9 LCD_

DB8

LCD_

DB7

LCD_

DB6

LCD_

DB5 LCD_DB4 LCD_

DB3 LCD_DB2 LCD_DB1 LCD_DB0

9

JP13JP13

5

LED_A

R590RR590R

ED_

L

ED_

L

ED_K3

L

ED_K4

L

_UP

Y

_DOWN

Y

RIGHT

X_

LEFT

X_

K1 K2

DGND

J8

J8 FH26-39S-0.3SH

FH26-39S-0.3SH

1

D

VD

2

B17

D

3

B16

D

4

B15

D

5

B14

D

6

B13

D

7

DB12

8

DB11

9

DB10

0

1

DB9

11

DB8

12

B7

D

13

DB6

14

DB5

5

1

DB4

6

1

DB3

17

DB2

18

DB1

19

DB0

20

VDD

21

RD

22

WR

23

RS

24

CS

25

RESET

26

IM0

27

IM1

8

2

ND

G

9

2

ED-A

L

0

3

EDK1

L

1

3

EDK2

L

2

3

EDK3

L

3

EDK4

L

4

3

Y+

5

3

Y-

6

3

X+

7

3

X-

8

3

NC

9

3

GND

W

2.8" 320x240

PIN 3

PIN 1

PINs

PINs on

on BOT

BOT

9

LCD_DB0

LCD_DB4 LCD_DB2 LCD_DB3 LCD_DB1 LCD_DB8 LCD_DB6 LCD_DB7 LCD_DB5

LCD_DB9

TFT

FTM28

R61 DNPR61 DNP

1 2

3

4 5

R63DN

LCD DI

0C34D-8bi

1 2

3

4 5

SPLAY

t

8

7

R

A2

6

D

NP

8

7

R

A3

6

D

NP

P

DGND

ED

4.3.8.2 Backlight Control

The LCD backlight is made of four integrated white chip-LEDs arranged in parallel. These are driven by an AAT3155 charge pump, MN8.The AAT3155 is controlled by the SAM3S through a single PIO line PC13 interface; the 0 Ohm resistor R68 is mounted in series on this line, which permits to use it for other custom purposes. In that case, the pull-up resistor R64 maintains the charge pump permanently enabled by default.

On the anode drive line, a 0 Ohm resistor R59 is implemented in series for an optional current limitation.

Figure 4-9. Backlight Control

SAM3S-EK Development Board User Guide 4-7

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

PA12

PA13

PA14

PA17

PA11

X_RIGHT Y_UP X_LEFT Y_DO WN

PA16

DGND

+3V3

AGND_TP AGND_TP

R62 100K

R70 0RR70 0R

R67 0RR67 0R

R66 0RR66 0R

R65 100K

C6

0

100nF

C6

0

100nF

C58 100nF

L2 10uH/100

mA

L2 10uH/100

mA

R72 100K

R

69 0R

R

69 0R

C61

4.7uF

C61

4.7uF

T

P9

SM

D

T

P9

SM

D

R71 1

R

R71 1

R

C59 100nF

TP8 SMD

R740RR74 0R

R73 100

K

R73 100

K

MN7 ADS7843

E

MN7 ADS7843

E

XP

2

YP

3

XM

4

YM

5

DCLK

1

6

DIN

1

4

DOUT

1

2

CS

1

5

BUSY

13

PENIR

Q

11

VR

EF

9

VC

C1

1

VC

C2

10

GND

6

IN

3

7

IN

4

8

4.3.8.3 Touch Screen Interface

The LCD module integrates a 4-wire touch panel controlled by MN7 (ADS7843) which is a slave device on the SAM3S SPI bus. The controller sends back the information about the X and Y positions, as well as a measurement for the pressure applied to the touch panel. The touch panel can be used with either a stylus or a finger.

The ADS7843 touch panel controller connects to the SPI0 interface via the NPCS0 control signal. Two interrupt signals are connected and provide events information back to the microcontroller: PenIrq and Busy.

Note: PenIrq (PA16) is shared with ZigBEE signal IRQ0.

Busy (PA17) is shared with ZigBEE signal IRQ1. Therefore, if using a ZigBEE interface in concurrence with the TouchScreen controller, take care not to have both drivers enabled at the same time on either PA16 or PA17.

For that purpose, 0 Ohm resistors have been implemented on these PIO lines in order to disconnect either end driver from the other:

 On the touch panel controller side, R67 and R69.

 On ZigBEE side, R117 and R120.

for further information, refer to the “Schematics” section.

Touch ADC auxiliary inputs IN3/IN4 of the ADS7843 are connected to test point (TP8, TP9) for optional function extension.

Figure 4-10. Touch Panel Control

4.3.9 JTAG/ICE

A standard 20-pin JTAG/ICE connector is implemented on the SAM3S-EK for the connection of a compatible ARM JTAG emulator interface, such as the SAM-ICE from Segger.

Notes: 1. The NRST signal is connected to BP1 system button and is also used to reset the LCD

module. The 0 ohm resistor R44 may be removed in order to isolate the JTAG port from this system reset signal.

2. The TDO pin is in input mode with the pull-up resistor disabled when the Cortex M3 is not in debug mode. To avoid current consumption on VDDIO and/or VDDCORE due to floating input, the internal pull-up resistor corresponding to this PIO line must be enabled.

4-8 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

Figure 4-11. JTAG Interface

+3V3

DGND

N

RST

PB5

PB7

PB6

PB4

R43 100

K

R43 100

K

R4

1

100

K

R4

1

100

K

R39 100

K

R39 100

K

J6J

6

VT

ref

1

Vsupply

2

nTRST

3

G

ND1

4

TDI

5

GND

2

6

T

M

S

7

GND

3

8

TCK

9

GND

4

1

0

RTC

K

1

GND

5

1

2

TDO

1

3

GND6

1

4

n

SRST

1

5

GND

7

1

6

DBGRQ

1

7

GND

8

1

8

DBGACK

19

GND

9

2

0

R42 100

K

R42 100

K

R40 100

K

R40 100

K

R440

R

R440

R

4.3.10 Audio Interface

The SAM3S–EK board supports both audio recording and playback.

The audio volume can be adjusted using the potentiometer RV1, and the microphone amplifier gain can be adjusted via jumpers (fixed gain of 24 or 26 dB).

4.3.10.1 Microphone Input

The embedded microphone is connected to an audio pre-amplifier using the TS922 operational amplifier (MN11). The gain is set by using JP14 and JP15 jumpers; both must be set or removed at the same time.

Evaluation Kit Hardware

By modifying the jumper positions, you can select each of the following gain values:

 20 dB (default setting, both JP14 and JP15 are off)

 26 dB (both JP14 and JP15 are on).

Note:

3. The TB1 series 0 Ohm resistor is a reservation for future impedance adaptation facility.

Under specific amplifier settings conditions, this enables the easy insertion of a capacitor or any other bipolar device on the audio path. On the other hand, R83 is a default 0 Ohm resistor that enables the disconnection of PB0 from the audio input path for custom usage.

4. The audio pre-amplifier MN11 is powered by a dedicated low dropout regulator MIC5219-3.3 (MN14).

SAM3S-EK Development Board User Guide 4-9

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

JP14 and JP15 should be set or removed togethe

r

AG

ND

AGND AGND

AVDD

AG

ND

AGN

D

AGND

AVDD

AG

ND

AGND

DGN

D

AVDD

AGND

VCC33

PB0

C72 1

nF

C72 1

nF

R80 1

K

R80 1

K

R90 100

K

R90 100

K

C67 1uF

C74 100nF

R84

1

K

R84

1

K

R87 47K

R79

1

K

R79

1

K

R781KR78 1K

R7

7

470R

R7

7

470R

B2 BN03K314S

300

RB2 BN03K314S

300

R

C71 2

2nF

C71 2

2nF

R830RR83 0R

R88 470R

T

B1

0R

T

B1

0R

C63 22uF

C62 100pF

C7

7

4.7u

F

C7

7

4.7u

F

R85 1

K

R85 1

K

C7

3

22u

F

C7

3

22u

F

R75 47KR75 47K

MN11 TS92

2

MN11 TS92

2

IN1

-

2

IN1+

3

OUT2

7

IN2-

6

IN2+

5

GND

4

VCC

8

O

UT1

1

JP14JP14

R76 47KR76 47K

R9

3

100

K

R9

3

100

K

R910RR91 0R

JP15JP15

C69 1nF

R86 47K

R8

2

1K

R8

2

1K

C68 1uF

MIC1 SVB6050

12

R81 100R

Figure 4-12. Microphone Input

4.3.10.2 Headphone Output

The SAM3S-EK evaluation kit supports mono/stereo audio playback driven by a TPA0223 audio amplifier connected to two DAC channels of the microcontroller.

The TPA0223 is a 2W mono Bridge-Tied-Load (BTL) amplifier designed to drive speakers with as low as 4 Ohm impedance. The amplifier can be reconfigured on the fly to drive two stereo Single-Ended (SE) signals into head phones.

Figure 4-13. Headphone Output

1

0

J

1 2

M

N13

3

5

1

9

2

N13

TPA02

VDD

RIN

MONO-

LIN

2

Q

2

Q

3DG

IN

SH

PAD

11

ND

AG

RO/M

O/M

L

ST/M

UTD0WN

BYPASS

GND

PB14{

6

O+

AGN

10

O-

7

N

2

4

8

3,7}

C81

R951KR95

97 1K

R

D

C83 220uF

1100

R10

3 100

R10

C860.47uFC860.47uF

+

20uF

2

1K

+

AGN

R102100

KR10

K

KR10

K

0

JP20JP2

AGND

1

J1

J1 EARJACK

EARJACK

5 4

3

2 1

D

P

VDD_AM

K

C87

uF

1

AG

ND

+

V

3K314S30

BN0

C79

C79 1uF

1uF

ND

C840.

DIO_O

C840.

UTL

C880.47uFC 880.47uF

PB13

AU

4-10 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

G

F

7u

4

2

TP1

D

SM

JP17JP17

C850.47uFC850.47uF

9

P1

J

( to DAC output

0R

AGNDD

connector )

AUDIO_OUTL

VDD_AM

+

C8

0

10uF

R9833

R99 47

R10033

R10447

R10533

C82

C82 1

1

P

0n

0

1

F

K

SD1SD1

SD2SD2

B3

5

Using a readily available 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no

PC21

PB1

0

PB11

DGND

DGND FGND

FGN

D

C94 10pF

R

110 47K

R

110 47K

R116 27RR116 27R

5V D- D+ ID G

J15

USB Micro B

5V D- D+ ID G

J15

USB Micro B

123

475

6

8

9

RV1 V5.5MLA0603

R

V2

V5.5MLA060

3

R

V2

V5.5MLA060

3

R

112 68K

R

112 68K

R11427RR11427R

ADVREF

DGND

VC

C

33

+5V

JP2JP2

1

2

3

C5 100nFC5100nF

AT91SAM3SAT91SAM3S

ADVREF

1

R13

2.2K

R13

2.2K

MN2

LM

4040-2.

5

MN2

LM

4040-2.

5

plug is inserted. When closed, a 100-kOhm/1-kOhm divider pulls the ST/MN input low. When a jack plug is inserted, the 1-kOhm resistor is disconnected and the ST/MN input is pulled high. The mono speaker (J10 connector) is also physically disconnected from the RO/MO+ output so that no sound is heard from the speaker while the headphones are inserted.

4.3.11 USB Device

The SAM3S UDP port is compliant with the Universal Serial Bus (USB) rev 2.0 Full Speed device specification. J15 is a micro B-type receptacle for USB device.

Both 27-Ohm resistors R114 and R116 build up a 90-Ohm differential impedance together with the (embedded) 6-Ohm output impedance of the SAM3S full speed channel drivers.

R110 and R112 build up a divider bridge from VBUS +5V to implement plug-in detection (5V level gets lowered to a PIO compatible 3.3V level) through PC21.

Figure 4-14. USB

Evaluation Kit Hardware

4.3.12 Analog Interface

4.3.12.1 Analog Reference

SAM3S-EK Development Board User Guide 4-11

The 2V5 voltage reference is based on an LM4040 (Precision Micropower Shunt Voltage Reference).

This ADVREF level can be set as 2.5V or 3.3V via the jumper JP2.

Figure 4-15. Analog Vref

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

Potentiometer

AD12B5

ADC

DGND

VCC33

PB1

J

P18JP18

1

2

3

CN1 BN

C

CN1 BN

C

1 2

3

4

5

JP16JP16

VR1 10K

13

2

R

96

49.9R

1%

R

96

49.9R

1%

C8

9

10nF

C8

9

10nF

R

94

0

R

94

0

R

C78 10

nF

C78 10

nF

SO

LDE

R DROP 2 pins open.Normal

DAC01

DAC

AU

D

IO_OUT

L

DGND

PB1

4

C90 2.2uFC90 2.2uF

JP21JP21

R10

9

49.9R 1%

R10

9

49.9R 1%

SD1SD

1

2

R

106

0R

R

106

0R

CN2 BN

C

CN2 BN

C

1 2

3

4

5

SD2SD2

1

2

4.3.12.2 Analog Input

The BNC connector CN1 is connected to the ADC port PB1 as an external analog input. An on-board 50Ohm resistor termination can be applied by closing jumper JP16. A low pass filter can be implemented for the BNC connector CN1 by replacing R94 and C78 with custom resistor and capacitor values, depending on your application requirements.

A 10-KOhm potentiometer (VR1) is also connected to this channel to implement an easy access to ADC programming and debugging (or implement an analog user control like display brightness, volume, etc.).

Either of these two functions can be selected by jumper JP18.

Figure 4-16. ADC Input

4.3.12.3 Analog Output

The BNC connector CN2 is connected to the DAC port PB13 and provides an external analog output. An on-board 50-Ohm resistor termination can be enabled by closing jumper JP21. A filter can be implemented on this output channel by replacing R106 and C90 with appropriate resistor and capacitor values, depending on the application requirements.

Figure 4-17. DAC Output

4.3.13 QTouch Elements

QTouch keys consist in a series of sensors formed by the association of a copper area and the capacitive effect of human fingers approaching it.

4.3.13.1 Keys

4-12 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

The SAM3S-EK implements five individual capacitive touch keys (UP, DOWN, RIGHT, LEFT and VALID) using five pairs of PIO.

4.3.13.2 Slider

PC25

PC2

4

PC31

PC30

PC2

9

PC28

PC23

PC22

PC

27

PC

26

R

53 1K

R

53 1K

C

49

22nF

C

49

22nF

R601

K

R601

K

R51 1KR51 1K

R571KR571K

C

51

22nF

C

51

22nF

R

55

1KR

55

1K

C47 22nF

K1 DNPK1DNP

C5

3

22nF

C5

3

22nF

C52 22nF

PA1

PA0

PA

3

PA2

PA5

PA4

R54 1KR54 1K

R

50 1K

R

50 1K

C50 22nF

C

46

22nF

C

46

22nF

S1 DNPS1DNP

SL

SM

SR

R52 1KR52 1K

C

48

22nF

C

48

22nF

PB3

PC12

DGND

NRST

JP26JP26

BP1BP1

1

4

2

3

BP3BP3

1

4

2

3

JP25JP25

BP2BP2

1

4

2

3

Evaluation Kit Hardware

Figure 4-18. QST Keys

A group of channels forms a Slider. A Slider is composed of three channels for a QTouch acquisition method using three pairs of PIO. Such a sensor is used to detect a linear finger displacement on a sensitive area. A typical implementation is volume control.

Figure 4-19. QT_Slider

4.3.14 User Buttons

There are two mechanical user buttons on the SAM3S-EK, which are connected to PIO lines and defined to be "left" and "right" buttons by default.

In addition, a mechanical button controls the system reset, signal NRST.

SAM3S-EK Development Board User Guide 4-13

Figure 4-20. System Buttons

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

PA1

9

PA2

0

PC20

+

3V3

DGND

D

4Red-le

dD

4Red-le

d

R113 220

R

R113 220

R

Q

1

IRLML250

2

Q

1

IRLML250

2

1

3

2

R

115 100K

R

115 100K

D3 Green-ledD3 Green-led

R11

7

2

0

R

R11

7

2

0

R

R111 220R

D

2Bl

ue-ledD

2Bl

ue-led

PA2

8

PA29

PA6

PA26 PA27

PA30 PA31

DGND

+3V3

DGND

+

C25 10uF

+

C25 10uF

RA1 68KX4

123

45

678

R18 10K

R

17

10K

R

17

10K

C26 100nF

J

3

TF01A

J

3

TF01A

DAT2

1

DAT3

2

CMD

3

VCC

4

C

LK

5

VSS

6

DAT0

7

DAT1

8

GND

10

CD

9

Sh1

11

Sh2

12

Sh3

13

R200RR20

0R

4.3.15 LEDs

There are three LEDs on the SAM3S-EK board:

 A blue LED (D2) and a green LED (D3), which are user defined and controlled by the GPIO.

 A red LED (D4), which is a power LED indicating that the 3.3V power rail is active. It is also controlled

by the GPIO and can be treated as a user LED as well. The only difference with the two others is that it is controlled through a MOS transistor. By default, the PIO line is disabled; a pull-up resistor controls the MOS to light the LED when the power is ON).

Figure 4-21. LEDs

4.3.16 SD/MMC Card

The SAM3S EK has a high-speed 4-bit multimedia MMC interface, which is connected to a 4-bit SD/MMC micro card slot featuring a card detection switch.

Figure 4-22. SD Card

4.3.17 ZigBEE

SAM3S has a 10-pin male connector for the RZ600 ZigBEE module.

4-14 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

Note: 0 Ohm resistors have been implemented in series with the PIO lines that are used else-

where in the design, thereby enabling their individual disconnection, should a conflict occur in your application.

Figure 4-23. ZigBEE Interface

IRQ0_ZBE

E

IRQ1_ZB

EE SPIO_NPCS2# MI

SO

M

OSI

S

PCK

S

LP_TR

ZB

_RST

N

PA1

3

PA16

PB2 PA12 PA14

PA15

PA17

PA18

DGND

+3

V3

C95 18pF

R

120 0R

R

120 0R

J16J16

1

2

3

4

5

6

7

8

9 10

R119 0RR119 0R

R118 0RR118 0R

JP27JP2

7

R121 0RR121 0R

C96

2.2n

F

C96

2.2n

F

C97

2.2uF

C97

2.2uF

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15

PC19

PC17

PC21

PC16

PC20

PC18

PB6

PB1

PB3

PB7

PB4

PB0

PB5

P

B2

PB14

PB9

PB11 PB12

PB8

PB13

PB10

PA6

PA9

PA1

1

PA1

4

PA1

3

PA7 PA8

PA1

2

PA1

0

PA15

PA2

2

PA27

PA23

PA29 PA30

PA25

PA21

PA28

PA24

PA26

PA31

PA16 PA17 PA18 PA19 PA20

+3V3

+3V3 +3V3

+

3V3

DGND

+

3V3

+3V3

DGND

+5

V

+3V3

+5

V

+5V

+3V3

PC[0..31]

PB[0..14]

PA[0..31

]

J

P23JP23

1

2

3

JP22JP22

1

2

3

J14J

14

1 2 3 4 5 6 7 8 9 1

0

11 1

2

13 1

4

15 1

6 17 18 19

2

0 21

2

2 23

2

4

J13J13

1

2

3

4

5

6

7

8

9 1

0

1

2

1

3

1

4

15 1

6

1

7

18

1

9

20

2

1

22

2

3

24

2

5

26

2

7

28

2

9

30

3

1

32

3

4

3

5

3

6

3

7

3

8

39 4

0

J12J12

1

2

3

4

5

6

7

8

9

1

0

1

2

1

3

14

1

5

1

6

1

7

1

8

19

2

0

21

2

23

2

4 25 26 2

7

28

2

9

30 31 32 33 34 35 36 37 38 39

4

0

JP24JP24

1

2

3

4.3.18 PIO Expansion

The SAM3S product features three PIO controllers, PIOA, PIOB and PIOC, which are multiplexed with the I/O lines of the embedded peripherals. Each PIO Controller controls up to 32 lines (16 for PIOB). Expansion ports J12, J13 and J14 provide PIO lines access for customer defined usage.

Figure 4-24. PIO Expansion

Evaluation Kit Hardware

Note: All PIO lines are available on these expansion connectors, except those that are used for

the QTouch elements.

11031C–ATARM–30-Mar-11

SAM3S-EK Development Board User Guide 4-15

Evaluation Kit Hardware

4.4 Configuration

This section describes the PIO usage, the jumpers, the test points and the solder drops of a SAM3S-EK board.

4.4.1 PIO Usage

Table 4-1. PIO Port A Pin Assignments and Signal Descriptions

I/O

No

Line

1 PA0 PWMH0 TIOA0 A17 WKUP0 QTouch slider (left) SNS

2 PA1 PWMH1 TIOB0 A18 WKUP1 QTouch slider (left) SNSK

3 PA2 PWMH2 SCK0 DATRG WKUP2 QTouch slider (middle) SNS

4 PA3 TWD0 NPCS3 QTouch slider (middle) SNSK

5 PA4 TWCK0 TCLK0 WKUP3 QTouch slider (right) SNS

6 PA5 RXD0 NPCS3 WKUP4 QTouch slider (right) SNSK

7 PA6 TXD0 PCK0 MCI card detection

8 PA7 RTS0 PWMH3 XIN32 CLK32KHz

9 PA8 CTS0

10 PA9 URXD0 NPCS1 PWMFI0 WKUP6 UART receive data

11 PA10 UTXD0 NPCS2 UART transmit data

12 PA11 NPCS0 PWMH0 WKUP7 NPCS0# (TSC)

13 PA12 MISO PWMH1 MISO_TSC ZigBEE MISO

14 PA13 MOSI PWMH2 MOSI_TSC ZigBEE MOSI

15 PA14 SPCK PWMH3 WKUP8 SPCK_TSC ZigBEE CLK

16 PA15 TF TIOA1 PWML3 WKUP14 / PIO_DCEN1 ZigBEE SLPTR

17 PA16 TK TIOB1 PWML2 WKUP15 / PIO_DCEN2 IRQ_TSC ZigBEE IRQ0

Peripheral APeripheral BPeripheral

C Extra Function

AD12BTR

G

System

Function Comment

WKUP5 XOUT32 CLK32KHz

18 PA17 TD PCK1 PWMH3 AD0 BUSY_TSC ZigBEE IRQ1

19 PA18 RD PCK2 A14 AD1 ZigBEE RSTN

20 PA19 RK PWML0 A15 AD2/ WKUP9 Blue LED (UserLED1)

21 PA20 RF PWML1 A16 AD3/ WKUP10 Green LED (UserLED2)

22 PA21 RXD1 PCK1 AD8 USART RXD

23 PA22 TXD1 NPCS3 NCS2 AD9 USART TXD

24 PA23 SCK1 PWMH0 A19 POI_DCCLK USART transceiver enable

25 PA24 RTS1 PWMH1 A20 POI_DC0 USART RTS

26 PA25 CTS1 PWMH2 A23 POI_DC1 USART CTS

27 PA26 DCD1 TIOA2 MCDA2 POI_DC2 MCI data bit 2

28 PA27 DTR1 TIOB2 MCDA3 POI_DC3 MCI data bit 3

29 PA28 DSR1 TCLK1 MCCDA POI_DC4 MCI command

4-16 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

Table 4-1. PIO Port A Pin Assignments and Signal Descriptions (Continued)

Evaluation Kit Hardware

I/O

No

Line

30 PA29 RI1 TCLK2 MCCK POI_DC5 MCI clock

31 PA30 PWML2 NPCS2 MCDA0 WKUP11 / POI_DC6 MCI data bit 0

32 PA31 NPCS1 PCK2 MCDA1 POI_DC7 MCI data bit 1

Peripheral APeripheral BPeripheral

C Extra Function

System

Function Comment

Table 4-2. PIO Port B Pin Assignments and Signal Descriptions

I/O

No

Line

1 PB0 PWMH0 AD4 Microphone input

2 PB1 PWMH1 AD5 Analog input

3 PB2 URXD1 NPCS2 AD6 / WKUP12 ZigBee chip select

4 PB3 UTXD1 PCK2 AD7 User push-button 1

5 PB4 TWD1 PWMH2 TDI JTAG data in

6 PB5 TWCK1 PWML0 WKUP13

7PB6 TMS/SWDIO JTAG test mode select

8PB7 TCK/SWCLK JTAG clock

Peripheral APeripheral BPeripheral

C Extra Function

System

Function Comment

TDO/

TRACESWO

JTAG data out

9PB8 XOUT CLK12MHz

10 PB9 XIN CLK12MHz

11 PB10 DDM USB DM

12 PB11 DDP USB DP

13 PB12 PWML1 ERASE Flash erase selector

14 PB13 PWML2 PCK0 DAC0 Audio Output R

15 PB14 NPCS1 PWMH3 DAC1 Audio Output L

SAM3S-EK Development Board User Guide 4-17

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

Table 4-3. PIO Port C Pin Assignments and Signal Descriptions

No I/O Line Peripheral A

Peripheral BPeripheral

C

Extra

Function

System

Function Comments

1 PC0 D0 PWML0 EBI D0

2 PC1 D1 PWML1 EBI D1

3 PC2 D2 PWML2 EBI D2

4 PC3 D3 PWML3 EBI D3

5 PC4 D4 NPCS1 EBI D4

6 PC5 D5 EBI D5

7 PC6 D6 EBI D6

8 PC7 D7 EBI D7

9 PC8 NWR0/NWE TFT LCD write enable

10 PC9 NANDOE NAND Flash output enable

11 PC10 NANDWE NAND Flash write enable

12 PC11 NRD TFT LCD read enable

13 PC12 NCS3 AD12 User push-button 2

14 PC13 NWAIT PWML0 AD10 LCD backlight control

15 PC14 NCS0 NAND Flash chip select

16 PC15 NCS1 PWML1 AD11 TFT LCD chip select

17 PC16 A21/NANDALE NAND Flash ALE

18 PC17 A22/NANDCLE NAND Flash CLE

19 PC18 A0/NBS0 PWMH0 RDYBSY NAND Flash RDY/BSY

20 PC19 A1 PWMH1 TFT LCD RegSel

21 PC20 A2 PWMH2 Red LED (Power)

22 PC21 A3 PWMH3 USB Vbus detection

23 PC22 A4 PWML3 QTouch valid button SNS

24 PC23 A5 TIOA3 QTouch valid button SNSK

25 PC24 A6 TIOB3 QTouch up button SNS

26 PC25 A7 TCLK3 QTouch up button SNSK

27 PC26 A8 TIOA4 QTouch down button SNS

28 PC27 A9 TIOB4 QTouch down button SNSK

29 PC28 A10 TCLK4 AD13 QTouch left button SNS

30 PC29 A11 TIOA5 AD14 QTouch left button SNSK

31 PC30 A12 TIOB5 QTouch right button SNS

32 PC31 A13 TCLK5 QTouch right button SNSK

4-18 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

4.4.2 Jumpers

The SAM3S-EK board jumpers are essentially used for two main purposes: functional selection or current measurement. Details are given below.

Table 4-4. Jumpers Setting

Designation Label Default Setting Feature

JP1 JTAG OPEN Close to select the JTAG boundary scan of the SAM3S

Evaluation Kit Hardware

JP2 ADVREF 1-2

JP3 ERASE OPEN Close to reinitialize the Flash contents and some of its NVM bits.

JP4 TEST

JP5 VDDPLL CLOSE Access for current measurement on VDDPLL

JP6 VDDIO CLOSE Access for current measurement on VDDIO

JP7 VDDIN CLOSE Access for current measurement on VDDIN

JP8 VDDCORE CLOSE Access for current measurement on VDDCORE

JP9 CE FLASH CLOSE NCS0 enable NAND Flash chip select

JP10 RS485 OPEN Maintain differential impedance for RS485 interface

JP11 RS485 CLOSE Maintain impedance matching for RS485 interface

JP12 RS485 OPEN Maintain differential impedance for RS485 interface

JP13 CS CLOSE NCS1 chip select LCD

JP14 - JP15 MIC GAIN0

JP16 ADC input OPEN Close for impedance matching on ADC BNC port

JP17 – JP19 MIC Gain stage Close to mux RIN/LIN into MONO-IN path within audio PA

JP18 SELECT ADC INP

JP20 MONO/STEREO CLOSE Close to fix in mono speaker, no matter the stereo plug state

JP21 DAC output OPEN Close for impedance matching on DAC BNC port

Not populated

(OPEN)

CLOSE (both) 20db

OPEN (both) 26db

1-2 2-3

Analog reference voltage selection between 3.3V (close 1-2) and

2.5V (close 2-3)

Close for manufacturing test or fast programming mode

Close both to lower gain stage on microphone input.

ADC input potentiometer ADC input BNC

JP22

JP23

JP24

JP25 BP2 CLOSE Open to disconnect and free PB3 for custom usage

JP26 BP3 CLOSE Open to disconnect and free PC12 for custom usage

JP27 ZIGBEE CLOSE

SAM3S-EK Development Board User Guide 4-19

PIO expansion J12

voltage supply

PIO expansion J13

voltage supply

PIO expansion J14

voltage supply

2-3 Set to 3.3V (position 1-2 sets to 5V)

Power supply connection/disconnection for the ZigBEE module May also be used as a current measurement point

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

Table 4-5. Audio Input Configuration

JP17 JP19 MONO-STEREO INPUT

OFF OFF PIN test point (TP12)

OFF ON Left-in only

4.4.3 Test Points

Some test points have been placed on the SAM3S-EK board for the verification of important signals.

Table 4-6. Test Points

Designation Part Description

TP1 Ring Hook GND

TP2 Ring Hook GND

TP3 Ring Hook GND

TP4 Ring Hook GND

ON OFF Right-in only

ON ON Sum of Left-in and Right-in

TP5 Pad UART TXD

TP6 Pad UART RXD

TP7 Pad LCD Backlight driver anode

TP8 Pad Aux ADC input for Touch Screen controller

TP9 Pad Aux ADC input for Touch Screen controller

TP10 Ring Hook +5V

TP11 Ring Hook +3V3

TP12 Pad Optional Audio PA input

4.4.4 Solder Drops

There are two solder drops designed on the SAM3S-EK for isolation.

Table 4-7. Solder Drops

Designation Default Setting Feature

SD1 OPEN Isolation of DAC output from shared channel (PB14)

SD2 CLOSE Connects PB14 to the AUDIO_OUTL channel

4.4.5 Assigned PIO Lines, Disconnection Possibility

As pointed out in some previous interface description, 0 Ohm resistors have been inserted on the path of the receiver PIO lines of the SAM3S-EK. These are the PIO lines connected to an external driver on the board. The 0 Ohm resistors allow disconnecting each of these for custom usage (through PIO expansion connectors for example). This feature gives the user an added level of versatility for prototyping a system of his own. See the table below.

4-20 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

Table 4-8. Disconnecting Possibility

Designation Default Assignment PIO

R19 0R PC18, RDY/BSY on NAND Flash

R20 0R PA29

R22 DNP Optional write protection on NAND Flash

R25 0R PA21

R26 0R PA25

R27 0R PA24

R28 0R PA22

R31 0R PA23

R33 0R PA22

R34 0R PA21

R35 0R PA24

R36 0R PA25

R44 0R NRST

R47 0R PA9

Evaluation Kit Hardware

R48 0R R2OUT/MN5

R59 0R LCD backlight LED anode

R66 0R PA11

R67 0R PA5

R68 0R PC13

R69 0R PA4

R70 0R Vref TSC

R118 0R PA3 ZB_RSTN

R119 0R PA5 IRQ1_ZBEE

R120 0R PA4 IRQ0_ZBEE

R121 0R PA6 SLP_TR

Table 4-9. Default Not Populated Parts

Reference Function

J1, R1 External clock resource input

Y1, R3, R7 Backup 12 MHz crystal

R6, R8 Isolation on 12 MHZ clock source and GPIO expansion

R9, R10 Isolation on 32 KHz clock source and GPIO expansion

R22 Optional write protection NAND Flash

R23 Optional pull-up for open drain output or equivalent device

R24, R30 Differential impedance matching for RS485 cable

SAM3S-EK Development Board User Guide 4-21

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

Table 4-9. Default Not Populated Parts

Reference Function

D1 Optional ESD protection for LCD touch panel

R61, R63, RA2, RA3 Optional data bus termination for LCD controller

JP4 Test mode selection for the SAM chip

J2 Optional QFP socket for the SAM3 chip

K1 Virtual component for QTouch keys set - implemented as copper areas

S1 Virtual component for QTouch slider set - implemented as copper areas

TPxx Surface-mounted test points (copper area)

4.5 Connectors

4.5.1 Power Supply Connector J9

The SAM3S-EK evaluation board can be powered from a 5VDC power supply connected to the external power supply jack J9. The positive pole is the center pin.

Figure 4-25. Power Supply Connector J9

Table 4-10. Power Supply Connector J9 Signal Descriptions

Pin Mnemonic Signal Description

1 Center +5vcc

2 Gnd Ground reference

4.5.2 USART Connector J5 With RTS/CTS Handshake Support

Figure 4-26. Male RS232/USART Connector J5

4-22 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

Table 4-11. Serial COM1 Connector J5 Signal Descriptions

Pin Mnemonic Signal Description

1, 4, 6, 9 NC NO CONNECTION

2 TXD TRANSMITTED DATA RS232 serial data output signal

3 RXD RECEIVED DATA RS232 serial data input signal

5GND GROUND

7 RTS READY TO SEND Active-positive RS232 input signal

8 CTS CLEAR TO SEND Active-positive RS232 output signal

4.5.3 UART Connector J7

Male RS232/UART connector J7

Evaluation Kit Hardware

Table 4-12. Male RS232/UART Connector J7 Signal Descriptions

Pin Mnemonic Signal Description

1, 4, 6, 7, 8, 9 NC NO CONNECTION

2 TXD TRANSMITTED DATA RS232 serial data output signal

3 RXD RECEIVED DATA RS232 serial data input signal

5 GND GROUND

4.5.4 USB Device Connector J15

Figure 4-27. Micro-B USB Connector J15

Table 4-13. Micro-B USB Connector J15 Signal Descriptions

Pin Mnemonic Signal Description

1 Vbus 5v power

2 DM Data -

3 DP Data +

4 Gnd Ground

5 Shield Shield

SAM3S-EK Development Board User Guide 4-23

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

4.5.5 TFT LCD Connector J8

One 39-pin connector is available on the board to connect the LCD module, backlight and touch screen.

Figure 4-28. LCD Connector J8

Table 4-14. LCD Connector J8 Signal Descriptions

Pin Mnemonic Pin Mnemonic

1 3V3 2 LCD_DB17 (PC7)

3 LCD_DB16 (PC6) 4 LCD_DB15 (PC5)

5 LCD_DB14 (PC4) 6 LCD_DB13 (PC3)

7 LCD_DB12 (PC2) 8 LCD_DB11 (PC1)

9 LCD_DB10 (PC0) 10 LCD_DB09 (NC)

11 LCD_DB08 (NC) 12 LCD_DB07

13 LCD_DB06 (NC) 14 LCD_DB05 (NC)

15 LCD_DB04 (NC) 16 LCD_DB03 (NC)

17 LCD_DB02 (NC) 18 LCD_DB01 (NC)

19 LCD_DB00 (NC) 20 3V3

21 RD (PC11) 22 WR (PC8)

23 RS (PC19) 24 CS (PC15)

25 RESET 26 IM0

27 IM1 28 GND

29 LED-A 30 LED-K1

31 LED-K2 32 LED-K3

33 LED-K4 34 Y UP

35 Y DOWN 36 X RIGHT

37 X LEFT 38 NC

39 GND

4-24 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

4.5.6 JTAG Debugging Connector J6

This JTAG connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm male) that mates with IDC sockets mounted on a ribbon cable. Its signal assignment is compatible with the SAM-ICE or any similar third-party interface.

Figure 4-29. JTAG/ICE Connector J6

Table 4-15. JTAG/ICE Connector J13 Signal Descriptions

Pin Mnemonic Description

This is the target reference voltage. It is used to check if the target has power, to

1 VTref. 3.3V power

create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd on the target board and must not have a series resistor.

Evaluation Kit Hardware

2 Vsupply. 3.3V power

nTRST TARGET RESET — Active-low

3

4 GND Common ground

5

6 GND Common ground

7 TMS TEST MODE SELECT –

8 GND Common ground

9

10 GND Common ground

11

12 GND Common ground

output signal that resets the target

TDI TEST DATA INPUT — Serial data

output line, sampled on the rising edge

of the TCK signal

TCK TEST CLOCK — Output timing

signal, for synchronizing test logic and

control register access

RTCK

Input Return test clock signal from the

target

This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.

JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.

JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU.

JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target’s JTAG state machine, sampled on the rising edge of the TCK signal.

JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU.

Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.

13

14 GND Common ground

SAM3S-EK Development Board User Guide 4-25

TDO JTAG TEST DATA OUTPUT —

Serial data input from the target

JTAG data output from target CPU. Typically connected to TDO on target CPU.

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

Table 4-15. JTAG/ICE Connector J13 Signal Descriptions (Continued)

Pin Mnemonic Description

15 nSRST RESET — Active-low reset signal. Target CPU reset signal

16 GND Common ground

17 RFU This pin is not connected in SAM-ICE.

18 GND Common ground

19 RFU This pin is not connected in SAM-ICE.

20 GND Common ground

4.5.7 SD/MMC - MCI Connector J3

Figure 4-30. SD/MMC Connector J3

Table 4-16. SD/MMC Connector J3 Signal Descriptions

Pin Mnemonic Pin Mnemonic

1 RSV/DAT3 2 CDA

3GND4VCC

5CLK6GND

7 D AT 0 8 DAT 1

9 DAT2 10 Card Detect

11 GND 12

4-26 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

4.5.8 Analog Connector CN1 & CN2

Figure 4-31. Analog Input Connector CN1 and Analog Output CN2, Bottom View

Table 4-17. Analog Input, Output Connector CN1, CN2 Signal Descriptions

Pin Mnemonic

1, 2, 3, 4 GND

5 Analog input PB1 for CN1 and analog output PB13 for CN2 respectively

4.5.9 RS485 Connector J14

Evaluation Kit Hardware

Figure 4-32. RS485 Connector J14

Table 4-18. RS485 J14 Signal Descriptions

Pin Mnemonic

1 A - non-inverted RS485 signal A

2 Frame ground

3 B - non-inverted RS485 signal B

SAM3S-EK Development Board User Guide 4-27

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

4.5.10 Headphone Connector J11

Figure 4-33. Headphone J11

Table 4-19. Headphone J11 Signal Descriptions

Pin Mnemonic

1AGND

2 Out left

3

4

5 Out Right

4.5.11 ZigBEE Connector J16

Figure 4-34. ZigBee Connector J16

Table 4-20. Connector J16 Signal Descriptions

Signal

Function

Reset /RST 1 2 Misc.

Interrupt Request

Name Port Pin Pin Port

IRQ 3 4 SLP_TR SLP_TR

Signal

Name Function

Option on Misc. Port Set by Zero Ohm Resistor or Solder Shunts

EEPROM for MAC address, CAP array settings and serial number

TST: test mode activation CLKM: RF chip clock output

SPI chip

select

SPI MISO MISO 7 8 SCLK SPI CLK

Power

Supply

4-28 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

/SEL 5 6 MOSI SPI MOSI

GND GND 9 10 VCC VCC VCC

Voltage range: 1.8v to 5.5v, typically regulated to 3.3v

4.5.12 PIO Expansion Port C Connector J12

Figure 4-35. PIO Expansion Connector J12

Table 4-21. Connector J12 Signal Descriptions

Pin Mnemonic Pin Mnemonic

1 +5V or +3v3 2 +5V or +3v3

3 GND 4 GND

5 PC0 6 PC16

7 PC1 8 PC17

9PC210PC18

11 PC3 12 PC19

13 PC4 14 PC20

Evaluation Kit Hardware

15 PC5 16 PC21

17 PC6 18 NC

19 PC7 20 NC

21 PC8 22 NC

23 PC9 24 NC

25 PC10 26 NC

27 PC11 28 NC

29 PC12 30 NC

31 PC13 32 NC

33 PC14 34 NC

35 PC15 36 NC

37 GND 38 GND

393V3403V3

SAM3S-EK Development Board User Guide 4-29

11031C–ATARM–30-Mar-11

Evaluation Kit Hardware

4.5.13 PIO Expansion Port A Connector J13

Figure 4-36. PIO Expansion Connector J13

Table 4-22. Connector J13 Signal Descriptions

Pin Mnemonic Pin Mnemonic

1 +5V or +3v3 2 +5V or +3v3

3 GND 4 GND

5NC6PA16

7NC8PA17

9NC10PA18

11 NC 12 PA19

13 NC 14 PA20

15 NC 16 PA21

17 PA6 18 PA22

19 PA7 20 PA23

21 PA8 22 PA24

23 PA9 24 PA25

25 PA10 26 PA26

27 PA11 28 PA27

29 PA12 30 PA28

31 PA13 32 PA29

33 PA14 34 PA30

35 PA15 36 PA31

37 GND 38 GND

393V3403V3

4-30 SAM3S-EK Development Board User Guide

11031C–ATARM–30-Mar-11

4.5.14 PIO Expansion Port B Connector J14

Figure 4-37. PIO Expansion Connector J14

Table 4-23. Connector J14 Signal Descriptions

Pin Mnemonic Pin Mnemonic

1 +5V or +3v3 2 +5V or +3v3

3 GND 4 GND

5 PB0 6 PB8

7 PB1 8 PB9

9 PB2 10 PB10

11 PB3 12 PB11

13 PB4 14 PB12

Evaluation Kit Hardware

15 PB5 16 PB13

17 PB6 18 PB14

19 PB7 20 NC

21 GND 22 GND

233V3243V3

SAM3S-EK Development Board User Guide 4-31

11031C–ATARM–30-Mar-11

5.1 Schematics

This section contains the following schematics:

 Block diagram

 General information

 Microcontroller

 NAND Flash, serial interface

 TFT LCD & Touch

 Audio & Power Supply

 USB, LEDs, push-buttons & ZigBEE

Section 5

Schematics

SAM3S-EK Development Board User Guide 5-1

11031C–ATARM–30-Mar-11

5

4

3

2

1

SAM3S-EK RevB Block Diagram

D D

ATMEL Cortex M3 Processor SAM3S (LQFP100)

Reset,Debug Logic

C C

Audio PA

Microphone

USB FS Device

B B

RS232 & RS485

AD/DA

Power Manage

2.8 Inch TFT-LCD

MicroSD Card

Nand Flash

QTouch Input

ZIGBEE IF

A A

B PP 26-NOV-09

User Interface (PIO PortA,B,C)

SAM3S-EK

Block Diagram

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

5

4

3

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

2

B PP 26-NOV-09

INIT EDIT

A

REV

SCALE

1/1

DES.

XX-XXX-XX

DATE

1

XX-XXX-XXNL XXX

DATEMODIF.

VER.

DATEMODIF.

VER.

DATEMODIF.

VER.

REV. SHEET

1

B

7

5

4

3

2

1

REVISION HISTORY

REV DATA

D D

A

2009.07 ORIGINAL RELEASED

B 2009.11 UPDATED

NOTE

SCHEMATICS CONVENTIONS

(1) Resistance Unit: "K" is "Kohm", "R" is "Ohm¸"

(2) "DNP" means the component is not populated by default

TEST POINT

PAGE REFERENCE FUNCTION

TABLE OF CONTENTS

PAGE

1 2

C C

3 4 5 6 7

Block Diagram Reference guide Microcontroller NAND Flash, RS232, RS485, MCI, JTAG LCD, Touch items Audio, AD/DA, Power IO Expansion, USB, ZigBEE, LED, Button

DESCRIPTION

3 TP1, TP2, TP3, TP4 GND

TP5 UART TXD

4

TP6 UART RXD

5

TP7 LCD backlight driver anode

TP8, TP9 Aux ADC input for TSC

6

TP12 Optional audio PA input

JUMPER and SOLDERDROP

PAGE REFERENCE FUNCTION

3 JP1 Close to select JTAG boundary scan

JP2 Analog reference voltage selection between 3.3V and 2.5V

JP3 Close to reinitialize the Flash contents and some of its NVM bits

JP4 Close for manufacturing test or fast programming mode

JP5, JP6, JP7, JP8 Access for current measurement on each power rail

4 JP9 Nand Flash chip select enable

JP11

JP10, JP12 OPEN RS485 pull resistor selectors

JP13

5 LCD chip select enable

JP14, JP15 Sync close to degrade gain stage on microphone input

6

JP17, JP19 Close to mux RIN/LIN into MONO-IN path within audio PA

JP16, JP21 Close for impedance matching on AD/DA BNC port

JP18 ADC input selection between BNC port and potentiometer

JP20 Close to fix in mono speaker mode, no matter stereo plug state

SD1 DAC path isolation on sharing channel

SD2

7 JP22, JP23, JP24 DC voltage selection between 3.3V and 5V on PIO expansion ports

JP25 Button BP2 disable

JP26

JP27 Power consumption measure for ZigBEE module

DEFAULT

OPEN

1-2

OPEN

CLOSE

OPEN

1-2

OPEN

CLOSE

2-3

CLOSE

RS485 bus termination enable

Lead PB13 as AUDIO_OUTL channel

Button BP3 disable

PIO MUXING

PIOA USAGE

PA0

TSLIDR_SL_SNS

PA1

B B

A A

TSLIDR_SL_SNSK

PA2

TSLIDR_SM_SNS

PA3

TSLIDR_SM_SNSK

PA4

TSLIDR_SR_SNS

PA5

TSLIDR_SR_SNSK

PA6

MCI_CD

PA7

CLK_32K

PA8

CLK_32K

PA9

RX_UART0

PA10

TX_UART0

PA11

TSC_CS

PA12

MISO

PA13

MOSI

PA14

SPCK

PA15

ZB_SLPTR

5

PIOA USAGE

PA16

PA17

PA18

PA19

PA20

PA21

PA22

PA23

PA24

PA25

PA26

PA27

PA28

PA29

PA30

PA31

TSC_IRQ/ZB_IRQ0

TSC_BUSY/ZB_IRQ1

ZB_RSTN

LED_BLUE

LED_GREEN

RXD1

TXD1

COM1EN

RTS1

CTS1

MCI

PIOB USAGE

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

MIC INPUT

ANA INPUT

ZB_NPCS2

USER_PB1

JTAG

CLK_12M

USB_DDM

USB_DDP

ERASE

AUDIO OUT R

AUDIO OUT L

4

PIOC USAGE

PC0

D0

D1

PC1

D2

PC2

D3

PC3

D4

PC4

D5

PC5

D6

PC6

D7

PC7

WR_LCD

PC8

NAND_OE

PC9

NAND_WE

PC10

RD_LCD

PC11

USER_PB2

PC12

EN_LCD

PC13

NAND_NCS0

PC14

NSC1_LCD

PC15

PIOC USAGE

PC16

PC17

PC18

PC19

PC20

PC21

PC22

PC23

PC24

PC25

PC26

PC27

PC28

PC29

PC30

PC31

NAND_ALE

NAND_CLE

NAND_RDYBSY

REGSEL_LCD

LED_RED(POWER)

USB_CNX

TVALID_SNS

TVALID_SNSK

TUP_SNS

TUP_SNSK

TDWN_SNS

TDWN_SNSK

TLEFT_SNS

TLEFT_SNSK

TRIGHT_SNS

TRIGHT_SNSK

3

DEFAULT NO POPULATE PARTS

PAGE REFERENCE FUNCTION

3 J1, R1 External clock resource input

Y1, R3, R7 Backup 12MHz crystal

R6, R8 Isolation between 12MHz clock source and GPIO line

R9, R10 Isolation between 32KHz clock source and GPIO line

4 R22 Optional write protection on NAND flash

R23

R24, R30

R25

D1 Optional ESD protection for LCD touch panel

5

R61, R62, RA2, RA3 Optional databus termination for LCD controller

2

Optional pull up for open drain output on equivalent device

Differential impedance matching for RS485 cable

Disconnect RS485 Receive data from PA21

SAM3S-EK

Describe

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

A

REV

SCALE

INIT EDIT

1/1

26-NOV-09PPB

XX-XXX-XX

DES.

DATE

DES.

DATE

DES.

DATE

1

XX-XXX-XXNL XXX

DATEMODIF.

VER.

DATEMODIF.

VER.

DATEMODIF.

VER.

REV. SHEET

2

B

7

5

4

3

2

1

C5 100nFC5100nF

2

TP2

TP2 GND

GND

VCC33

1

3

PC[0..31] {4,5,7}

PA[0..31] {4,5,7}

+5V

JP2JP2

MN2

LM4040-2 .5

DGND

PB[0..14] {4,6,7}

TP3

TP4

GND

DGND

R13

2.2K

NOT POPUL ATE D

J1J1

1

2

3 54

D D

C

B

A A

VDDIO

VDDCORE

VDDIO

DGND

PA16 PC7 PA15 PA14 PC6 PA13 PA24 PC5

PC4 PA25 PA26 PC3 PA12 PA11 PC2 PA10

PA9 PC1 XOUT32 XIN32

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DGND

R1 DNPR1 DN P

R2

49.9R 1%R249.9R 1%

DGND

C3 20pFC320pF

C4 20pFC420pF

PC0

PA20

R3 DNPR3 DN P

12

3

Y1Y1 DNP

R7 DNPR7 DN P

R110RR11 0R

12

3

Y3

32.768KH z

XOUT32

R120RR12

0R

VDDCORE

PC12

PA23

PA19

PC15

PC13

PA22

PA18

PA21

PC26

PA17

PC27

SOCKE T

XIN32

VDDOUT

VDDIN

DGND

PB3

PC31

C1 20 pFC1 2 0pF

C2 20 pFC2 2 0pF

PB2

PC30

PB1

PC29

Y2 12MHzY2 12MHz

PB0

ADVREF

12345678910111213141516171819202122232425

PB2{7}

PB3{7}

PB10{7}

PB11{7}

PB4{4,7} PB6{4,7} PB7{4,7} PB5{4,7}

NRST{4,5,7}

PB0{6 ,7} PB1{6 ,7}

J2J2

R4 0RR4 0R

R5 0RR5 0R

+3V3

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

PB14

XIN XOUT

PC25 PB13 PC24

PC23 PB11 PB10 PB12 PC22

PC21 PB7 PC20 PA31 PC19 PB6 PC18 JTAGSEL PB5

PB9

R6 DNPR6 DN P

PB8

R8 DNPR8 DN P

JP1

JP3JP3

JP4 DNPJP4 DNP

VDDPLL

VDDIO

VDDCORE

DNP

XIN

XOUT

PB2

PB3

PB10

PB11

JTAGSEL

PB4 PB6 PB7 PB5

NRST

PB0 PB1

PB12

TEST

97

PB9_XIN

96

PB8_XOUT

7

PB2_URXD1_NPCS2_AD12B6

9

PB3_UTXD1_PCK2_AD12B7

88

PB10_DDM

89

PB11_DDP

77

JTAGSEL

51

PB4_TWD1_PWMH2_TDI

79

PB6_TMS_SWDIO

83

PB7_TCK_SWCLK

76

PB5_TWCK1_PWML0_TDO

60

NRST

3

PB0_PWMH0_AD12B4

5

PB1_PWMH1_AD12B5

87

PB12_PWML1_ERASE

61

TEST

VDDINVDDOUT

VDDCORE

51525354555657585960616263646566676869707172737475

VDDIN

10

C6 100nFC6 100nF

VDDPLL

VDDCORE

PC0

PC1

PC0_D0_PWML025PC1_D1_PWML147PC2_D2_PWML243PC3_D3_PWML3

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

29

68

40

37

58

PC5_D535PC6_D632PC7_D7

PC4_D4_NPCS1

71

62

65

19

21

23

PC11_NRD

PC14_NCS0

PC9_NANDOE

PC10_NANDWE

PC8_NWR0_NWE

PC12_NCS3_AD12B12

PC13_NWAIT_PWML0_AD12B10

AT91SAM3S-LQFP100

VDDCORE

C9 100nFC9 100nF

16

C22

C22 100nF

100nF

VDDCORE

VDDCORE36VDDCORE

85

56

C12 100nFC12 100nF

C11 100nFC11 100nF

DGND

R141RR14 1R

C23

4.7uF

C13 DNPC13 DNP

L1

L1 10uH/100 mA

10uH/100 mA

C10 100nFC10 100nF

11

C7 100nFC7 100nF

DGND

JP5JP5

JP8JP8

VDDOUT

C8 2.2uFC8 2.2uF

PC16

PC17

PC18

PC19

PC20

PC21

PC22

PC23

PC24

PC25

PC26

PC27

PC28

PC29

PC30

PC31

MN1

86

84

92

75

78

73

PC19_A1_PWMH180PC20_A2_PWMH282PC21_A3_PWMH3

PC16_A21_NANDALE

PC17_A22_NANDCLE

PC18_A0_NBS0_PWMH0

PC15_NCS1PWML1_AD12B11

17

94

54

8

6

PA0_PWMH0_TIOA0_A17 PA1_PWMH1_TIOB0_A18

PC23_A5_TIOA390PC24_A6_TIOB3

PC26_A8_TIOA413PC27_A9_TIOB4

PC25_A7_TCLK3

PC22_A4_PWML3

PA2_PWMH2_SCK0_DATRG

PC28_A10_TCLK4

PC29_A11_TIOA5_AD12B134PC30_A12_TIOB5_AD12B14

PC31_A13_TCLK5_AD12B15

PA16_TK_TIOB1_PWML2

PA17_TD_PCK1_PWMH3_AD12B0

PA18_RD_PCK2_A14_AD12B1

PA19_RK_PWML0_A15_AD12B2

PA20_RF_PWML1_A16_AD12B3

PA21_RXD1_PCK1_AD12B8

PA22_TXD1_NPCS3_NCS2_AD12B9

PA23_SCK1_PWMH0_A19 PA24_RTS1_PWMH1_A20

PA25_CTS1_PWMH2_A23 PA26_DCD1_TIOA2_MCDA2 PA27_DTR1_TIOB2_MCDA3

PA28_DSR1_TCLK1_MCCDA

PA30_PWML2_NPCS2_MCDA0

PA31_NPCS1_PCK2_MCDA1

PB13_PWML2_PCK0_DACO0

PB14_NPCS1_PWMH3_DACO1

GND45GND95GND

GND

VDDPLL

70

26

100

C14 100nFC14 100nF

DGND

VDDPLL

VDDOUT

GND

2

VDDIO27VDDIO69VDDIO

C15 100nFC15 100nF

MN1

PA3_TWD0_NPCS3

PA4_TWCK0_TCLK0

PA5_RXD0_NPCS3

PA6_TXD0_PCKO

PA7_RTS0_PWMH3

PA8_CTS0_AD12BTRG

PA9_URXD0_NPCS1

PA10_UTXD0_NPCS2

PA11_NPCS0_PWMH0

PA12_MISO_PWMH1 PA13_MOSI_PWMH2

PA14_SPCK_PWMH3

PA15_TF_TIOA1_PWML3

PA29_RI1_TCLK2_MCCK

ADVREF

VDDIO

91

C17 100nFC17 100nF

VDDIO

VDDIN

DGND

+

C18 100nFC18 100nF

DGND

C24

C24 10uF

10uF

98

C20 4.7uFC20 4.7uF

C19 100nFC19 100nF

JP6JP6

JP7JP7

50

C16 100nFC16 100nF

VDDIO

C21 4.7uFC21 4.7uF

74 72 67 66 55 53 52 49 48 46 44 42 41 33 31 30 28 12 14 18 24 15 20 22 34 38 39 57 59 63 64 81

1

93

99

XIN32 XOUT32

ADVREF

PB13

PB14

+3V3

R9 DNPR9 DN P R10 DNPR10 DNP

PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31

PB13 {6,7}

PB14 {6,7}

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14

DGND

TP1

TP1 GND

GND

C

B

NOT POPUL ATE D

26-NOV-09B PP

INIT EDIT

A

PC28

PA5

PA4

PA27

PC8

NRST

PA28

PA30

PA3

PC10

PA29

TEST

PC9

PB4

PA6

VDDCORE

5

PA2

PC11

VDDIO

PC16

PC14

PA1

PA0

PC17

DGND

SAM3S-EK

Microcontroller

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

4

3

2

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

A

REV

SCALE

1/1

26-NOV-09B PP

XX-XXX-XX

DES.

DATE

1

XX-XXX-XXNL XXX

DATEMODIF.

VER.

DATEMODIF.

VER.

DATEMODIF.

VER.

REV. SHEET

3

B

7

5

4

3

2

1

PC[0..31]{3,5 ,7}

PC17 PC16

D D

C C

B B

PA10{3,7}

A A

PA9{3,7}

5

PC9 PC10

PC14

PC18

+3V3

R21 47KR21 47K

+3V3

PA23

PA22 PA21 PA24 PA25

+3V3

+3V3 +3V 3

R45

R45 100K

100K

TP5

TP5 SMD

SMD

R19 0RR19 0R

+3V3

C31

4.7uF

DGND

R32

R32 47K

47K

R31 0RR31 0R

R33 0RR33 0R R34 0RR34 0R R35 0RR35 0R R36 0RR36 0R

R37 47KR37 47K

+3V3

R46

R46 100K

100K

R47 0RR47 0R

R48 0RR48 0R

+3V3

R15

R16

47K

JP9JP9

R22

R22 DNP

DNP

DGND

C32

C33

100nF

C36

C36 100nF

100nF

DGND

C39

100nF

C40

C40 100nF

100nF

C41

C41 100nF

100nF

DGND

TP6

SMD

MN3MN3 MT29F2G08AADW P

16

CLE

17

ALE

8

RE

18

WE

9

CE

7

R/B

19

WP

1

N.C1

2

N.C2

3

N.C3

4

N.C4

5

N.C5

6

N.C6

10

N.C7

11

N.C8

14

N.C9

15

N.C10

20

N.C11

21

N.C12

22

N.C13

23

N.C14

24

N.C15

25

N.C16

26

N.C17

NAND FLASH

MN5

MN5 ADM3312 EARU

ADM3312 EARU

3

VCC

1

V+

21

V-

23

GND

19

SD

5

EN

T1IN7T1OUT

10

R1OUT T2IN8T2OUT

11

R2OUT T3IN9T3OUT

12

R3OUT

USART

MN6

MN6 MAX3232 CSE

MAX3232 CSE

16

VCC

2

V+

6

V-

15

GND

11

T1IN

12

R1OUT

10

T2IN

9

R2OUT

UART

4

C1+

C2+

C3+

R1IN

R2IN

R3IN

C1+

C2+

T1OUT

R1IN

T2OUT

R2IN

R40

R40 100K

100K

45

R18

R18 10K

10K

678

8

VCC

5

GND

6

A

7

B

R41

R41 100K

100K

R44 0RR44 0R

NAND FLA SH,SERIAL INTERFACE

29

I/O0

30

I/O1

31

I/O2

32

I/O3

41

I/O4

42

I/O5

43

I/O6

44

I/O7

48

N.C28

47

N.C27

46

N.C26

45

N.C25

40

N.C24

39

N.C23

38

PRE

35

N.C22

34

N.C21

33

N.C20

28

N.C19

27

N.C18

37

VCC

12

VCC

36

VSS

13

VSS

6

20

C1-

2

4

C2-

24

22

C3-

18 15 17 14 16

R38 0RR38 0R

13

1

3

C1-

4

5

C2-

14 13 7 8

C38

C38 100nF

100nF

C42

C42 100nF

100nF

C34

C34 100nF

100nF

C35

C35 100nF

100nF

C37

C37 100nF

100nF

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

C27

C27 100nF

100nF

C28

C28 100nF

100nF

+3V3

DGND

C29

C29 1uF

1uF

1 6 2 7 3 8 4 9 5

FGND

1 6 2 7 3 8 4 9 5

FGND

R17

10K

PA[0..31]{3,5,7}

PA26 PA27 PA28

PA29

PA30 PA31

PA6

PA23

PA21

R25 DNPR25 DNP

PA25

R26 0RR26 0R

PA24

R27 0RR27 0R

PA22

R28 0RR28 0R

J5J5

10

11

PB4{3 ,7} PB6{3 ,7} PB7{3 ,7}

PB5{3 ,7}

NRST{3,5,7}

J7J7

10

11

3

10K

R20 0RR20 0R

+3V3 +3V3

R23

R23 DNP

DNP

MN4

MN4 ADM3485 ARZ

ADM3485 ARZ

1

RO

2

RE

3

DE

4

DI

RS 485

R39

R39 100K

100K

2

+3V3

123

RA1

RA1 68KX4

68KX4

+3V3

DGND

+

C25

C25 10uF

10uF

C30

C30 100nF

100nF

DGND

C26

C26 100nF

100nF

J3 TF01AJ3TF01A

1

DAT2

2

DAT3

3

CMD

4

VCC

5

CLK

6

VSS

7

DAT0

8

DAT1

10

GND

9

CD

SD CARD

R24

R24 DNP

DNP

JP10JP1 0

Sh1 Sh2 Sh3

11 12 13

J4J4

1

2

3

JP11JP1 1

JP12JP1 2

R30

R30 DNP

DNP

DGND

J6J6

VTref1Vsupply nTRST3GND1 TDI5GND2 TMS7GND3 TCK9GND4 RTCK11GND5 TDO13GND6 nSRST15GND7 DBGRQ17GND8 DBGACK19GND9

FGND

2 4 6 8 10 12 14 16 18 20

R42

R42 100K

100K

R29

R29 120R

120R

R43

R43 100K

100K

+3V3

ICE INTERFACE

26-NOV-09PP

B

INIT EDIT

A

REV

SCALE

SAM3S-EK

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

SCALE

1/1

26-NOV-09PP

DES.

1

DGND

XX-XXX-XX

DATE

XX-XXX-XXNL XXX

DATEMODIF.

VER.

DATEMODIF.

VER.

DATEMODIF.

VER.

REV. SHEET

4

B

7

5

+3V3

+

C43

C44

C45

100nF

JP13JP1 3

R59 0RR59 0R

C45 100nF

100nF

LCD_DB17

LCD_DB16 LCD_DB15 LCD_DB14 LCD_DB13 LCD_DB12 LCD_DB11 LCD_DB10

LCD_DB9 LCD_DB8 LCD_DB7 LCD_DB6 LCD_DB5 LCD_DB4 LCD_DB3 LCD_DB2 LCD_DB1 LCD_DB0

LED_K1 LED_K2 LED_K3 LED_K4 Y_UP Y_DOWN X_RIGHT X_LEFT

10uF

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PC11 PC8 PC19

PC15

10uF

DGND

LED_A

PC[0..31]{3 ,4,7}

D D

NRST{3,4,7}

C C

X_RIGHT Y_UP X_LEFT Y_DOWN

B B

+3V3

DGND

1

5

DGND

PC13 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31

R56

R56 10K

10K

NRST

R58

4.7K

The part is placed as close as possible to J8

3

4

D1

D1 PACDN04 4Y5R

PACDN04 4Y5R

TVS, SOT2 3-5

2

NOT POPULATED

R49

R49 47K

47K

4

DGND

J8

J8 FH26-39S -0.3SHW

FH26-39S -0.3SHW

1

VDD

2

DB17

3

DB16

4

DB15

5

DB14

6

DB13

7

DB12

8

DB11

9

DB10

10

DB9

11

DB8

12

DB7

13

DB6

14

DB5

15

DB4

16

DB3

17

DB2

18

DB1

19

DB0

20

VDD

21

RD

22

WR

23

RS

24

CS

25

RESET

26

IM0

27

IM1

28

GND

29

LED-A

30

LEDK1

31

LEDK2

32

LEDK3

33

LEDK4

34

Y+

35

Y-

36

X+

37

X-

38

NC

39

GND

LCD

LCD_DB0

LCD_DB4 LCD_DB2 LCD_DB3 LCD_DB1 LCD_DB8 LCD_DB6 LCD_DB7 LCD_DB5

LCD_DB9

PIN 39

PIN 1

R61 DNPR61 DNP

1 2 3 4 5 1 2 3 4 5

R63 DNPR63 DNP

PINs

PINs on

on BOT

BOT

2.8" 320x240 TFT LCD DISPLAY

FTM280C 34D-8bit

8 7

RA2

6

DNP

8 7

RA3

6

DNP

DGND

3

2

S1 DNPS1DNP

1

SR

PA1

PA0

PA3

PA2

R50 1KR 50 1K

C46

C46 22nF

22nF

R52 1KR 52 1K

C48

C48 22nF

22nF

SL

SM

SR

PA5

PA4

PC25

PC24

PC31

PA[0..31]{3,4,7}

PA0 PA1 PA2 PA3 PA4 PA5 PA11 PA12 PA13 PA14 PA16 PA17

PC30

PC29

PC28

PC23

PC22

R54 1KR 54 1K

C50

C50 22nF

22nF

R51 1KR 51 1K

C47

C47 22nF

22nF

R53 1KR 53 1K

C49

C49 22nF

22nF

R55 1KR 55 1K

C51

C51 22nF

22nF

R57 1KR 57 1K

C52

C52 22nF

22nF

K1 DNPK1DNP

+3V3

R62

PA14 PA13 PA12

R62 100K

100K

R66 0RR66 0R

R67 0RR67 0R

R70 0RR70 0R

C58

C59

100nF

AGND_TP

PA11

PA17

C60

C60 100nF

100nF

+3V3

R711RR71 1R

C61

4.7uF

R65

R65 100K

100K

4

R69 0RR69 0R

L2

L2 10uH/100 mA

10uH/100 mA

R740RR74 0R

+3V3

DGND

PA16

+3V3

PC13

R680RR68 0R

B1

B1 BN03K31 4S300R

BN03K31 4S300R

3

+3V3

R64

R64 47K

47K

DGND

MN8

MN8 AAT3155 ITP-T1

AAT3155 ITP-T1

10

C1+

C54

C54 1uF

1uF

9

C1-

11

EN/SET

5

IN

C57

4.7uF

4

GND

LCD BACKLIGHT

OUTCP

C2+

7

C55

C55 1uF

6

C2-

8

3

D1

2

D2

1

D3

12

D4

1uF

LED_A

LED_K1 LED_K2 LED_K3 LED_K4

MN7

MN7 ADS7843 E

ADS7843 E

X_RIGHT Y_UP X_LEFT Y_DOWN

TP8

TP8 SMD

SMD

A A

R72

R72 100K

100K

AGND_TP

2

XP

3

YP

4

XM

5

R73

R73 100K

100K

YM

7

IN3

8

IN4

TP9

TP9 SMD

SMD

LCD TOUCH SCREEN

5

DCLK

DOUT

BUSY

PENIRQ

VREF VCC1 VCC2

GND

16 14

DIN

12 15

CS

13 11

9 1 10

6

TP7

TP7 SMD

SMD

DGND

PC27

PC26

C56

C56 1uF

1uF

2

R60 1KR 60 1K

C53

C53 22nF

22nF

QTOUCH ELEMENTS

INIT EDIT

A

REV

SCALE

SAM3S-EK

TFT-LCD & QTouch

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26-NOV-09PPB

XX-XXX-XX

DES.

DATE

DES.

DATE

DES.

DATE

1

XX-XXX-XXNL XXX

DATEMODIF.

VER.

DATEMODIF.

VER.

DATEMODIF.

VER.

REV. SHEET

5

B

7

5

4

3

2

1

AUDIO IN

C62

C62 100pF

AVDD

R77

R77 470R

470R

D D

C C

{3,7}

PB13

B B

C63

C63 22uF

22uF

12

AGND

C73

C73 22uF

22uF

AGND AGN D

AUDIO_OUT L

R781KR78 1K

MIC1

MIC1 SVB6050

SVB6050

R851KR85 1K

R88

R88 470R

470R

C84 0.47uFC84 0.47u F

C88 0.47uFC88 0.47u F

C67

C67 1uF

1uF

C68

C68 1uF

1uF

TP12

+5V

DGND

SMD

R791KR79 1K

R821KR82 1K

AGND

BN03K31 4S300R

C79

C79 1uF

1uF

JP17JP1 7

C85 0.47uFC85 0.47u F

JP19JP1 9

C69

C69 1nF

1nF

AGND AGN D

C77

4.7uF

B3

+

AGND

R801KR80 1K

R841KR84 1K

C72

C72 1nF

1nF

AVDD

R90

R90 100K

100K

R93

R93 100K

100K

AGND

VDD_AMP

C80

C80 10uF

10uF

R98 33KR98 33K

R99 47KR99 47K

R100 33KR10 0 33K

R104 47KR10 4 47K

R105 33KR10 5 33K

R86

R86 47K

47K

JP14 and JP15 should be set or removed together

MN13

MN13 TPA0223 DGQ

TPA0223 DGQ

3

C82

C82 100nF

100nF

5

1

9

R87

R87 47K

47K

JP15JP1 5

VDD

RIN

MONO-IN

LIN

R75 47KR75 47K

R76 47KR76 47K

MN11

MN11 TS922

TS922

2

IN1-

3

IN1+

7

OUT2

6

IN2-

5

IN2+

RO/MO+

LO/MO-

ST/MN

SHUTD0WN

BYPASS

PAD

GND

11

AGND

AUDIO OUT

MN14

MN14 MIC5219-3.3 YMM

MIC5219-3.3 YMM

2

IN

DGND

C93

C93 470pF

470pF

4

1

EN

4

BYP

C91

4.7uF

A A

5

DGND

OUT

GND GND GND GND

3

5 6 7 8

100pF

MN10

R89

R89 169K 1%

169K 1%

R92

R92 102K 1%

102K 1%

C78

C78 10nF

10nF

MN10 BNX002-0 1

BNX002-0 1

1

2

3

SV

CV

4

SG

CG1

5

CG2

6

CG3

+

C75

C75 100uF

100uF

+3V3

+5V

DGND

C76

C76 100nF

100nF

+

C66

C66 22uF

22uF

3

JP18JP1 8

2

PB1 {3,7}

1

ADC

SOLDER DROP 2 pins open.Normal

AUDIO_OUT L

1 2

SD1SD1

1 2

SD2SD2

DAC

INIT EDIT

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SAM3S-EK

Audio & Pow er Supply

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DES.

1

PB14 {3,7}

26-NOV-09PPB

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DATE

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DATEMODIF.

VER.

DATEMODIF.

VER.

DATEMODIF.

VER.

REV. SHEET

6

B

7

MN9

J9

JP14JP1 4

J9

MP179P 2 .1mm

3

R81

R81 100R

100R

1

OUT1

8

VCC

4

GND

6

AGND

10

7

2

4

+

C81 220 uF

+

C81 220 uF

R95 1KR 95 1K

R97 1KR 97 1K

+

C83 220 uF

+

C83 220 uF

R101 100KR1 01 100K

R103 100KR1 03 100K

C86 0.47uFC86 0.47u F

AVDD

AGND

C74

C74 100nF

100nF

C71

C71 22nF

22nF

AGND

B2 BN03K3 14S300RB2 BN03K 314S300R

R910RR91 0R

8

AGND

VCC33+5V

+

C92

C92 10uF

10uF

DGND

TB10RTB1 0R

VCC33

DGND

AGND

R102 100KR1 02 100K

JP20JP2 0

3

R830RR83 0R

J10J10

1 2

J11

J11 EARJACK

EARJACK

5 4 3 2 1

VDD_AMP

AGND

C87

C87 1uF

1uF

PB0 {3,7}

+5V

CN1

CN1 BNC

BNC

AD12B5

CN2

CN2 BNC

BNC

DAC01

MN9 ZEN056V 130A24LS

ZEN056V 130A24LS

1

1 2

MN12

MN12 MIC29152W U

MIC29152W U

Micrel's 1.5A LDO, TO 263-5

2

VIN

1

SD

GND1

3

DGND

5

1 2 3 4

Potentiometer

5

1 2 3 4

2

VR1

VR1 10K

10K

2

6

VOUT

GND2

DGND

VCC33

DGND

3

ADJ

JP16JP1 6

R96

49.9R 1%

13

JP21JP2 1

R109

49.9R 1%

+

C65

C64

22uF

100nF

4

5

R940RR94 0R

2

C89

C89 10nF

10nF

R1060RR106 0R

C90 2.2uFC90 2.2uF

5

PB[0..14]{3,4,6}

D D

PA[0..31]{3,4,5}

PC[0..31]{3,4 ,5}

4

3

2

1

DGND

JP23JP2 3

1

2

J13J13

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

DGND

JP24JP2 4

1

2

J14J14

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

3

PB8 PB9 PB10 PB11 PB12 PB13 PB14

DGND

3

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

+3V3 + 3V3

DGND

PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31

JP22JP2 2

+5V +3 V3 +5V +5V+3V3 +3V3

1

3

2

J12J12

1 2 3 4 5 6

PC0

7 8

PC1

9 10

PC2

11 12

PC3

13 14

PC4

15 16

PC5

17 18

PC6

19 20

PC7

21 22

PC8

23 24

PC9

25 26

PC10

27 28

PC11

29 30

PC12

31 32

PC13

33 34

PC14

35 36

C C

PC15

37 38

+3V3 + 3V3 +3V3+3V3

39 40

DGND DGN D

PC16 PC17 PC18 PC19 PC20 PC21

PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15

PIO EXPANSION

J15

USB Micro B

5V D- D+ ID G

8 9

FGND

B B

PC21 PC2 0

R110 47KR11 0 47K

R112 68KR11 2 68K Q1

PB10

R114 27RR114 27R

PB11

R116 27RR116 27R

RV2

RV2 V5.5MLA0 603

V5.5MLA0 603

C94

C94 10pF

10pF

DGND

123

6

475

RV1

RV1 V5.5MLA0 603

V5.5MLA0 603

DGND FGN D

Q1

IRLML2502

DGND

PA19

PA20

1

R111

R111 220R

220R

R113

R113 220R

220R

R117

R117 220R

220R

32

D2 Blue-ledD2 Blue-led

D3 Green-ledD3 Green-led

R115 100KR1 15 100K

D4 Red-ledD4 Red-led

LEDS

+3V3

DGND

BP1BP1

1

3 42

BP2BP2

1

3 42

BP3BP3

1

3 42

BUTTONS

+3V3 +5 V

NRST {3,4,5}

JP25JP2 5

PB3

JP26JP2 6

PC12

USB

DGND

ZB_RSTN IRQ1_ZBEE SPIO_NPCS2# MISO

A A

PA18

R118 0RR118 0R

R119 0RR119 0R

PB2 PA12 PA1 4

J16J16

1 2 3 4 5 6 7 8 9 10

R120 0RR120 0R R121 0RR121 0R

C95

C95 18pF

18pF

C96

2.2nF

ZIGBEE

5

4

3

PA16 PA15PA17 PA13

DGND

C97

2.2uF

IRQ0_ZBEE SLP_TR MOSI SPCK

JP27JP2 7

+3V3

26-NOV-09PPB

INIT EDIT

A

REV

SCALE

SAM3S-EK

MISC

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2

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26-NOV-09PPB

XX-XXX-XX

DES.

DATE

DES.

DATE

DES.

DATE

1

XX-XXX-XXNL XXX

DATEMODIF.

VER.

DATEMODIF.

VER.

DATEMODIF.

VER.

REV. SHEET

7

B

7

6.1 Self-Test

A test package software is available to implement a functional test for each section of the board. Refer to the SAM3S-EK page on www.atmel.com.

6.2 Board Recovery

Closing JP3 and powering the board will assert ERASE and clear GPNVM bit 1, and thereby selects the boot from the ROM by default. The MCU will boot from the internal ROM to enable a SAM-BA connection through the UART. Connect the SAM3S-EK UART port (J3) to a PC COM port through an RS232 crossover cable.

You can then run the SAM-BA application from that PC to program the internal Flash of the MCU as well as the GPNVM bit 1.

Section 6

Troubleshooting

SAM3S-EK Development Board User Guide 6-1

11031C–ATARM–30-Mar-11

7.1 Revision History

Table 7-1.

Document Comments

Section 7

Revision History

Change Request Ref.

11031C Note 2 added to

11031B A note added at the end of

11031A First issue.

Section 4.3.9 ”JTAG/ICE” 7637

Section 4.3.4, ” Reset Circuitry”.7565

SAM3S-EK Development Board User Guide 7-1

11031C–ATARM–30-Mar-11

Headquarters International

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Product Contact

Web Site

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Literature Requests

www.atmel.com/literature

Atmel Munich GmbH

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Technical Support

AT91SAM Support Atmel technical support

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Sales Contacts

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11031C–ATARM–30-Mar-11

Atmel SAM3S-EK User guide

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 SAM3S Evaluation Kit

1.2 User Guide

Section 1

Introduction

1.3 References and Applicable Documents

2.1 Deliverables

Section 2

Kit Contents

2.2 Electrostatic Warning

3.1 Power up the Board

3.2 DevStart

Section 3

Power Up

3.3 Recovery Procedure

3.4 Sample Code and Technical Support

4.1 Board Overview

Section 4

Evaluation Kit Hardware

4.2 Features List

4.3 Function Blocks

4.3.1 Processor

4.3.2 Memory

4.3.3 Clock Circuitry

4.3.4 Reset Circuitry

4.3.5 Power Supply and Management

4.3.6 UART

4.3.7 USART

4.3.8 Display Interface

4.3.9 JTAG/ICE

4.3.10 Audio Interface

4.3.11 USB Device

4.3.12 Analog Interface

4.3.13 QTouch Elements

4.3.14 User Buttons

4.3.15 LEDs

4.3.16 SD/MMC Card

4.3.17 ZigBEE

4.3.18 PIO Expansion

4.4 Configuration

4.4.1 PIO Usage

4.4.2 Jumpers

4.4.3 Test Points

4.4.4 Solder Drops

4.4.5 Assigned PIO Lines, Disconnection Possibility

4.5 Connectors

4.5.1 Power Supply Connector J9

4.5.2 USART Connector J5 With RTS/CTS Handshake Support

4.5.3 UART Connector J7

4.5.4 USB Device Connector J15

4.5.5 TFT LCD Connector J8

4.5.6 JTAG Debugging Connector J6

4.5.7 SD/MMC - MCI Connector J3

4.5.8 Analog Connector CN1 & CN2

4.5.9 RS485 Connector J14

4.5.10 Headphone Connector J11

4.5.11 ZigBEE Connector J16

4.5.12 PIO Expansion Port C Connector J12

4.5.13 PIO Expansion Port A Connector J13

4.5.14 PIO Expansion Port B Connector J14

5.1 Schematics

Section 5

Schematics

6.1 Self-Test

6.2 Board Recovery

Section 6

Troubleshooting

7.1 Revision History

Section 7

Revision History