Atmel ATTNY 24, ATTNY 44 Service Manual

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Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 120 Powe rful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation

• Non-volatile Program and Data Memories

– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny24/44/84)

Endurance: 10,000 Write/Erase Cycles

– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny24/44/84)

Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes Internal SRAM (ATtiny24/44/84) – Programming Lock for Self-Programming Flash Program and EEPROM Data

Security

• Peripheral Features

– Two Timer/Counters, 8- and 16-bit counters with two PWM Channels on both – 10-bit ADC

8 single-ended channels

12 differential ADC channel pairs with programmable gain (1x, 20x)

Temperature Measurement – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Universal Serial Interface

• Special Microcontroller Features

– debugWIRE On-chip Debug System – In-System Programmab le via SPI Port – External and Internal Interrupt Sources – Pin Change Interrupt on 12 pins – Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator – On-chip Temperature Sensor

• I/O and Pac kages

– 14-pin SOIC, PDIP and 20-pin QFN/MLF: Twelve Programmable I/O Lines

• Operating Voltage:

– 1.8 - 5.5V for ATtiny24V/44V/84V – 2.7 - 5.5V for ATtiny24/44/84

• Speed Grade

– ATtiny24V/44V/84V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V – ATtiny24/44/84: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

• Industrial Temperature Range

• Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 380 µA – Power-down Mode:

1.8V: 100 nA

8-Bit Microcontroller

8-bit

Microcontroller with 2/4/8K Bytes In-System Programmable Flash

ATtiny24/44/84

Preliminary Summary

Rev. 8006FS–AVR–02/07

1. Pin Configurations

Figure 1-1. Pinout ATt i ny 24 /4 4/ 84

PDIP/SOIC

VCC

(PCINT8/XTAL1/CLKI) PB0

(PCINT9/XTAL2) PB1

(PCINT11/RESET/dW) PB3

(PCINT10/INT0/OC0A/CKOUT) PB2

(PCINT7/ICP/OC0B/ADC7) PA7

(PCINT6/OC1A/SDA/MOSI/ADC6) PA6

(ADC4/USCK/SCL/T1/PCINT4) PA4

(ADC3/T0/PCINT3) PA3 (ADC2/AIN1/PCINT2) PA2 (ADC1/AIN0/PCINT1) PA1

(ADC0/AREF/PCINT0) PA0

NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect

1 2 3 4 5 6 7

QFN/MLF

PA 5

DNC

2019181716

1 2 3 4 5

DNC

14 13 12 11 10

DNC

GND

GND PA0 (ADC0/AREF/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/T0/PCINT3)

PA4 (ADC4/USCK/SCL/T1/PCINT4)

PA5 (ADC5/DO/MISO/OC1B/PCINT5)

Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/ADC6) Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5)

DNC

PA 6

PA7 (PCINT7/ICP/OC0B/ADC7)

PB2 (PCINT10/INT0/OC0A/CKOUT)

PB3 (PCINT11/RESET/dW)

PB1 (PCINT9/XTAL2)

PB0 (PCINT8/XTAL1/CLKI)

VCC

DNC

1.1 Disclaimer

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

ATtiny24/44/84

8006FS–AVR–02/07

2. Overview

2.1 Block Diagram

ATtiny24/44/84

The ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATt iny24/ 44/ 84 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Figure 2-1. Block Diagram

VCC

GND

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

PROGRAMMING

LOGIC

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

X Y Z

ALU

STATUS

ISP INTERFACE

8-BIT DATABUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

MCU STATUS

TIMER/

COUNTER0

TIMER/

COUNTER1

INTERRUPT

UNIT

EEPROM

INTERNAL CALIBRATED OSCILLATOR

TIMING AND

CONTROL

OSCILLATORS

8006FS–AVR–02/07

DATA REGISTER

PORT A

ANALOG

COMPARATOR

PORT A DRIVERS

PA 7- PA 0

DATA DIR.

REG.PORT A

ADC

DATA REGISTER

PORT B

PORT B DRIVERS

PB3-PB0

DATA DIR.

REG.PORT B

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/ O lines, 32 general purpose working registers, a 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software selectable power saving modes. The Idle m ode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, an d Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured ng Atmel’s high density non-volatile memory technology. The Onchip ISP Flash allows the Program memory to be re-programmed In-System thr ough an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core.

The ATtiny24/44/84 AVR is supported with a full suite of pr ogram and system d evelopment to ols including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

ATtiny24/44/84

8006FS–AVR–02/07

2.2 Pin Descriptions

2.2.1 VCC

Supply voltage.

2.2.2 GND

Ground.

2.2.3 Port B (PB3...PB0)

Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the cloc k is not ru nn in g.

Port B also serves the functions of various special features of the ATtiny24/44/84 as listed on

Section 12.3 ”Alternate Port Functions” on page 61.

2.2.4 RESET

ATtiny24/44/84

capability. To use pin PB3 as an I/O pin, instead of

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 22-3 on page

183. Shorter pulses are not guaranteed to gener at e a re se t.

2.2.5 Port A (PA7...PA0)

Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in ”Alter nate Port Functions” on page

3. Resources

A comprehensive set of development tools, drivers and application notes, and datasheets are available for download on http://www.atmel.com/avr.

8006FS–AVR–02/07

4. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x3F (0x5F) SREG I T H S V N Z C Page 9

0x3E (0x5E) SPH – – – – – – SP9 SP8 Page 12 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Page 12 0x3C (0x5C) OCR0B 0x3B (0x5B) GIMSK – INT0 PCIE1

0x3A (0x5A GIFR – INTF0 PCIF1

0x39 (0x59) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 Page 90

0x38 (0x58) TIFR0 – – – – OCF0B OCF0A TOV0 Page 90

0x37 (0x57) SPMCSR – – – CTPB RFLB PGWRT PGERS SPMEN Page 163

0x36 (0x56) OCR0A

0x35 (0x55) MCUCR –PUDSESM1SM0– ISC01 ISC00 Page 53

0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF Page 46

0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 C S0 0 Page 88

0x32 (0x52) TCNT0 Timer/Counter0 Page 89

0x31 (0x51) OSCCALCAL7CAL6CAL5CAL4CAL3CAL2CAL1CAL0 Page 33

0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – WGM01 WGM00 Page 85 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – WGM11 WGM10 Page 114 0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Page 116 0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte Page 118 0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte Page 118 0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte Page 118 0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte Page 118

0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High Byte Page 118

0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte Page 118

0x27 (0x47) DWDR DWDR[7:0] Page 159

0x26 (0x46) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Page 33

0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte Page 119

0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte Page 119

0x23 (0x43) GTCCR TSM – – – – – – PSR10 Page 122

0x22 (0x42) TCCR1C FOC1A FOC1B – – – – – – Page 117

0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Page 46

0x20 (0x40) PCMSK1 – – – – PCINT11 PCINT10 PCINT9 PCINT8 Page 54 0x1F (0x3F) EEARH – – – – – – – EEAR8 Page 23 0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 Page 23 0x1D (0x3D) EEDR EEPROM Data Register Page 23 0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE Page 23 0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Page 72 0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Page 72

0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 Page 72

0x18 (0x38) PORTB – – – – PORTB3 PORTB2 PORTB1 PORTB0 Page 72

0x17 (0x37) DDRB

0x16 (0x36) PINB

0x15 (0x35) GPIOR2 General Purpose I/O Register 2 Page 25

0x14 (0x34) GPIOR1 General Purpose I/O Register 1 Page 25

0x13 (0x33) GPIOR0 General Purpose I/O Register 0 Page 25

0x12 (0x32) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Page 55 0x11 (0x31)) Reserved

0x10 (0x30) USIBR USI Buffer Register Page 131 0x0F (0x2F) USIDR USI Data Register Page 131 0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Page 131 0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Page 132 0x0C (0x2C) TIMSK1 0x0B (0x2B) TIFR1 0x0A (0x2A) Reserved –

0x09 (0x29) Reserved

0x08 (0x28) ACSR ACD ACBG

0x07 (0x27) ADMUX REFS1 REFS0 MUX5 MUX4 MUX3 MUX2

0x06 (0x26) ADCSRA ADEN ADSC

0x05 (0x25) ADCH ADC Data Register High Byte Page 155

0x04 (0x24) ADCL ADC Data Register Low Byte Page 155

0x03 (0x23) ADCSRB BIN ACME –ADLAR– ADTS2 ADTS1 ADTS0 Page 156

0x02 (0x22) Reserved –

0x01 (0x21) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Page 138,Page 157

0x00 (0x20) PRR – – – – PRTIM1 PRTIM0 PRUSI PRADC Page 36

– – – – DDB3 DDB2 DDB1 DDB0 Page 72 – – – – PINB3 PINB2 PINB1 PINB0 Page 73

– –ICIE1– – OCIE1B OCIE1A TOIE1 Page 119 – –ICF1– – OCF1B OCF1A TOV1 Page 120

Timer/Counter0 – Output Compare Regist er B

Timer/Counter0 – Output Compare Regist er A

ACO ACI ACIE ACIC ACIS1 ACIS0 Page 137

ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Page 154

PCIE0 PCIF0

– – – – Page 53 – – – – Page 54

–

MUX1 MUX0 Page 151

Page 89

ATtiny24/44/84

8006FS–AVR–02/07

ATtiny24/44/84

Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

8006FS–AVR–02/07

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